METHOD FOR PRODUCEING A SEMICONDUCER UNIT WITH SELF-ALIGNED UPPER CONTACTS AT CABLE ENDS

Abstract

Method for manufacturing a semiconductor unit (100) comprising: Resetting a first odd-numbered hard mask (110-1) and a first even-numbered hard mask (120-1) to form a reset odd-numbered and a reset even-numbered hard mask, wherein the reset odd-numbered and even-numbered hard masks each have an upper surface beneath an upper surface of an adjacent replacement layer (103); Forming a first conductive hard mask (160-1) comprising a first conductive hard mask material on the recessed odd-numbered hard mask and a second conductive hard mask (160-2) on the recessed even-numbered hard mask; and Forming self-aligned upper through-contacts (185) at conductor ends corresponding to a first odd-numbered and a first even-numbered conductive conductor (130-1, 130-2), at least partially based on the first and second conductive hard mask.

Description

BACKGROUND

[0001] The present invention relates generally to semiconductor devices and more particularly to semiconductor devices having conductive lines and vias and to methods for forming the same.

[0002] Lithographic alignment of vias and conductive lines can be achieved through thick, opaque conductive layers (e.g., metal layers). At small dimensions, overlay and alignment errors can have a significant impact on the contact resistance of vias and dielectric barriers. A variation in the critical dimension (CD) can introduce additional overlay and alignment variation. A limited overlay shift can cause the via to either move away from the line end or be clipped by the line end, resulting in a reduction in the CD of the via.

[0003] Document US 2018 / 0 061 750 A1 describes a multilevel semiconductor device and a method for manufacturing a multilevel semiconductor device, comprising a first interlayer dielectric (ILD) with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and lies directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD layer is formed over the silicide, and a via is formed through the second ILD layer over one of the one or more metal lines. One or more second metal lines are formed over the second ILD, one of which is formed in the via.The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

[0004] Document DE 10 2018 203 792 A1 describes a method for forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with respect to the opening in the patterned sacrificial layer. A metal layer is formed on a region of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned, with the metal layer masking the metal hardmask layer over the region.

[0005] Document DE 10 2018 115 204 A1 describes semiconductor devices and methods for their fabrication. A method comprises forming a first mask layer over a target layer; forming a plurality of spacers over the first mask layer; and forming a second mask layer over the plurality of spacers and patterning the second mask layer to create a first opening, wherein, in a plan view, a major axis of the opening extends in a direction perpendicular to a major axis of a spacer of the plurality of spacers.The method further includes depositing a sacrificial material in the opening; patterning the sacrificial material; etching the first mask layer using the plurality of spacers and the patterned sacrificial material; etching the target layer using the etched first mask layer to create second openings in the target layer; and filling the second openings in the target layer with a conductive material.

[0006] The document US 2019 / 0 244 806 A1 describes surface-aligned lithographic patterning processes for the production of back-end-of-line (BEOL) interconnect lines and the resulting structures. SUMMARY

[0007] According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided.The method comprises: recessing a first odd hard mask and a first even hard mask to form recessed odd and even hard masks, the recessed odd and even hard masks each having a top surface below a top surface of an adjacent replacement layer, forming a first conductive hard mask comprising a first conductive hard mask material on the recessed odd hard mask and a second conductive hard mask on the recessed even hard mask, and forming self-aligned top vias at line ends corresponding to a first odd and a first even conductive line based at least in part on the first and second conductive hard masks.

[0008] According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method comprises: recessing a first odd-numbered hard mask and a first even-numbered hard mask to form recessed odd-numbered and recessed even-numbered hard masks, wherein the recessed odd-numbered and even-numbered hard masks each have a top surface below a top surface of an adjacent replacement layer. The first odd-numbered hard mask is formed to comprise a material different from that of the first even-numbered hard mask to facilitate selective etching of the first odd-numbered and even-numbered hard masks.The method further comprises forming a first conductive hard mask comprising a first conductive hard mask material on the recessed odd hard mask and a second conductive hard mask on the recessed even hard mask. The first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along a direction of a first odd and a first even conductive line. The method further comprises forming self-aligned top vias at line ends corresponding to the first odd and the first even conductive line based at least in part on the first and second conductive hard masks.

[0009] According to yet another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises: forming a first odd-numbered hard mask on a first odd-numbered conductive line and a first even-numbered hard mask on a first even-numbered conductive line. The first odd-numbered hard mask is formed to comprise a material different from that of the first even-numbered hard mask to facilitate selective etching of the first odd-numbered and first even-numbered hard masks. The method further comprises: forming first dielectric layers on sidewalls of the first odd-numbered and first even-numbered hard masks and the first odd-numbered and first even-numbered conductive lines, forming a first cut region corresponding to the first even-numbered conductive line,and forming a second cut region corresponding to the first odd-numbered conductive line, recessing the first odd-numbered hard mask and the first even-numbered hard mask to form recessed odd-numbered and recessed even-numbered hard masks, wherein the recessed odd-numbered and even-numbered hard masks each have an upper surface below an upper surface of an adjacent replacement layer, replacing the first dielectric layers with the respective replacement layers, and forming a first conductive hard mask comprising a first conductive hard mask material on the recessed odd-numbered hard mask and a second conductive hard mask on the recessed even-numbered hard mask. The first and second conductive hard masks are formed in such a way thatthat they have a semi-circular cross-sectional shape along a direction of the first odd-numbered and the first even-numbered conductive lines. The method further comprises: forming self-aligned top vias at line ends corresponding to the first odd-numbered and the first even-numbered conductive lines, based at least in part on the first and second conductive hard masks.

[0010] According to yet another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises: forming a first odd-numbered hard mask on a first odd-numbered conductive line and a first even-numbered hard mask on a first even-numbered conductive line. The first odd-numbered hard mask is formed to comprise a material different from that of the first even-numbered hard mask to facilitate selective etching of the first odd-numbered and first even-numbered hard masks. The method further comprises: forming first dielectric layers on sidewalls of the first odd-numbered and first even-numbered hard masks and the first odd-numbered and first even-numbered conductive lines, forming a first cut region corresponding to the first even-numbered conductive line,and forming a second cut region corresponding to the first odd-numbered conductive line, forming a first sacrificial layer within the first cut region and a second sacrificial layer within the second cut region, recessing the first odd-numbered hard mask and the first even-numbered hard mask to form recessed odd-numbered and recessed even-numbered hard masks, wherein the recessed odd-numbered and even-numbered hard masks each have an upper surface below an upper surface of an adjacent replacement layer, replacing the first dielectric layers with the respective replacement layers, and forming a first conductive hard mask comprising a first conductive hard mask material,on the recessed odd-numbered hard mask and a second conductive hard mask on the recessed even-numbered hard mask. The first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along a direction of the first odd-numbered and first even-numbered conductive lines. The method further comprises: forming an additional hard mask material on the recessed odd-numbered and recessed even-numbered hard masks and the first and second conductive hard masks, performing a planarization process after forming the additional hard mask material, forming a third and fourth conductive hard mask based on a patterning of a via not at a line end after the planarization process, forming self-aligned top vias at line ends,corresponding to the first odd-numbered and the first even-numbered conductive lines, based at least in part on the first and second conductive hard masks, and performing additional processing. Performing additional processing includes removing the first and second sacrificial layers to form openings between the self-aligned upper vias, forming second dielectric layers in the openings, and replacing the replacement layers with third dielectric layers.

[0011] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following description provides details of preferred embodiments with reference to the following figures in which: Fig. 1 is a top-down view of the formation of hard masks on conductive lines during the fabrication of a semiconductor device according to an embodiment of the present invention; Fig. 2 a cross-sectional view through an odd-numbered conductive line of a region of an odd-numbered conductive line of the Fig. 1 according to an embodiment of the present invention; Fig. 3 a cross-sectional view through an even-numbered conductive line of a region of an even-numbered conductive line of the Fig. 1 according to an embodiment of the present invention; Fig. 4 is a top-down view of the formation of a first cut portion corresponding to the even-numbered conductive line during the manufacture of the semiconductor device according to an embodiment of the present invention; Fig. 5 a cross-sectional view through the odd-numbered conductive line of the Fig. 3 according to an embodiment of the present invention; Fig. 6 a cross-sectional view through the even-numbered conductive line of the Fig. 3 according to an embodiment of the present invention; Fig. 7 is a top-down view of the formation of a second cut portion corresponding to the odd-numbered conductive line during the manufacture of the semiconductor device according to an embodiment of the present invention; Fig. 8 a cross-sectional view through the odd-numbered conductive line of the Fig. 7 according to an embodiment of the present invention; Fig. 9 a cross-sectional view through the even-numbered conductive line of the Fig. 7 according to an embodiment of the present invention; Fig. 10 is a cross-sectional view of the formation of a sacrificial material within the first cutting region according to an embodiment of the present invention; Fig. 11 is a cross-sectional view of the formation of a sacrificial material within the second cutting region according to an embodiment of the present invention; Fig. 12 is a cross-sectional view of the formation of a conductive hard mask on the material formed within the first cutting region according to an embodiment of the present invention; Fig. 13 is a cross-sectional view of the formation of a conductive hard mask on the material formed within the second cutting region according to an embodiment of the present invention; Fig. 14 is a cross-sectional view of hard mask filling and planarization within the odd-numbered conductive line region according to an embodiment of the present invention; Fig. 15 is a cross-sectional view of a hard mask fill and planarization within the even-numbered conductive line region according to an embodiment of the present invention; Fig. 16 is a top-down view of the formation of additional mask material on additional of the conductive lines during fabrication of the semiconductor device according to an embodiment of the present invention; Fig. 17 is a top-down view of the removal of the hard masks from the conductive lines during fabrication of the semiconductor device according to an embodiment of the present invention; Fig. 18 is a top-down view of the removal of the sacrificial material from the cut regions and the dielectric material fill during the fabrication of the semiconductor device according to an embodiment of the present invention; Fig. 19 a cross-sectional view through the odd-numbered conductive line of the Fig. 18 according to an embodiment of the present invention; Fig. 20 a cross-sectional view through the even-numbered conductive line of the Fig. 18 according to an embodiment of the present invention; and Fig. 21 is a block diagram / flowchart illustrating a system / method for manufacturing a semiconductor device according to an additional embodiment of the present invention. DETAILED DESCRIPTION

[0013] The embodiments described herein provide for the formation of self-aligned top vias or top-down vias at ends of a conductive line. More specifically, a cut mask may be used to define a cut of a conductive line, and selective deposition may be used to form self-aligned top vias on both sides of the cut corresponding to the ends of the conductive line. The critical dimension (CD) of the via at the end of the conductive line may be controlled by the coverage of the selective deposition along the direction of the conductive line. As a result, no variation in the CD of the via is introduced, which would otherwise result from lithographically aligning the via to a previously formed cut of the conductive line.

[0014] It is understood that aspects of the present invention are described with respect to a given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may be varied within the scope of aspects of the present invention.

[0015] It is also to be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it may be directly on top of the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements. It is also to be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or directly coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0016] The present embodiments may include a design for an integrated circuit chip that may be created in a graphical computer programming language and stored in a computer storage medium (such as a floppy disk, tape, physical hard disk, or virtual hard disk, such as in a storage access network). If the designer does not manufacture chips or the photolithographic masks used to manufacture chips, the designer may transmit the resulting design directly or indirectly to such companies by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet). The stored design is then converted into a suitable format (e.g.,GDSII) for the production of photolithographic masks, which typically contain multiple copies of the corresponding chip design to be formed on a wafer. The photolithographic masks are used to define areas of the wafer (and / or the layers thereon) that are to be etched or otherwise processed.

[0017] Methods described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier containing either surface interconnects or embedded interconnects, or both). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product incorporating integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products incorporating a display, keyboard or other input device, and a central processor.

[0018] It is also understood that material compounds are described in terms of listed elements, e.g. SiGe. These compounds have different proportions of the elements within the compound, e.g. SiGe has Si x Ge 1-x where x is less than or equal to 1, etc. Furthermore, additional elements may be included in the compound, and it may still function according to the principles herein. Compounds with additional elements are referred to herein as alloys.

[0019] Referring now to the drawings, in which like reference numerals represent the same or similar elements, and first to Fig. 1, a top-down view of a semiconductor device 100 is provided. As shown, the device 100 includes dielectric layers 102. The dielectric layers 102 may include any suitable dielectric material according to the embodiments described herein. For example, the bottom dielectric layer may include, e.g., silicon dioxide (SiO2), low-k dielectrics, nitride layers, and combinations thereof. In one embodiment, the dielectric layers 102 may include an ultra-low-k dielectric material (a ULK material). For example, the dielectric layers 102 may include a dielectric material having a dielectric constant k less than or equal to, e.g., about 2.5.

[0020] As further shown, a plurality of hard masks are formed on a plurality of conductive lines. More specifically, "odd" hard masks 110-1 and 110-2 are formed on "odd" conductive lines within regions (not shown) of odd-numbered conductive lines, and "even" hard masks 120-1 and 120-2 are formed on "even" conductive lines within regions (not shown) of even-numbered conductive lines.

[0021] The odd-numbered hard masks 110-1 and 110-2 comprise a material that differs from that of the even-numbered hard masks 120-1 and 120-2. More specifically, the material for the hard masks may be selected to support selective etching of the hard masks during processing, as described in more detail below. Furthermore, the odd-numbered hard masks 110-1 and 110-2 may comprise the same material or different materials, and the even-numbered hard masks 120-1 and 120-2 may comprise the same material or different materials.

[0022] Examples of suitable materials used to form the odd-numbered hard masks 110-1 and 110-2 may include a silicon nitride material (e.g., SiN), a silicon carbide material (e.g., SiC), etc. Examples of suitable materials used to form the even-numbered hard masks 120-1 and 120-2 may include a silicon oxide material (SiO x ), a spin-on-glass (SOG) material, etc. However, the odd-numbered hard masks and the even-numbered hard masks may comprise any suitable materials according to the embodiments described herein.

[0023] With reference to Fig. 2 is a cross-sectional view of the unit 100 through a line 1-1' of Fig. 1, which corresponds to a cross section through one of the regions of the odd-numbered conductive lines, and with reference to Fig. 3 is a cross-sectional view of the unit 100 through a line 2-2' of Fig. 1, which corresponds to a cross-section through one of the areas of the even-numbered conductive lines.

[0024] As in Fig. 2, the device 100 includes an odd-numbered conductive line 130-1 and the odd-numbered hard mask 110-1 formed on the odd-numbered conductive line 130-1. As shown in Fig. 3, the device 100 includes an even-numbered conductive line 130-2 and the even-numbered hard mask 120-1 formed on the even-numbered conductive line 130-2. The dielectric layers 102 are formed along the sidewalls of the conductive lines 130-1 and 130-2 and the hard masks 110-1 and 120-1. Examples of suitable conductive materials that may be used to form the conductive lines 130-1 and 130-2 include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), etc.

[0025] With reference to the Fig. 4 to 6, openings 137-1 and 137-2 and an intersection region 150-2 corresponding to the even-numbered conductive line 130-2 are formed. As shown in this illustrative example, the openings 137-1 and 137-2 may be formed, for example, by forming a mask material 135, patterning the mask material 135 into the hard masks 110-1 and 120-1, etching the hard mask 120-1 selectively with respect to the hard mask 110-1, and etching the even-numbered conductive line 130-2 to form an intersection region 150-2. The mask material 135 may then be removed after the formation of the intersection region 150-2.

[0026] Any suitable process may be used to form the openings 137-1 and 137-2 and the cut region 150-2 according to the embodiments described herein. In one embodiment, reactive ion etching (RIE) may be used. Selective RIE may, for example, be used to remove the material of the hard mask 120-1 (e.g., SiO x ) selectively with respect to the material of the hard mask 110-1 (e.g. SiN).

[0027] The mask material 135 may comprise any suitable material according to the embodiments described herein. In some embodiments, the mask material 135 may comprise multiple layers. For example, the mask material 135 may comprise an organic planarization layer (OPL), an anti-reflective coating (ARC) layer (e.g., a SiARC layer), and a resist layer, which may form a three-layer lithography mask. As another example, the mask material 135 may comprise an OPL, a dielectric layer (e.g., an oxide), a bottom ARC layer (a BARC layer), and a resist layer, which may form a four-layer lithography mask. The structure in the mask material 135 may be formed using any suitable lithography process (e.g., using deep UV or extreme UV lithography) with any suitable lithography stack (not shown).

[0028] With reference to the Fig. 7 to 9, openings 147-1 and 147-2 and an intersection region 150-1 corresponding to the odd-numbered conductive line 130-1 are formed. As shown in this illustrative example, the openings 147-1 and 147-2 may be formed by forming a mask material 145, patterning the mask material 145 into the hard masks 110-1 and 120-1, etching the hard mask 110-1 selectively with respect to the hard mask 120-1, and etching the odd-numbered conductive line 130-1 to form the intersection region 150-1. The mask material 135 may then be removed after the formation of the intersection region 150-1.

[0029] Any suitable process may be used to form the openings 147-1 and 147-2 and the cut region 150-1 according to the embodiments described herein. In one embodiment, RIE may be used. Selective RIE may, for example, be used to select the material of the hard mask 120-1 (e.g., SiO x ) selectively with respect to the material of the hard mask 110-1 (e.g. SiN).

[0030] The mask material 145 may comprise any suitable material according to the embodiments described herein. In some embodiments, the mask material 145 may comprise multiple layers, similar to the mask material 135. For example, the mask material 145 may comprise an OPL, an ARC (e.g., a SiARC layer), and a resist layer, which may form a three-layer lithography mask. As another example, the mask material 145 may comprise an OPL, a dielectric layer (e.g., an oxide), a BARC layer, and a resist layer, which may form a four-layer lithography mask. The structure in the mask material 145 may be formed using any suitable lithography process (e.g., deep UV or extreme UV lithography) with any suitable lithography stack (not shown).

[0031] With reference to Fig. 10, a cross-sectional view of the device 100 corresponding to the region of an odd-numbered conductive line is provided, illustrating the formation of a sacrificial layer 155-1 within the cutting region 150-1, and with reference to Fig. 11, a cross-sectional view of the device 100 corresponding to the region of an even-numbered conductive line is provided, illustrating the formation of the sacrificial layer 155-2 within the cutting region 150-2.

[0032] The sacrificial layers 155-1 and 155-2 may comprise any suitable material according to the embodiments described herein. Examples of suitable materials that may be used to form the sacrificial layers 155-1 and 155-2 include a titanium nitride material (e.g., TiN), a titanium oxide material (e.g., TiO x ), an aluminum oxide material (e.g. AlO x ), an aluminum nitride material (e.g. AlN), etc., but are not limited to these.

[0033] Any suitable process may be used to form the sacrificial layers 155-1 and 155-2 according to the embodiments described herein. For example, the sacrificial layers 155-1 and 155-2 may be formed in the cut regions 150-1 and 150-2 by filling the cut regions 150-1 and 150-2 with sacrificial material, performing a planarization process (e.g., chemical mechanical planarization (CMP)), and recessing the sacrificial material in the cut regions 150-1 and 150-2 to form the sacrificial layers 155-1 and 155-2. For example, if the sacrificial material comprises a metal oxide, a chlorine-based etch chemistry may be used to etch the sacrificial material selectively with respect to the hard masks 110-1 and 120-1 and the dielectric layers 102 (e.g., using RIE).

[0034] At this point, the dielectric layers 102 are replaced by replacement layers 103. Replacing the dielectric layers 102 with the replacement layers 103 may include removing the dielectric layers 102 using one or more etching processes, filling the cavity with replacement material, and planarizing (e.g., by CMP) or etching back the replacement material to form the replacement layers 103. The replacement layers 103 may comprise any suitable material according to the embodiments described herein. For example, the replacement layers 103 may comprise, e.g., an organic planarization layer (OPL) or another organic spin-coated material.

[0035] With reference to the Fig. 12 and Fig. 13, the hard masks 110-1 and 120-1 are selectively recessed with respect to the sacrificial layers 155-1 and 155-2, a conductive hard mask 160-1 is formed on the sacrificial layer 155-1 and the hard mask 110-1, and a conductive hard mask 160-2 is formed on the sacrificial layer 155-2 and the hard mask 110-2. More specifically, the conductive hard masks 160-1 and 160-2 may be formed by selectively depositing a conductive hard mask material. As shown in FIGS. Fig. 12 and Fig. 13, the conductive hard masks 160-1 and 160-2 may be formed to have a semi-circular or semi-circular cross-sectional shape along the direction of the conductive lines 130-1 and 130-2. The conductive hard masks 160-1 and 160-2 may comprise any suitable material according to the embodiments described herein. Examples of suitable materials that may be used to form the conductive hard masks 160-1 and 160-2 include, but are not limited to, titanium (Ti), tantalum (Ta), a titanium nitride material (e.g., TiN), a tantalum nitride material (e.g., TaN), etc.

[0036] Any suitable process may be used to reset the hard masks 110-1 and 120-1 and form the conductive hard masks 160-1 and 160-2 according to the embodiments described herein. For example, the reset of the hard masks 110-1 and 120-1 may be performed using a timed RIE etch process, a wet etch process, or a combination thereof that can selectively etch the hard masks 110-1 and 120-1 with respect to the layers 103, 155-1, and 155-2. In one embodiment, a fluorocarbon-based RIE process may be used to reset the hard masks 110-1 and 120-1.

[0037] With reference to the Fig. 14 and Fig. 15, additional hard masks 170-1 and 170-2 are formed on the hard masks 110-1 and 120-1, respectively. In this illustrative embodiment, the additional hard masks 170-1 and 170-2 may be formed by depositing an additional hard mask material and performing a planarization process (e.g., CMP). As can be seen from the Fig. 14 and Fig. 15, the planarization may result in the conductive hard masks 160-1 and 160-2 having a flat top surface.

[0038] With reference to Fig. 16 provides a top-down view illustrating the formation of additional hard masks 170-3 and 170-4, as well as additional conductive hard masks 180-1 and 180-2, corresponding to odd-numbered hard masks 110-2 and even-numbered hard masks 120-2, respectively. Additional hard masks 170-3 and 170-4 may comprise the same material as or a different material than additional hard masks 170-1 and 170-2, and additional conductive hard masks 180-1 and 180-2 may comprise the same material as or a different material than additional conductive hard masks 160-1 and 160-2.

[0039] Any suitable process may be used to form the additional hard masks 170-3 and 170-4, as well as the additional conductive hard masks 180-1 and 180-2, according to the embodiments described herein. For example, patterning a non-end-of-line via for the even-numbered hard mask 120-2 may be performed to form a mask, the even-numbered hard mask 120-2 may be etched to form an opening based on the mask, and the mask may be removed. Patterning a non-end-of-line via for the odd-numbered hard mask 110-2 may be performed to form a mask, the odd-numbered hard mask 110-2 may be etched to form an opening based on the mask, and the mask may be removed.After forming the openings in the odd and even hard masks 110-2 and 120-2, a material for an additional conductive hard mask may be formed in the openings, and a planarization process (e.g., CMP) may be performed.

[0040] With reference to Fig. 17, the additional hard masks 170-1 through 170-4, the odd-numbered hard masks 110-1 and 110-2, and the even-numbered hard masks 120-1 and 120-2 are removed using any suitable etching process in accordance with the embodiments described herein. The removal of the material results in the formation of upper vias.

[0041] With reference to Fig. 18, a top-down view of a semiconductor device 100 is provided, illustrating the formation of self-aligned top vias 185, the removal of replacement layers 103 and sacrificial layers 155-1 and 155-2, and the formation of dielectric layers 190 and 195.

[0042] The upper vias 185 are each formed at a line end corresponding to a conductive line. The upper vias 185 can be formed, for example, by partially etching the conductive lines 130-1 and 130-2 using the hard masks 160-1, 160-2, 180-1, and 180-2. Then, the replacement layer 103s may be removed using an etching process (e.g., RIE), the sacrificial layers 155-1 and 155-2 may be removed using another etching process (e.g., a wet etching process), the dielectric layer 190 may be formed by depositing a dielectric material and performing a planarization process (e.g., CMP), and the dielectric layer 195 may be formed by filling the space previously occupied by the sacrificial layers 155-1 and 155-2 and performing a planarization process (e.g., CMP).

[0043] Dielectric layers 190 and 195 may comprise any suitable material according to the embodiments described herein. For example, dielectric layer 190 may comprise a low-k, or ULK, dielectric material, and dielectric layer 195 may comprise a "moderate-k," low-k, or ULK dielectric material. As used herein, a moderate-k dielectric material refers to a dielectric material having a dielectric constant between about 4 and about 7. Dielectric layers 190 and 195 may comprise the same dielectric materials or different dielectric materials.

[0044] With reference to Fig. 19 is a cross-sectional view of the unit 100 through a line 1-1' of Fig. 18, which corresponds to a cross section through one of the areas of odd-numbered conductive lines, and with reference to Fig. Figure 20 is a cross-sectional view of the unit 100 through a line 2-2' of Fig. 18, which corresponds to a cross-section through one of the areas of even-numbered conductive lines.

[0045] With reference to Fig. 21, a block diagram / flowchart illustrating a system / method 200 for manufacturing a semiconductor device according to one embodiment is shown.

[0046] In block 202, at least one first odd-numbered hard mask is formed on a first odd-numbered conductive line, and at least one first even-numbered hard mask is formed on a first even-numbered conductive line. First dielectric layers may be formed on exposed sidewalls of the first odd-numbered and first even-numbered hard masks and the first odd-numbered and first even-numbered conductive lines.

[0047] The first odd-numbered hard mask may be formed to comprise a material different from that of the first even-numbered hard mask. More specifically, the material of the first odd-numbered and first even-numbered hard masks may be selected to facilitate selective etching of the hard masks during processing. Furthermore, in an embodiment where a second odd-numbered and a second even-numbered hard mask are formed on a second odd-numbered and a second even-numbered conductive line, respectively, the first and second odd-numbered hard masks may be formed to comprise the same or different materials.

[0048] Examples of suitable materials used to form the odd-numbered hard masks may include a silicon nitride material (e.g., SiN), a silicon carbide material (e.g., SiC), etc. Examples of suitable materials used to form the even-numbered hard masks may include a silicon oxide material (SiO x ), a spin-on-glass (SOG) material, etc. However, the odd-numbered and even-numbered hard masks may comprise any suitable materials according to the embodiments described herein.

[0049] Examples of suitable conductive materials that can be used to form the odd and even conductive lines include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), etc.

[0050] Further details regarding block 202 are described above with reference to the Fig. 1 to 3.

[0051] In block 204, a first intersection region corresponding to the first even-numbered conductive line is formed. Forming the first intersection region may include forming a first mask material on the first odd-numbered and first even-numbered hard masks, patterning the first mask material to the first odd-numbered and first even-numbered hard masks to form first odd-numbered and first even-numbered openings, respectively, etching the first even-numbered hard mask selectively with respect to the first odd-numbered hard mask, and etching the first even-numbered conductive line through the first even-numbered opening to form the first intersection region. The first mask material may then be removed.

[0052] Any suitable process may be used to form the first openings and the first cut region according to the embodiments described herein. In one embodiment, reactive ion etching (RIE) may be used. Selective RIE may, for example, be used to select the material of the first even-numbered hard mask (e.g., SiO x ) selectively with respect to the material of the first odd-numbered hard mask (e.g. SiN).

[0053] The first mask material may be formed to include any suitable material according to the embodiments described herein. In some embodiments, the first mask material may be formed to include multiple layers. For example, the first mask material may be formed to include an organic planarization layer (OPL), an anti-reflective coating (ARC) layer (e.g., a SiARC layer), and a resist layer, which may form a three-layer lithography mask. As another example, the first mask material may be formed to include an OPL, a dielectric layer (e.g., an oxide), a lower ARC layer (a BARC layer), and a resist layer, which may form a four-layer lithography mask. The structure in the first mask material may be formed using any suitable lithography process (e.g.,deep UV or extreme UV lithography) with any suitable lithography stack (not shown).

[0054] Further details regarding block 204 are described above with reference to the Fig. 4 to 6.

[0055] In block 206, a second intersection region corresponding to the first odd-numbered conductive line is formed. Forming the second intersection region may include forming a second mask material on the first odd-numbered and first even-numbered hard masks, patterning the second mask material to the first odd-numbered and first even-numbered hard masks to form second odd-numbered and second even-numbered openings, respectively, etching the first even-numbered hard mask selectively with respect to the first odd-numbered hard mask, and etching the first odd-numbered conductive line through the second odd-numbered opening to form the second intersection region. The second mask material may then be removed.

[0056] Any suitable process may be used to form the second openings and the second cut region according to the embodiments described herein. In one embodiment, RIE may be used. For example, selective RIE may be used to select the material of the first even-numbered hard mask (e.g., SiO x ) selectively with respect to the material of the first odd-numbered hard mask (e.g. SiN).

[0057] The second mask material may be formed to comprise any suitable material according to the embodiments described herein. In some embodiments, the second mask material may be formed to comprise multiple layers, similar to the first mask material. For example, the second mask material may comprise an OPL, an ARC (e.g., a SiARC layer), and a resist layer, which may form a three-layer lithography mask. As another example, the second mask material may comprise an OPL, a dielectric layer (e.g., an oxide), a BARC layer, and a resist layer, which may form a four-layer lithography mask. The structure in the second mask material may be formed using any suitable lithography process (e.g., deep UV or extreme UV lithography) with any suitable lithography stack (not shown).

[0058] Further details regarding block 206 are described above with reference to the Fig. 7 to 9 described.

[0059] In block 208, a first sacrificial layer is formed within the first cutting region, and a second sacrificial layer is formed within the second cutting region. The sacrificial layers may be formed to comprise any suitable material in accordance with the embodiments described herein. Examples of suitable materials that may be used to form the sacrificial layers include a titanium nitride material (e.g., TiN), a titanium oxide material (e.g., TiO x ), an aluminum oxide material (e.g. AlO x ), an aluminum nitride material (e.g. AlN), etc., but are not limited to these.

[0060] Any suitable process may be used to form the sacrificial layers according to the embodiments described herein. For example, the sacrificial layers may be formed in the cut regions by filling the cut regions with sacrificial material, performing a planarization process (e.g., chemical mechanical planarization (CMP)), and recessing the sacrificial material in the cut regions to form the sacrificial layers. For example, if the sacrificial material comprises a metal oxide, a chlorine-based etch chemistry may be used to selectively etch the sacrificial material with respect to the first odd-numbered and even-numbered hard masks and the dielectric layers (e.g., using RIE).

[0061] Further details regarding block 208 are described above with reference to the Fig. 10 and Fig. 11 described.

[0062] In block 210, the first odd and even hard masks are reset to form a reset odd and even hard mask. Any suitable process may be used to reset the first odd and even hard masks according to the embodiments described herein. For example, the first odd and even hard masks may be reset using a timed RIE etch process, a wet etch process, or a combination thereof that can selectively etch the first odd and even hard masks with respect to the dielectric layers and the sacrificial layers. In one embodiment, a fluorocarbon-based RIE process may be used to reset the first odd and even hard masks.

[0063] In block 212, a first conductive hard mask and a second conductive hard mask are formed. The first conductive hard mask may be formed on the first sacrificial layer and the recessed odd-numbered hard mask, and the second conductive hard mask may be formed on the second sacrificial layer and the recessed even-numbered hard mask. More specifically, the first and second conductive hard masks may be formed by selectively depositing a first conductive hard mask material.

[0064] The first and second conductive hard masks may be formed to have a semi-circular or semi-circular cross-sectional shape along the direction of the first odd-numbered and first even-numbered conductive lines. The first and second conductive hard masks may comprise any suitable material according to the embodiments described herein. Examples of suitable materials that may be used to form the first and second conductive hard masks include, but are not limited to, titanium (Ti), tantalum (Ta), a titanium nitride material (e.g., TiN), a tantalum nitride material (e.g., TaN), etc. Any suitable process may be used to form the first and second conductive hard masks according to the embodiments described herein.

[0065] Forming the first and second conductive hard masks may further comprise replacing the dielectric material with respective replacement layers. Replacing the dielectric material with the replacement layers may comprise removing the dielectric material using one or more etching processes, filling the cavity with a replacement material, and planarizing (e.g., by CMP) or etching back the replacement material to form the replacement layers. The replacement layers may comprise any suitable material according to the embodiments described herein. For example, the replacement layers may comprise, e.g., an organic planarization layer (OPL) or another organic material formed by spin-on coating.

[0066] Further details regarding blocks 210 and 212 are described above with reference to the Fig. 12 and Fig. 13 described.

[0067] In block 214, an additional hardmask material is formed. Forming the additional hardmask material may include depositing the additional hardmask material on the recessed odd and even hardmasks and the first and second conductive hardmasks. Furthermore, the additional hardmask material may be formed on the second odd and even hardmasks. A planarization process (e.g., CMP) may then be performed. The planarization process may result in the first and second conductive hardmasks having a flat top surface.

[0068] In block 216, third and fourth conductive hard masks are formed based on a patterning of a via not at a line end. More specifically, an opening to the second even-numbered conductive line may be formed through the additional hard mask material and the second even-numbered hard mask, an opening to the second odd-numbered conductive line may be formed through the additional hard mask material and the second odd-numbered hard mask, a second conductive hard mask material may be formed within the openings in the second even-numbered and second odd-numbered conductive lines, and a planarization process (e.g., CMP) may be performed. Examples of suitable materials that may be used to form the third and fourth conductive hard masks include titanium (Ti), tantalum (Ta), a titanium nitride material (e.g., TiN), a tantalum nitride material (e.g., TaN), etc., but are not limited to these. Any suitable process may be used to form the third and fourth conductive hard masks according to the embodiments described herein.

[0069] In block 218, self-aligned top vias are formed at line ends. The line ends correspond to the conductive lines (e.g., the first odd and even conductive lines). Any suitable process may be used to form the self-aligned top vias according to the embodiments described herein. For example, forming the self-aligned top vias may include removing the odd and even hard masks and the additional hard mask material, and partially etching the first odd and even conductive lines using the conductive hard masks.

[0070] Further details regarding blocks 214 to 218 are given above with reference to the Fig. 14 to 17 described.

[0071] In block 220, additional processing is performed.

[0072] The additional processing may include removing the replacement layers and the sacrificial layers. The replacement layer may be removed using one etching process (e.g., RIE), and the sacrificial layers may be removed using another etching process (e.g., a wet etching process).

[0073] The additional processing may further include forming second dielectric layers in spaces between the odd-numbered and even-numbered conductive lines, and forming third dielectric layers within spaces previously occupied by the replacement and sacrificial layers. More specifically, the second dielectric layer may be formed by depositing a dielectric material and performing a planarization process (e.g., CMP), and the third dielectric layer may be formed by filling the space previously occupied by the replacement and sacrificial layers and performing a planarization process (e.g., CMP).

[0074] Further details regarding block 220 are described above with reference to the Fig. 18 to 20 described.

Claims

[1] A method of manufacturing a semiconductor device (100), comprising: Resetting a first odd-numbered hard mask (110-1) and a first even-numbered hard mask (120-1) to form a recessed odd-numbered hard mask and a recessed even-numbered hard mask, the recessed odd-numbered and even-numbered hard masks each having a top surface below a top surface of an adjacent replacement layer (103); forming a first conductive hard mask (160-1) comprising a first conductive hard mask material on the recessed odd-numbered hard mask and a second conductive hard mask (160-2) on the recessed even-numbered hard mask; and Forming self-aligned top vias (185) at line ends corresponding to a first odd-numbered and a first even-numbered conductive line (130-1, 130-2) based at least in part on the first and second conductive hard masks. [2] The method according to claim 1, wherein the first and second conductive hard masks (160-1, 160-2) are formed to have a semi-circular cross-sectional shape along a direction of the first odd-numbered and first even-numbered conductive lines (130-1, 130-2). [3] The method of claim 1, further comprising: Forming an additional hard mask material on the recessed odd and recessed even hard masks (110-1, 120-1) and the first and second conductive hard masks (160-1, 160-2); performing a planarization process after forming the additional hard mask material; and Forming a third and a fourth conductive hard mask (180-1, 180-2) based on a patterning of a via not at a line end after the planarization process. [4] The method of claim 3, wherein forming the third and fourth conductive hard masks (180-1, 180-2) further comprises: forming an opening to a second even-numbered conductive line (130-4) through the additional hard mask material and a second even-numbered hard mask (120-2) formed on the second even-numbered conductive line; forming an opening to a second odd-numbered conductive line (130-3) through the additional hard mask material and a second odd-numbered hard mask (110-2) formed on the second odd-numbered conductive line; Forming a second conductive hard mask material within the openings to the second even-numbered (130-4) and the second odd-numbered conductive line (130-3); and Performing a planarization process after forming the first and second conductive hard mask materials to form the third and fourth conductive hard masks (180-1, 180-2). [5] The method of claim 3, wherein forming the self-aligned upper vias (185) further comprises: Removing the recessed odd and even hard masks (110-1, 120-1) and the additional hard mask material; and partially etching the first odd-numbered and the first even-numbered conductive lines (130-1, 130-2) using the first and second conductive hard masks (160-1, 160-2). [6] The method of claim 1, further comprising: Forming the first odd-numbered hard mask (110-1) on the first odd-numbered conductive line (130-1) and the first even-numbered hard mask (120-1) on the first even-numbered conductive line (130-2); Forming first dielectric layers (102) on sidewalls of the first odd-numbered and the first even-numbered hard masks (110-1, 120-1) and the first odd-numbered and the first even-numbered conductive lines (130-1, 130-2); and Forming a first intersection region (150-2) corresponding to the first even-numbered conductive line (130-2) and a second intersection region (150-1) corresponding to the first odd-numbered conductive line (130-1). [7] The method of claim 6, wherein the first odd hard mask (110-1) is formed to have a material different from that of the first even hard mask (120-1) to assist in selective etching of the first odd and first even hard masks. [8] The method of claim 6, wherein forming the first cutting region (150-2) further comprises: Forming a first mask material (135) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1); Patterning the first mask material (135) into the first odd-numbered and the first even-numbered hard mask (110-1, 120-1) to form a first odd-numbered and a first even-numbered opening (137-1, 137-2), respectively; Etching the first even-numbered hard mask (120-1) selectively with respect to the first odd-numbered hard mask (110-1); and Etching the first even-numbered conductive line (130-2) through the first even-numbered opening (137-2) to form the first cutting region (150-2). [9] The method of claim 8, wherein forming the second cutting region (150-1) further comprises: Forming a second mask material (145) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1) and within the first cutting region (150-2); Patterning the second mask material (145) into the first odd-numbered and the first even-numbered hard mask (110-1, 120-1) to form a second odd-numbered and a second even-numbered opening (147-1, 147-2), respectively; Etching the first odd-numbered hard mask (110-1) selectively with respect to the first even-numbered hard mask (120-1); and Etching the first odd-numbered conductive line (130-1) through the second even-numbered opening (147-2) to form the second cutting region (150-1). [10] The method of claim 6, further comprising replacing the first dielectric layers (102) with the replacement layers (103). [11] The method of claim 10, further comprising: Forming a first sacrificial layer (155-2) within the first cutting region (150-2); and Forming a second sacrificial layer (155-1) within the second cutting region (150-1). [12] The method of claim 11, further comprising performing additional processing comprising: Removing the first and second sacrificial layers (155-1, 155-2) to form openings between the self-aligned upper vias (185); forming second dielectric layers (195) in the openings; and Replacing the replacement layers (103) by third dielectric layers (190). [13] The method of claim 1, wherein the first odd-numbered hard mask (110-1) is formed to have a material different from that of the first even-numbered hard mask (120-1) to facilitate selective etching of the first odd-numbered and first even-numbered hard masks; and wherein the first and second conductive hard masks (160-1, 160-2) are formed to have a semi-circular cross-sectional shape along a direction of the first odd-numbered and first even-numbered conductive lines (130-1, 130-2). [14] The method of claim 13, further comprising: Forming an additional hard mask material on the recessed odd and recessed even hard masks (110-1, 120-1) and the first and second conductive hard masks (160-1, 160-2); performing a planarization process after forming the additional hard mask material; and Forming a third and a fourth conductive hard mask (180-1, 180-2) based on a patterning of a via not at a line end after the planarization process; wherein forming the third and fourth conductive hard masks (180-1, 180-2) further comprises: forming an opening to a second even-numbered conductive line (130-4) through the additional hard mask material and a second even-numbered hard mask (120-2) formed on the second even-numbered conductive line; forming an opening to a second odd-numbered conductive line (130-3) through the additional hard mask material and a second odd-numbered hard mask (110-2) formed on the second odd-numbered conductive line; Forming a second conductive hard mask material within the openings to the second even-numbered and second odd-numbered conductive lines (130-3, 130-4); and Performing a planarization process after forming the first and second conductive hard mask materials to form the third and fourth conductive hard masks (180-1, 180-2). [15] The method of claim 14, wherein forming the self-aligned upper vias (185) further comprises: Removing the recessed odd and even hard masks and the additional hard mask material; and partially etching the first odd-numbered and the first even-numbered conductive lines (130-1, 130-2) using the first and second conductive hard masks (160-1, 160-2). [16] The method of claim 13, further comprising: Forming the first odd-numbered hard mask (110-1) on the first odd-numbered conductive line (130-1) and the first even-numbered hard mask (120-1) on the first even-numbered conductive line (130-2); Forming first dielectric layers (102) on sidewalls of the first odd-numbered and the first even-numbered hard masks (110-1, 120-1) and the first odd-numbered and the first even-numbered conductive lines (130-1, 130-2); and Forming a first intersection region (150-2) corresponding to the first even-numbered conductive line (130-2) and a second intersection region (150-1), which corresponds to the first odd-numbered conductive line (130-1); wherein forming the first cutting area (150-2) further comprises: Forming a first mask material (135) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1); Structuring the first mask material (135) to the first odd-numbered and the first even-numbered hard mask to form a first odd-numbered and a first even-numbered opening (137-1, 137-2), respectively; Etching the first even-numbered hard mask (120-1) selectively with respect to the first odd-numbered hard mask (110-1); and Etching the first even-numbered conductive line (130-2) through the first even-numbered opening (137-2) to form the first cutting region (150-2); and wherein forming the second cutting area (150-1) further comprises: Forming a second mask material (145) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1) and within the first cutting region (150-2); Structuring the second mask material (145) to the first odd-numbered and the first even-numbered hard mask to form a second odd-numbered or a second even-numbered opening (147-1, 147-2); Etching the first odd-numbered hard mask (110-1) selectively with respect to the first even-numbered hard mask (120-1); and Etching the first odd-numbered conductive line (130-1) through the second even-numbered opening (147-2) to form the second cutting region (150-1). [17] The method of claim 16, further comprising: Replacing the first dielectric layers (102) with replacement layers (103); Forming a first sacrificial layer (155-2) within the first cutting region (150-2); and Forming a second sacrificial layer (155-1) within the second cutting region (150-1). [18] The method of claim 17, further comprising performing additional processing comprising: Removing the first and second sacrificial layers (155-1, 155-2) to form openings between the self-aligned upper vias (185); forming second dielectric layers (195) in the openings; and Replacing the replacement layers (103) by third dielectric layers (190). [19] A method according to claim 1, comprising: Forming the first odd-numbered hard mask (110-1) on the first odd-numbered conductive line (130-1) and the first even-numbered hard mask (120-1) on the first even-numbered conductive line (130-2), wherein the first odd-numbered hard mask is formed to have a material different from that of the first even-numbered hard mask to assist in selective etching of the first odd-numbered and first even-numbered hard masks; forming first dielectric layers (102) on sidewalls of the first odd and even hard masks and the first odd and even conductive lines; Forming a first intersection region (150-2) corresponding to the first even-numbered conductive line, and forming a second intersection region (150-1) corresponding to the first odd-numbered conductive line; and Replacing the first dielectric layers (102) with respective replacement layers (103); wherein the first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along a direction of the first odd-numbered and first even-numbered conductive lines. [20] The method of claim 19, further comprising: Forming an additional hard mask material on the recessed odd and recessed even hard masks (110-1, 120-1) and the first and second conductive hard masks (160-1, 160-2); performing a planarization process after forming the additional hard mask material; and Forming a third and a fourth conductive hard mask (180-1, 180-2) based on a patterning of a via not at a line end after the planarization process. [21] The method of claim 20, wherein: forming the third and fourth conductive hard masks (180-1, 180-2) further comprises: forming an opening at a second even-numbered conductive line (130-4) through the additional hard mask material and a second even-numbered hard mask (120-2) formed on the second even-numbered conductive line (130-4); forming an opening to a second odd-numbered conductive line (130-3) through the additional hard mask material and a second odd-numbered hard mask (110-2) formed on the second odd-numbered conductive line (130-3); Forming a second conductive hard mask material within the openings to the second even-numbered and second odd-numbered conductive lines (130-3, 130-4); and performing a planarization process after forming the first and second conductive hard mask materials to form the third and fourth conductive hard masks (180-1, 180-2); and forming the self-aligned upper vias (185) further comprises: Removing the recessed odd and even hard masks (110-1, 120-1) and the additional hard mask material; and partially etching the first odd-numbered and the first even-numbered conductive lines (130-1, 130-2) using the first and second conductive hard masks (160-1, 160-2). [22] The method of claim 19, wherein: forming the first cutting area (150-2) further comprises: Forming a first mask material (135) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1); Structuring the first mask material (135) to the first odd-numbered and the first even-numbered hard mask to form a first odd-numbered and a first even-numbered opening (137-1, 137-2), respectively; Etching the first even-numbered hard mask (120-1) selectively with respect to the first odd-numbered hard mask (110-1); and Etching the first even-numbered conductive line (130-2) through the first even-numbered opening (137-2) to form the first cutting region (150-2); and forming the second cutting area (150-1) further comprises: Forming a second mask material (145) on the first odd-numbered and the first even-numbered hard mask (110-1, 120-1) and within the first cutting region (150-2); Structuring the second mask material (145) to the first odd-numbered and the first even-numbered hard mask to form a second odd-numbered or a second even-numbered opening (147-1, 147-2); Etching the first odd-numbered hard mask (110-1) selectively with respect to the first even-numbered hard mask (120-1); and Etching the first odd-numbered conductive line (130-1) through the second even-numbered opening (147-2) to form the second cutting region (150-1). [23] The method of claim 19, further comprising: Forming a first sacrificial layer (155-2) within the first cutting region (150-2); Forming a second sacrificial layer (155-1) within the second cutting region (150-1); and Perform additional processing which includes: Removing the first and second sacrificial layers (155-1, 155-2) to form openings between the self-aligned upper vias (185); forming second dielectric layers (195) in the openings; and Replacing the replacement layers (103) by third dielectric layers (190). [24] A method according to claim 1, comprising: Forming the first odd-numbered hard mask (110-1) on the first odd-numbered conductive line (130-1) and the first even-numbered hard mask (120-1) on the first even-numbered conductive line (130-2), wherein the first odd-numbered hard mask is formed to have a material different from that of the first even-numbered hard mask to assist in selective etching of the first odd-numbered and first even-numbered hard masks; forming first dielectric layers (102) on sidewalls of the first odd and even hard masks and the first odd and even conductive lines; Forming a first intersection region (150-2) corresponding to the first even-numbered conductive line (130-2) and forming a second intersection region (150-1) corresponding to the first odd-numbered conductive line (130-1); Forming a first sacrificial layer (155-2) within the first cutting region (150-2) and a second sacrificial layer (155-1) within the second cutting region (150-1); and Replacing the first dielectric layers (102) with respective replacement layers (103); wherein the first and second conductive hard masks (160-1, 160-2) are formed to have a semi-circular cross-sectional shape along a direction of the first odd-numbered and first even-numbered lines (130-1, 130-2); and wherein the method further comprises: Forming an additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks (160-1, 160-2); performing a planarization process after forming the additional hard mask material; Forming a third and a fourth conductive hard mask (180-1, 180-2) based on a patterning of a via not at a line end after the planarization process; and Perform additional processing which includes: Removing the first and second sacrificial layers (155-1, 155-2) to form openings between the self-aligned upper vias (185); forming second dielectric layers (195) in the openings; and Replacing the replacement layers (103) by third dielectric layers (190).

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