IMAGE ELEMENT FOR A DISPLAY DEVICE AND DISPLAY DEVICE

Abstract

Image element (1) for a display device (100), comprising - a first and second supply connection (Vdd, Vss), - a light-emitting semiconductor device (B) located between the first and second supply terminals, - a comparator unit with a first and second input (3E1, 3E2) and an output (3A), which is configured to set a voltage at the output (3A) depending on a comparison of a voltage applied to the first and a voltage applied to the second input (3E1, 3E2), - a supply switch (A) configured to control a current flow between the first and second supply terminals (Vdd, Vss) via the light-emitting semiconductor device (B) depending on the voltage applied to the output (3A) of the comparator unit, - a selection input (4) and a data input (5), - a storage element and a control switch configured to supply a data signal (data) provided via the data input (5) to the first input (3E1) of the comparator unit and to store it in the storage element, depending on a selection signal (scan) applied to the selection input (4), wherein the second input (3E2) of the comparator unit is provided for receiving a ramp signal (Vpwm) so that a current flow through the light-emitting semiconductor device (B) can be adjusted depending on the data signal (data), wherein the data signal (data) comprises a predetermined number of digital data bits, the storage element has several data capacitors (Cprog1, Cprog2, Cprog3) corresponding to the predetermined number of digital data bits, and the control switch has several control units (T21, T22, T23) corresponding to the predetermined number of digital data bits, wherein the control units (T21, T22, T23) are configuredEach of the digital data bits is supplied, depending on the selection signal (scan), to an adder connected upstream of the first input (3E1) of the comparator unit and stored in each of the data capacitors (Cprog1, Cprog2, Cprog3), wherein the image element (1) further comprises: , - a reset input (11) which is intended to receive a predefined reset signal (blank), - a ramp capacitor (Cpwm) with a first and second electrode (CpwmE1, CpwmE2), wherein the first electrode (CpwmE1) is coupled to the second input (3E2) of the comparator unit and the second electrode (CpwmE2) is coupled to the second supply terminal (Vss), - a ramp current source (T5) coupled to the first electrode (CpwmE1) of the ramp capacitor (Cpwm) and configured to charge the ramp capacitor (Cpwm), and - a ramp transistor (T3) with a control electrode (T3S), discharge electrode (T3A) and source electrode (T3Q), which is coupled via its discharge electrode (T3A) to the second supply terminal (Vss), via its control electrode (T3S) to the reset input (11) and via its source electrode (T3Q) to the first electrode (CpwmE1) of the ramp capacitor (Cpwm), so that depending on the specified reset signal (blank) the ramp capacitor (Cpwm) can be discharged and a ramp-like curve of the voltage applied to the second input (3E2) of the comparator unit can be set as a ramp signal (Vpwm).

Description

[0001] The invention relates to an image element and a display device with a plurality of image elements.

[0002] Conventional pixel control systems for display devices operate in a cross-matrix arrangement and use current dimming to control brightness by changing the intensity of the light emitted by the pixels. This is also known as analog dimming. It is used, for example, for OLEDs and LCDs. Such a control method is disadvantageous for LED displays due to its negative impact on color accuracy.

[0003] Document US 2005 / 0067968 A1 describes a device for generating a ramp voltage. The device includes a circuit for generating a first ramp voltage, from which a plurality of phase-shifted ramp voltages are derived, and a control circuit. The first ramp signal is generated by a digital-to-analog converter. A circuit for generating the plurality of ramp voltages comprises a plurality of voltage-generating circuit sections connected in parallel to a voltage input terminal to which the first ramp voltage is applied. Each voltage-generating circuit section comprises a capacitor, an operational amplifier, a first switch, a second switch, and a third switch. The control circuit turns on the third switches, shifting the switching time of each third switch from the off to the on state. The video elements receive the ramp signals.

[0004] Document US 2003 / 0085862 A1 describes a display device with a plurality of image elements. Each image element comprises an image element electrode, a plurality of capacitance elements for storing a charge corresponding to each bit of a digital image signal, and a charge transfer transistor for delivering the charge stored in the capacitance elements to the image element electrode depending on a timing signal.

[0005] The task is to provide an image element for a display device as well as a display device with an alternative control method.

[0006] For this purpose, an image element and a display device are specified according to the independent patent claims.

[0007] According to a first aspect, the invention relates to a picture element for a display device. A picture element is defined as an electronic subunit of the display device that is configured to display a pixel or a subpixel of the display device. In particular, in the case of a polychromatic display device, individual pixels can be formed by several differently colored subpixels, for example, by a red subpixel, a green subpixel, and a blue subpixel. Such a combination is hereinafter also referred to as an RGB triplet.

[0008] In one embodiment, the image element has a first supply connection. This could be, for example, an electrical connection through which a predetermined operating voltage or current is supplied to the image element. The image element also has a second supply connection. This second supply connection could, for example, be a ground connection. However, the second supply connection could also be an electrical connection for supplying a predetermined operating voltage or current.

[0009] In one embodiment, the image element comprises a light-emitting semiconductor component arranged between the first and second supply terminals. The semiconductor component is, in particular, a light-emitting diode (LED). For electrical supply, the semiconductor component is coupled to the first and second supply terminals, particularly indirectly. Specifically, it is provided that a driver unit is connected upstream of the semiconductor component for each image element to control the current flow.

[0010] In one embodiment, the image element comprises a comparator unit with a first input, a second input, and an output. The comparator unit is configured to set a voltage at its output based on a comparison of the voltage applied to the first input of the comparator unit with the voltage applied to the second input of the comparator unit. In particular, the comparator unit can include or be configured as a comparator or a 1-bit analog-to-digital converter. In this context, the comparator unit can, in particular, have additional inputs for power supply, which are connected, for example, to the first and second power supply terminals. The first input is, for example, a non-inverting input. The second input is, for example, an inverting input.In particular, the comparator can be configured to output the voltage applied to the first supply terminal if the voltage applied to the first input is greater than the voltage applied to the second input, and otherwise to output the voltage applied to the second supply terminal.

[0011] In one embodiment, the image element includes a power switch configured to control the current flow between the first and second power supply terminals through the light-emitting semiconductor device, depending on the voltage applied to the output of the comparator unit. The power switch is, for example, a transistor. Specifically, the power switch is configured to allow current flow through the semiconductor device when a predetermined threshold of the voltage applied to the output of the comparator unit is exceeded, and to block current flow otherwise.

[0012] In one embodiment, the image element has a selection input and a data input. Signals provided via the selection input can also be referred to as a selection signal, "select," or "scan"; in this context, the selection input can be provided for connection to a column line of the display device. Signals provided via the data input can also be referred to as a data signal or "data"; in this context, the data input can be provided for connection to a row line of the display device.

[0013] In one embodiment, the image element comprises a storage element and a control switch. The control switch is configured to feed a data signal provided via the data input to the first input of the comparator unit, depending on a selection signal present at the selection input, and to store it in the storage element. The selection signal is, in particular, a predefined voltage pulse for switching the control switch. The data signal is, in particular, a predefined voltage that corresponds to a brightness level of the semiconductor device during normal light-emitting operation. The storage element is, for example, a capacitor configured to maintain an applied voltage for a predefined duration, such as the time until the next image is to be displayed on the display device (e.g., the reciprocal of the refresh rate of the display device).The control switch is, for example, a transistor. Specifically, the control switch is configured to allow the voltage representing the data signal to be supplied to the first input of the comparator and the memory element when a predetermined threshold of the voltage applied to the selection input (representing the selection signal) is exceeded, and to block it otherwise. In other words, the memory element and the control switch form a so-called "sample-and-hold" unit.

[0014] In one embodiment, the second input of the comparator unit is provided for receiving a ramp signal. For example, the ramp signal can be generated externally with respect to the image element and supplied to it, or it can be generated by an internal circuit within the image element. The ramp signal is, in particular, a predefined, periodic voltage waveform. For example, the ramp signal could be a sawtooth signal, especially one with a linearly increasing sawtooth. Alternatively, the periodic increase can also be non-linear, such as logarithmic or exponential. In this context, "periodic" means that a sawtooth- or ramp-like signal component, with each rise and fall, repeats itself identically or substantially identically within a predefined time (period).

[0015] The ramp signal is specifically chosen such that, when compared to the voltage representing the data signal, a pulse-width modulated (PWM) voltage waveform is generated at the output of the comparator unit, the pulse width of which depends on the data signal, for example, the amplitude of an analog data signal. In particular, the current flow through the light-emitting semiconductor device can thus be adjusted depending on the data signal, specifically by means of the PWM voltage waveform.

[0016] In this context, the period of the ramp signal is chosen to be many times shorter than the time interval between two successive "scan" voltage pulses, e.g., by a factor of 2-100, preferably by a factor of 50. Accordingly, the period is also chosen to be at least 1 to many times shorter than the refresh rate of the display device.

[0017] Advantageously, the proposed image element can generate an analog PWM signal at the pixel or sub-pixel level. This requires only a low integration depth within the image element, while a complex and precise circuit can be located outside of it.

[0018] In one embodiment, the data signal comprises a predetermined number of digital data bits. The storage element has several data capacitors corresponding to the predetermined number of digital data bits. The control switch has several control units corresponding to the predetermined number of digital data bits, each configured to feed one of the digital data bits, depending on the selection signal, to an adder connected upstream of the first input of the comparator unit and to store it in one of the data capacitors.

[0019] The digital data bits represent a predefined range of values, for example [0;7] with 3 data bits, each representing a gradation of the brightness of the semiconductor device. The individual data bits are supplied to the image element sequentially, with the selection signal comprising a number N of pulses corresponding to the predefined number N of digital data bits. Alternatively, a delay element is connected upstream of each control unit, delaying a single pulse of the selection signal between successive control units according to the temporal sequence of the data bits. The data capacitors can have different capacitances in this context to represent a multiplier of the data bit value.For example, with 3 data bits, the first data capacitor could have 4 times the capacitance of the third data capacitor, and the second data capacitor could have 2 times the capacitance of the third data capacitor. In this context, the control circuitry of the semiconductor device can be designed such that the charge of each data capacitor remains constant. Alternatively, it is also conceivable to connect a corresponding multiplier to each adder.

[0020] This allows digital data signals to be advantageously used to generate the analog PWM signal at the pixel or sub-pixel level. In this context, the ramp signal is primarily in analog form.

[0021] In one embodiment, the semiconductor device is configured as an LED and has a first electrode and a second electrode. This can be, in particular, a so-called microLED. In one embodiment, the comparison unit is configured as a comparator. In another embodiment, the supply switch is configured as a supply transistor. This is exemplified by a thin-film transistor. In one embodiment, the control switch comprises a control transistor. This is also exemplified by a thin-film transistor. In one embodiment, both the supply transistor and the control transistor each have a control electrode, a drain electrode, and a source electrode. Here and in the following, a drain electrode is understood to be the drain terminal of a transistor.Similarly, the source electrode refers to a source terminal and the control electrode to a gate terminal of the transistor. In one embodiment, the storage element comprises a data capacitor with a first electrode and a second electrode.

[0022] In one embodiment, the supply transistor is coupled to the first supply terminal via its source electrode. Furthermore, the supply transistor is coupled to the comparator output via its control electrode. Additionally, the supply transistor is coupled to the first electrode of the LED via its discharge electrode. The LED is coupled to the second supply terminal via its second electrode. The control transistor is coupled to the data input via its source electrode. Furthermore, the control transistor is coupled to the select input via its control electrode. Finally, the control transistor is coupled to the first input of the comparator and the first electrode of the data capacitor via its discharge electrode. The second electrode of the data capacitor is coupled to the second supply terminal.

[0023] The components of the image element connected upstream of the LED according to this design are collectively referred to here and in the following as the driver unit. Advantageously, the aforementioned driver unit enables the (sub-)pixel-internal generation of a PWM signal for operating the LED. An expensive, complex, or space-consuming microcontroller that could be used in this context is merely optional.

[0024] In one embodiment, the image element has a ramp input for receiving an externally generated ramp signal and coupled to the second input of the comparator unit. Advantageously, the same ramp signal can be supplied to several image elements of a display device, in particular to all image elements of the display device, so that all image elements are based on the same reference value, the installation space for the image elements can be kept compact, and components for generating the ramp signal can be eliminated.

[0025] In one embodiment, the image element has a reset input for receiving a predefined reset signal. The image element also includes a ramp capacitor with a first and second electrode, the first electrode being connected to the second input of the comparator and the second electrode to the second supply terminal. Furthermore, the image element includes a ramp current source connected to the first electrode of the ramp capacitor and configured to charge the ramp capacitor. The image element also includes a ramp transistor with a control electrode, a discharge electrode, and a source electrode. The ramp transistor is connected to the second supply terminal via its discharge electrode. Additionally, the ramp transistor is connected to the reset input via its control electrode.Furthermore, the ramp transistor is coupled to the first electrode of the ramp capacitor via its source electrode.

[0026] The ramp transistor is specifically configured to allow current flow between the first electrode of the ramp capacitor and the second supply terminal when a predetermined threshold voltage representing the specified reset signal is exceeded, and to block current flow otherwise. If the ramp transistor allows current flow, the ramp capacitor can be discharged through the ramp transistor; otherwise, the ramp capacitor can be charged by the ramp current source. Depending on the charge state of the ramp capacitor, this results in a voltage controllable by the reset signal, which is applied as a ramp signal to the second input of the comparator unit. The reset signal is specifically chosen to produce a ramp-like voltage waveform at the second input of the comparator unit.In particular, the reset signal can be a pulse signal whose period matches that of the ramp signal.

[0027] Advantageously, in addition to the analog PWM signal, an analog ramp signal can also be generated to create the PWM signal at the pixel or sub-pixel level.

[0028] In one embodiment, the image element includes a power supply source arranged between the first supply terminal and the power switch, configured to provide current for operating the light-emitting semiconductor device. This power supply source can be, for example, a transistor connected to the first supply terminal via its source electrode and to the power switch via its output electrode, or connected to the second electrode of the light-emitting semiconductor device via its source electrode. The second electrode of the second electrode is connected to the first supply terminal via its first electrode and to the power switch via its output electrode. A control electrode of this transistor can, for example, serve as the control input of the power supply source.

[0029] In one embodiment, the image element has a dimming input. The supply current source has a control input that is coupled to the dimming input. Depending on a voltage applied to the dimming input as a dimming signal, the supply current source is configured to control the amplitude of the current flow between the first and second supply terminals via the light-emitting semiconductor device. In particular, the same dimming signal can be supplied to several image elements, for example, to image elements that each form a sub-pixel of a pixel, especially an RGB triplet, or to all image elements of a column or row of the display device, or to all image elements of the display device in order to implement global dimming of several image elements of the display device. In an alternative embodiment, the supply current source can also be combined with the supply transistor, i.e.,During the on-time, the supply transistor regulates the current flow (e.g., in the saturation region); during the off-time, it is non-conducting. A high level at the output of the comparator then corresponds to a voltage that, via the supply transistor, induces a corresponding current in the LED.

[0030] In one embodiment, the image element has a dimming input and a further comparator unit with a first and second input and an output. The first input of the further comparator unit is coupled to the dimming input. The output of the comparator unit is coupled to the second input of the further comparator unit. The further comparator unit is configured to adjust a voltage at its output depending on a comparison of the voltages applied to the first and second inputs, so that, depending on the voltage applied as a dimming signal at the dimming input, the amplitude of the voltage at the output of the comparator unit can be adjusted.In particular, this allows the amplitude of the voltage at the output of the further comparator unit to be set to an amplitude of the dimming signal, while at the same time the pulse width of the signal at the output of the comparator unit can be maintained as the pulse width of the signal at the output of the further comparator unit.

[0031] In one embodiment, the image element comprises a dimming capacitor with a first and second electrode. The first electrode of the dimming capacitor is coupled to the control input of the power supply. The second electrode of the dimming capacitor is coupled to the second supply terminal. Furthermore, the image element comprises a dimming transistor with a control electrode, a discharge electrode, and a source electrode, which is coupled to the dimming input via its source electrode. The dimming transistor is also coupled to the selection input via its control electrode and to the first electrode of the dimming capacitor via its discharge electrode. The dimming signal, or a voltage representing the dimming signal, can thus be fed to the control input of the power supply and stored in the dimming capacitor, depending on the selection signal or the voltage representing the selection signal applied to the selection input.In other words, the dimming capacitor and the dimming transistor form a so-called "sample-and-hold" unit. This advantageously allows for individual dimming ("local dimming") of individual image elements.

[0032] If the same dimming signal is to be supplied to several image elements in order to enable global dimming of several image elements of a display device, in further embodiments a single sample-and-hold unit can be assigned to these several image elements and coupled to the respective supply current source.

[0033] In one embodiment, the image element has a set input for receiving a reference voltage. The supply current source is configured as the first compensation transistor. The ramp current source is configured as the second compensation transistor. Both the first and second compensation transistors have a control electrode, a discharge electrode, and a source electrode. The first compensation transistor is coupled to the first supply terminal via its source electrode. Furthermore, the first compensation transistor is coupled to the set input via its control electrode. Additionally, the first compensation transistor is coupled to the source electrode of the supply transistor via its discharge electrode. The second compensation transistor is coupled to the first supply terminal via its source electrode. Furthermore, the second compensation transistor is coupled to the set input via its control electrode.Furthermore, the second compensation transistor is coupled to the source electrode of the ramp transistor via its outflow electrode.

[0034] The first and second compensation transistors are arranged in close proximity to each other, particularly to minimize mismatch errors. Preferably, the two compensation transistors are configured according to the common-centroid layout to compensate for gradients in the gate oxide. In this context, reference is made to the work of Daniel Payne in "A Review of an Analog Layout Tool called HiPer DevGen" and Nurahmad Omar in "Automated Layout Synthesis Tool for Op-Amp," the full content of which is hereby incorporated by reference.

[0035] In particular, the two compensation transistors are manufactured using the same process, for example on the same wafer, and thus exhibit identical properties due to the manufacturing process and are subject to identical environmental influences due to their arrangement. Therefore, in this configuration, a deviation in the first compensation transistor, such as in the current flow for operating the corresponding LED, compared to other image elements of the display device (e.g., due to inaccuracies in layer thickness), advantageously leads to a corresponding deviation in the second compensation transistor. This configuration allows such a deviation to be compensated analogously, i.e.,The signal is not discretized and is fed back to the ramp capacitor, so that in the case of an increased charging current, a steeper charging curve results, thus a lower duty cycle of the PWM signal and consequently a reduced brightness of the LED, and thus mismatch errors between individual image elements can be compensated without additional calibration.

[0036] In one embodiment, the image element has a dimming terminal. The ramp current source is designed as a dimming transistor with a control electrode, a discharge electrode, and a source electrode. The dimming transistor is coupled to the first supply terminal via its source electrode. Furthermore, the dimming transistor is coupled to the dimming terminal via its control electrode. Finally, the dimming transistor is coupled to the source electrode of the ramp transistor via its discharge electrode.

[0037] By wiring it according to this configuration, the voltage applied to the ramp capacitor for charging the ramp capacitor can be controlled depending on the voltage applied to the dimming terminal. The voltage applied to the dimming terminal can be supplied to the image element, for example, by a dimming signal different from the previously mentioned dimming signal. Depending on this dimming signal, it is particularly possible to control the duty cycle of the PWM signal. Analogous to previous configurations, the same dimming signal can be supplied to multiple image elements to implement global dimming of several image elements of the display device.

[0038] In one embodiment, the image element has a calibration input. Furthermore, the image element has a calibration transistor with a control electrode, a return electrode, and a source electrode. The calibration transistor is coupled to the calibration input via its source electrode. Additionally, the calibration transistor is coupled to the selection input via its control electrode. Furthermore, the calibration transistor is coupled to the dimming terminal via its return electrode. The image element also has a calibration capacitor with a first electrode and a second electrode. The calibration capacitor is coupled to the dimming terminal via its first electrode. Furthermore, the calibration capacitor is coupled to the second supply terminal via its second electrode.By wiring it according to this configuration, a calibration signal present at the calibration input can be supplied to the dimming terminal, depending on the selection signal applied at the selection input. This calibration signal can be stored in the calibration capacitor. Specifically, the calibration transistor is configured to allow the supply of the voltage representing the calibration signal to the dimming terminal and the calibration capacitor when a predetermined threshold value of the voltage at the selection input (representing the selection signal) is exceeded, and to block it otherwise. In other words, the calibration capacitor and the calibration transistor form a so-called "sample-and-hold" unit.

[0039] According to a second aspect, the invention relates to a display device. The display device is, in particular, a MicroLED display or another display based on active matrix technology.

[0040] In one embodiment, the display device has a multitude of image elements according to the first aspect. The image elements are arranged in a matrix-like manner in rows and columns.

[0041] The display device also has a plurality of column lines, each connected to the respective selection input of the image elements in one of the columns. Furthermore, the display device has a plurality of row lines, each connected to the respective data input of the image elements in one of the rows.

[0042] Furthermore, the display device includes a control device connected to the multitude of column lines and capable of generating a pulse as a selection signal for a selected column line from among the multitude of column lines. The control device is also connected to the multitude of row lines and capable of generating a data signal for a selected row line from among the multitude of row lines.

[0043] In one embodiment, the display device has a plurality of ramp lines, each connected to the ramp input of one of the image elements. The control device is connected to the plurality of ramp lines and is capable of generating a ramp signal externally for the plurality of ramp lines with respect to the image elements. In particular, the same ramp signal can be supplied to several image elements, for example, all image elements of a column or row of the display device, all image elements of a portion such as a quadrant of the display device, or all image elements of the display device.

[0044] In an alternative embodiment, the display device has a plurality of reset lines, each connected to the reset input of one of the image elements. The control device is connected to the plurality of reset lines and is capable of generating a pulse as a predefined reset signal for a selected reset line from the plurality of reset lines. In particular, the same reset signal can be supplied to several image elements, for example, all image elements of a column or row of the display device, all image elements of a portion such as a quadrant of the display device, or all image elements of the display device.

[0045] In one embodiment, the display device has a plurality of first dimming lines, each connected to the dimming input of one of the image elements. Alternatively, the first dimming lines are each connected to the dimming input of one of the image elements of a portion, such as a quadrant, of the display device, or one of the image elements of a row or column of the display device. Alternatively, the first dimming lines are connected to the dimming input of one of the image elements of an RGB triplet of the display device. The control device is connected to the plurality of first dimming lines and is capable of generating a first dimming signal for a selected first dimming line from the plurality of first dimming lines.

[0046] Alternatively or additionally, in one embodiment, the display device has a plurality of second dimming lines, each connected to the dimming terminal of one of the image elements. The control device is connected to the plurality of second dimming lines and is capable of generating a second dimming signal for a selected second dimming line from the plurality of second dimming lines.

[0047] Alternatively or additionally, in one embodiment, the display device has a plurality of set lines, each connected to the set input of one of the image elements. Furthermore, the display device has a reference voltage source connected to the plurality of set lines and suitable for providing a reference voltage for the plurality of set lines.

[0048] Alternatively or additionally, in one embodiment, the display device has a plurality of calibration lines, each connected to the calibration input of one of the image elements. The control device is connected to the plurality of calibration lines and is capable of generating a calibration signal for a selected calibration line from the plurality of calibration lines.

[0049] In one embodiment, the display device comprises a plurality of first delay elements, each coupled to the column lines of two consecutive columns and configured to provide the selection signal at the respective second column line with a predetermined first time duration τ1 compared to the respective first column line. Furthermore, the display device comprises a plurality of second delay elements, each coupled to the ramp lines of two consecutive columns and configured to provide the ramp signal at the respective second ramp line with a predetermined second time duration τ2 compared to the respective first ramp line. The predetermined first time duration τ1 is in a predetermined ratio to the predetermined second time duration τ2.

[0050] In one embodiment, the specified ratio τ1 / τ2 = 1. In other words, the ramp signal and the selection signal are synchronous with each other.

[0051] Further advantageous embodiments and developments of the image element and the display device result from the exemplary embodiments described below in conjunction with the figures.

[0052] They show: Fig. 1 a first embodiment of an image element for a display device, Fig. 2. Exemplary detailed view of the image element according to Fig. 1, Fig. 3 exemplary signal waveforms during the intended operation of the image element according to Fig. 1, Fig. 4 a second embodiment of an image element for a display device, Fig. 5 a signal profile in the intended operation of the image element 1 according to Fig. 4, Fig. 6 a third embodiment of an image element for a display device, Fig. 7. A signal curve when operating an LED of the image element according to Fig. 6, Fig. 8 a fourth embodiment of an image element for a display device, Fig. 9-11 Signal overview in the intended operation of a picture element for a display device according to a fifth and sixth embodiment, Fig. 12 a seventh embodiment of an image element for a display device, Fig. 13 an eighth embodiment of an image element for a display device, Fig. 14 a ninth embodiment of an image element for a display device, Fig. 15 an eleventh embodiment of an image element for a display device, Fig. 16 a twelfth embodiment of an image element for a display device, Fig. 17 an exemplary display device.

[0053] Identical, similar, or similarly functioning elements are marked with the same reference symbols in the figures. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements, particularly layer thicknesses, may be exaggerated for clarity and / or better understanding.

[0054] A display device with active matrix control can, for example, be based on microLEDs, where each pixel of the display device corresponds to a cell with three microLEDs (sub-pixels). Each microLED consists of a red, a green, and a blue chip. A circuit with active components in the form of thin-film transistors (TFTs) is assigned to each of these sub-pixels to regulate the current through the respective microLED. Such a unit is referred to here and in the following as the image element of the display device. To adjust the brightness of individual sub-pixels ("dimming"), the current can be controlled analogously via a programming voltage. Since there is a dependency between color coordinates and current in LEDs, such purely analog operation can lead to changes in the white point (color coordinates / color gamut). To avoid this problem, the brightness of the sub-pixels can be adjusted using pulse-width modulation (PWM).This is referred to as digital operation. This pulse-width modulation can be generated by repeatedly programming the pixel cells. A sub-pixel is then only powered with the nominal current for a certain period of time and remains off for the rest of the time. The viewer perceives the average brightness over time as a static brightness of the sub-pixel.

[0055] In this process, pulse-width modulation is generated outside the display device using a repeating programming sequence. However, to achieve a color depth of 8 bits per color (24 bits total, standard) with digital operation, switching times are required for high-resolution displays with a refresh rate of at least 60 Hz that cannot be achieved with current TFT technology.

[0056] As an alternative to generating pulse-width modulation via the external programming voltage, a microcontroller can be connected to one or more LEDs within a pixel to control their operation. However, this is associated with high costs and enormous space requirements, especially if such a microcontroller is assigned to each sub-pixel of the display device.

[0057] The following describes a pixel and a display device that enable the pixel-precise generation of pulse-width modulation (PWM) for (sub)pixels of an active-matrix display device. In particular, it is proposed to generate an analog PWM signal within a pixel to efficiently achieve high dynamic range with respect to bit depths, grayscale levels, and dimming, while maintaining a low integration depth within the pixel. A complex and precise circuit for controlling the individual pixels can be located outside of the pixels.

[0058] Fig. Figure 1 shows a first embodiment of an image element 1 for a display device 100.

[0059] A picture element 1 with a light-emitting semiconductor device B in a matrix arrangement of a display device 100 (cf. Fig. 17) is controlled via a combination of a selection signal scan and a data signal data. The selection signal scan is, for example, a pulse with a pulse width of 10 ns, which is generated for each of the pixels 1 of a display device 100 and is repeated after 16 ms (this corresponds to the frame rate of the display device 100). The data signal is, for example, an analog grayscale value provided by a digital-to-analog converter.

[0060] The display device 100 has a plurality of image elements 1, each arranged in rows x and columns y ( Fig. 17). By means of a control device 12, which is arranged externally with respect to the individual image elements 1, the selection signal scan is provided to the image elements 1 via a plurality of column lines y1 to yn, each connected to a corresponding selection input 4, and the data signal data is provided to the image elements 1 via a plurality of row lines x1 to xm, each connected to a corresponding data input 5 (supply connections are not shown in detail).

[0061] Image element 1 is assigned a memory for an analog voltage signal, the data signal data. Instead of converting this analog voltage signal into an analog current value, image element 1 generates a pulse-width modulated current flow Iled depending on the analog voltage signal, the amplitude of which can additionally be controlled analogously (during the on-time).

[0062] For this purpose, a unit 1S is assigned to image element 1 ( Fig. 2), which includes a circuit with active components, e.g., in the form of thin-film transistors (TFTs). This can, in particular, be a microcontroller (µIC) or a TFT circuit of the active matrix backplane of the display device 100. The image element 1 has a first supply terminal Vdd and a second supply terminal Vss, each of which can provide a supply voltage or a supply current for operating the semiconductor device B. A supply switch A can be connected upstream of the semiconductor device B and can control the current flow Iled depending on a PWM signal PWM generated by the unit 1S. Based on Fig. Figure 2 shows two exemplary detailed views of image element 1 according to Fig. 1 shown.

[0063] As shown on the left, the power switch A is implemented as an example using a PMOS transistor and is connected upstream of the semiconductor device B. A first supply voltage is provided via the first supply terminal Vdd, while the second supply terminal Vss is connected to ground or, for example, a negative operating voltage of the semiconductor device B. The first supply terminal Vdd is connected to the power switch A via a power supply current source T4. The power supply current source T4 is, for example, controllable, implemented as a PMOS transistor, and configured to provide a current at the input of the power switch A depending on a dimming signal dim. Depending on the PWM signal PWM, the current flow Iled is pulse-width modulated, so that the brightness of the semiconductor device B can be adjusted. This setup can also be referred to as a "common cathode".

[0064] In the diagram on the right, ground is connected to the second supply terminal. The first supply terminal, Vdd, provides, for example, the first supply voltage or a positive operating voltage for the semiconductor device B. The first supply terminal, Vdd, is connected via the semiconductor device B to the supply current source T4, which is connected downstream of the supply switch A. The supply current source T4 and the supply switch A are shown here as examples of NMOS transistors. This configuration can also be described as a "common anode".

[0065] The center shows Fig. 2. One possible implementation of unit 1S. Via a selection input 4 (see below). Fig. 1) The selection signal scan, the data signal data via a data input 5, and a ramp signal Vpwm with a sawtooth-like voltage waveform are provided to unit 1S. The data signal data is applied to a switch T2, which, depending on the selection signal scan, stores the data signal in a data capacitor Cprog (sample-and-hold) and feeds it to the first input 3E1 of a comparator unit. The comparator unit is implemented as a comparator 3, flip-flop, or similar device. The ramp signal Vpwm is applied to a second input 3E2 of the comparator unit. Depending on the amplitude of the data signal data and the slope and pulse width of the ramp signal Vpwm, the pulse width of the PWM signal PWM at output 3A of the comparator unit is determined.

[0066] The ramp signal Vpwm is, for example, a voltage output by a digital-to-analog converter that periodically exhibits a logarithmic, exponential, or linear slope. A maximum and minimum voltage of the ramp signal Vpwm define, for example, a dimming range of the semiconductor component B, i.e., a minimum and maximum pulse width of the PWM signal PWM. The ramp signal Vpwm exhibits, for example, an integer multiple of sawtooth waves for each frame of the display device 100; in other words, the reciprocal of the frame rate of the display device 100 corresponds to N times the period of the ramp signal Vpwm. Specifically, the ramp signal Vpwm exhibits exactly one sawtooth wave for each (sub)pixel of the display device 100 per frame. Based on Fig. Figure 3 is an example sawtooth waveform of the ramp signal Vpwm and an analog grayscale value of the data signal data in the intended operation of the image element 1 according to Fig. Figure 1 shows the time t. The ramp signal Vpwm is synchronous with the data signal data, meaning that a ramp start always occurs, for example, after the pulse of the selection signal scan has finished and the corresponding analog grayscale value of the data signal data has been loaded into the data capacitor Cprog.

[0067] The ramp signal Vpwm exhibits a non-linear slope as an example. Depending on the configuration, the semiconductor device B is in a switched-on state (duration ton) as long as a voltage V represented by the data signal data is greater than a voltage V represented by the ramp signal Vpwm, and otherwise in a switched-off state (duration toff), or vice versa.

[0068] As on the left in Fig. As shown in Figure 3, the ramp signal Vpwm and the data signal data can cover the same voltage range or, to improve resolution, cover different voltage ranges, for example in the low nanosecond range (in Fig. 3 shown on the right). In this context, various combinations of ramp signal Vpwm and data signal data are particularly conceivable: For example, a linear ramp signal Vpwm can be combined with a linear data signal data, a non-linear ramp signal Vpwm with a linear data signal data, or a linear ramp signal Vpwm with a non-linear data signal data.

[0069] In the first embodiment, the ramp signal Vpwm is provided to several image elements 1 of a display device 100, in particular to all image elements 1 of a quadrant of the display device 100 or to all image elements 1 of the display device 100. Such an approach is also referred to here and in the following as "global". As shown by Fig. As shown in Figure 17, the control device 12 can be connected in this context to a plurality of supply lines z1 to zn with a corresponding ramp input 6 of the image elements 1 in order to provide the same ramp signal Vpwm. The individual supply lines z1-zn are coupled, for example, via delay elements D2, which allow a delay of approximately exactly one period. Synchronously, the column lines y1-yn are coupled, for example, via delay elements D1, which allow the same delay. Moreover, the delay elements D1 and D2 can serve as amplifiers to maintain the integrity of the individual signals. Advantageously, a global ramp signal Vpwm enables dynamic adjustment of the brightness of the display device 100 via the pulse width of the respective PWM signal PWM for the display device 100 as a whole or for quadrants.

[0070] Based on the Fig. Figure 4 shows a second embodiment of an image element 1 for a display device 100. In contrast to the first embodiment, here the ramp signal Vpwm is generated by a circuit internal to the image element instead of a global ramp signal Vpwm. According to the image element 1 Fig. In this context, 1 is instead of ramp entrance 6 ( Fig. 1) for example a reset input 11 ( Fig. 4) assigned, via which a blank reset signal is provided.

[0071] The data signal `data` is stored in the data capacitor `Cprog`. Switch T2 is implemented here as a control transistor T2, whose source electrode T2Q is connected to data input 5, its control electrode T2S to selection input 4, and its output electrode to the first electrode CprogE1 of the data capacitor `Cprog`, which is coupled to the second supply terminal Vss via its second electrode CprogE2. The first electrode CprogE1 is also coupled to the first input 3E1 of a comparator 3, at whose output 3A the PWM signal PWM is output.The PWM signal PWM is supplied to a control electrode T1S of a supply transistor T1, which is connected via its source electrode T1Q to the first supply terminal Vdd via a supply current source T4 and via its output electrode T1A to a first electrode 2E1 of an LED 2, which is connected via its second electrode 2E2 to the second supply terminal Vss.

[0072] A power source T5, connected to the first supply terminal Vdd, is coupled to the first electrode CpwmE1 of a ramp capacitor Cpwm and charges it with a constant charging current Icharge. The ramp capacitor Cpwm is connected to the second supply terminal Vss via its second electrode CpwmE2. The constant charging current Icharge generates a linear increase in the voltage Vpwm across the ramp capacitor Cpwm over time t. The comparator 3 is coupled via its second input 3E2 to the first electrode CpwmE1 of the ramp capacitor Cpwm, compares the voltage Vprog applied to the data capacitor Cprog with the voltage Vpwm applied to the ramp capacitor Cpwm and switches its output 3A to “low” when the same voltage is applied to the ramp capacitor Cpwm as to the data capacitor Cprog.After one period T, the ramp capacitor Cpwm is discharged via the reset signal, and the process begins again. In this context, the reset input 11 is coupled to a control electrode T3S of a ramp transistor T3, which is coupled via its discharge electrode T3A to the second supply terminal Vss and via its source electrode to the first electrode CpwmE1 of the ramp capacitor Cpwm.

[0073] Fig. Figure 5 shows a signal waveform during the intended operation of image element 1 according to Fig. 4. Initially, the ramp capacitor Cpwm is active. The voltage Vprog (target gray value) represented by the data signal data is stored in the data capacitor Cprog and is greater than the voltage Vpwm (ramp signal) applied to the ramp capacitor Cpwm. The output 3A of comparator 3 is therefore at a "high" level, and the control transistor T1 (e.g., NMOS) switches on. Subsequently, the ramp capacitor Cpwm charges. After time ton1, the ramp signal Vpwm exceeds the voltage Vprog represented by the data signal data, and the output 3A assumes a "low" level, so that the control transistor T1 blocks the current flow Iled. After one period T has elapsed, a pulse is provided as a blank reset signal, so that the ramp capacitor Cpwm discharges and the process (with a changed data signal data and a correspondingly different ton2) can be restarted.

[0074] Based on Fig. Figure 6 shows a third embodiment of an image element 1 for a display device 100, which differs from the second embodiment in that the supply current source T4 is controllable: The amplitude of the current flow Iled across LED 2 during the on-time ton is determined externally by a global dimming signal dim via an adjustable current source T4. In this context, the image element 1 has an additional dimming input 7. The dimming signal dim can, for example, adjust several image elements 1 simultaneously, such as a pixel with 3 subpixels (RGB), several pixels at once, such as an entire row x, an entire column y, or the entire display device 100. The current source T4 can also be combined with the control transistor T1; that is, during the on-time ton, the control transistor T1 regulates the current (e.g., in the saturation range), while during the off-time toff, it is non-conducting.

[0075] Fig. Figure 7 shows an exemplary current flow Iled across LED 2 in the third embodiment. The amplitude L of the current Iled is globally defined by the dimming signal dim. The duty cycle of the PWM signal PWM, or the pulse width DC of the current Iled, is defined pixel-level by the PWM signal PWM, the ramp signal Cpwm, and the data signal data.

[0076] Fig. Figure 8 shows a fourth embodiment of an image element 1 for a display device 100, which differs from the third embodiment in that a dimming capacitor Cdim and a dimming transistor T6 are connected upstream of the controllable supply current source T4. The dimming capacitor Cdim is connected to the input side of the current source T4 via its first electrode CdimE1 and to the second supply terminal Vss via its second electrode CdimE2. The dimming transistor T6 is connected to the first electrode CdimE1 of the dimming capacitor Cdim via its discharge electrode T6A, to the selection input 4 via its control electrode T6S, and to the dimming input 7 via its source electrode T6Q.

[0077] The value of the current flow Iled through LED 2 during the on-time ton is pre-programmed by the dimming signal dim via the adjustable supply current source T4. In contrast to the global dimming signal according to the third embodiment, the dimming signal dim can be programmed via a separate data line (column) and stored in the dimming capacitor Cdim. In one embodiment, several (sub-)pixels can share such a dimming signal dim or a dimming capacitor Cdim. For example, an RGB pixel shares a dimming capacitor Cdim, or a group of RGB pixels shares a dimming capacitor Cdim or a data signal dim.

[0078] According to a fifth embodiment, a nominal level of the current flow Iled across the LED 2 (hereinafter referred to as Iled,nominal) is set such that the nominal brightness of the LED 2 is already achieved with a duty cycle of less than 100% (see Fig. 9 and Fig. 10) In other words, to operate, for example, a nominal TFT backplane with a nominal µLED at nominal brightness, the amplitude Iled,nominal is chosen so high that the LED 2 is not continuously switched on. This means that in light-emitting operation, to achieve the nominal brightness of the LED 2, the on-time ton,nominal is smaller than the maximum possible on-time ton,max ( Fig. 9) This leaves a "buffer" `ton,buffer` that can be used to correct excessively dim LEDs (or pixel circuits with insufficient current) by means of pulse-width modulation, thus enabling error compensation or white balance. For example, `ton,buffer` corresponds to a fraction of the period T of 5%, 10%, or 15%. The maximum on-time `ton,max` corresponds to the period T of the pulse-width modulation and thus a duty cycle of 100%.

[0079] As in Fig. As shown in Figure 10, a proportion of Vprog,buffer above a nominal voltage Vprog,nominal of the voltage Vprog represented by the data signal data can be used to set the duty cycle of the pulse width modulation greater than ton,nominal (i.e., to use ton,buffer) and thereby, for example, to make an LED that is too dark brighter.

[0080] Alternatively or additionally, a sixth embodiment can be described as shown in the following example. Fig. Figure 11 shows that calibration is achieved by adjusting the charging current Icharge via the ramp current source T5. The on-time ton (shown as a dashed line), or the duty cycle of the pulse width modulation, can be increased compared to the nominal on-time ton,nominal by using a lower charging current Icharge and a resulting flatter voltage rise Vpwm* compared to the ramp signal Vpwm, compared to the ramp signal Vpwm at the nominal charging current Icharge,nominal.

[0081] Advantageously, in contrast to the fifth embodiment, the calibration according to the sixth embodiment can be achieved by adjusting the duty cycle of the pulse-width modulation via the charging current Icharge. Regardless of the calibration strength (steepness of the ramp signal Vpwm's charging curve), for example, an 8-bit resolution of the voltage Vprog represented by the data signal data automatically divides the pulse-width modulation into uniform 8-bit (256) steps. Therefore, the data signal data does not need to have a higher resolution than is required for the pure color resolution.

[0082] In summary, according to the fifth and sixth embodiments, a buffer remains for calibration (also towards higher brightness levels) via pulse-width modulation if the nominal current level is set such that the pulse-width modulation for the nominal brightness of LED 2 does not have a 100% on-time tone. The buffer in the on-time can be used for compensation or adjustment measures. The buffer can be addressed by means of a so-called overhead of the data signal `data` or by changing (decreasing) the charging current `Icharge` of the ramp capacitor `Cpwm`.

[0083] Fig. Figure 12 shows a seventh embodiment of an image element 1 for a display device 100, which differs from the third embodiment in that the image element 1 has a set input 8 via which a reference voltage Vset can be provided. Furthermore, the controllable supply current source T4 is configured as the first compensation transistor and the ramp current source T5 as the second compensation transistor. A source electrode T4Q of the first compensation transistor is connected to the first supply terminal Vdd, its discharge electrode T4A is connected to the source electrode T1Q of the control transistor T1, and its control electrode T4S is connected to the set input 8. A source electrode T5Q of the second compensation transistor is connected to the first supply terminal Vdd, its discharge electrode T5A is connected to the source electrode T3Q of the ramp transistor T3, and its control electrode T5S is connected to the set input 8.The first and second compensation transistors are arranged in such a way that extrinsic influences, such as ambient temperature, affect both transistors essentially identically (indicated by component T45). Furthermore, the two transistors can be manufactured using the same process to compensate for intrinsic deviations from the norm. For example, the first and second compensation transistors form a current mirror.

[0084] In other words, the charging current Icharge is driven by a current source T5, which, due to manufacturing tolerances, is subject to the same influences as the current source T4, for example, by being placed very close together and sharing a common gate connection (set terminal 8). Set terminal 8 is connected to a voltage reference and, together with the transistor geometries, precisely sets the operating point. For example, the width-to-length ratio of the first compensation transistor is 10, while the width-to-length ratio of the second compensation transistor is 1. It should be noted that the reference voltage Vset is not itself suitable for calibration, as any changes to it would also be compensated, as explained above.

[0085] If the first compensation transistor T4 has a deviation from the other pixels of the display device 100 (e.g., higher current at the same gate voltage), for example due to inaccuracies in the layer thickness, then the corresponding second compensation transistor T5 will also have this deviation (leading to a higher charging current Icharge). This deviation is fed back to the ramp capacitor Cpwm via analog feedback (not discretized), since a higher charging current Icharge results in a steeper charging curve and thus a lower duty cycle, which leads to a reduced brightness of LED 2 and ultimately results in brightness compensation.

[0086] In particular, in combination with the fifth or sixth embodiment (ton,nominal < T), this analog compensation can also correct the current flow Iled upwards.

[0087] Inaccuracies, which are typically compensated pixel-by-pixel by white balance, are partly due to manufacturing process variations in the TFT backplane and partly due to variations in the LEDs used. White correction is usually performed by a microcontroller or FPGA, which, after measuring the actual brightness, determines a correction factor for each (sub)pixel. This factor is then used to correct each value of the data signal. However, the digitized nature of the correction (i.e., using discretized values) introduces further inaccuracies, and a perfect match is never possible due to the limited resolution.

[0088] According to the seventh embodiment, however, the error component of the TFT circuit is compensated automatically in an analogous and therefore non-discrete manner; consequently, no resolution needs to be maintained for this error component in the external white balance. White balance is therefore only required for a portion of the LED error. Fig. Figure 13 shows an eighth embodiment of an image element 1 for a display device 100, which differs from the third embodiment in that the image element has a dimming terminal 9 via which a dimming signal Set_I_charge can be provided. In addition, the ramp current source T5 is designed as a dimming transistor, whose source electrode T5Q is connected to the first supply terminal Vdd, whose control electrode T5S is connected to the dimming terminal 9, and whose discharge electrode T5A is connected to the source electrode T3Q of the ramp transistor T3.

[0089] A global brightness setting (e.g. dimming) can be used as an alternative or in addition to the analog setting of the supply current source T4 (DC, see below). Fig. 6) This can also be achieved by adjusting the ramp current source T5 and the charging current Icharge, and thus implemented via pulse width modulation. As an example, the adjustment is made here using a voltage as a dimming signal Set_I_charge. If only global dimming is desired (and the LEDs 2 are not set above their nominal brightness), then no duty cycle overhead (see fifth and sixth examples) is necessary.

[0090] Calibration may be necessary due to inaccuracies and aging effects in the active circuit components. Fig. Figure 14 shows a ninth embodiment of an image element 1 for a display device 100, which differs from the eighth embodiment in that the image element 1 has a calibration input 10 via which a calibration signal data2 can be provided. Furthermore, the image element 1 has a calibration transistor T6 and a calibration capacitor CprogData. The calibration transistor T6 is connected with its source electrode T6Q to the calibration input 10, with its output electrode T6A to the dimming terminal 9, and with its control electrode to the source electrode T3Q of the ramp transistor T3. The calibration capacitor CprogData is connected with its first electrode CprogDataE1 to the dimming terminal 9 and with its second electrode CprogDataE1 to the second supply terminal Vss.

[0091] The charging current Icharge now allows for pixel-precise external control of the duty cycle or pulse width of the current flow Iled via the LED 2. This is achieved by connecting the ramp current source T5 of each (sub-)pixel to a separate sample-and-hold stage with its own calibration input 10 and supplying it with a separate calibration signal data2. This can be used, for example, for white point calibration.

[0092] According to a tenth embodiment, the calibration input 10 of each image element 1 of the display device 100, as described in the ninth embodiment, which controls the respective slope of the ramp signal Vpwm via the charging current Icharge, is connected to or supplied with standard 8-bit data sources (standard ICs). The pulse width modulation can be resolved with a total of 16 bits by using two separate, cost-effective "standard" 8-bit data sources.

[0093] In other words, in this embodiment, an 8-bit voltage source is used for pixel-fine (white) calibration, whereas a nominal gray level of the (sub)pixel is set as usual via another 8-bit voltage source, so that two separate, cost-effective standard source driver ICs can be used.

[0094] To achieve white balance, the data signal can alternatively be given a large bit overhead; that is, instead of the standard 8-bit gray level (8 bits per color), the data signal is resolved to 12-14 bits for precise white balance. However, data sources in standard display driver ICs are only designed with 8-bit resolution. In this context, a more expensive, specially adapted source driver IC with up to 16-bit accuracy can be used instead of the two 8-bit standard source driver ICs mentioned above.

[0095] Fig. Figure 15 shows an eleventh embodiment of an image element 1 for a display device 100, which differs from the previous embodiments in that the data signal `data` is in digital form instead of analog form. The data signal `data` comprises N data bits, for example, 8 bits (only 3 bits are shown here for clarity). Correspondingly, the image element 1 has N control units T21, T22, T23 and N data capacitors Cprog1, Cprog2, Cprog3, each forming a sample-and-hold unit. In this context, the selection signal `scan` comprises N pulses, or a single pulse, which is supplied to the individual control units T21, T22, T23 by delay elements between them, synchronously with the individual data bits of the data signal `data`.For example, the display device 100 has a frame rate of 60 Hz with 8 bit gray levels and 1920 columns y, so that there is enough time for several such pulses (There is a time frame of 1 / 60 sec (frame) to "program" 1920 columns, since the programming is sequential, 8 CLK cycles are necessary for this).

[0096] The comparator unit has N first inputs 3E1 and is configured as a comparator 3 or similar. Depending on the value of the individual data bits, it may be possible to stagger the capacitance of the data capacitors or to connect a correspondingly staggered multiplier to the inputs (e.g., within the comparator 3) before the applied voltage is fed to an adder and the result is compared with the ramp signal Vpwm applied to the second input 3E2.

[0097] Fig.Figure 16 shows a twelfth embodiment of an image element 1 for a display device 100, which differs from the previous embodiments in that both the data signal data and the ramp signal Vpwm are in digital form instead of analog form. Both the data signal data and the ramp signal Vpwm comprise N data bits, for example 8 bits (only 3 bits are shown here for clarity). Correspondingly, the image element 1 has N comparator elements 31, 32, 33, which are configured for comparing individual bits ("bit-by-bit comparator"), wherein a first input of each comparator element 31, 32, 33 is supplied with the digital data signal data and a second input of each comparator element 31, 32, 33 is supplied with the digital ramp signal Vpwm. These comparators could be, for example, flip-flops or similar devices.Depending on the value of the individual data bits, correspondingly staggered multipliers are connected to the outputs of the comparison elements 31, 32, 33 before the generated current is fed to a node. This node is connected to a unit 13 on its output side.

[0098] Furthermore, a global voltage reference Vref is supplied to unit 13. Each input of unit 13 has a capacitor that is charged by the output of the node or the voltage reference Vref and is connected on its output side to a corresponding input of a further comparator element 34. The PWM signal PWM is then present at the output of the further comparator element 34. The weighted currents of the comparators 31, 32, and 33, summed in the node, charge, for example, a capacitor in unit 13. When the threshold of the voltage reference Vref is reached, the downstream further comparator element 34 is triggered. This further comparator element 34 is, for example, also a comparator, a flip-flop, or similar device.Each of the comparison elements 31, 32, 33 can, for example, be preceded by a delay element D, so that the individual data bits of the data signal data and the ramp signal Vpwm are supplied to the individual comparison elements 31, 32, 33 synchronously with a pulse of the selection signal scan. For example, the display device 100 has a frame rate of 60 Hz with 24-bit grayscale and 1920 columns y, so that there is enough time for several such pulses: A 60 Hz frame rate corresponds to 16 ms in which the image must be completely built up, i.e., the following time is available for each horizontal pixel: 16 ms / 1920 columns (=pixels) / 24 bits = 0.3 µs (pulse duration / bit) or 0.15 µs on-time at 50% on-time / pulse-on time.

[0099] In summary, in the above embodiments, the PWM signal PWM is not specified by external programming, but is generated in the individual image elements 1, which correspond to (sub-)pixels of the display device 100. Within the image element 1, an analog or digital voltage signal can be converted into a digital signal (PWM signal PWM) using TFTs. A microcontroller is only optional for generating the PWM signal PWM. Optionally, the current level of the individual LEDs can also be adjusted globally or pixel-by-pixel. Furthermore, optional calibration of the display device 100 or compensation of inaccuracies in a pixel's current source is enabled by means of the generated PWM signal PWM and feedback of the current flow Iled via the LED 2. In particular, the nominal maximum brightness of the LED 2 can be set to, for example,90% is limited and a remaining portion is used for calibration by regulating the nominal current flow Iled via the LED 2 during the on-time ton via the supply current source T4 and can be fixed or programmed, for example via the additional sample-and-hold stage according to the ninth embodiment (additional calibration capacitor CprogData and additional calibration input 10 per image element 1) for pixel-fine programming of the analog current level or via a global (or row-wise or column-wise) dimming signal according to the third or eighth embodiment which is supplied from outside to implement a day / night mode and intermediate stages.

[0100] Advantageously, the image element 1, as described in previous embodiments, can be used in a conventional active-matrix structure of a display device 100, where voltage programming is performed via selection signals scan and data signals data. By using the selection signal scan as an external trigger for the pulse-width modulation, the number of connecting leads can be reduced. In this context, the reset terminal 11 is connected to the selection input 4, and the reset signal blank corresponds to the selection signal scan. Since the pulse-width modulation is generated within the image element 1, switching the image element 1 on and off via programming is unnecessary: ​​typically, the analog image information is stored within a hold capacitor of a 2T1C cell. If the pulse-width modulation is also implemented via this hold capacitor and the scan transistor, the data rate increases by 2^N of the desired PWM resolution.Compared to alternatives for generating pulse width modulation, fewer active circuit components are needed, thus enabling integration into a TFT circuit.

[0101] This patent application claims priority over German patent application 10 2020 100 335.8, the disclosure content of which is hereby incorporated by reference.

[0102] The invention is not limited to the description provided by means of the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the claims, even if that feature or combination itself is not explicitly stated in the claims or exemplary embodiments. Reference symbol list 1 image element 1S Unit B, 2 Semiconductor device / LED 2E1, 2E2 LED electrodes 3 Comparator 4 Selection input scan selection signal 5 Data input data signal 6 Ramp entrance Vpwm ramp signal 7 dimming inputs dim dimming signal 8 Set input Vset, Vref Reference voltage 9 dimming connection Set_I_charge Dimming signal 10 Calibration input data2 calibration signal 11 Reset input blank reset signal 3E1, 3E2, 3A comparator inputs / output A, T1 supply switch / transistor T2 control transistor T3 ramp transistor T4 supply power source T5 ramp power source T6 dimming transistor T1S-T6S control electrode T1A-T6A Drain electrode T1Q-T6Q source electrode T21, T22, T23 control units Cprog, Cprog1, Cprog2, Cprog3 data capacitors CprogE1, CprogE2 capacitor electrodes CPWM ramp capacitor CpwmE1, CpwmE2 Capacitor electrodes CDIM dimming capacitor CdimE1, CdimE2 capacitor electrodes CProgData calibration capacitor CprogDataE1, CprogDataE2 capacitor electrodes D1, D2 delay elements 100 Display device Vdd, Vss supply connection Iled current flow x lines y columns y1-yn column lines x1-xm line lines 12 Control device Z1-zn ramp lines τ1, τ2, ton, ton1, ton2, toff Duration T Period iCharge charging current T45 assembly unit

Claims

[1] Image element (1) for a display device (100), comprising - a first and second supply connection (Vdd, Vss), - a light-emitting semiconductor device (B) located between the first and second supply terminals, - a comparator unit with a first and second input (3E1, 3E2) and an output (3A), which is configured to set a voltage at the output (3A) depending on a comparison of a voltage applied to the first and a voltage applied to the second input (3E1, 3E2), - a supply switch (A) configured to control a current flow between the first and second supply terminals (Vdd, Vss) via the light-emitting semiconductor device (B) depending on the voltage applied to the output (3A) of the comparator unit, - a selection input (4) and a data input (5), - a storage element and a control switch configured to supply a data signal (data) provided via the data input (5) to the first input (3E1) of the comparator unit and to store it in the storage element, depending on a selection signal (scan) applied to the selection input (4), wherein the second input (3E2) of the comparator unit is provided for receiving a ramp signal (Vpwm) so that a current flow through the light-emitting semiconductor device (B) can be adjusted depending on the data signal (data), wherein the data signal (data) comprises a predetermined number of digital data bits, the storage element has several data capacitors (Cprog1, Cprog2, Cprog3) corresponding to the predetermined number of digital data bits, and the control switch has several control units (T21, T22, T23) corresponding to the predetermined number of digital data bits, wherein the control units (T21, T22, T23) are configuredto supply one of the digital data bits, depending on the selection signal (scan), to an adder connected upstream of the first input (3E1) of the comparator unit and to hold it in each of the data capacitors (Cprog1, Cprog2, Cprog3), wherein the image element (1) further comprises:, - a reset input (11) which is intended to receive a predefined reset signal (blank), - a ramp capacitor (Cpwm) with a first and second electrode (CpwmE1, CpwmE2), wherein the first electrode (CpwmE1) is coupled to the second input (3E2) of the comparator unit and the second electrode (CpwmE2) is coupled to the second supply terminal (Vss), - a ramp current source (T5) coupled to the first electrode (CpwmE1) of the ramp capacitor (Cpwm) and configured to charge the ramp capacitor (Cpwm), and - a ramp transistor (T3) with a control electrode (T3S), discharge electrode (T3A) and source electrode (T3Q), which is coupled via its discharge electrode (T3A) to the second supply terminal (Vss), via its control electrode (T3S) to the reset input (11) and via its source electrode (T3Q) to the first electrode (CpwmE1) of the ramp capacitor (Cpwm), so that depending on the specified reset signal (blank) the ramp capacitor (Cpwm) can be discharged and a ramp-like curve of the voltage applied to the second input (3E2) of the comparator unit can be set as a ramp signal (Vpwm). [2] Image element (1) according to claim 1, wherein - the light-emitting semiconductor device (B) is designed as a light-emitting diode, LED, (2) and has a first and second electrode (2E1, 2E2), - the comparison unit is designed as a comparator (3), - the supply switch (A) is configured as a supply transistor (T1) and the control switch comprises a control transistor (T2), wherein the supply transistor (T1) and the control transistor (T2) each have a control electrode (T1S, T2S), a drain electrode (T1A, T2A) and a source electrode (T1Q, T2Q), and - the storage element comprises a data capacitor (Cprog) with a first and second electrode (CprogE1, CprogE2), wherein - the supply transistor (T1) is coupled via its source electrode (T1Q) to the first supply terminal (Vdd), via its control electrode (T1S) to the output (3A) of the comparator (3) and via its discharge electrode (T1A) to the first electrode (2E1) of the LED (2), - the LED (2) is coupled to the second supply connection (Vss) via the second electrode (2E2), - the control transistor (T2) is coupled via its source electrode (T2Q) to the data input (5), via its control electrode (T2S) to the selection input (4) and via its output electrode (T2A) to the first input (3E1) of the comparator (3) and the first electrode (CprogE1) of the data capacitor (Cprog), and - the second electrode (CprogE2) of the data capacitor (Cprog) is coupled to the second supply terminal (Vss). [3] Image element (1) according to claim 2, comprising a supply current source (T4) arranged between the first supply terminal (Vdd) and the supply switch (A) and configured to provide a current (Iled) for operating the light-emitting semiconductor device (B). [4] Image element (1) according to claim 3, comprising a dimming input (7), wherein - the supply power source (T4) has a control input (T4S) which is coupled to the dimming input (7), and - the supply current source (T4) is set up to control an amplitude of the current flow (Iled) between the first and second supply terminals (Vdd, Vss) via the light-emitting semiconductor device (B), depending on a dimming signal (dim) applied to the dimming input (7). [5] Image element (1) according to claim 4, comprising - a dimming capacitor (Cdim) with a first and second electrode (CdimE1, CdimE2), wherein the first electrode (CdimE1) is coupled to the control input (T4S) of the supply current source (T4) and the second electrode (CdimE2) is coupled to the second supply terminal (Vss), and - a dimming transistor (T6) with a control electrode (T6S), drain electrode (T6A) and source electrode (T6Q), which is coupled via its source electrode (T6Q) to the dimming input (7), via its control electrode (T6S) to the selection input (4) and via its drain electrode (T6A) to the first electrode (CdimE1) of the dimming capacitor (Cdim), so that the dimming signal (dim) can be supplied to the control input (T4S) of the supply current source (T4) depending on the selection signal (scan) present at the selection input (4) and can be stored in the dimming capacitor (Cdim). [6] Image element (1) according to one of claims 3 to 5, comprising a set input (8) for receiving a reference voltage (Vset), wherein - the supply current source (T4) is configured as the first compensation transistor and the ramp current source (T5) as the second compensation transistor, wherein the first and second compensation transistors each have a control electrode (T4S, T5S), a discharge electrode (T4A, T5A) and a source electrode (T4Q, T5Q), and - the first compensation transistor is coupled via its source electrode (T4Q) to the first supply terminal (Vdd), via its control electrode (T4S) to the set input (8) and via its discharge electrode (T4A) to the source electrode (T1Q) of the supply transistor (T1), and - the second compensation transistor is coupled via its source electrode (T5Q) to the first supply terminal (Vdd), via its control electrode (T5S) to the set input (8) and via its outflow electrode (T5A) to the source electrode (T3Q) of the ramp transistor (T3). [7] Image element (1) according to claim 1, comprising a dimming connection (9), wherein - the ramp current source (T5) is designed as a dimming transistor, - the dimming transistor has a control electrode (T5S), drain electrode (T5A) and source electrode (T5Q) and is coupled via its source electrode (T5Q) to the first supply terminal (Vdd), via its control electrode (T5S) to the dimming terminal (9) and via its drain electrode (T5A) to the source electrode (T3Q) of the ramp transistor (T3), so that a voltage applied to the ramp capacitor (Cpwm) for charging the ramp capacitor (Cpwm) can be controlled depending on a dimming signal (Set_I_charge) applied to the dimming terminal (9). [8] Image element (1) according to claim 7, comprising - a calibration input (10), - a calibration transistor (T6) with a control electrode (T6S), drain electrode (T6A) and source electrode (T6Q), which is coupled via its source electrode (T6Q) to the calibration input (10), via its control electrode (T6S) to the selection input (4), and via its drain electrode (T6A) to the dimming terminal (9), and - a calibration capacitor (CprogData) with a first and second electrode (CprogDataE1, CprogDataE2), which is coupled via its first electrode (CprogDataE1) to the dimming terminal (9) and via its second electrode (CprogDataE2) to the second supply terminal (Vss), so that a calibration signal (data2) present at the calibration input (10) can be supplied to the dimming terminal (9) depending on the selection signal (scan) present at the selection input (4) and can be stored in the calibration capacitor (CprogData). [9] Display device (100) with - a plurality of image elements (1) according to one of the preceding claims, arranged in a matrix-like manner in rows (x) and columns (y), - a plurality of column lines (y1-yn), each connected to the respective selection input (4) of the image elements (1) of one of the columns (y), - a multitude of line lines (x1-xm), each connected to the respective data input (5) of the image elements (1) of one of the lines (x), - a control device (12) connected to the plurality of column lines (y1-yn) and suitable for generating a pulse as a selection signal (scan) for a selected column line from the plurality of column lines (y1-yn), and connected to the plurality of row lines (x1-xm) and suitable for generating a data signal (data) for a selected row line from the plurality of row lines (x1-xm). [10] Display device (100) according to claim 9, comprising - a plurality of reset lines, each connected to the reset input (11) of one of the image elements (1), wherein the control device (12) is connected to the plurality of reset lines and is suitable to generate a pulse as a predetermined reset signal (blank) for a selected reset line from the plurality of reset lines. [11] Display device (100) according to one of claims 9 or 10, comprising - a plurality of first dimming lines, each connected to the dimming input (7) of one of the image elements (1) or to the dimming input (7) of one of the image elements (1) of a row (x) or column (y) of the display device (100) or to the dimming input (7) of one of the image elements (1) of an RGB triplet of the display device (100), wherein the control device (12) is connected to the plurality of first dimming lines and is suitable for generating a first dimming signal (dim) for a selected first dimming line from the plurality of first dimming lines. [12] Display device (100) according to any one of claims 9 to 11, comprising - a plurality of second dimming lines, each connected to the dimming terminal (9) of one of the image elements (1), wherein the control device (12) is connected to the plurality of second dimming lines and is suitable to generate a second dimming signal (Set_I_charge) for a selected second dimming line from the plurality of second dimming lines. [13] Display device (100) according to any one of claims 9 to 12, comprising - a plurality of set lines, each connected to the set input (8) of one of the image elements (1), and a reference voltage source connected to the plurality of set lines and suitable for providing a reference voltage (Vset) for the plurality of set lines. [14] Display device (100) according to any one of claims 9 to 13, comprising - a plurality of calibration lines, each connected to the calibration input (10) of one of the image elements (1), wherein the control device (12) is connected to the plurality of calibration lines and is suitable to generate a calibration signal (Data2) for a selected calibration line from the plurality of calibration lines.

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