Memory controller for solid-state memory units

Abstract

Computer system for controlling the operation of an array of non-volatile memory cells (2) comprising cells that are selectively configurable for single-bit and multi-bit storage, comprising the computer system: one or more computer processors; a memory controller (4); one or more computer-readable storage media; and Program instructions stored on computer-readable storage media, wherein the program instructions are executable by a processing unit of a memory controller (4) to cause the memory controller (4) to: selectively configuring the array (2) for operation in a hybrid mode, in which the array (2) has cells configured for both single-bit storage and multi-bit storage, and in a multi-bit mode, in which all cells in the array are configured for multi-bit storage; and dynamic switching between the hybrid mode and multibit mode configuration of the array (2) depending on whether array capacity utilization exceeds a defined threshold, which is associated with improved array lifetime; and Before operating the array, define a threshold value depending on a set of system parameters for the array, where the parameters refer to information selected from the group consisting of the following: - Raw cell lifetime in single-bit mode and in multi-bit mode, - Size of the array (2), - Array workload types (2), - one of a static hybrid mode in which a proportion of the single-bit and multi-bit cells are static, and a dynamic hybrid mode in which the proportion for the operation of the array (2) in the hybrid mode is dynamically determined, and - whether write heat segregation is available for operating the array (2) in hybrid mode.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to memory controllers for solid-state memory units and in particular to controllers for non-volatile memory arrays comprising memory cells.

[0002] Solid-state storage (SSD) is non-volatile storage that uses memory cells based on electronic circuits, usually in integrated circuits (ICs), to store data, as opposed to traditional magnetic or optical media such as hard disk drives and tapes. Solid-state storage units (SSDs), such as flash memory units, are more robust than traditional storage units due to the absence of moving parts. SSDs offer superior bandwidth, significant power savings, and random input / output (I / O) performance that is orders of magnitude better than that of hard disk drives (HDDs).

[0003] In SSDs, the memory consists of an array of non-volatile memory cells divided into memory areas or "blocks," each containing a set of memory locations into which data can be written. Flash memory, for example, is divided into memory blocks that contain data write locations called "pages." Each memory location contains a set of memory cells, each of which can store a certain number of data bits, and the memory can be selectively configured to store a different number of bits per cell. For example, most 3D NAND flash chips support selective block configuration in more than one memory mode, typically a single-bit or SLC (single-level cell) memory mode, where each cell stores 1 bit, and a multi-bit memory mode, where each cell stores more than one bit.Common multibit flash modes include: MLC (Multi-Level-Cell) mode for storing 2 bits per cell; TLC (Triple-Level-Cell) mode for storing 3 bits per cell; and QLC (Quad-Level-Cell) mode for storing 4 bits per cell. SLC memory is the fastest and most durable, but has the lowest capacity and highest cost, while QLC memory is the cheapest, but also the slowest and least durable.

[0004] Memory controllers provide a dedicated control unit for managing the operation of non-volatile memory arrays. Memory controllers manage memory configuration, data placement, address allocation, and various other operations necessary for the internal management of memory arrays. If the array supports different memory modes, a hybrid memory controller can divide the available memory blocks into two pools operating in different modes. For example, a hybrid SLC / QLC flash controller divides the physical flash blocks into two pools, one operating in SLC mode and the other in QLC mode. Advantages of hybrid controllers include improved lifetime, lower read latency, and lower, more predictable write latency.

[0005] In this context, a document has already been published. Document US 2013 / 0046917A1 describes a flash memory controller with a recording medium and a processing circuit. This circuit controls the function of the flash memory controller via a plurality of thresholds to write data to target data blocks.

[0006] Despite these advances already made, there is still a need to further improve control circuits for flash memory in order to further improve access times and the lifespan of individual blocks. SUMMARY

[0007] This problem is solved by the subject matter of the independent patent claims. Further embodiments are specified by the respective dependent patent claims.

[0008] Aspects of the present invention disclose a method, computer program, and system for controlling the operation of an array of non-volatile memory cells, the array comprising cells that are selectively configurable for single-bit and multi-bit storage. The method includes a memory controller that selectively configures the array for operation in a hybrid mode, in which the array comprises cells configured for both single-bit and multi-bit storage, and a multi-bit mode, in which all cells in the array are configured for multi-bit storage. The method further includes dynamic switching by the memory controller between the hybrid and multi-bit mode configurations of the array, depending on whether array capacity utilization exceeds a defined threshold, which is associated with improved array lifetime. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an exemplary figure of a schematic representation of a storage unit according to an embodiment of the present invention. Fig. 2 is a flowchart showing exemplary steps of a memory control method according to an embodiment of the present invention, which is controlled by a memory controller of the unit of Fig. 1 is executed. Fig. Figure 3 is an exemplary representation of a hybrid-mode configuration of a storage array in the unit of Fig. 1 according to an embodiment of the present invention. Fig. Figure 4 is an exemplary representation of lifetime capacity utilization characteristics of a storage array according to an embodiment of the present invention. The Fig. 5a, Fig. 5b, Fig. 5c, Fig. 5d and Fig. Figure 5e are exemplary representations of characteristics for storage arrays with different system parameters and different workload types according to an embodiment of the present invention. Fig. Figure 6 is a flowchart showing exemplary steps of a storage control method according to an embodiment of the present invention, which takes into account different workload types. Fig. Figure 7 is a flowchart showing exemplary steps of a preferred storage control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] The present invention may be a system, a method, and / or a computer program product. The computer program product may comprise a computer-readable storage medium (or media) containing computer-readable program instructions to induce a processor to execute aspects of the present invention.

[0010] A computer-readable storage medium can be a physical unit capable of holding and storing instructions for use by a system for executing instructions. For example, a computer-readable storage medium can be an electronic storage unit, a magnetic storage unit, an optical storage unit, an electromagnetic storage unit, a semiconductor storage unit, or any suitable combination thereof, without limitation. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM).Flash memory), static random-access memory (SRAM), portable compact storage disk-read-only memory (CD-ROM), DVD (digital versatile disc), USB flash drive, floppy disk, a mechanically coded unit such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer-readable storage medium shall not, in its use herein, be understood as volatile signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses traveling through an optical fiber cable), or electrical signals transmitted by a wire.

[0011] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to individual data processing units or, via a network such as the internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routing computers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each data processing unit receives computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within the respective data processing unit.

[0012] Computer-readable program instructions for executing the steps of the present invention can be assembly instructions, ISA (Instruction Set Architecture) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., as well as conventional procedural programming languages ​​such as C or similar languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter case, the remotely located computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be established with an external computer (for example, via the internet using an internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute the computer-readable program instructions by using state information from the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0013] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of processes, devices (systems), and computer program products according to embodiments of the invention. It is pointed out that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be executed by means of computer-readable program instructions.

[0014] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or any other programmable data processing device to create a machine, such that the instructions executed by the processor of the computer or other programmable data processing device generate means for implementing the functions / steps specified in the block(s) of the flowcharts and / or block diagrams.These computer-readable program instructions may also be stored on a computer-readable storage medium capable of controlling a computer, programmable data processing device and / or other units to function in a particular manner, such that the computer-readable storage medium on which instructions are stored has a manufactured product, including instructions that implement aspects of the function / step specified in the block(s) of the flowchart and / or block diagrams.

[0015] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device or other unit to cause the execution of a series of process steps on the computer or other programmable device or other unit in order to generate a process executed on a computer, such that the instructions executed on the computer, other programmable device or other unit implement the functions / steps specified in the block(s) of the flowcharts and / or block diagrams.

[0016] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, processes, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams can represent a module, segment, or part of instructions that includes one or more executable instructions for performing the specific logical function(s). In some alternative embodiments, the functions specified in the blocks may occur in a different order than shown in the figures. For example, two blocks shown consecutively may in reality be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order depending on the corresponding functionality.It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or steps, or execute combinations of special hardware and computer instructions.

[0017] The block diagram of Fig. Figure 1 shows a general architecture of a storage unit embodying the invention. In this example, the unit 1 is a flash memory unit with an array of flash memory cells (i.e., the flash memory array 2) that are selectively configurable for single-bit and multi-bit storage. In an exemplary embodiment, the array 2 is a 3D NAND flash array. The unit 1 includes a memory controller 3 for controlling the operation of the memory array 2. The memory controller 3 includes control logic. In exemplary embodiments, the memory controller 3 implements the control logic through a flash control processor (FCP) 4, a read / write interface (R / WI / F) 5 (for handling data read and write requests to the unit), and a flash interconnect interface 6 (for transmitting data / control signals between the FCP 4 and the flash memory 2). The unit 1 further includes volatile memory (e.g.,the DRAM 7) for the temporary storage of various metadata during the operation of the memory controller 3.

[0018] In general, the flash memory array 2 can comprise one or more chips or packages of chips, each chip being able to contain one or more flash memory dies and provide one or more memory channels, each of which can have one or more chips or packages. In some embodiments, the flash memory array 2 can also be part of a larger memory array that provides additional flash or other memory.

[0019] In various embodiments of the present invention, read and write operations in the flash memory 2 are performed on a page-by-page basis, while erase operations are performed on a block-by-block basis. Data can only be written to a flash block after the flash block has been successfully erased, and a write-out-of-place scheme can be used to improve write throughput and latency. In a write-out-of-place scheme, a stored data page is not updated in its location in the flash memory. Instead, the updated page is written to another free flash page, and the corresponding old flash page is marked as invalid.

[0020] Accordingly, the write-out-of-place (WOP) scheme, like other flash memory properties, uses certain housekeeping operations that must be performed for the internal management of the flash memory. For example, when pages are updated and old pages are invalidated, a garbage collection procedure can take place to eliminate invalid data and free up memory locations for new input data. The garbage collection procedure restores still-valid data from an occupied flash block before it is erased, copying valid pages to a different flash block.

[0021] Garbage collection and block erasure can also be performed as part of other internal management procedures that actually involve moving data within the flash memory. Wear leveling, for example, addresses the wear characteristics of flash memory. Flash memory has a finite number of write-erase cycles (or program-erase cycles, P / E cycles) before memory integrity begins to degrade. Wear leveling techniques aim to distribute write-erase cycles evenly across all available flash blocks based on write-erase cycle counts to prevent uneven wear.

[0022] In various embodiments, the memory controller 3 can communicate directly with hosts to handle read / write requests to the unit 1. In exemplary embodiments, the memory controller 3 can be managed by a higher-level controller that handles host requests for multiple units in a storage system. The FCP 4 can generally control the operation of the unit 1 by managing data read and write operations in the flash memory array 2 in response to requests received through the R / W interface 5. The FCP 4 executes a flash translation layer (FTL) software layer that maintains address metadata in the DRAM 7 for data stored in the flash array. The address metadata maps logical block addresses belonging to input data blocks from the host / higher-level controller to physical addresses (flash page numbers) in the flash.In exemplary embodiments, the FCP 4 can control all internal management procedures in array 2, with all associated metadata being maintained in DRAM 7.

[0023] In some embodiments, internal management functions can be fully or partially controlled by local controllers on the flash chips, with the FCP 4 providing overall control. Specifically, the FCP 4 includes functionality for controlling the configuration of the flash memory array 2 (as described in detail below). The FCP 4 can also implement various other procedures common to flash memory, such as error-correcting encoding / decoding and heat-sensitive functionality to identify "hot" and "cold" data and adjust storage strategies accordingly.

[0024] In this example, the control functionality of the memory controller 3 is implemented via program instructions (e.g., program modules executed by the FCP 4). Generally, the program modules can comprise routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement certain abstract data types. According to embodiments of the present invention, the FCP 4 can be implemented by a processing unit comprising one or more processors and can include processor memory (comprising ROM, RAM, cache memory, etc.) that stores program instructions executable by a processing unit to perform the described operations. For example, the FCP 4 can comprise an FPGA with an embedded CPU for executing program instructions. In further embodiments, the control logic of the memory controller 3 can be implemented by hard-wired logic circuits.In general, however, the control logic can be implemented by hardware or software or a combination thereof, and different implementations will be obvious to experts from the description herein.

[0025] When operating storage unit 1, FCP 4 can selectively configure flash memory array 2 to operate in a hybrid mode, in which the array contains cells configured for both single-bit and multi-bit storage, and in a multi-bit mode, in which all cells in the array are configured for multi-bit storage. In this example, FCP configures flash memory array 2 to operate in an SLC / QLC hybrid mode or in a QLC-only mode. In hybrid mode, the array has a pool of SLC blocks in which the memory cells are configured as SLC cells for single-bit storage and a pool of QLC blocks in which the cells are configured as QLC cells for 4-bit storage. In QLC-only mode, all blocks in the array are configured for QLC storage.

[0026] Fig. Figure 2 is a flowchart showing exemplary steps of a configuration control process. In different embodiments, according to different embodiments of the present invention, the FCP 4 performs the processing steps of the process described in Figure 2. Fig. 2 shown flowcharts.

[0027] At runtime of Unit 1, FCP 4 determines the current capacity utilization for the flash memory array 2 (step 10). FCP 4 can determine the capacity utilization using any suitable metric, for example, by the number or proportion of occupied (or free) flash blocks in the array, or by the amount or proportion of valid data (e.g., valid flash pages) in the array. In the present embodiment, FCP 4 measures the capacity utilization of the amount of valid data as a percentage of the total array capacity in QLC-only mode (i.e., the maximum possible array capacity). Furthermore, FCP 4 can determine the current capacity utilization from metadata (which, for example, is stored in the flash memory array 2 at the end of each runtime) that is loaded into DRAM 7 by FCP 4 upon power-up.

[0028] In decision step 11, FCP 4 determines whether the array capacity utilization is less than a threshold TH defined in FCP 4 for the array. In response to a finding (e.g., upon first use of unit 1) that the array capacity utilization is less than a threshold TH (decision step 11, Y branch), FCP 4 configures a hybrid mode (step 12).

[0029] In step 12, the FCP 4 controls the configuration of array 2 through control signals via the I / F 6 connection for operation in SLC / QLC hybrid mode. Fig. Figure 3 is an exemplary representation of the hybrid operating mode. Here, in hybrid mode, FCP 4 configures a pool 20 of SLC flash blocks and a pool 21 of QLC flash blocks for the flash memory array 2. In an exemplary embodiment, the ratio of SLC to QLC blocks is fixed.

[0030] During hybrid mode operation, FCP 4 preferentially writes data to the single-bit cells in SLC pool 20 and, if necessary, moves data from the SLC pool to the QLC cells in pool 21 to free up storage capacity in the SLC pool. SLC pool 20 thus provides an initial storage tier into which data is preferably written first. When blocks in the SLC tier are exhausted, a garbage collection (GC) process cleans up the blocks in the usual way. Valid data can be moved within the SLC tier or, if necessary, removed and moved to the QLC tier. In the case of a high write load on array 2, FCP 4 can also place data directly into QLC pool 21. Within the QLC tier, a garbage collection process moves data within that tier (i.e., no data is promoted to the SLC tier).

[0031] During operation in hybrid mode, FCP 4 monitors the capacity utilization in flash memory array 2 (step 13). In exemplary embodiments, FCP 4 can monitor capacity utilization based on the validity flags maintained as metadata for flash pages. In decision step 14, FCP 4 determines whether the capacity utilization has exceeded the threshold TH.

[0032] Upon determining that capacity utilization has not exceeded the TH threshold (decision step 14, N branch), FCP 4 returns to step 13 to continue monitoring operation in hybrid mode. Upon determining that capacity utilization has exceeded the TH threshold (decision step 14, Y branch), FCP 4 proceeds to step 15 to configure multibit mode.

[0033] In step 15, FCP 4 controls the configuration of flash memory array 2 for operation in QLC-only mode via control signals over connection I / F 6. Referring again to step 11, in response to a detection that the current usage exceeds the threshold TH, FCP 4 further transitions to step 13 in QLC mode at the beginning of each operating period (decision step 11, N branch). In various embodiments, FCP 4 dynamically reconfigures the array. For example, FCP 4 reconfigures all flash blocks in SLC pool 20 for QLC storage. In exemplary embodiments, FCP 4 first moves valid pages in the SLC blocks into a QLC block and then reconfigures the released SLC blocks for QLC storage.The FCP 4 can use a sequence of commands / operations that are usually manufacturer-specific for flash chips to switch the operating mode of flash blocks from one mode to another.

[0034] In QLC-only mode, FCP 4 monitors capacity utilization (in step 16). Furthermore, in step 17, FCP 4 determines whether capacity utilization has fallen below the TH threshold. Upon detecting that capacity utilization has fallen below the TH threshold, FCP 4 returns to step 12 and dynamically reconfigures the array for hybrid mode operation. Accordingly, FCP 4 configures pool 20 of SLC blocks from free QLC blocks in array 2, and hybrid mode operation then resumes (as previously described).

[0035] The above procedure is continued for the runtime of unit 1, wherein, according to embodiments of the present invention, the FCP 4 dynamically switches between the hybrid and multibit configurations of the array as soon as the array capacity utilization exceeds the threshold TH. As described below, the threshold TH is defined such that the lifetime of the array is improved by the dynamic switching between operating modes described above. At the end of the runtime, the FCP 4 stores essential metadata contained in the DRAM 7 in the unit's non-volatile memory (e.g., in the flash array 2) for retrieval upon the next power-up. The stored metadata may include the current capacity utilization of the array for loading into the FCP 4 (from step 10).

[0036] Embodiments of the present invention take into account that a suitable value for the switching threshold TH depends on system parameters relating to the specific design and operation of the flash memory array 2 in the storage unit 1. In particular, the choice of the threshold depends on a set of system parameters that may include: nominal cell lifetime in single-bit and multi-bit mode; array size; workload type for the array; whether the hybrid mode is static or dynamic (as described below); and whether heat-write segregation is enabled for operation of the array in hybrid mode.

[0037] The nominal cell lifetime depends on the memory cell design (e.g., the specific 3D NAND technology used) and can be specified in terms of nominal P / E cycles (i.e., the number of P / E cycles cells can support before degradation or failure). Nominal cell lifetime can be defined on a block-by-block basis (e.g., for flash blocks with a specific number of pages / cells). Array size can be specified by the number of chips, packages, etc., of a specific type / capacity (e.g., with a specific number of flash blocks per chip / package) used in the array, and the amount of capacity allocated for overprovision. Array size parameters can further specify the number of SLC / multibit blocks used for hybrid operation.

[0038] The workload type can be defined according to various standard definitions (e.g., uniformly distributed or Zipf X / Y (for different values ​​of X / Y, where the skew factor of a Zipf distribution is chosen so that X percent of the write workload goes into Y percent of the address space), etc.). For operation of the array in hybrid mode, either a static hybrid mode (in which the ratio of single-bit to multi-bit cells is static) or a dynamic hybrid mode (in which the ratio is determined dynamically) can be specified for the unit. The activation / deactivation of the heat-write segregation functionality can also be configured. The functionality mentioned above allows the memory controller to distinguish between "hot" and "cold" data and preferentially write / maintain hot data in the SLC pool for faster access, while the multi-bit pool is primarily used for cold data.

[0039] In an exemplary embodiment, all relevant system parameters for storage unit 1 can be predefined. A suitable switching threshold TH for the unit can then be defined based on an analysis of the array lifetime as a function of capacity utilization in hybrid and multibit mode. Fig. Figure 4 is an exemplary representation of lifetime capacity utilization characteristics for an exemplary unit (e.g., storage unit 1) in SLC / QLC hybrid and QLC-only modes. The example shown in Fig. 4 is based on a random write workload and a nominal block lifetime (P / E cycles (pec)) of 100k for SLC blocks and 8.5k for QLC blocks in an exemplary NAND flash unit.

[0040] Fig. Figure 4 shows the array lifetime in terms of write cycles of the unit before a failure occurs (e.g., array degradation exceeds a defined threshold) as a function of capacity utilization (as previously defined). Thus, it shows Fig. 4. A clear transition point exists at just over 20% capacity utilization, above which the QLC-only mode becomes advantageous compared to the SLC / QLC hybrid mode. Switching between the hybrid and multibit modes can thus improve the lifetime of the array as a whole. Embodiments of the present invention can provide significant performance improvements compared to previous hybrid units, where the unit's lifetime is determined by which pool wears out first. In practice, a wear imbalance between the pools is likely, and when the lifetime of one pool is exhausted, the remaining lifetime of the other pool cannot be utilized.

[0041] In the embodiment described above, the switching threshold TH is defined as the one in Fig. 4. The displayed optimal value (i.e., the capacity utilization level at which the mode that ensures a better array lifetime switches between hybrid and multibit mode) is defined. Accordingly, embodiments of the present invention can optimize the lifetime of the flash memory array 2 via dynamic mode switching operation.

[0042] Various embodiments of the present invention can define the threshold TH as a fixed value based on known system parameters for the unit. Fig. Figures 5a to 5e show illustrative examples of how lifetime / capacity utilization characteristics change with different system parameters according to different embodiments of the present invention.

[0043] Fig. Section 5a contains an exemplary presentation of how the characteristics of Fig. 4. Change with other hybrid mode parameters according to different embodiments of the present invention. Fig. 5a is the hybrid mode curve of Fig. 4 is designated as “static hybrid (baseline)”, which corresponds to operation in a static hybrid mode. An alternative hybrid mode is a dynamic or adaptive hybrid mode in which the size of the SLC pool is dynamically adjusted during an initial operating phase to set the SLC / QLC ratio according to current utilization, workload characteristics, and currently occupied space of both the SLC and QLC pools, and / or characteristics of the NAND flash memory cells (e.g., the ratio of the average lifespan of blocks in SLC-only and QLC-only modes). Once the SLC / QLC ratio is established, the blocks remain statically assigned to their current pools until re-evaluation. In one embodiment, the blocks then remain statically assigned to their current pools, while in other embodiments, blocks can switch between pools for wear leveling.

[0044] More curves in Fig. Figure 5a shows characteristics for: a dynamic hybrid mode (“dynamic hybrid (baseline)”); a static hybrid mode with active heat-write segregation (“static hybrid (heat-sensitive)”); and a dynamic hybrid mode with active heat-write segregation (“dynamic hybrid (heat-sensitive)”). In each case, it contains Fig. 5a shows a clear point where the QLC-only mode is advantageous compared to the SLC / QLC hybrid mode. Additionally, it shows Fig. 5a The optimal switching thresholds are indicated by the corresponding arrows.

[0045] The Fig. 5b and Fig. Figure 5c shows equivalent curves for other workload types. Fig. 5b concerns Zipf's 95 / 20 and Fig. 5c concerns Zipf's 80 / 20. Fig. 5d and Fig. Figure 5e shows further curves for different modes with a nominal block lifetime of 40k for SLC blocks and 4.5k for QLC blocks in an example NAND flash unit. Optimal thresholds for switching from hybrid to QLC-only mode are shown as previously. Note that for some hybrid modes, the hybrid mode lifetime exceeds the QLC-only lifetime at all capacity utilizations.

[0046] In some storage units, one or more system parameters may change during the unit's lifetime. In particular, the workload type often changes during operation, and this can significantly affect the optimal switching thresholds, as described in the Fig. Figures 5a to 5c are shown. In an exemplary embodiment, the control logic of the storage controller 3 is therefore suitable to monitor the workload type during the operation of the array and to dynamically define the switching threshold depending on the workload type.

[0047] Fig. 6 is a flowchart that shows a basic operation for the unit of Fig. Figure 1 shows embodiments of the present invention. In step 30, the FCP 4 loads the current capacity utilization for the flash memory array 2 at runtime.

[0048] In step 31, FCP 4 determines the current workload type. In various embodiments, FCP 4 can determine a workload type in a generally known manner based on measurements of read / write traffic by maintaining and utilizing one or more metrics that respond to user I / O workload. Examples include: so-called write gain for the SLC and QLC tiers; the number of pages invalidated by new writes in the SLC and QLC tiers; the average number of pages per block deemed valid during garbage collection in the SLC and QLC tiers; and the number of pages assigned specific heat levels when heat-sensitive tier allocation is used. FCP 4 can also determine the current workload type from metadata (which, for example, is stored in Flash Memory Array 2 at the end of each runtime).Furthermore, the FCP 4 can load the current workload type into DRAM 7 upon power-up. If the workload is unknown (e.g., upon first use of unit 1), the FCP 4 can assume a random write workload.

[0049] In step 32, FCP 4 defines a workload-dependent switching threshold THW based on the current workload type and other known system parameters. In various embodiments, FCP 4 can define the threshold (in step 32) using predefined tables or other data structures that specify optimal thresholds for the unit's current parameters and different workload types. Such tables / structures can be stored in FCP 4's persistent memory or, during runtime, in DRAM 7 and loaded into persistent memory (e.g., array 2) upon shutdown.

[0050] In step 33, FCP 4 configures Flash Storage Array 2 to operate in hybrid or QLC-only mode based on a comparison of current capacity utilization against the THW threshold (generally as described above). FCP 4 can then proceed with array operation in the configured mode, monitoring capacity utilization (in step 34) and comparing it against the THW threshold (in decision step 35). If it detects that the threshold has been exceeded (decision step 35, Y branch), FCP 4 returns to step 33 and reconfigures the array for operation in the other mode. If it detects that the threshold has not been exceeded (decision step 35, N branch), FCP 4 continues monitoring the workload type (step 36).

[0051] In both modes, FCP 4 continues to monitor the workload type (in step 36). Upon detecting a change in workload type (decision step 37, Y branch), FCP 4 returns to step 32 and redefines the THW threshold for the new workload type. Operation then continues as before, with the array being reconfigured to the other mode as needed based on the threshold comparison from step 32. Furthermore, if no change in workload type is detected (decision step 37, N branch), FCP 4 can continue operating the array in the configured mode, monitoring capacity utilization (in step 34).

[0052] Depending on the unit's parameters, the lifetime in hybrid mode can differ from the lifetime in multibit mode for certain workload types (e.g., in the Fig. 5b and Fig. 5c) exceed any capacity utilization. If FCP 4 detects such a workload type in step 37, FCP 4 can define the THW threshold (in step 32) as 100% capacity utilization, causing operations to revert to hybrid mode (if necessary) and remain in that mode until the workload type changes.

[0053] The in relation to Fig. The embodiment shown and described in Figure 6 enables the FCP 4 to adapt to changing workloads in a given unit. In exemplary embodiments, the FCP 4 can appropriately define the switching threshold to accommodate changes in one or more system parameters. In further embodiments, the FCP 4 can consider several different parameter sets covering all common ranges and combinations of different parameters for arrays of storage units.

[0054] Pre-stored tables / data structures can specify suitable values ​​for the switching threshold for different parameter sets, such as different workload types, based on predetermined characteristics. The FCP 4 can then provide a generic memory controller that can adapt to all given array constructions and operating parameters. In various embodiments, the FCP 4 is capable of receiving the set of system parameters for the array before it is operated and defining the switching threshold based on these parameters.

[0055] Furthermore, according to embodiments of the present invention, the FCP 4 can load the system parameters and select the switching threshold accordingly upon the initial power-up of a given unit, at the beginning of each runtime, and / or whenever parameters are changed during operation. In particular, parameters other than the workload may change during operation in some units. For example, the hybrid mode can be selected as dynamic or static for different operating periods. Additionally, heat-write segregation can be selectively enabled / disabled. The size of the active flash memory array 2 can also be selectable in some cases (e.g., from a maximum number of NAND packages available in a unit).

[0056] Fig. Figure 7 is a flowchart showing basic operating steps for an embodiment of the FCP 4 according to various aspects of the present invention. In step 40, the FCP 4 loads the system parameters for the current operating period. The parameter set can specify the current status of any variable parameters (as described above), for example, the current capacity utilization and workload type, together with any "fixed" parameters (e.g., nominal pec values ​​for the array cell types) that were not previously loaded into the FCP 4.

[0057] In step 41, FCP 4 defines a workload-dependent switching threshold THWP for the current parameter set. In step 42, FCP 4 selects either the hybrid mode or the QLC-only array configuration based on a comparison of the current capacity utilization with the THWP threshold.

[0058] In step 43, FCP 4 configures the array for operation in the selected mode and with the specified operating parameters (e.g., dynamic or static hybrid mode, active / inactive heat write tiering, etc.). The system configuration can include data and read path configuration (e.g., queue management in Flash I / F 6), configuration of the SLC / QLC pool sizes (e.g., based on the size of the active array), and, depending on the SLC / QLC pool configuration, general flash management or other functionality (e.g., garbage collection, calibration, etc.). The unit then continues operating for this configuration, with FCP 4 controlling the array's operation according to the specified parameters. The remaining steps 44 through 47 of Fig. 7 correspond to steps 34 to 37 of Fig. 6, which were previously described in more detail above.

[0059] It is understood that various changes and modifications can be made to the exemplary embodiments described above. For example, the hybrid / multibit mode can use a multibit memory other than QLC memory (e.g., TLC or MLC memory). Memory controllers incorporating the invention can be used with non-volatile memory arrays based on cells other than NAND flash cells (e.g., NOR flash cells, PCM cells (phase-change memory cells), RRAM cells (resistive RAM cells), NVRAM cells (non-volatile RAM cells), etc.).

[0060] While features are generally described herein with reference to an entity that embodies the invention, corresponding features may be provided in a method / computer program product that embodies the invention, and vice versa.

Claims

[1] A computer system for controlling the operation of an array of non-volatile memory cells (2) comprising cells selectively configurable for single-bit and multi-bit storage, the computer system comprising: one or more computer processors; a memory controller (4); one or more computer-readable storage media; and Program instructions stored on the computer-readable storage media, the program instructions being executable by a processing unit of a memory controller (4) to cause the memory controller (4) to: selectively configuring the array (2) to operate in a hybrid mode in which the array (2) has cells configured for single-bit storage as well as cells configured for multi-bit storage, and in a multi-bit mode in which all cells in the array are configured for multi-bit storage; and dynamically switching between the hybrid mode and the multibit mode configuration of the array (2) depending on whether an array capacity utilization exceeds a defined threshold associated with an improved lifetime of the array; and prior to operation of the array, defining a threshold value depending on a set of system parameters for the array, where the parameters indicate information selected from the group consisting of: - Raw cell lifetime in single-bit mode and multi-bit mode, - Size of the array (2), - Array workload types (2), - one of a static hybrid mode in which a proportion of the single-bit and multi-bit cells are static, and a dynamic hybrid mode in which the proportion for the operation of the array (2) in the hybrid mode is determined dynamically, and - whether write heat segregation is available for operating the array (2) in hybrid mode. [2] The computer system of claim 1, wherein the threshold is defined as a capacity utilization level to switch between the hybrid mode and the multi-bit mode. [3] The computer system of claim 1, further comprising program instructions stored on the computer-readable storage media for execution using the memory controller (4) for: Monitoring a workload type during operation of the array (2); and dynamically defining the threshold depending on the workload type. [4] The computer system of claim 1, further comprising program instructions stored on the computer-readable storage media for execution using the memory controller (2) for: Controlling the operation of the array (4) according to the set of system parameters. [5] The computer system of claim 1, further comprising program instructions stored on the computer-readable storage media for execution using the memory controller (2) for: preferentially writing data into single-bit cells of the array (2) during operation of the array (2) in hybrid mode; and Moving data from single-bit to multi-bit cells, freeing up storage capacity in the single-bit cells. [6] The computer system of claim 1, further comprising: a storage unit; and wherein the memory unit comprises an array (2) of non-volatile memory cells comprising cells selectively configurable for single-bit and multi-bit storage. [7] A computer system according to claim 6, wherein the array (2) comprises flash memory cells. [8] The computer system of claim 7, wherein the flash memory cells are selectively configurable for single-bit and 4-bit storage. [9] A method for controlling the operation of an array of non-volatile memory cells having cells selectively configurable for single-bit and multi-bit storage, the method comprising: selectively configuring the array (2) by a memory controller for operation in a hybrid mode in which the array (2) has cells configured for single-bit storage as well as cells configured for multi-bit storage, and in a multi-bit mode in which all cells in the array are configured for multi-bit storage; and dynamic switching between the hybrid mode and the multibit mode configuration of the array (2) by the memory controller depending on whether the array capacity utilization exceeds a defined threshold associated with an improved lifetime of the array (2); and prior to operation of the array (2), defining a threshold value depending on a set of system parameters for the array (2), wherein the parameters indicate information selected from the group consisting of:. - Raw cell lifetime in single-bit mode and multi-bit mode, - Size of the array (2), - Array workload types (2), - one of a static hybrid mode in which a proportion of the single-bit and multi-bit cells are static, and a dynamic hybrid mode in which the proportion for the operation of the array (2) in the hybrid mode is determined dynamically, and - whether write heat segregation is available for operating the array (2) in hybrid mode. [10] The method of claim 9, wherein the threshold is defined as a capacity utilization level to switch between the hybrid mode and the multibit mode. [11] The method of claim 9, further comprising: Monitoring the workload type by the storage controller during operation of the array (2); and Dynamic definition of the threshold by the memory controller depending on the workload type. [12] A computer program product for controlling the operation of an array (2) of non-volatile memory cells comprising cells selectively configurable for single-bit and multi-bit storage, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a processing unit of a memory controller (4) to cause the memory controller (4) to carry out the method according to any one of claims 9 to 11.

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