Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component

Abstract

Optoelectronic semiconductor device (1) comprising - a carrier (2) having a structured surface (2A), - a semiconductor layer sequence (3) arranged on the support (2), wherein the semiconductor layer sequence (3) comprises the following: - a first semiconductor layer (4) with a first surface (4A), - a second semiconductor layer (6) with a first surface (6A), - a first main surface (3A) and a second main surface (3B) opposite the first main surface (3A), wherein the first surfaces (4A, 6A) of the first and second semiconductor layers (4, 6) are at least partially arranged on the first main surface (3A) and wherein the second main surface (3B) faces the structured surface (2A) of the support, - at least one side surface (3C) that connects the first and second main surfaces (3A, 3B), - a directionally reflective layer (7) and - a planarization layer (8) arranged between the structured surface (2A) and the directionally reflecting layer (7), wherein: - the structured surface (2A) is arranged on one side of the support (2) facing the semiconductor layer sequence (3), - the support (2) has structural elements (2B) on the structured surface (2A) which are spaced apart by spaces (2C), wherein in a first region (I) of the support (2) the planarization layer (8) is arranged in the spaces (2C) and extends in a vertical direction (V) at least to the upper ends of the structural elements (2B) and - the planarization layer (8) in the first region (I) has a surface (8A) facing the directionally reflecting layer (7), wherein the surface (8A) has a planar or concave curved shape.

Description

[0001] The present application relates to an optoelectronic semiconductor device and a method for manufacturing an optoelectronic semiconductor device. In particular, the optoelectronic semiconductor device is a radiation-emitting semiconductor device, for example an LED.

[0002] There are various chip designs, which are associated with different assembly technologies. One possible chip design is a flip-chip design, in which a semiconductor chip is mounted upside down and bond pads of opposite polarity for external electrical contact are arranged on the same side of the semiconductor body of the chip. The flip-chip design can have a mesa structure, where part of the chip substrate is not covered by the semiconductor body, exposing irregularities. These irregularities impair the effectiveness of the reflective layers on the mesa structure, so that when the semiconductor chip is mounted on a leadframe or printed circuit board, for example, it suffers from light absorption by the leadframe or circuit board.

[0003] Documents US 2016 / 0111600A1, US 2012 / 0248469A1 and DE 102018117018A1 describe various examples of radiation-emitting semiconductor devices that have structured substrates.

[0004] The problems to be solved in the present application are to provide an improved optoelectronic semiconductor device in which, in particular, light absorption is reduced, and an improved method for manufacturing an optoelectronic semiconductor device in which, in particular, light absorption is reduced. These problems can be solved, inter alia, by an optoelectronic semiconductor device with the features of the independent device claim and by a method with the features of the independent method claim.

[0005] According to at least one embodiment of an optoelectronic semiconductor device, the optoelectronic semiconductor device comprises a substrate having a structured surface and a sequence of semiconductor layers arranged on the substrate. In the context of the present application, "structured surface" preferably means that the surface is structured in a predetermined manner and, in particular, has a regular, non-random pattern. For example, the structured surface is arranged on a side of the substrate facing the sequence of semiconductor layers. Due to its roughness, the structured surface contributes to increasing the coupling efficiency of the optoelectronic semiconductor device. In particular, the refractive index difference between the sequence of semiconductor layers and the substrate is linearly reduced by a "transition layer" formed on the structured surface of the substrate.

[0006] Furthermore, the semiconductor layer sequence comprises a first semiconductor layer with a first surface, a second semiconductor layer with a first surface, a first principal surface, and a second principal surface opposite the first principal surface. The semiconductor layer sequence also comprises at least one side surface connecting the first and second principal surfaces. In particular, the first surfaces of the first and second semiconductor layers are at least partially arranged on the first principal surface of the semiconductor layer sequence. Preferably, the second principal surface faces the structured surface of the substrate. In the context of the present application, "arranged on (...)" means in a non-parallel, preferably vertical, direction.

[0007] Furthermore, the optoelectronic semiconductor device comprises a directionally reflective layer. In the context of the present application, "directionally reflective" refers to a reflection property characterized by the fact that a major part of the radiation is reflected in one direction or within a small angular range.

[0008] Furthermore, the optoelectronic semiconductor device includes a planarization layer, which is positioned between the structured surface and the directionally reflective layer. Advantageously, the planarization layer helps to compensate for irregularities present on the structured surface of the substrate.

[0009] According to at least one embodiment, the carrier has structural elements on its structured surface that are spaced apart by gaps.

[0010] According to at least one embodiment, the planarization layer is arranged in the spaces between the structural elements in a first region of the support and extends vertically at least to the upper ends of the structural elements. Preferably, the structural elements in the first region of the support are completely embedded in the planarization layer.

[0011] In particular, a surface of the planarization layer facing the structured surface in the first area exhibits a pattern that is complementary to that of the structured surface.

[0012] According to at least one embodiment, a surface of the planarization layer, which in the first region faces the directionally reflecting layer and is therefore turned away from the structured surface in the first region, has a flat or concavely curved shape. Advantageously, this design allows the directionally reflecting layer to be applied to a smooth surface and thus exhibits a significantly higher reflection coefficient than without the planarization layer.

[0013] In a preferred embodiment of the optoelectronic semiconductor device, the planarization layer is arranged on at least one face of the semiconductor layer sequence. The planarization layer can at least partially cover one or more faces, preferably all faces, of the semiconductor layer sequence.

[0014] According to at least one embodiment, the planarization layer at least partially covers the first principal surface of the semiconductor layer sequence. For example, the planarization layer can level the semiconductor layer sequence so that a surface on which the directionally reflective layer is applied is flat.

[0015] According to at least one embodiment, the directional reflective layer comprises or consists of a dielectric material. The directional reflective layer can be a single layer or a multilayer comprising at least two sublayers with higher and lower refractive indices. Preferably, the directional reflective layer is a distributed Bragg reflector (DBR) layer. Suitable materials for the directional reflective layer or the sublayers are oxides such as SiO₂, TiO₂, Nb₂O₅, Al₂O₃, or nitrides such as Si₃N₄ or SiNₓ, where "x" denotes a non-stoichiometric amount of nitride, or fluorides such as MgF₂.Suitable thicknesses of the directionally reflective layer are in the range between 500 nm and 6000 nm, preferably in the range between 1000 nm and 5000 nm, particularly preferably between 1500 nm and 4500 nm, with deviations of 10% being tolerable.

[0016] According to a preferred embodiment, the support in the first region projects laterally beyond the second semiconductor layer. In particular, the first region of the support can be an edge region of the support that is not covered by the sequence of semiconductor layers and laterally surrounds them in a top view of the optoelectronic semiconductor device.

[0017] According to at least one embodiment, parts of the semiconductor layer sequence are arranged in a second area of ​​the support in the spaces between the structural elements.

[0018] In particular, the support is a growth substrate on which the semiconductor layer sequence has been epitaxially deposited. In this context, "epitutional deposition on the growth substrate" means that the growth substrate is used for the deposition and / or growth of the semiconductor layer sequence. The second semiconductor layer, for example, is in direct contact with the structured surface of the support. Preferably, the semiconductor layer sequence is deposited over the entire structured surface and subsequently removed in the first region. Removing the semiconductor layer sequence in the first region creates a first, deep mesa, wherein the surfaces of the semiconductor layer sequence at the first mesa preferably run obliquely, i.e., at an angle between 0° and 90°, to a principal plane of extension of the support.

[0019] The support or growth substrate preferably comprises or consists of sapphire, SiC, and / or GaN. Particularly preferably, the growth substrate consists of sapphire, and the optoelectronic semiconductor device is a miniature sapphire flip chip. In the context of this application, "miniature" preferably refers to a size of approximately 200 × 200 µm. 2 The directionally reflective layer allows the component to be flipped and achieves significantly high reflection to emit radiation laterally and from the top.

[0020] According to at least one embodiment, the planarization layer comprises SiO2 and / or spin-on glass. Spin-on glass (SOG) is a material that is applied to a wafer as a liquid containing SiO2 suspended in a solvent and subsequently cured. Alternatively, the planarization layer can comprise a PECVD-SiO2 layer deposited by plasma-enhanced chemical vapor deposition (PECVD), for example, by high-density plasma chemical vapor deposition (HDPCVD). Light reflection at an interface between the semiconductor layer sequence and the planarization layer containing SiO2 or spin-on glass is lower than at an interface between the semiconductor layer sequence and the directionally reflecting layer.Consequently, the planarization layer containing SiO2 or spin-on glass increases the light yield.

[0021] In a preferred embodiment of the optoelectronic semiconductor device, the first semiconductor layer has a first conductivity type and the second semiconductor layer has a second conductivity type. In particular, the first semiconductor layer is a p-doped layer, while the second semiconductor layer is an n-doped layer. Preferably, an active zone is located between the first and second semiconductor layers. Further layers, doped or undoped, can be arranged between the first semiconductor layer and the active zone, as well as between the second semiconductor layer and the active zone. Furthermore, the first and second semiconductor layers can be single layers or multiple layers.

[0022] According to at least one embodiment, the active zone is designed to generate electromagnetic radiation. In this case, the term "electromagnetic radiation" refers in particular to infrared, visible, and / or ultraviolet electromagnetic radiation. Specifically, the active zone is designed to emit blue or green light. During operation, a major portion of the generated radiation can be emitted laterally, i.e., from the side surfaces of the optoelectronic semiconductor device. A smaller portion of the radiation can be emitted from the top surface of the optoelectronic semiconductor device.

[0023] Materials based on nitride compound semiconductors are suitable for the semiconductor layer sequence. In this context, "based on nitride compound semiconductors" means that at least one layer of the semiconductor layer sequence is a nitride III / V compound semiconductor material, preferably Al. n Gam In 1-n-m N, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1 and n+m ≤ 1, without necessarily having a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants and additional components that impart the characteristic physical properties of the Al. n Ga m In 1-n-m The N-materials do not change significantly. For the sake of simplicity, however, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, N), even though some of these can be replaced by small amounts of other substances.

[0024] According to at least one embodiment, the optoelectronic semiconductor device further comprises an omnidirectionally reflective layer arranged on a side of the directionally reflective layer facing away from the substrate. The omnidirectionally reflective layer can cover an area of ​​the directionally reflective layer that covers at least a portion of the second area of ​​the substrate and / or at least a portion of the first area of ​​the substrate.

[0025] In the context of the present application, “omnidirectionally reflective” refers to a reflection property characterized by the fact that the radiation is distributed largely uniformly over all possible reflection angles.

[0026] In particular, the omnidirectional reflective layer is a metallic layer. The omnidirectional reflective layer preferably contains Al, Rh, or Ag. The omnidirectional reflective layer can further reduce transmission losses.

[0027] According to at least one embodiment, the semiconductor layer sequence on at least one side surface is structured to include structural elements. Preferably, the structural elements are arranged on one or all side surfaces of the second semiconductor layer. Furthermore, the semiconductor layer sequence on the first main surface can be structured to include structural elements. These structural elements can, for example, have the form of prisms. In particular, the structured surfaces are roughened surfaces. With roughened surfaces featuring structural elements such as prisms, lateral light emission at the first, deep mesa region is increased. This is advantageous, for example, for the use of a miniature sapphire flip chip in a backlight unit.

[0028] According to at least one embodiment, the second semiconductor layer projects laterally beyond the first semiconductor layer. In other words, the semiconductor layer sequence on the first mesa can have a second mesa, wherein the surfaces of the semiconductor layer sequence at the second mesa preferably run obliquely, i.e., at an angle between 0° and 90°, to a principal extension plane of the substrate. In particular, the second mesa is created by ablating an edge region of the semiconductor layer sequence.

[0029] The first and second mesa serve to electrically insulate the side wall of the component.

[0030] According to at least one embodiment, the optoelectronic semiconductor device comprises a dielectric layer arranged between the planarization layer and the semiconductor layer sequence and / or the substrate. In other words, the dielectric layer forms an intermediate layer between the planarization layer and the semiconductor layer sequence and / or the substrate. The dielectric layer can be a single layer or a multilayer. The thickness of the dielectric layer can range from 50 nm to 650 nm. The dielectric layer can comprise or consist of at least one of the following materials: Al₂O₃, SiO₂, TiO₂, silicon nitride, silicon oxynitride, Nb₂O₅, MgF₂. For example, the dielectric layer is multilayered and comprises a 40 to 120 nm thick sublayer of Al₂O₃ and a 50 to 500 nm thick sublayer of SiO₂.The dielectric layer serves, for example, to passivate the first mesa and can, for this purpose, comprise a layer of Al₂O₃, since Al₂O₃ is impermeable to moisture. Furthermore, the dielectric layer can serve as an adhesion promoter for the planarization layer and, for this purpose, comprise a layer of SiO₂, since SiO₂ is an adhesion promoter for spin-on glass.

[0031] In an advantageous embodiment, the optoelectronic semiconductor device comprises a first contact structure for electrically connecting the first semiconductor layer and a second contact structure for electrically connecting the second semiconductor layer. Preferably, the first contact structure has a first bond pad arranged on a bottom surface of the optoelectronic semiconductor device, and the second contact structure has a second bond pad arranged on the bottom surface, the first and second bond pads being provided for external contacting of the optoelectronic semiconductor device. In particular, the first and second bond pads are each metallic layers. The first and second bond pads can each have multiple layers.For example, the first and second bond pads can each comprise at least one of the following layers: an adhesive layer, a reflective layer, a barrier layer, and an encapsulation layer. Suitable materials for the adhesive layer include, for example, Ti, Cr, Al, Mo, Ni, or W. Suitable materials for the reflective layer include, for example, Ag, Al, or Rh. Suitable materials for the barrier layer include, for example, Ti, Pt, Ni, Cr, Rh, or Ru. And the encapsulation layer can, for example, contain or consist of Au.

[0032] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor device, a substrate is provided having a structured surface. Furthermore, a sequence of semiconductor layers is provided, comprising a first semiconductor layer with a first surface, a second semiconductor layer with a first surface, a first main surface, a second main surface opposite the first main surface, and at least one side surface connecting the first and second main surfaces. The first surfaces of the first and second semiconductor layers are at least partially located on the first main surface, and the second main surface faces the structured surface of the substrate. A planarization layer is then deposited onto the structured surface. Finally, a directionally reflective layer is deposited onto the planarization layer.

[0033] According to at least one embodiment of the method, the carrier has structural elements on its structured surface which are spaced apart by gaps, wherein in a first region of the carrier the planarization layer is arranged in the gaps and extends in a vertical direction at least to the upper ends of the structural elements, wherein the planarization layer in the first region has a surface which faces the directionally reflecting layer and has a planar or concave curved shape.

[0034] According to an advantageous aspect of the process, the planarization layer is formed by first applying a volume of spin-on glass to the structured surface of the support and rotating the support so that the spin-on glass covers at least one side. In particular, a volume of 4 to 5 ml can be applied to the wafer. The wafer can then be rotated, preferably at a rotational speed of 1400 to 1600, and more specifically 1500, revolutions per minute. Subsequently, the volume of spin-on glass is cured, preferably at a temperature of 220 to 300°C for about 100 minutes. The planarization layer thus produced has a thickness of 1.5 to 2 µm. The process of applying a volume of spin-on glass, rotating the wafer, and curing the volume of spin-on glass can be repeated several times to increase the thickness of the planarization layer.

[0035] According to at least one embodiment, the planarization layer is formed by plasma-enhanced chemical vapor deposition (PECVD). The planarization layer can be formed from SiO₂ using PECVD with a tetraethyl orthosilicate (TEOS) precursor. In particular, the planarization layer can be formed by high-density plasma chemical vapor deposition (HDPCVD). HDPCVD is a special form of PECVD that uses an inductively coupled plasma (ICP) source to generate a higher plasma density than a standard parallel-plate PECVD system. The higher plasma density offers several advantages, including deposition at lower temperatures than with PECVD, typically 80 °C to 150 °C, higher layer quality at lower temperatures, and improved trench-filling capabilities to obtain better planarized layers.

[0036] In an advantageous variant of the process, the semiconductor layer sequence on at least one side surface is structured by wet chemical etching in such a way that it has structural elements.

[0037] In a preferred embodiment of the method, the semiconductor layer sequence is formed by an etching process, for example by dry chemical etching, with a first and second mesa.

[0038] The method described above is particularly suitable for the fabrication of the optoelectronic semiconductor devices described here. Features described in connection with the device therefore also apply to the method and vice versa.

[0039] The described optoelectronic semiconductor component can be used as a backlight unit for an LCD (Liquid Crystal Device) panel.

[0040] Further features, embodiments and advantages will become apparent from the following description of the exemplary embodiments in conjunction with the figures.

[0041] They show: Fig. 1A a schematic cross-sectional view of a section of an optoelectronic semiconductor device according to a first embodiment and the Fig. 1B and Fig. 1C Schematic representations of microscope images of parts of cross-sections of the optoelectronic semiconductor device according to the first embodiment, Fig. 2 a top view of the optoelectronic semiconductor device according to the first embodiment in an unfinished state, Fig. 3 a schematic representation of a microscope image of the underside of an optoelectronic semiconductor device according to a comparative example and Fig. 4 a schematic representation of a microscope image of part of a cross-section of the optoelectronic semiconductor device according to the comparative example, Fig. 5 and Fig. 6 schematic cross-sectional views of sections of optoelectronic semiconductor devices according to various comparative examples, Fig. 7 to 15 schematic cross-sectional views of sections of optoelectronic semiconductor devices according to various embodiments, Fig. 16 a schematic representation of a microscopic image of part of a cross-section of an optoelectronic semiconductor device according to a further embodiment.

[0042] In the illustrated embodiments and figures, identical, similar, or similarly functioning elements may be designated with the same reference numerals. The depicted elements and their proportions are not necessarily to scale; rather, individual elements may be exaggerated for clarity and / or better understanding.

[0043] Fig. Figure 1A shows a cross-sectional view of a section of an optoelectronic semiconductor device 1 along the in Fig. 2 shown line AA'. Fig. 1B and Fig. Figure 1C shows schematic representations of microscopic images of parts of cross-sections of the optoelectronic semiconductor device 1 according to the first embodiment along line AA'. The Fig. 1B and Fig. The images underlying 1C were acquired using a focused ion beam (FIB) microscope at an acceleration rate of 5.0 kV, whereby Fig. 1C an enlarged section from Fig. 1B shows.

[0044] The optoelectronic semiconductor device 1 comprises a support 2 and a sequence of semiconductor layers 3 arranged on the support 2. In the context of the present application, “arranged on (...)” means in a non-parallel direction, preferably following a vertical direction V. A principal extent plane of the support 2 is arranged perpendicular to the vertical direction V.

[0045] The support 2 has a structured surface 2A on one side facing the semiconductor layer sequence 3. The surface of the support 2 is structured at the structured surface 2A such that it has structural elements 2B. In particular, the structural elements 2B are arranged in a predetermined manner, preferably in a regular, non-random pattern. Due to its roughness, the structured surface 2A contributes to increasing the coupling efficiency of the optoelectronic semiconductor device 1. In particular, the refractive index difference between the semiconductor layer sequence 3 and the support 2 is linearly reduced by a "transition layer" formed at the structured surface 2A of the support 2.

[0046] The semiconductor layer sequence 3 comprises a first semiconductor layer 4, which is preferably a p-doped layer, further comprises a second semiconductor layer 6, which is preferably an n-doped layer, and further comprises an active zone 5 arranged between the first and second semiconductor layers 4, 6. The first semiconductor layer 4 has a first surface 4A facing away from the second semiconductor layer 6. The second semiconductor layer 6 has a first surface 6A facing away from the support 2.

[0047] The semiconductor layer sequence 3 has a first main surface 3A and a second main surface 3B opposite the first main surface 3A. The first surfaces 4A, 6A of the first and second semiconductor layers 4, 6 are at least partially located on the first main surface 3A of the semiconductor layer sequence 3. In particular, part of the first surface 6A of the second semiconductor layer 6 is covered by the active zone 5 and the first semiconductor layer 4 and is therefore not located on the first main surface 3A. Furthermore, the second main surface 3B faces the structured surface 2A of the support 2 and is preferably in direct contact with the structured surface 2A. The semiconductor layer sequence 3 also comprises at least one side surface 3C that connects the first and second main surfaces 3A, 3B.

[0048] The semiconductor layer sequence 3 preferably comprises a material based on nitride compound semiconductors, as mentioned above. And the active zone 5 is configured to emit blue or green light.

[0049] Furthermore, the optoelectronic semiconductor device 1 includes a directionally reflective layer 7, which is designed to reflect a major part of the radiation in a main direction or in a small angular range.

[0050] As mentioned above, the directional reflecting layer 7 comprises or consists of a dielectric material. The directional reflecting layer 7 can be a single layer or a multilayer comprising at least two sublayers with higher and lower refractive indices. Preferably, the directional reflecting layer 7 is a distributed Bragg reflector (DBR) layer. Suitable materials for the directional reflecting layer 7 or its sublayers are oxides such as SiO₂, TiO₂, Nb₂O₅, Al₂O₃, or nitrides such as Si₃N₄ or SiNₓ, where “x” denotes a non-stoichiometric amount of nitride, or fluorides such as MgF₂.Suitable thicknesses of the directionally reflective layer are in the range between 500 nm and 6000 nm, preferably in the range between 1000 nm and 5000 nm, particularly preferably between 1500 nm and 4500 nm, with deviations of 10% being tolerable.

[0051] Furthermore, the optoelectronic semiconductor device 1 comprises a planarization layer 8, which is arranged between the structured surface 2A and the directionally reflective layer 7. Advantageously, the planarization layer 8 helps to compensate for the structural elements 2B or irregularities present on the structured surface 2A of the substrate 2. The planarization layer 8 comprises spin-on glass and is transparent to the radiation emitted during operation from the active zone 5. Spin-on glass (SOG) is a material that is applied to a wafer as a liquid with SiO2 suspended in a solvent and subsequently cured. The solvent content of the liquid can be between 0.5 and 0.7, preferably 2 / 3.

[0052] In a first region I of the support 2, the planarization layer 8 is arranged in spaces 2C between the structural elements 2A such that a surface of the planarization layer 8 facing the structured surface 2A in first region I has a pattern complementary to that of the structured surface 2A. The structural elements 2B are completely embedded in the planarization layer 8 in first region I of the support 2. In a second region II of the support 2, portions of the semiconductor layer sequence 3 are arranged in the spaces 2C between the structural elements 2B. The support 2 preferably serves as the growth substrate and is most preferably made of sapphire.

[0053] The planarization layer 8 has a vertical extent d3, or thickness, which exceeds the maximum vertical extent d1, or thickness, of the semiconductor layer sequence 3. In other words, the planarization layer 8 projects beyond the semiconductor layer sequence 3 in the vertical direction V. The maximum vertical extent d1, or thickness, of the semiconductor layer sequence 3 can, for example, be between 5 and 12 µm and is preferably 9 µm. The planarization layer 8 is arranged on the side face(s) of the semiconductor layer sequence 3 and covers the first main face 3A of the semiconductor layer sequence 3.

[0054] A surface 8A of the planarizing layer 8, facing the directionally reflective layer 7, has a planar shape within the usual manufacturing tolerances. Advantageously, this configuration allows the directionally reflective layer 7 to be applied to a smooth surface and therefore exhibits a significantly higher reflection coefficient than without the planarizing layer (see the figures in the Fig. 3 to 7 illustrated embodiments).

[0055] Preferably, the optoelectronic semiconductor device 1 is a miniature sapphire flip chip with a size of approximately 200 × 200 µm. 2 , wherein the directionally reflecting layer 7 enables the device 1 to be turned around and a significantly high reflection to emit radiation laterally, i.e. on one or more side surfaces 1A of the optoelectronic semiconductor device 1, or on a top surface 1B.

[0056] As from the Fig. 1A, Fig. 1B, Fig. 1C and Fig. As can be seen in Figure 2, the semiconductor layer sequence 3 comprises a first, deep mesa 3D and a second mesa 3E, wherein the surfaces of the semiconductor layer sequence 3 at the mesas 3D and 3E are inclined, i.e., at an angle between 0° and 90°, to the main extension plane of the support 2. The vertical extent d2, or thickness, of the semiconductor layer sequence 3 at the first deep mesa 3E can be between 4 and 8 µm and is preferably 7 µm.

[0057] Furthermore, the first semiconductor layer 4 has a depression 9, and the second semiconductor layer 6 is arranged at the bottom of the depression 9 (see Fig. 2).

[0058] In connection with the Fig. Sections 3 to 6 describe in more detail the problems that exist with a component without a planarization layer.

[0059] The in Fig. Image 4 shown was taken with a focused ion beam (FIB) microscope at an acceleration rate of 500 kV and a width of 25.61 µm.

[0060] Fig. Figure 3 shows a bottom surface 1C of an optoelectronic semiconductor device 1 according to a comparative example, which has a semiconductor layer sequence with a first mesa 3D and a second mesa 3E. The optoelectronic semiconductor device 1 comprises a first contact structure 10 with a first bond pad 11 and a second contact structure 14 with a second bond pad 15.

[0061] Fig. Figure 4 shows a cross-section along line B'B of the in Fig. Figure 3 shows the optoelectronic semiconductor device 1. The optoelectronic semiconductor device 1 comprises a directionally reflective layer 7, which is approximately 4 µm thick, a semiconductor layer sequence 3, and a substrate 2 with structural elements 2B. The rough substrate 2 reduces the effective reflection coefficient of the directionally reflective layer 7 at the first deep mesa 3D. This results in higher radiation transmission (see arrows) and thus higher light intensity on a non-reflective plate on which the optoelectronic semiconductor device 1 can be mounted.

[0062] The Fig. 5 and Fig. Figure 6 shows schematic cross-sectional views of optoelectronic semiconductor devices 1 according to comparative examples, in which the directionally reflecting layer 7 at the first mesa 3D is rough as a result of the rough substrate 2.

[0063] The optoelectronic semiconductor device 1 according to the in Fig. The example shown in Figure 5 comprises a first contact structure 10 with a TCO layer 12 that is applied directly to the first semiconductor layer 4.

[0064] Transparent conductive oxides (TCOs) are transparent conductive materials, typically metal oxides such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, or indium tin oxide (ITO). Besides binary metal-oxygen compounds like ZnO, SnO₂, or In₂O₃, ternary metal-oxygen compounds such as Zn₂SnO₄, CdSnO₃, ZnSnO₃, MgIn₂O₄, GaInO₃, Zn₂In₂O₅, or In₄Sn₃O₁₂, or mixtures of various transparent conductive oxides also belong to the TCO group. Furthermore, TCOs do not necessarily have a stoichiometric composition and can also be p- or n-doped.

[0065] Furthermore, the first contact structure 10 comprises a metal layer 13A arranged on the TCO layer 12 and a metallic via 13B arranged between the TCO layer 12 and the bond pad 11. Corresponding to the first contact structure 10, the second contact structure 14 can also comprise a TCO layer and a metallic via (not shown) arranged between the TCO layer and the bond pad 15. In particular, the metallic vias 13B are formed from the same material as the bond pads 11 and 15.

[0066] In particular, the metallic via(s) 13B is / are laterally surrounded by the directionally reflective layer 7. The metallic via(s) 13B and / or the bond pads 11, 15 can have a significant influence on the total reflection occurring in the device 1.

[0067] The optoelectronic semiconductor device 1 according to the in Fig. The example shown in Figure 6 comprises a first contact structure 10 with a TCO layer 12 deposited directly onto the first semiconductor layer 4. Furthermore, the first contact structure 10 includes a metal layer 13A located in a recess 7A of the directionally reflective layer 7, which contacts the TCO layer 12 at the bottom of the recess 7A. A metallic via 13B is arranged between the metal layer 13A and the bond pad 11, the metallic via 13B being embedded in a passivation layer 16 located between the metal layer 13A and the bond pad 11.

[0068] According to the first contact structure 10, the second contact structure 14 can also contain a TCO layer, a metal layer and a metallic via (not shown).

[0069] This in conjunction with the ones in the Fig. The optoelectronic semiconductor device 1 described in the embodiments shown in Figures 1 and 7 to 16 can comprise first and second contact structures as described in the Fig. 3 to 6 are described.

[0070] In connection with the Fig. Sections 7 to 16 describe further embodiments of optoelectronic semiconductor devices 1. In particular, differences from the first embodiment of an optoelectronic semiconductor device 1 are explained.

[0071] The optoelectronic semiconductor device 1 according to the second embodiment of Fig. 7 comprises a planarization layer 8 that covers the first region I of the support 2 and extends beyond the upper ends of the structural elements 2B, but not beyond the second semiconductor layer 6 in the vertical direction V. The planarization layer 8 can have a thickness d3 between 2 µm and 3 µm, preferably 2.5 µm. Furthermore, the structural elements 2B can have a vertical extent of approximately 2 µm. The side faces 3C of the semiconductor layer sequence 3 are only partially covered by the planarization layer 8.

[0072] The covering of the structural elements 2B by the planarization layer 8 is sufficient to create a smooth surface 8A onto which the directionally reflective layer 7 is applied, resulting in reduced transmission losses. With a thickness d3 of 2 µm to 3 µm, it is possible to produce the planarization layer 8 in a few, in particular one or two, process steps.

[0073] The optoelectronic semiconductor device 1 according to the third embodiment of Fig. 8 comprises a planarization layer 8 that covers the first and second regions I, II of the support 2. In particular, the planarization layer 8 extends from the structured surface 2A in the first region I across the side surface(s) 3C of the semiconductor layer sequence 3 to the first main surface 3A of the semiconductor layer sequence 3. Preferably, the side surface(s) 3C and the first main surface 3A of the semiconductor layer sequence 3 are completely covered by the planarization layer 8. Furthermore, the structural elements 2B are completely embedded in the planarization layer 8.

[0074] Preferably, the thickness d3 of the planarization layer 8 on the first main surface 3A is less than on the side surface(s) 3C. Furthermore, the thickness d3 of the planarization layer 8 on the side surface(s) 3C is less than on the structured surface 2A in the first region I. This can be a consequence of the fabrication process, in which the material volume for producing the planarization layer 8 is arranged on the first mesa 3D and rotated such that it creeps from the structured surface 2A, across the side surface(s) 3C, to the first main surface 3A of the semiconductor layer sequence 3.

[0075] In addition to the advantage of reduced transmission losses due to the smooth surface 8A of the planarization layer 8, which faces the directionally reflecting layer 7 in the first region I, the planarization layer 8 of the third embodiment has the effect of electrical insulation of the first and second mesa 3D, 3E.

[0076] The optoelectronic semiconductor device 1 according to the fourth embodiment of Fig. 9 comprises a planarization layer 8 extending from the structured surface 2A in the first region I to the side surface(s) 3C of the semiconductor layer sequence 3. In particular, the side surface(s) 3C of the semiconductor layer sequence 3 is / are completely covered by the planarization layer 8, with the first principal surface 3A being free of the planarization layer 8.

[0077] Advantageously, the smooth surface 8A of the planarization layer 8, which faces the directionally reflecting layer 7 in the first region I, contributes to reducing transmission losses and thus light absorption.

[0078] Fig. Figure 10 shows an arrangement of optoelectronic semiconductor devices 1 according to a fifth embodiment prior to singulation along a singulation line S or a separation trench. The material volume for producing the planarization layers 8 of the optoelectronic semiconductor devices 1 can be arranged on the first mesas 3D of adjacent optoelectronic semiconductor devices 1, the first mesas 3D together forming a depression 17 in which the material volume is collected. The depression 17 is narrow, with a width w of 15 µm to 25 µm, preferably 20 µm, such that the material volume, which creeps over the side surfaces 3C during rotation, is formed with a concavely curved surface 8A. Thus, in the finished optoelectronic semiconductor devices 1, the surface 8A of the planarization layer 8 facing the directionally reflecting layer 7 is concavely curved.The applied directionally reflective layer 7 also has a concave curved shape. The planarization layer 8 thus formed covers the structured surface 2A in the first region I and the side surface 3C, but leaves the first main surface 3A uncovered. Furthermore, the structural elements 2B are completely embedded in the planarization layer 8. Preferably, the thickness d3 of the planarization layer 8 is between 3 µm and 5 µm, preferably 4 µm.

[0079] The in the Fig. The optoelectronic semiconductor devices 1 shown in Figures 11 to 13 are essentially designed as in the fifth embodiment, but additionally feature an omnidirectionally reflective layer 18 arranged on a side of the directionally reflective layer 7 facing away from the support 2. In particular, the omnidirectionally reflective layer 18 is a metallic layer. The omnidirectionally reflective layer 18 preferably contains Al, Rh, or Ag. The omnidirectionally reflective layer 18 can further reduce transmission losses.

[0080] In the Fig. In the sixth embodiment shown in Figure 11, the omnidirectionally reflective layer 18 covers an area of ​​the directionally reflective layer 7 that lies above the first area I of the carrier 2 and part of the second area II. This further reduces the transmission losses in the first area I.

[0081] In the seventh, in Fig. In the embodiment shown in 12, the omnidirectionally reflective layer 18 covers an area of ​​the directionally reflective layer 7 that lies above the first and second areas I, II of the carrier 2, thus ensuring high reflectivity on the entire component 1.

[0082] In the eighth, in Fig. In the embodiment shown in Figure 13, the omnidirectionally reflective layer 18 covers an area of ​​the directionally reflective layer 7 that lies above the second area II of the carrier 2, thus ensuring good reflectivity in the radiation-generating area in which the active zone 5 is located.

[0083] The in Fig. The optoelectronic semiconductor device 1 shown in Figure 14 is essentially designed as in the first embodiment, but additionally comprises structural elements 19 on the side surface(s) 3C and on the first main surface 3A. The structural elements 19 can, for example, have the form of prisms. Preferably, the structural elements 19 have a size ranging from the nanoscale to several micrometers. The structural elements 19 arranged on the first mesa 3D and on the second mesa 3E increase the light yield there (see arrows).

[0084] The in Fig. The optoelectronic semiconductor device 1 shown in Figure 15 is essentially designed as in the first embodiment, but additionally comprises a dielectric layer 20 arranged between the planarization layer 8, the semiconductor layer sequence 3, and the support 2. The dielectric layer 20 covers the support 2 in the first region I. Furthermore, the dielectric layer 20 covers the side surfaces 3C and the first main surface 3A of the semiconductor layer sequence 3.

[0085] The dielectric layer 20 can be a single layer or a multilayer. Its thickness can range from 50 nm to 650 nm. The dielectric layer 20 can comprise or consist of at least one of the following materials: Al₂O₃, SiO₂, TiO₂, silicon nitride, silicon oxynitride, Nb₂O₅, or MgF₂. For example, the dielectric layer 20 can be multilayered and comprise a 40 to 120 nm thick sublayer of Al₂O₃ and a 50 to 500 nm thick sublayer of SiO₂. The dielectric layer 20 is intended, for example, for the passivation of the first Mesa 3D and can therefore comprise a layer of Al₂O₃, since Al₂O₃ is moisture-resistant. Furthermore, the dielectric layer 20 can serve as an adhesion promoter for the planarization layer 8 and can contain a layer of SiO2 for this purpose, since SiO2 is an adhesion promoter for spin-on glass. Fig. Figure 16 shows a schematic representation of a microscopic image of part of a cross-section of an optoelectronic semiconductor device according to a further embodiment. The image, on which Fig. 16 based, was recorded with a Focused-Ion-Beam (FIB) microscope at an acceleration rate of 2.0 kV.

[0086] The in Fig. The optoelectronic semiconductor device 1 shown in Figure 16 corresponds essentially to the first embodiment, but includes a planarization layer 8 containing SiO2, which is formed by a PECVD process using a TEOS precursor. The planarization layer 8 has a vertical extent d3 of approximately 3.6 µm between the structural elements 2B and a vertical extent d4 of approximately 2.6 µm on the structural elements 2B. The vertical extent d4 is thus reduced by approximately 1 µm compared to the vertical extent d3. The vertical extent d5 of the structural elements 2B is approximately 1.5 µm. The gap 2C between two structural elements 2B can have a lateral extent a of approximately 2.9 µm. In general, the thicker the planarization layer 8, the smaller the difference in vertical extent. In the Fig.In the embodiment shown in Figure 16, the planarization layer 8 comprises three sublayers, wherein the first sublayer closest to the support 2 has a thickness d6 of about 1.2 µm, the second sublayer arranged on the first sublayer has a thickness d6' of about 1.15 µm and the third sublayer arranged on the second sublayer has a thickness d6'' of about 1.23 µm. Reference symbol list 1 optoelectronic semiconductor device 1A Side surface 1B Top 1C Underside 2 carriers 2A structured surface 2B Structural element 2C gap 3 Semiconductor layer sequence 3A first main area 3B second main area 3C side surface 3D first Mesa 3E second mesa 4 first semiconductor layer 4A First surface of the first semiconductor layer 5 active zones 6 second semiconductor layer 6A First surface of the second semiconductor layer 7 directionally reflective layer 7A Advanced Level 8 Planarization layer 8A Surface 9 In-depth study 10 First contact structure 11 Bond pad of the first contact structure 12 TCO layer 13A Metal layer 13B metallic through-hole 14 second contact structure 15 Bond pad of the second contact structure 16 Passivation layer 17 Further Study 18 omnidirectional reflective layers 19 structural element 20 dielectric layer I first area of ​​the carrier II second area of ​​the carrier a lateral extension d1, d2, d3, d4, d4', d5, d6, d6', d6'' vertical extent S singulation line V vertical direction w width

Claims

[1] Optoelectronic semiconductor device (1) comprising - a carrier (2) having a structured surface (2A), - a semiconductor layer sequence (3) arranged on the support (2), wherein the semiconductor layer sequence (3) comprises the following: - a first semiconductor layer (4) with a first surface (4A), - a second semiconductor layer (6) with a first surface (6A), - a first main surface (3A) and a second main surface (3B) opposite the first main surface (3A), wherein the first surfaces (4A, 6A) of the first and second semiconductor layers (4, 6) are at least partially arranged on the first main surface (3A) and wherein the second main surface (3B) faces the structured surface (2A) of the support, - at least one side surface (3C) that connects the first and second main surfaces (3A, 3B), - a directionally reflective layer (7) and - a planarization layer (8) arranged between the structured surface (2A) and the directionally reflecting layer (7), wherein: - the structured surface (2A) is arranged on one side of the support (2) facing the semiconductor layer sequence (3), - the support (2) has structural elements (2B) on the structured surface (2A) which are spaced apart by spaces (2C), wherein in a first region (I) of the support (2) the planarization layer (8) is arranged in the spaces (2C) and extends in a vertical direction (V) at least to the upper ends of the structural elements (2B) and - the planarization layer (8) in the first region (I) has a surface (8A) facing the directionally reflecting layer (7), wherein the surface (8A) has a planar or concave curved shape. [2] Optoelectronic semiconductor device (1) according to the preceding claim, wherein the carrier (2) projects laterally beyond the second semiconductor layer (6) in the first region (I). [3] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein parts of the semiconductor layer sequence (3) are arranged in a second region (II) of the support (2) in the spaces (2C) between the structural elements (2B). [4] Optoelectronic semiconductor device (1) according to any of the preceding claims, wherein the planarization layer (8) comprises SiO2 and / or spin-on glass. [5] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein the planarization layer (8) is arranged on the at least one side surface (3C) of the semiconductor layer sequence (3). [6] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein the planarization layer (8) at least partially covers the at least one side surface (3C) of the semiconductor layer sequence (3). [7] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein the planarization layer (8) at least partially covers the first main area (3A) of the semiconductor layer sequence (3). [8] Optoelectronic semiconductor device (1) according to one of the preceding claims, further comprising an omnidirectionally reflective layer (18) arranged on a side of the directionally reflective layer (7) facing away from the support (2). [9] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein the semiconductor layer sequence (3) on the at least one side surface (3C) is structured such that it has structural elements (19). [10] Optoelectronic semiconductor device (1) according to one of the preceding claims, wherein the second semiconductor layer (6) extends laterally beyond the first semiconductor layer (4). [11] Optoelectronic semiconductor device (1) according to any of the preceding claims, comprising a dielectric layer (20) arranged between the planarization layer (8) and the semiconductor layer sequence (3) and / or the support (2). [12] Method for manufacturing an optoelectronic semiconductor device (1) comprising the following steps: - Providing a carrier (2) having a structured surface (2A), - providing a semiconductor layer sequence (3) comprising - a first semiconductor layer (4) with a first surface (4A), - a second semiconductor layer (6) with a first surface (6A), - a first main surface (3A) and a second main surface (3B) opposite the first main surface (3A), wherein the first surfaces (4A, 6A) of the first and second semiconductor layers (4, 6) are at least partially arranged on the first main surface (3A) and wherein the second main surface (3B) faces the structured surface (2A) of the support (2), - at least one side surface (3C) that connects the first and second main surfaces (3A, 3B), - Applying a planarization layer (8) to the structured surface (2A) and - Applying a directionally reflective layer (7) to the planarization layer (8), wherein: - the support (2) has structural elements (2B) on the structured surface (2A) which are spaced apart by spaces (2C), wherein in a first region (I) of the support (2) the planarization layer (8) is arranged in the spaces (2C) and extends in a vertical direction (V) at least to the upper ends of the structural elements (2B) and - the planarization layer (8) in the first region (I) has a surface (8A) facing the directionally reflecting layer (7), wherein the surface (8A) has a planar or concave curved shape. [13] Method according to the preceding claim, wherein the planarization layer (8) is formed by applying a volume of spin-on glass to the structured surface (2A) in a first area (I) of the support (2) and rotating the support (2) such that the spin-on glass covers the at least one side surface (3C). [14] Method according to claim 12, wherein the planarization layer (8) is formed by plasma-enhanced chemical vapor deposition. [15] Method according to one of claims 12 to 14, wherein the semiconductor layer sequence (3) on the at least one side surface (3C) is structured by wet chemical etching such that it has structural elements (19).

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