FAST HIGH-FREQUENCY ENCLOSURE

Abstract

Component housing comprising: a chip carrier (510) containing a cavity and one or more microwave waveguides configured to transmit signals; and a chip (220) having one or more contact pads arranged within the cavity of the chip carrier (510); a block configured to press the chip (220) into the cavity of the chip carrier (510), wherein: each contact pad is aligned with a corresponding connector contact pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier (510); at least one of the one or more contact pads is connected to the connector contact pad of the corresponding microwave waveguide by means of an overlapping capacitive coupling between the at least one contact pad and the aligned corresponding connector contact pad of the microwave waveguide;and the block comprises one or more springs which are functionally capable of pressing the chip (220) onto the cavity of the chip carrier (510), wherein a distance between the at least one contact surface and the aligned corresponding connector contact surface of the microwave waveguide is controllable on the basis of the applied mechanical pressure between the chip (220) and the chip carrier (510).

Description

BACKGROUNDTechnical FieldThe present disclosure relates generally to chip packaging (packaging) and, more particularly, to efficient packaging of superconducting devices.Description of the Prior ArtIn order for a semiconductor chip to be able to exchange data with the outside world, it is usually encapsulated in a carrier housing which not only enables data transmission with external components, but also protects the chip both physically and thermally. Conventional packaging techniques typically rely on a "permanent" connection between the package and the packaged chip. Common connections between the on-chip pads and the package connector pads may include permanent soldering, thermosonic bonding, or other permanent bonding techniques, thereby rendering subsequent disconnection and replacement impractical.DE 11 2016 001 769 T5 describes an arrangement for a quantum data processing unit. EP 3 111 380 B1 describes a quantum computer system comprising a control system and a quantum processor unit, wherein the control system generates control information for different devices in the quantum processor unit, each having different operating frequencies, and a multiplexer system is used to transmit the signals to the respective devices.SUMMARYAccording to an embodiment, a device package comprises a chip carrier including a cavity and one or more microwave waveguides configured to pass signals. There is a chip that is one or more contact pads and is disposed within the cavity of the chip carrier. Each contact pad is aligned with a corresponding connector contact pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is connected to the pad of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one pad and the aligned respective connector pad of the microwave waveguides.In one embodiment, the chip is a quantum chip.In an embodiment, the chip carrier is a printed circuit board (PCB).In one embodiment, there is a block configured to push the chip into the cavity of the chip carrier. The chip may be a quantum chip and the block may be a thermalization block that is operatively capable of thermalizing the quantum chip.In an embodiment, the block comprises one or more springs operatively capable of urging the chip onto the cavity of the chip carrier.In one embodiment, the microwave waveguides are superconductive and comprise either a superconductor or copper coated with a superconductor. For example, the microwave waveguide may comprise niobium or copper coated with a superconductor such as tin.In an embodiment, the superconducting microwave waveguides of the chip carrier are guided in three dimensions to a connector plane comprising a ball grid array (BGA).In an embodiment, an alignment between the chip and the cavity of the chip carrier is within 0.2 times a width of the connector contact pad.In an embodiment, the chip carrier comprises a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a particular chip including one or more contact pads located within the at least one additional cavity. Each pad of the particular chip is aligned with a corresponding connector pad of a microwave waveguide of the chip carrier. At least one of the one or more contact pads of the particular chip is connected to its aligned corresponding connector contact pad of the chip carrier by means of an overlapping capacitive coupling.In one embodiment, the chip is a quantum chip and the particular chip is not a quantum chip.According to an embodiment, a chip packaging system includes a chip carrier including a cavity and one or more microwave waveguides configured to pass signals. An interposer chip (interposer chip) includes one or more pads and is disposed within the cavity of the chip carrier. One or more chips are bonded to the interposer chip. Each contact pad of the interposer die is aligned with a corresponding microwave waveguide connector of the one or more microwave waveguides of the die carrier. At least one of the one or more pads is connected to the pad of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one pad and the aligned respective connector pad of the microwave waveguide.In one embodiment, the chip is a quantum chip and the chip carrier is a printed circuit board (PCB).In one embodiment, there is a block configured to push the interposer chip into the cavity of the chip carrier.In an embodiment, the block comprises one or more springs operatively capable of urging the interposer chip onto the cavity of the chip carrier.According to an embodiment, a method of packaging a chip comprises providing a chip carrier including a cavity and one or more microwave waveguides for propagating signals. A chip having one or more contact pads is led into the cavity of the chip carrier. Each pad of the chip is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is connected to the connector of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one pad and the aligned respective connector pad of the microwave waveguide.In an embodiment, the chip is pressed into the cavity of the chip carrier by a thermalization block.In an embodiment, the pressing comprises one or more springs of the thermalization block pressing the chip onto the cavity of the chip carrier.In an embodiment, the chip carrier comprises a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a particular chip including one or more contact pads located within the at least one additional cavity. Each pad of the particular chip is aligned with a corresponding connector pad of a microwave waveguide of the chip carrier. At least one of the one or more contact pads of the particular chip is connected to its aligned corresponding connector contact pad of the chip carrier by means of an overlapping capacitive coupling.In one embodiment, the functionality of the chip is determined. After determining that the chip is defective, the chip is removed and replaced with a new chip.These and other features will become apparent from the following detailed description of illustrated embodiments of the specification, which is to be read in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe drawings illustrate illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition to or in place of. Details that may be obvious or unnecessary may be omitted to provide room for more effective illustration. Some embodiments may be practiced with additional components or steps and / or without all of these illustrated components or steps. The occurrence of the same reference number in different drawings denotes the same or similar components or steps. FIG. 1A provides a perspective view of a capped chip according to an illustrative embodiment. FIG. 1B provides a top view of the circuit board of FIG. 1A with a cutout according to an illustrative embodiment.FIGS. 1C and 1D illustrate a top view and a bottom view, respectively, of the chip including a waveguide output point according to an illustrative embodiment. FIG. 2A provides a cross-sectional view of a housing according to an illustrative embodiment. FIG. 2B illustrates a chip carrier cutout according to an illustrative embodiment configured to receive a chip. FIG. 3 illustrates a multi-chip configuration of a package according to an illustrative embodiment. FIG. 4 provides a cross-section of a chip connected to a circuit board using wire bonds, according to an illustrative embodiment. FIG. 5 provides a cross-sectional view of a chip connected to a circuit board by means of capacitive coupling, according to an illustrative embodiment. FIG. 6 is a cross-sectional view of a chip connected to a circuit board including a spring-loaded thermalization structure, according to an illustrative embodiment. FIG. 7 is a cross-sectional view of a structure including a chip connected to a circuit board including a carrier chip according to an illustrative embodiment.FIGS. 8A to 8C provide exemplary simulation results of coupling capacitance between the pad of a chip and a connector pad on a circuit board at a fixed vertical distance between the coplanar waveguides of 100 nm.DETAILED DESCRIPTIONOverviewIn the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. It should be understood, however, that the present teachings may be practiced without such details. In other instances, well-known methods, operations, components, and / or circuits are described at a relatively high level without details in order to avoid unnecessarily obscuring aspects of the present teachings.In one aspect, spatially relative terminology such as "front," "rear," "top," "bottom," "below," "below," "bottom / bottom / bottom," "above," "top / top / top," "lateral / lateral / lateral," "left / left," "right / right / right," and the like is used with reference to the orientation of the described figures. Since components of embodiments of the disclosure may be positioned in a number of different orientations, directional terminology is used for purposes of illustration and is in no way limiting. Therefore, it is to be understood that spatially relative terminology is intended to include different orientations of the unit in use or operation in addition to the orientation depicted in the figures. For example, if the unit in the figures is turned over, elements described as "below" or "below" other elements would then be oriented "above" the other elements or features. Thus, for example, the term "below" may include an orientation that is above as well as below. The unit may be otherwise oriented (rotated 90 degrees or viewed or referred to in other orientations) and the spatially related descriptors used herein should be interpreted accordingly.As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to a first surface of a chip.As used herein, the term "vertical" describes an orientation that is perpendicular to a first surface of a chip, a chip carrier, or a semiconductor body.As used herein, the terms "coupled / connected" and / or "electrically coupled / connected" are not intended to mean that the elements must be directly coupled / connected to each other, but intervening elements may be provided between the "coupled / connected" or "electrically coupled / connected" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low impedance electrical connection between the elements that are electrically connected together.Although the terms "first / first / first", "second / second / second", etc. may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and likewise a second element could be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.Example embodiments are described herein with reference to cross-sectional views that are schematic views of idealized or simplified implementations (and intermediate structures). Thus, deviations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, regions illustrated in the figures are schematic in nature and do not necessarily illustrate the actual shape of a region of a unit and do not limit the scope of protection.It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described below can be combined with elements of other embodiments.The present disclosure relates generally to fast and easily interchangeable chip packaging. By way of example and not limitation, the concepts presented herein are discussed in the context of quantum technology and quantum chips, although it should be understood that these teachings may also be applied to other types of chips. As regards quantum technology, the electromagnetic energy associated with a qubit can be stored, for example, in so-called Josephson junctions and in the capacitive and inductive elements used to form the qubit. In other examples, spin qubits may be present, which may be coupled to resonators or topological qubits, microfabricated ion traps, etc. Other types of microwave components that can be matched or easily replaced are also supported by the teachings set forth herein, including (and without limitation) circulators, isolators, amplifiers, filters, active control electronics such as rapid single flux quantum (RSFQ), etc.In one example, to read out the qubit state, a microwave signal is applied to the microwave readout resonator, which connects the qubit at the resonator frequency. The transmitted (or reflected) microwave signal passes through several heat isolation stages and low noise amplifiers used to block or reduce the noise and improve the signal-to-noise ratio. The amplitude and / or phase of the returned / output microwave signal carries information about the qubit state, such as whether the qubit is dephased to the ground state or excited state. The microwave signal carrying the quantum information about the qubit state is normally weak (e.g. on the order of a few microwave photons). Various circuits and techniques may be used to measure this weak signal. For example, low-noise quantum limited amplifiers (QLAs) such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs) may be used as preamplifiers at the output of the quantum system to improve the signal-to-noise ratio of the output chain by adding the minimum amount of noise specified by the quantum mechanics. In addition to Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers such as Josephson circulators, Josephson isolators and Josephson mixers may be used in scalable quantum processors.The ability to contain multiple qubits is crucial to be able to realize the potential of quantum computers. Applicants have found that to increase the computing power and reliability of a quantum computer, various levels of processing can be done. First, this applies to the qubit number itself. In principle, the more qubits present in a quantum processor, the more states can be manipulated and stored. The second are low error rates, which is relevant to reliably manipulating qubit states and performing successive operations to provide consistent results and not just unreliable data. Third, qubit technology is an area that is still under development, and it is still a problem to provide a qubit having a predetermined frequency with high accuracy. For example, in some scenarios, consistent generation of a qubit having a center frequency of 5.20 GHz may not be achieved multiple times. It would therefore be desirable to have a modular system with multiple quantum chips to be able to easily exchange qubits that do not have the desired center frequency or are simply defective.Therefore, to improve the fault tolerance of a quantum computer system, a large number of physical qubits should be used to store a logical quantum bit. This makes the local information independent of the local location, so that the quantum computer is less susceptible to local errors and the performance of self-basis measurement of qubits, similar to parity checks on conventional computers, thereby achieving a more fault tolerant quantum bit.In order for a semiconductor chip such as a quantum chip to be able to exchange data with the outside world, it is usually connected to or encapsulated in a carrier housing, which not only enables the data transmission but also protects the quantum chip both physically and thermally. Various problems may arise with current carrier housings. For example, conventional bonding is a time-consuming and resource-intensive process that may not provide suitable impedance matching in the transition between a chip carrier, such as a printed circuit board (PCB), and the chip. Further, conventional bonds may reduce the ability to provide a cavity for efficiently guiding the chip onto the PCB or for providing sufficient access to the chip surface in question for treatment or inspection purposes.Conventional capping techniques may include through-silicon vias (TSVs) that may involve manufacturing issues and impact uniformity during the manufacturing process. The package may even result in stress on the chip during cooling. For example, point-like forces on the chip, such as spring contact pins, may lead to chip breakage. Differences in coefficients of expansion between the chip and the package may load the chip (e.g., laterally). Furthermore, in conventional quantum chip packages, the overlap of lossy / normal materials with the different modes of qubits may induce losses, collectively referred to herein as "induced decoherence of the package.".Concepts discussed herein provide various improvements for encapsulating chips such as quantum chips, as will be described in more detail below. For example, due to independence from physical bonding between the contact pads of the chip and the corresponding connector contact pads on the chip carrier such as a PCB, the effort and time to connect the chip and the PCB may be substantially reduced. The simplicity and flexibility in removing chips from the PCB allows chips to be easily individually replaced with other chips that meet desired criteria. Such flexibility may be particularly helpful in uniformity testing and material assessment, for example. In addition, chips can be easily replaced with those having a more desirable qubit frequency, since no physical bonds need to be removed and reattached during the replacement. The chip carrier and corresponding connector pads can be readily reused due to the lack of physical bonding wires connected between the chip and the PCB. Since the chip is not mechanically fixed to the chip carrier as in conventional packages, the stress during cooling is mitigated. Further, the teachings set forth herein readily enable modular multichip units.The techniques described herein may be implemented in a variety of ways. Example implementations are provided below with reference to the following figures.Example Capping ArchitecturesFigures 1A-1D together provide an overview of a system illustrating various aspects of the present capping concepts according to an illustrative embodiment. More specifically, FIG. 1A provides a perspective view of a capped chip 100A. In various scenarios, a capped chip may operate at room temperature or at cryogenic temperatures. The coaxial lines 102 may be connected to various test and measurement devices (e.g., operating at room temperature) to determine whether one or more chips connected to the chip carrier should be replaced by simply removing and plugging on the chip described herein. In various embodiments, the leads on the chip carrier may be microstrips and / or coplanar waveguides (CPWs). In an embodiment, the chip carrier is a PCB.FIG. 1B provides a top view 100B of the PCB of FIG. 1A including a cutout that is operatively capable of receiving a chip 100C. A chip 100C may be placed (e.g., plugged) directly onto the connector pads of the PCB (e.g., coplanar waveguide (CPW) lines in the PCB). In this regard, FIGS. 1C and 1D illustrate a top view and a bottom view, respectively, of the chip including a waveguide launcher (waveguide launcher) 130. There are equivalent waveguide output points on the PCB 100B facing the waveguide output points (e.g., 130) of the chip. For example, the center line in the waveguide output point 130 is the signal line and the outer two lines are ground. Each waveguide output point acts as a pad connected by capacitive coupling.Reference is now made to FIG. 2A, which provides a cross-sectional view of a housing 200A, according to an illustrative embodiment. FIG. 2A includes a chip 220 connected to a PCB for data transfer purposes by means of capacitive coupling between the pads on the chip 220 and the corresponding connector pads on the PCB 228. The actual connector pads and the on-chip pads are not shown in FIG. 2A, but will be discussed in more detail later, inter alia in the context of FIG. 2B. For example, by means of capacitive coupling, signals from the chip 220 are transmitted via the connector pads on the PCB 228 and pass through a CPW leading to initial pads of the PCB 228. Two fasteners 242 and 244 are used to press the chip into the PCB cavity and align the chip, PCB, and thermalization block with each other (discussed in more detail in the context of FIG. 5 ). These initial pads on the chip 220 are respectively aligned with corresponding connector pads on the PCB 228 and are capable of exchanging data by sending microwave signals using capacitive coupling. In this regard, FIG. 2B illustrates a chip carrier (e.g., PCB) including a cutout 200C configured to receive a chip 200B. For example, the chip 200B may be placed (e.g., flipped) on the PCB cutout 200C with the pads on the chip 130 (e.g., sometimes referred to herein as waveguides or waveguide output points) aligned with the corresponding connector pads on the PCB in the cutout 200C.Accordingly, the chip (which may be a quantum chip) may be placed directly (e.g. as a flip chip) on a recess of a chip carrier (e.g. PCB) without requiring a physical connection between the contact pads of the chip and the connector pads on the chip carrier. For example, the architectures described herein do not require permanent soldering, permanent wire, thermosonic, or other permanent bond between the chip and the PCB. Instead, the chip 200B is flipped over and positioned on the cavity of the chip carrier such that the contact pads on the chip are directly aligned with and face the connector contact pads on the chip carrier (e.g., PCB). The actual transfer of signals between a pad on the chip and its corresponding connector on the chip carrier is done by means of capacitive coupling (i.e. a large overlap capacitance between the pad on the chip and the corresponding connector on the PCB). The chip and PCB are held together in a non-invasive and non-durable and easily removable manner to cap the chip, as will be discussed in more detail below.Thus, the capacitive coupling between the pads (e.g., waveguide output points) on the chip and the corresponding connector pads on the PCB allows data transfer between the chip and the PCB. The PCB's CPWs may be used to route signals between different chips and / or devices. In one embodiment, superconducting lines and / or vias may be used in the PCB (e.g., tin-plated copper) to route signals in three dimensions and / or connect the signals to a connector plane (e.g., ball grid array).In one embodiment, the chip 200B is aligned laterally to a degree better than ~0,2* w, where w is the width of the connector pad (e.g., capacitor pad). For example, the alignment is better than 50 μm. Applicants have determined that such a tolerance provides adequate overlap between the die pads and the connector pads on the chip carrier (e.g., PCB that includes a cutout for receiving the die) such that a desired overlap capacitance is achieved for reliable capacitive coupling. Such alignment is provided by making a precise cut-out of the PCB 200C into which the chip 200C is routed. The chip 200B is pressed against the PCB to minimize the distance "d" (see FIG. 5 ) between the contact surface on the chip and its corresponding connector on the PCB. In various embodiments, the minimization of the distance d may be realized with a spring-based mechanism or thermal structure (e.g., copper block) that clamps the chip 200B and the PCB between two parts with a fastener (e.g., screw, etc.). These concepts will be discussed in more detail later.Although a chip carrier configured to receive a single chip is exemplarily shown in FIGS. 1A and 2B, it should be understood that the teachings herein are not limited thereto. In this regard, reference is now made to FIG. 3 which illustrates a multi-chip configuration 300 of a package according to an illustrative embodiment. In various embodiments, the multichip configuration 300 may comprise an array of similar chips (e.g., qubit chips) 302 or a combination of different types of chips (e.g., control logic, amplifiers, readout circuits, power supply, quantum chip, etc.) connected to the PCB 350 for data transfer purposes by means of capacitive coupling between the pads of the chips 302- 324 and their corresponding connector pads on the multichip PCB 350. Two or more of the chips 302- 324 may communicate with each other via capacitive coupling between the pads on the chips and the connector pads on the PCB 350. If any of the chips 302-324 are not functioning properly, this chip can be easily replaced with another chip by quickly removing the old chip and inserting the new chip. Such flexibility is achieved by not having the chips 302- 324 permanently connected to the PCB 350, but capacitively coupled. In this way, the functionality of the multichip configuration 300 may be enabled and easily maintained over time.To better understand the features of the teachings listed herein, it may be helpful to provide a comparison to a known capping technology. To this end, FIG. 4 provides a cross-section of a chip connected to a PCB 410 by wire bonds 402. A structure 400 includes a thermalization structure 414, sometimes referred to as a (e.g., copper) die pad, that is operable to hold a chip 406 over a cavity 416. The quantum chip 406 is itself physically connected to the PCB 410 using durable wire bonds (e.g., 402). Typically, a shield 404 is present that is functionally capable of encapsulating the quantum chip 406. The shield 404 is held to the top surface of the PCB 410 by a fixture 412 which mechanically clamps or screws the shield 404 to the PCB 410 and thermalization structure 414. A shield 408 may be present on the PCB. The PCB may include an RF connector 418, which is operable to exchange data with other components using RF signals. Because wire bonds (e.g., 402) are relatively durable interconnects, the quantum chip 406 cannot be readily replaced.In contrast, reference is now made to FIG. 5, which is a cross-section of a chip 506 connected to a chip carrier (e.g., PCB) 510 by means of capacitive coupling, according to an illustrative embodiment. A structure 500 includes a thermalization structure 514 that is operatively capable of supporting the chip (e.g., quantum chip and / or control chip) 506 below a cavity 516. The thermalization structure 514 may include copper. In some embodiments, a shield 508 is present that is operatively capable of completing the encapsulation of the chip 506 and protecting the chip surface from stray fields or external influences. The shield may be attached to the bottom surface of the chip carrier (e.g., PCB) 510 by means of an attachment 512 via which both the shield 508 and the thermalization structure 514 are mechanically clamped or screwed to the PCB 510. The clamping provided by the attachment 512 ensures that the thermal contact between the thermalization structure 514 and the chip 506 is sufficient. Good thermal and electrical contact to ground is achieved either with the copper block or already via the large ground contacts at all edges of the chip (e.g. wherever no waveguide is located). In one embodiment, a shield 502 is provided on the PCB 510 that is operable to protect the chip circuit from electromagnetic (EM) interference by providing a defined cavity.The PCB 510 may include one or more RF connectors (e.g., 518 and 530) that are operable to exchange data with other components using RF signals. In essence, the connection between the pads on the chip 506 and the connector pads of the PCB 510 is not via a permanent connection (e.g., permanent soldering, wire, thermosonic, or other permanent bonding). Rather, one or more connections between the chip 506 and the chip carrier 310 are made by means of a capacitive coupling between the contact pads of the chip 506 and the connector contact pads on the PCB 510 having a distance d. In an example, the overlap between a contact surface of the chip 506 and the chip carrier is about 500 μm. With a width of a CPW starting point (sometimes referred to herein as chip pad) of 100 μm, a coupling capacitance of 500 fF was observed with less than 5 dB attenuation of the signal. Due to such a non-permanent connection, the chip 506 may be easily removed from the chip carrier 510 and replaced. It should be appreciated that although the distance "d" is shown as a visible space in the exploded view, this space occurs regardless of the chip 506 being pressed against the PCB 510 using the thermalization structure 514 and the mount 512. In particular, as previously stated, the distance "d" may be minimized by increasing the contact pressure between the chip 506 and the PCB 510. This subsequently leads to a reduced distance "d" and a corresponding increase of the coupling capacitance between a contact surface of the chip 506 and the PCB 510. In some embodiments, the coupling capacitance may be varied by controlling the distance "d" based on the applied mechanical pressure (e.g., via screw fastening, springs, etc.) between a chip and a chip carrier.Accordingly, the waveguide is shifted toward the edge of the chip and is configured as a waveguide output point, sometimes referred to herein as a chip pad. The lateral dimensions (w) of the chip contact pad are configured in size such that the impedance remains the same but the size increases from w, e.g. from 10 μm to 200 μm. There is a corresponding waveguide exposed on the side of the chip carrier (e.g. PCB) 510 within an overlap region. In one embodiment, the length "l" is about 1 μm. Thus, placing the chip on the chip carrier, the two ends of these waveguides (e.g. the chip contact pad and the connector on the chip carrier) may form a plate capacitor of length l and width w. Applicants have found that if "l" and "w" are large enough (usually l=500 μm, w=100-200 μm), the capacitive coupling is sufficient so that chip-to-PCB transmission works adequately even when there is a separation "d" between the surface of the chip and the surface of the PCB (each including its respective waveguide). In this regard, FIGS. 8A-8C provide example simulation results of coupling capacitance between the pad of a chip and a connector on a PCB (i.e., their corresponding CPWs) at a fixed vertical distance between the CPWs of 100 nm. FIG. 8C shows that the capacitance is linear with the length l of the overlap.FIG. 6 is a cross-sectional view of a die 506 connected to the PCB 510, which includes a spring-loaded thermalization structure 514, according to an illustrative embodiment. Many components of FIG. 6 are substantially similar to those of FIG. 5 and therefore not re-illustrated for clarity. The main difference is that there are one or more spring contacts 620 between the thermalization structure 514 and the die 506, sometimes referred to herein as spring-loaded. Spring loading may help provide a defined constant force on the die that compensates for changes in geometry during cooling. Accordingly, the chip 606 is pressed onto the connector pads of the chip carrier by spring contacts pressing on its back side. The actual connection between the pads of the chip 606 and the connector pads on the PCB is made by means of the capacitive coupling discussed herein.FIG. 7 is a cross-sectional view 700 of a structure including a chip 706 connected to the chip carrier (e.g., PCB) 510 including a carrier chip 608, according to an illustrative embodiment. Many components of FIG. 7 are substantially similar to those of FIGS. 5 and 6, and therefore are not shown again for clarity. A significant difference between FIGS. 6 and 7 is that the (e.g., qubit) chip 608 is not directly connected to the chip carrier (e.g., PCB) 510. Rather, the chip 606 is connected to an interposer chip 608, sometimes referred to herein as a control chip using a ball grid array (BGA), where the interposer chip 608 is connected to the chip carrier 510 using a capacitive coupling. FIG. 7 illustrates that the chip 606 is located within a cavity 716 of the shield 708. The quantum chip 706 may be connected to the control chip 608 via superconducting interconnects (e.g., in-bumps) or the like. Advantageously, such interposer chips could be easily replaced and need not be connected to a PCB via wire bonds.In one embodiment, a plurality of similar types of chips (e.g., quantum chips) or a combination of different types of chips are connected to the interconnect chip 608 by a "durable" connection. The interposer chip 608 itself is coupled to the chip carrier (e.g., PCB) 510 using the capacitive coupling discussed above.The architectures discussed herein are useful in various fields including, but not limited to, microwave packaging (e.g., quantum engineering, quantum chips, superconducting quantum chips), quantum technology (e.g., quantum processors, quantum system packaging, superconducting qubit packaging, etc.), cryogenics (e.g., measurements, etc.), and the like.Conclusion: ConclusionThe descriptions of the various embodiments of the present teachings are intended to be illustrative, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are conceivable to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to explain the principles of the embodiments, the practical application, or the technical improvement over the technologies found on the market, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein.While there has been described in the foregoing what is considered to be the best mode and / or other examples, it is to be understood that various modifications may be made thereto and that the subject matter disclosed herein may be embodied in various forms and examples and that the teachings may be practiced in numerous applications, only some of which have been described herein. The following claims are intended to claim any and all applications, modifications, and variations that fall within the scope of the present teachings.The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative in nature. Neither these nor the discussions relating to them are intended to limit the scope of protection. While various advantages have been discussed herein, it should be appreciated that not all embodiments necessarily include all advantages. Unless otherwise indicated, all dimensions, values, grades, positions, orders, sizes, and other items set forth in this specification, including the following claims, are approximate, non-exact items. They are intended to have a range corresponding to the functions they relate to and corresponding to what is common in the field to which they belong.Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and / or other components, steps, features, objects, network effects, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.While the foregoing has been described in connection with exemplary embodiments, it is to be understood that the term "exemplary" is intended to be exemplary only and not best or optimal. Except as noted above, regardless of whether recited in the claims, nothing but what has been stated or illustrated is intended to be a preference for the public of any component, step, feature, object, benefit, or the like, and should not be interpreted as such preference.It should be understood that the terms and expressions used herein have the normal meaning that such terms and expressions are accorded with respect to their respective respective fields of research and investigation, except as having been given particular meanings expressly stated otherwise herein. Relational expressions such as first / first / first and second / second / second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or necessarily incorporating any actual such relationship or order between such entities or actions. The terms "comprise," "comprising," or any other variation thereof are intended to be included without limitation, such that a process, method, article, or apparatus comprising a list of components does not include only those elements, but may include other elements not expressly listed or characteristic of such a process, method, article, or apparatus. An element preceded by "a / an" does not exclude, without further limitations, the presence of additional identical elements in the process, method, article, or apparatus comprising the element / s.The Abstract of the Disclosure is provided to enable the reader to provide a quick review of the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, from the foregoing detailed description, it can be seen that in various embodiments, various features are grouped together to aid in describing the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments contain more features than are expressly recited in each claim. As the following claims show, the subject matter of the invention lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

Claims

A device package comprising: a die carrier (510) including a cavity and one or more microwave waveguides configured to pass signals; and a die (220) having one or more contact pads and disposed within the cavity of the die carrier (510), a block configured to press the die (220) into the cavity of the die carrier (510), wherein: each contact pad is aligned with a respective connector contact pad of a microwave waveguide of the one or more microwave waveguides of the die carrier (510); at least one of the one or more contact pads is connected to the connector contact pad of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one contact pad and the aligned respective connector contact pad of the microwave waveguide; and the block comprises one or more springs operatively capable of pressing the chip (220) onto the cavity of the chip carrier (510), wherein a distance between the at least one contact pad and the aligned corresponding connector contact pad of the microwave waveguide is controllable based on the applied mechanical pressure between the chip (220) and the chip carrier (510).The device package of claim 1, wherein the chip (220) is a quantum chip (406).The device package of claim 1, wherein the chip carrier (510) is a printed circuit board (PCB) (510).The device package of claim 1, wherein: the chip (220) is a quantum chip (406); and the block is a thermalization block operatively capable of thermalizing the quantum chip (406).The device package of claim 1, wherein the microwave waveguide is superconductive and comprises niobium or copper coated by a superconductor.The device package of claim 1, wherein the superconducting microwave waveguides of the chip carrier (510) are guided in three dimensions to a connector plane comprising a ball grid array (BGA).The device package of claim 1, wherein an orientation between the chip (220) and the cavity of the chip carrier (510) is within 0.2 times a width of the connector contact pad.The device package of claim 1, wherein: the chip carrier (510) comprises a plurality of additional cavities; at least one additional cavity of the plurality of additional cavities comprises a particular chip comprising one or more contact pads located within the at least one additional cavity; each contact pad of the particular chip is aligned with a corresponding connector contact pad of a microwave waveguide of the chip carrier (510); and at least one of the one or more contact pads of the particular chip is connected to its aligned corresponding connector contact pad of the chip carrier (510) by means of an overlapping capacitive coupling.The device package of claim 8, wherein: the chip (220) is a quantum chip (406); and the particular chip is not a quantum chip (406).A chip packaging system comprising: a chip carrier (510) including a cavity and one or more microwave waveguides configured to pass signals; an interposer chip (608) having one or more contact pads and disposed within the cavity of the chip carrier (510); and one or more chips bonded to the interposer chip (608), a block configured to press the interposer chip (608) into the cavity of the chip carrier (510), wherein: each contact pad of the interposer chip (608) is aligned with a corresponding connector contact pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier (510); at least one of the one or more contact pads is connected to the connector contact pad of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one contact pad and the aligned respective connector contact pad of the microwave waveguide; and the block comprises one or more springs operatively capable of pressing the interposer chip (608) onto the cavity of the chip carrier (510), wherein a distance between the at least one contact pad and the aligned respective connector contact pad of the microwave waveguide is controllable based on the applied mechanical pressure between the interposer chip (608) and the chip carrier (510).The chip packaging system of claim 10, wherein: the chip (220) is a quantum chip (406); and the chip carrier (510) is a printed circuit board (PCB) (510).A method of packaging a chip (220), comprising: providing a chip carrier (510) including a cavity and one or more microwave waveguides for propagating signals; guiding a chip (220) having one or more contact pads into the cavity of the chip carrier (510); pressing the chip (220) into the cavity of the chip carrier (510) with a thermalization block, the pressing comprising one or more springs of the thermalization block pressing the chip (220) onto the cavity of the chip carrier (510); aligning each contact pad of the chip (220) with a corresponding connector contact pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier (510); and coupling at least one of the one or more contact pads to the connector contact pad of the respective microwave waveguide by means of an overlapping capacitive coupling between the at least one contact pad and the aligned respective connector contact pad of the microwave waveguide, wherein a distance between the at least one contact pad and the aligned respective connector contact pad of the microwave waveguide is controllable based on the applied mechanical pressure between the chip (220) and the chip carrier (510).The method of claim 12, wherein: the chip carrier (510) comprises a plurality of additional cavities; at least one additional cavity of the plurality of additional cavities comprises a particular chip (220) having one or more contact pads located within the at least one additional cavity; each contact pad of the particular chip (220) is aligned with a corresponding connector contact pad of a microwave waveguide of the chip carrier (510); and at least one of the one or more contact pads of the particular chip (220) is connected to its aligned corresponding connector of the chip carrier (510) by means of an overlapping capacitive coupling.The method of claim 12, further comprising: determining the functionality of the die (220); and upon determining that the die (220) is defective: removing the die (220); and replacing the die (220) with a new die.

Images