Method, system, and computer program product for supporting large-word operations in a processor of a reduced instruction set ("RISC") computer
The integration of a special-purpose hardware execution unit with wider registers and synchronized state master bits addresses the challenge of performing large operand computations in RISC processors, notably improving SHA-3 processing efficiency.
Patent Information
- Application Number
- DE112022004046
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-10-14
- Filing Date
- 2022-10-09
- Publication Date
- 2025-07-31
- Estimated Expiration
- 2042-10-09
AI Technical Summary
Modern RISC processors face challenges in performing computations on operands larger than their register width, such as those required by Secure Hash Algorithm-3 (SHA-3), without breaking down the operands into smaller elements, which affects performance and efficiency.
Incorporating a special-purpose hardware execution unit (SPU) with wider registers than the CPU, synchronized by state master bits, to handle quadword operations, ensuring coherency and handling exceptions/interrupts to maintain optimal access to the shared state.
This approach significantly reduces the time required for SHA-3 computations, achieving faster processing of large state modifications by maintaining separate copies of the state and optimizing access, thus enhancing computational efficiency.
Smart Images
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Abstract
Claims
[1] A method for supporting large-word operations in a data processing environment by one or more processors, comprising: in response to receiving one or more control signals from a central processing unit, CPU, executing (1004) a set of operations on a state of a special execution unit (420), SPU, which is a processor and has a plurality of SPU registers (430), wherein word widths of one or more of the plurality of SPU registers (430) are each greater than word widths of a plurality of CPU registers of the CPU, and wherein a set of state master bits is used to synchronize the state of the SPU and a state of the CPU, for example, during exceptions and interrupts; and Storing (1006) results of the set of operations in the plurality of CPU registers or an alternative set of the plurality of SPU registers (430). [2] The method of claim 1, further comprising overlaying the state of the plurality of SPU registers (430) with the plurality of CPU registers in the CPU. [3] The method of claim 1, further comprising copying the state of the plurality of CPU registers to the plurality of SPU registers (430) using a set of arithmetic instructions or CPU internal operations. [4] The method of claim 1, further comprising copying the state of the plurality of SPU registers (430) to the plurality of CPU registers using the set of computation instructions. [5] The method of claim 1, further comprising: replicating the state of the SPU for each of a plurality of threads of the SPU; and Processing computational instructions issued by each of the plurality of threads of the SPU in the pipeline system. [6] The method of claim 1, further comprising implementing instructions by the SPU to perform a round of state permutation functions of the Secure Hash Algorithm-3, SHA-3, wherein the state of the SPU is a width of a first register having at least n number of bits and a second register having m number of bits, where n and m are positive integers. [7] The method of claim 1, further comprising: Executing a plurality of instructions by the SPU to perform a plurality of rounds of state permutation functions of the Secure Hash Algorithm-3, SHA-3; and Using one or more different coherency protocols between the plurality of CPU registers and the alternate set of the plurality of SPU registers (430) with the plurality of instructions. [8] A system for supporting large-word operations in a processor in a data processing environment, comprising: one or more computers with executable instructions that, when executed, cause the system to: in response to receiving one or more control signals from a central processing unit, CPU, executing (1006) a set of operations on a state of a special execution unit (420), SPU, which is a processor and has a plurality of SPU registers (430), wherein word widths of one or more of the plurality of SPU registers (430) are each greater than word widths of a plurality of CPU registers of the CPU, and wherein a set of state master bits is used to synchronize the state of the SPU and a state of the CPU, for example, during exceptions and interrupts; and Storing (1006) results of the set of operations in the plurality of CPU registers or an alternative set of the plurality of SPU registers (430). [9] The system of claim 8, wherein the executable instructions, when executed, cause the system to overlay the state of the plurality of SPU registers (430) with the plurality of CPU registers in the CPU. [10] The system of claim 8, wherein the executable instructions, when executed, cause the system to copy the state of the plurality of CPU registers to the plurality of SPU registers (430) using a set of arithmetic instructions or CPU-internal operations. [11] The system of claim 8, wherein the executable instructions, when executed, cause the system to copy the state of the plurality of SPU registers (430) to the plurality of CPU registers using the set of computation instructions. [12] The system of claim 8, wherein the executable instructions, when executed, cause the system to: replicating the state of the SPU for each of a plurality of threads of the SPU; and Processing computational instructions issued by each of the plurality of threads of the SPU in the pipeline system. [13] The system of claim 8, wherein the executable instructions, when executed, cause the system to execute, through the SPU, instructions to perform a round of state permutation functions of the Secure Hash Algorithm-3, SHA-3, wherein the state of the SPU is a width of a first register having at least n number of bits and a second register having m number of bits, where n and m are positive integers. [14] The system of claim 8, wherein the executable instructions, when executed, cause the system to: Executing a plurality of instructions by the SPU to perform a plurality of rounds of state permutation functions of the Secure Hash Algorithm-3, SHA-3; and Using one or more different coherency protocols between the plurality of CPU registers and the alternate set of the plurality of SPU registers (430) with the plurality of instructions. [15] A computer program product for supporting large-word operations in a processor in a data processing environment, the computer program product comprising: one or more computer-readable storage media and program instructions stored together on the one or more computer-readable storage media, the program instructions comprising: in response to receiving one or more control signals from a central processing unit, CPU: Program instructions for executing (1004) a set of operations on a state of a special execution unit (420), SPU, which is a processor and has a plurality of SPU registers (430), wherein word widths of one or more of the plurality of SPU registers (430) are each greater than word widths of a plurality of CPU registers of the CPU, and wherein a set of state master bits is used to synchronize the state of the SPU and a state of the CPU, for example, during exceptions and interrupts; and Program instructions for storing (1006) results of the set of operations in the plurality of CPU registers or an alternative set of the plurality of SPU registers (430). [16] The computer program product of claim 15, further comprising program instructions for overlaying the state of the plurality of SPU registers (430) with the plurality of CPU registers in the CPU. [17] The computer program product of claim 15, further comprising program instructions for: Copying the state of the plurality of CPU registers into the plurality of SPU registers (430) using a set of arithmetic instructions or CPU-internal operations; and Copying the state of the plurality of SPU registers (430) to the plurality of CPU registers using the set of arithmetic instructions. [18] The computer program product of claim 15, further comprising program instructions for: replicating the state of the SPU for each of a plurality of threads of the SPU; and Processing computational instructions issued by each of the plurality of threads of the SPU in the pipeline system. [19] The computer program product of claim 15, further comprising program instructions for executing instructions by the SPU to perform a round of state permutation functions of the Secure Hash Algorithm-3, SHA-3, wherein the state of the SPU is a width of a first register having at least a number of n bits and a second register having a number of m bits, where n and m are positive integers. [20] The computer program product of claim 15, further comprising program instructions for a Executing a plurality of instructions by the SPU to perform a plurality of rounds of state permutation functions of the Secure Hash Algorithm-3, SHA-3; and Using one or more different coherency protocols between the plurality of CPU registers and the alternate set of the plurality of SPU registers (430) with the plurality of instructions.