SCALABLE HIERARCHICAL PERFORMANCE DELIVERY SYSTEM

Abstract

Complete facility: a hierarchical power output circuit (100) which includes: a first level (102) of a power converter switching logic configured to generate one or more regulated first level supply voltages (102) from an input voltage; a second level (104) of a power converter switching logic configured to generate from corresponding first level regulated supply voltages (102) one or more second level regulated supply voltages (104) to a data processing element (110) comprising one or more integrated circuits configured to operate as a single logic computer system, wherein the data processing element (110) is configured to operate in a variety of power configurations having different numbers of load circuits; and wherein the hierarchical power output circuit (100) is configured to selectively activate different sections of the first and second power converter levels (102, 104) for corresponding to the multitude of power configurations of the data processing element (110).

Description

Technical area

[0001] This disclosure relates to electronic circuits and, more particularly, to power delivery and control systems. Description of related technology

[0002] Computers and other types of electronic systems exist in a wide variety of forms. Because such systems require a power supply to operate, power delivery systems also exist in a correspondingly wide variety of configurations. A power delivery system can, in some cases, be as simple as a single circuit to provide a regulated supply voltage, or can be as complex as a corresponding system requiring a number of different operating voltages at different currents. To manage the overall efficiency of the system, the design of a power delivery system for a particular load configuration may have a complexity corresponding to that load.

[0003] US 2021 / 0 064 120 A1 discloses systems and methods for supporting a peak current voltage regulator using a capacitor switching converter.

[0004] DE 11 2022 003 384 T5 discloses a system-on-chip with a power supply mode with a reduced number of phases.

[0005] US 2008 / 0 111 534 A1 discloses a dynamically configurable voltage regulator for integrated circuits.

[0006] US 2013 / 0 058 141 A1 discloses serial and parallel hybrid switchable capacitor networks for IC power supply.

[0007] US 2016 / 0 352 219 A1 discloses a multilevel multistate voltage regulator.

[0008] According to the state of the art, scaled computing architectures traditionally use custom-designed power delivery networks for each computing architecture, thereby increasing the complexity of implementing these computing architectures. SUMMARY

[0009] The invention solves the above technical problem. The invention is defined in the independent claims. Advantageous embodiments are defined in the dependent claims.

[0010] A hierarchical scalable power delivery system is disclosed. In one embodiment, the power delivery system includes a first level of power converter circuitry configured to generate one or more first-level regulated supply voltages and a second level of power converter circuitry configured to generate one or more second-level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level of power converter circuitry receives the one or more first-level supply voltages.The second-level power converter circuitry is configured to provide the second-level regulated supply voltages to a computing element configured to operate as a single logical computer system, wherein the computing element is configured to operate in a number of power configurations having different numbers of load circuits. Different sections of the hierarchical power delivery system can be selectively activated for corresponding loads of the computing element's power configurations.

[0011] In various embodiments, the power delivery system design of the present disclosure may be reused in a number of different configurations of the computing element (and more generally, a scalable electronic system). The computing element, in one embodiment, comprises a scalable computing architecture, the various implementations of which are transparent to software executing thereon. Accordingly, in various implementations, the scalable computing architecture may comprise a portion of an integrated circuit, the entirety of a single integrated circuit, or multiple instances of an integrated circuit coupled together in a package but otherwise operating as a computing element viewed by software as a single entity.The power delivery system disclosed herein can be scaled according to the particular implementation of the computing element such that the design can be used for any of the different configurations. The activated portions of the power delivery system are selected based on the particular implementation of the computing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following detailed description refers to the attached drawings, which are now briefly described. Fig. 1 is a block diagram of one embodiment of a power delivery system. Fig. 2 is a block diagram of one embodiment of a power delivery system configured for a first load configuration. Fig. 3 is a block diagram of one embodiment of a power delivery system configured for a second load configuration. Fig. 4 is a block diagram of one embodiment of a power delivery system configured for a third load configuration. Fig. 5 is a block diagram of one embodiment of a power delivery system having various control buses coupled between elements thereof. Fig. Figure 6 is a block diagram of a switching power converter used to generate a regulated supply voltage for a portion of a power delivery system. Fig. 7 is a block diagram illustrating one embodiment of a computer system, a computer-readable medium, and a manufacturing system. Fig. 8 is a block diagram of one embodiment of an example system. DETAILED DESCRIPTION OF EMBODIMENTS

[0013] A scalable hierarchical power delivery system is disclosed. The power delivery system of the present disclosure is usable in a number of different implementations of a computing element that is scalable from a portion of an integrated circuit to a number of different integrated circuits.

[0014] Generally speaking, different computer systems have different power requirements and, accordingly, have different power delivery systems. These power delivery systems may be customized for the particular computer system. Current trends in computing include the introduction of scalable computing architectures. A scalable computing architecture may include various implementations that have different levels of functionality while otherwise appearing transparent to software executing thereon. For example, a scalable computing architecture according to this disclosure could include a less than complete section of an integrated circuit, a complete section of the integrated circuit, or multiple versions of the integrated circuit.From an instruction set architecture (ISA) perspective, the different versions of the scalable computing architecture can still share a common ISA. Furthermore, operating system software, for example, can operate in largely the same way on the various configurations of the scalable computing architecture. However, such scalable architectures may require the use of custom-designed power delivery systems for the various configurations. Custom-designed power delivery systems can significantly increase the complexity of implementing different configurations of a computing architecture that has a number of different configurations.The present disclosure therefore contemplates a hierarchical power delivery system that is scalable to suit the various implementations of a scalable computing architecture, with a common design that can be reused in a number of different configurations.

[0015] In various embodiments, the power delivery system includes a first (upper) level of one or more power converters (e.g., switching power converters, such as buck converters) coupled to receive an input voltage from an input voltage source (e.g., a battery, AC mains, etc.). Using the input voltages, first-level power converters generate one or more supply voltages to be supplied to second-level power converters. The second-level power converters include power converters that, using the supply voltage(s) received from the first level, generate one or more regulated second-level supply voltages that can be provided to various loads in the system.The number of power converters enabled in the power delivery system levels can be configured to correspond to the number of loads within the computing element to be powered. For example, a first number of power converters is enabled for a single-die / integrated circuit (IC) version of the computing element, while a second number of power converters is enabled for a multi-die / IC version of the computing element.

[0016] The scalability discussed herein may enable the same basic design of the power delivery system to be used in a number of different configurations. Within the power delivery system, power converters may be enabled or disabled according to the particular configuration of the scalable computing architecture to which it provides power. This may advantageously avoid the need for customized designs for the various different configurations of the scalable computing architecture. Accordingly, the design of the power delivery system disclosed herein may be used in a wide variety of different configurations and devices, examples of which are described below with reference to Fig. 8 will be discussed.

[0017] While the above discussion is directed to a power delivery system for a scalable computing architecture, the above disclosure further contemplates a power delivery system that can be used with a wide variety of electronic systems that have a scalability aspect. Furthermore, the term computing architecture can be interpreted broadly to encompass a wide variety of systems and devices (including, but not limited to, those discussed below) in which computing operations are performed.

[0018] Further details of the hierarchical scalable power delivery system will now be discussed, beginning with a basic overview of one embodiment. The discussion then continues with an embodiment of the power delivery system used in three different implementations of a scalable computing architecture. The disclosure continues with a discussion of control buses within one embodiment of the power delivery system, an example of a coupled-inductor power converter used in portions thereof, and an embodiment of a manufacturing system that can be used to manufacture the power delivery system based on information stored on a computer-readable medium.The description concludes with examples of a number of different systems in which a particular embodiment of the power delivery system may be implemented, wherein the different systems implement a common scalable computing architecture. Hierarchical scalable power delivery system:

[0019] Now with reference to Fig. 1, a block diagram of a system comprising a hierarchical power delivery system and a data processing element is shown. In the embodiment shown, the system 11 includes a hierarchical power delivery system 100 and a data processing element 110. The hierarchical power delivery system 100 includes a first power converter level 102 coupled to receive an input voltage, V_in, from an external source, e.g., a battery. The first power converter level 102 includes one or more power converters configured to generate one or more regulated first-level supply voltages. These regulated first-level supply voltages are received by one or more power converters of a second power converter level 104.The power converters of power converter level 104 generate one or more second-level regulated supply voltages using the one or more first-level regulated supply voltages. These voltages are provided to the various loads of data processing element 110.

[0020] In the illustrated embodiment, the computing element 110 includes one or more integrated circuits (ICs) 111, shown generally herein as ICs 111-1 through 111-N. The computing element 110 is configurable and scalable, with the number of ICs varying from one implementation to the next. For example, in a first implementation, the computing element 110 may comprise a single IC die, while in a second implementation, the computing element 110 may comprise two or more IC dies. Implementations in which only a portion of an IC die is activated are also possible and are contemplated.

[0021] While the data processing element 110 is thus scalable, the number of ICs of a particular implementation is transparent to software executing thereon.

[0022] Thus, regardless of the number of specific ICs in a given implementation, the software executing thereon can view the computing element 110 as a single entity. Accordingly, in the illustrated embodiment, the computing element 110 can implement a computing architecture that can be scaled up or down as desired and is capable of executing software on the various implementations regardless of that scaling.

[0023] Each IC 111-1 to 111-N in the illustrated embodiment may include a number of different types of circuitry. For example, the ICs 111-1 to 111-N may include various types of processor cores, graphics processing units (GPUs), neural network processors, memory controllers, input / output (I / O) circuits, network switches for implementing various networks thereon, and the like. When two or more instances of the ICs 111-1 to 111-N are implemented to form a data processing element, the various functional circuits thereon may form larger complexes than those of an implementation using a single IC or portion thereof.For example, ICs 111-1 and 111-N may each include a complex of processor cores, and thus, an implementation of data processing element 110 with two or more ICs realizes a larger complex of processor cores spanning a number of ICs. The processor cores of one IC may communicate with those of another via one or more die-to-die interfaces between the individual ICs.

[0024] Thus, given the different power requirements of the different circuit logic implemented on an instance of IC 111-1 to 111-N, there may be multiple power converters generating appropriate voltages to meet the efficiency requirements of these loads. For example, processor cores may have different power requirements than I / O circuits. Accordingly, power converter layer 104 may include one or more power converters suitable for providing a first second-level supply voltage to the processor cores and one or more power converters providing a different second-level supply voltage to the I / O circuits.

[0025] The hierarchical power delivery system 100 in the illustrated embodiment is also scalable, mirroring the scalability of the computing element 110. In various embodiments, the power converter levels of the hierarchical power delivery system 100 may include a number of power converters (e.g., switching voltage regulators and the like) to meet the electrical requirements of the various loads, as discussed above. The number of power converters enabled for a particular implementation may thus correspond to the number of ICs 111-1 through 111-N in the particular implementation of the computing element 110. More generally, the power converter levels 102 and 104 may be arranged to enable more power supply capacity as more computing capacity is implemented in the computing element 110.In this way, the design of the hierarchical power delivery system 100 is reusable across a number of different implementations of the computing element 110. Reusing the design of the hierarchical power delivery system 100 across the scalability range of the computing element 110 can, in turn, avoid the need to provide specific power delivery solutions for various different implementations. This, in turn, can significantly simplify the design of various systems based on different implementations of the computing element 110, as well as reduce the time required to realize a functioning system for any particular implementation of such a design. Example configurations of the power delivery system in a scalable computing architecture:

[0026] Fig. Figure 2 is a block diagram illustrating one embodiment of a power delivery system implemented for a first load configuration. In the illustrated embodiment, system 200 includes an implementation of hierarchical power delivery system 100 and a corresponding implementation of data processing element 110. In this example, data processing element 110 includes two integrated circuits, ICs 270 and 280, coupled together via a die-to-die (D2D) interface 290. D2D interface 290 can be used to facilitate communication between the chips and to extend networks that may be implemented on either IC.For example, if both ICs 270 and 280 include a network of processor cores, the D2D interface 290 facilitates combining the on-chip networks to form a larger network of processor cores spanning both ICs.

[0027] The ICs 270 and 280 of this implementation of the data processing element 110 are powered by a correspondingly scaled implementation of the hierarchical power delivery system 110. In the illustrated embodiment, a first level of power converters is implemented by the power converter 204 and the power converter 208. The power converter 204 in the illustrated embodiment is a multi-phase switching power converter having phases 221 through 227, each coupled to a corresponding one of the inductors L21 through L27. Each of the phases is coupled to receive an input voltage V_in from a corresponding input voltage source. The inductors are coupled to a common node, Vreg1, on which a first regulated supply voltage is provided. A control circuit 220 in the illustrated embodiment is configured to control the operation of the power converter 204.The control functions performed by the control circuit 220 may include enabling or disabling certain of the phases 221 to 227 depending on, for example, load current requirements, controlling and switching operation between different modes, such as pulse frequency modulation (PFM) and pulse width modulation (PWM), starting the various phases, and so on.

[0028] It is noted that each of the phases 221 through 227 shown herein is considered to be activated, which is defined herein as having the ability to become active even if it is currently inactive. In contrast, as discussed with additional examples, a deactivated phase as defined herein is a phase whose ability to become active has been removed, so that it remains inactive throughout operation.

[0029] Power converter 208 in the illustrated embodiment is another first-level power converter. Similar to power converter 204, power converter 208 in the illustrated embodiment is also a multi-phase switching power converter, with phases 231 to 233 coupled to receive input voltage V_In. Each of phases 231 to 233 is coupled to a respective inductor L31 to L33, which in turn are coupled together at a common voltage supply node, VReg2, on which a respective second regulated supply voltage is provided. Control circuit 230 in the illustrated embodiment may perform the functions of adding or removing activated ones of phases 231 to 233 during operation depending on the load current demand, controlling operating modes (e.g., PFM, PWM), and the like.

[0030] In various embodiments, power converters 204 and 208 are buck converters that provide respective regulated supply voltages that are less than the input voltage V_in. However, embodiments implementing a first-level boost converter are possible and contemplated. It is further noted that the regulated supply voltages in this exemplary embodiment, Vreg1 and Vreg2, may be different from each other, although implementations where these voltages are substantially the same are also possible. Power converters 204 and 208 may be implemented using various different combinations of integrated circuits. For example, control circuits 220 and 230 may be implemented on a common integrated circuit die. Meanwhile, the phases of the converters may be implemented separately on different integrated circuits.Embodiments are possible and contemplated where high-side switches, low-side switches, and driver switches are all implemented on different integrated circuit dies relative to one another. Embodiments where these different integrated circuit dies are integrated into a common package are also possible and contemplated. Generally speaking, the disclosure contemplates a wide variety of different physical implementations for power converters 204 and 208.

[0031] A second level of power converters in the illustrated embodiment is implemented by the power converters of ICs 211 and 212. The IC 211 in the illustrated embodiment includes a plurality of power converters 241-250, each of which is coupled to receive the first regulated voltage, Vreg1, from the first-level power converter 204. The power converters 241-250 in this embodiment generate a third regulated supply voltage, Vreg3. In various embodiments, the power converters 241-250 are buck regulators, and thus Vreg3 is a voltage less than Vreg1. However, embodiments in which the power converters 241-250 are implemented as boost converters are possible and contemplated.

[0032] Various power converter architectures may be used to implement the power converters 241-250 of the IC 211. In various embodiments, the power converters 241-250 may be implemented as switching power converters and may include at least one inductor (not shown here for simplicity) and a switching circuit. The switching power converters may be implemented as buck converters or boost converters, depending on the power requirements of the respective loads. In one embodiment to be discussed below, the power converters 241-250 may be implemented as coupled-inductor power converters, in which pairs of inductors share a magnetic core and thus share magnetic fields. Embodiments in which bootstrapping occurs at the high-side switch of the inductors are also possible and are contemplated.The present disclosure also contemplates power converters implemented as linear regulators, such as low dropout (LDO) voltage regulators. In general, the disclosure contemplates implementations of power converters 241-250 in a wide variety of embodiments using different power converter architectures and control schemes.

[0033] The power converters 241 to 250 in the illustrated example are arranged to provide their respective generated supply voltages to loads on the ICs 270 and 280. In particular, the power converters 241 to 245 are arranged to provide corresponding instances of the third regulated supply voltage, Vreg3, to the loads 271 to 275 (of the IC 270), respectively. Meanwhile, the power converters 246 to 250 are arranged to provide corresponding instances of the third regulated supply voltage to the loads 281 to 285 (of the IC 280), respectively. These loads can be various types of circuitry, such as central processing unit (CPU) cores, graphics processing units (GPUs), or any other type of circuitry that operates based on the third regulated supply voltage.Additionally, one of the power converters in each of the groups 241 to 245 and 246 to 250 is coupled to provide a supply voltage for its respective side of the D2D interface 290.

[0034] In the illustrated embodiment, IC 212 includes power converters 261-265, each of which is configured to generate respective instances of a fourth regulated supply voltage, Vreg4. As with power converters 241-250, power converters 261-265 may also be implemented as switching power converters that include respective inductors (not shown here) as energy storage elements. In various embodiments, power converters 261-264 may be implemented as single-inductor buck converters, although embodiments implementing them as coupled-inductor buck converters, boost converters, or linear regulators (e.g., LDO regulators) are possible and contemplated. Each of power converters 261-264 is coupled to receive the second regulated supply voltage, Vreg2, output from power converter 208.In embodiments of buck converters and linear regulators, the regulated supply voltage Vreg4 may have a value that is smaller than that of Vreg2.

[0035] Power converters 261 and 262 in the illustrated embodiment are coupled to provide Vreg4 to load circuits 276 and 277, respectively, implemented on IC 270. Meanwhile, power converters 263 and 264 are coupled to provide Vreg4 to load circuits 286 and 287, respectively, on IC 280. The load circuits receiving Vreg4 can be virtually any type of circuitry for which Vreg4 is a suitable supply voltage. Such load circuits can include (but are not limited to) memory circuits, various types of power management circuits implemented on ICs 270 and 280, I / O circuits, and so on.

[0036] In various embodiments, a selected one of the power converters 261 may include control circuitry operable to control the startup order of other power converters in the hierarchical power delivery system 100, as discussed in more detail below.

[0037] Embodiments are also possible and contemplated in which various of the power converters may be turned off or placed into a sleep mode, e.g., when their respective load circuits are inactive. For example, in one embodiment, power converter 204, power converters 241-250, and power converters 261-264 may all be turned off if their respective coupled load circuits are inactive.

[0038] Embodiments are also contemplated where at least one power converter is an "always on" power domain converter. As used herein, the term "always on" is defined such that the power converter remains operational as long as it receives an input voltage. In one embodiment, power converter 208 may be an "always on" power converter that remains operational when receiving power from the input voltage source, V_in. However, in embodiments where power converter 208 is implemented as a multi-phase converter as shown herein, some phases may be deactivated when their correspondingly coupled load circuits (power converters 261 through 264) are not operating.For example, when power converters 261 through 264 are inactive, two of the three phases of power converter 208 may be inactive at any given time, with only a single phase being used to output the regulated supply voltage Vreg2. However, the use of certain rotation modes during such operation, with the active phase rotating among the various phases of a multi-phase power converter, is possible and contemplated. For example, control circuit 230 could alternate between activation phase 231 for a first cycle, phase 232 for a next cycle, and phase 233 for a cycle following it.

[0039] The Fig. The example shown in Figure 2 contemplates a full implementation for a particular embodiment of a scalable computing architecture that can utilize two separate ICs to form a single computing element, with a corresponding full implementation of the power delivery system 100. However, it is noted that this embodiment is not intended to be limiting. Embodiments that can scale up to 4, 8, or any other number of ICs to implement a single computing element are possible and contemplated, and thus the same applies to a power delivery system for such a scalable computing architecture.

[0040] Fig. Figure 3 illustrates the embodiment of the power delivery system discussed herein as implemented for a second load configuration. In this particular example, the scalable computing architecture of system 300 has been scaled down to use a single IC to form the computing element. When the computing element is implemented with only a single IC, the number of load circuits to be powered is Fig. 2 lower. Accordingly, the hierarchical power delivery system 100 is scaled accordingly, with selected ones of the power converters and / or phases thereof deactivated. As defined herein, the term "deactivated" is not to be confused with the term "inactive." By definition of this disclosure, an inactive power converter or an inactive phase thereof may be reactivated as needed according to operational requirements. For example, inactive phases of the power converters 204 and 208 may be deactivated during "power-saving" scenarios and then activated as the load current increases. In contrast, a deactivated power converter or a deactivated phase thereof, as defined herein, is permanently disabled from activation and thus remains inactive throughout operation of the power delivery system 100.In various embodiments, a disabled power converter may be present on an IC with other enabled power converters, but may be disabled due to some mechanism (e.g., blown fuses) so that they are permanently inoperative. In other embodiments, the power converters referred to as disabled may not be present at all. Accordingly, the definition of disabled according to the present disclosure is intended to include power converters that are present but have been rendered permanently inoperative by some mechanism, as well as those that are not present at all in implementations smaller than the fully scaled configuration.Furthermore, as defined herein, a power converter or phase thereof is considered to be enabled if it can be enabled to contribute to providing power to its respective load circuits even if it is inactive at a given time.

[0041] In this example, phases 226 and 227 of power converter 204 are deactivated because phases 221 through 225 are sufficient to provide a load current for the reduced configuration of their respective loads of power converters 241 through 245. Although phases 226 and 227 may be physically present in this configuration, they are deactivated here because the first supply voltage, Vreg1, can be more efficiently provided with the five remaining phases (phases 221 through 225) activated. Deactivating phases that are intended to remain permanently unused for a particular configuration can be achieved in various ways, such as by blowing fuses in a fuse network or by a mechanism that causes control circuit 220 to ignore the presence of the deactivated phases.Furthermore, as mentioned above, embodiments are possible and are considered in which these phases referred to as deactivated do not exist at all.

[0042] The power converters 241 through 245 of the IC 211 are enabled in the illustrated example and are thus configured to generate respective instances of Vreg3 based on Vreg1, as provided by the appropriately coupled configuration of the power converter 204. Since the data processing element 110 in this configuration includes only the IC 270, there are no loads that need to be powered by the power converters 246 through 250. Accordingly, the power converters 246 through 250 are disabled in this configuration. This allows the system to reduce power conversion losses throughout the power delivery architecture.

[0043] With respect to the power converter 208, all three phases thereof remain for the Fig. 3 is activated. However, only power converters 261 and 262 of IC 212 are activated, providing corresponding instances of Vreg4 to load circuits 276 and 277, respectively. Meanwhile, power converters 263 and 264 are deactivated in the illustrated embodiment because there are no corresponding load circuits requiring power.

[0044] Fig. Figure 4 illustrates the embodiment of the power delivery system discussed herein as implemented for a third load configuration. In the configuration of system 400, the data processing element enables only a portion of the circuitry on IC 270. This may be referred to as a "chop die" configuration. For example, if the Fig. 3 includes a data processing element having 16 activated processor cores on the IC 270, the data processing element of the system 400 can be Fig. 4 only have 8 of the cores enabled, with the remaining cores disabled. Additionally, while loads 276 and 277 are both still present on IC 270, their power requirements here are reduced due to the reduction in functionality in other areas of the chip.

[0045] Since the Fig. 4 has reduced power requirements relative to the previously discussed configurations, the hierarchical power delivery system 100 can also be scaled accordingly. In this particular configuration, only power converters 241, 242, and 243 of IC 211 are enabled, with power converters 244 through 250 disabled as a result of the loads utilizing instances of Vreg3 being reduced to loads 271, 272, and 273. Since IC 211 acts as a load for power converter 204, the number of enabled phases therein is reduced accordingly, with phases 221 through 223 being enabled while phases 224 through 227 are disabled. The reduced power requirements of loads 276 and 277 in this configuration further result in the requirements of power converter 208 being reduced.Accordingly, phases 231 and 232 are activated in this configuration, while phase 233 is deactivated.

[0046] It is noted that the various configurations of the scalable computing architecture of computing element 100 and the corresponding configurations of the hierarchical power delivery system are illustrated and discussed herein by way of example. However, the scope of this disclosure is not limited to the embodiments and examples discussed herein. Rather, the disclosure contemplates a wide variety of embodiments of a scalable power delivery system and correspondingly scalable electronic systems (e.g., computing architectures) arranged to receive power from any suitable embodiment of the foregoing. Within a given embodiment of a scalable power delivery system, the number and types of power converters may be any combination suitable for the scalable electronic system to be powered thereby. Control infrastructure for a power delivery system:

[0047] Fig. Figure 5 is a block diagram illustrating one embodiment of a control infrastructure for the corresponding embodiment of the hierarchical power delivery system 100, as discussed above. In the illustrated embodiment, a number of different signaling buses are provided to connect various control circuits associated with the different levels of the power delivery system 100. It should be noted that particular bus types and interfaces are discussed herein by way of example, but are not intended to limit the disclosure. Rather, the present disclosure contemplates a wide variety of implementations for implementing a control infrastructure for a power delivery system.

[0048] As in Fig. As shown in Figure 5, each of the power converters 241 to 250, 261 to 265, and 208 includes a System Power Management Interface (SPMI) with the control circuitry 220 (of the power converter 208), the power converter 261, and the power converter 263 coupled together via an SPMI bus 511. Additionally, each of the power converters 241 to 250 and 261 to 264 includes an SPMI interface for coupling to a corresponding load circuit (not shown here). The load-side SPMI interface on each of the power converters 241 to 250, as well as those on the power converters 261 to 264, are coupled to internal control units (not shown). Commands can be received via these particular SPMI interfaces.Additionally, certain load circuits may be coupled to a power manager circuit within their respective ICs to form corresponding point-to-point connections to internal control units of power converters 241 through 250 and 261 through 264. Through these interfaces and through SPMI bus 511, the control units of the various power converters may receive commands to change voltage, change operating modes, start-up procedures, stop-up procedures, and so on. Additionally, control units in certain of the power converters may initiate control functions via SPMI bus 511.

[0049] The control infrastructure also includes a serial general purpose I / O (SGPIO) bus 512 coupled between power converters 261-264 and power converters 241-250. Power converter 261 includes a first power-on control unit 291, while power converter 263 includes a second power-on control unit 293. First power-on control unit 291 in the illustrated embodiment may function as a first primary control unit for controlling a power-on sequence of power converter 204, power converters 241-245, and power converters 261-263. A second power-on control unit 293 may function as a second primary control unit for controlling the power-on sequence of power converters 246-250 and 264. In one embodiment, these control functions may be performed via the SPMI bus 511 and the SGPIO bus 512.For example, the power-on control unit 291 may initiate a power-on sequence for the power converter 204 via the SPMI bus 511, followed by initiating the power-on sequence for the power converters 241 to 245 via the SGPIO bus 512. Since the first power-on control unit 291 and the second power-on control unit 293 are configured to control power-on sequences for respectively coupled power converters, they may also control power-off sequences.

[0050] A multi-pin control bus is also coupled between each of the power converters 261 through 264. Activation commands can be transmitted over this bus (e.g., from the power-on control unit 291 to control logic in the power converters 262) to cause these converters to be activated, e.g., from a sleep state. A shutdown command can also be transmitted to place these converters into a sleep state or to turn them off for a system shutdown. The crash command can also initiate a shutdown resulting from a system crash. Power converters with coupled inductors:

[0051] Fig. Figure 6 is a schematic diagram of one embodiment of a coupled-inductor power converter. Various of the power converters in the power delivery systems within the scope of this disclosure may be implemented using a coupled-inductor configuration. For example, in one embodiment, power converters 241 through 250 may be implemented as coupled-inductor power converters. These types of power converters can provide high efficiency and fast transient response, making them suitable for low-voltage, high-speed loads, such as processor cores, and so on.

[0052] In the illustrated embodiment, as mentioned above, power converter 240 may correspond to various power converters in the power delivery systems discussed herein, such as power converters 241 through 250. Power converter 240 includes two inductors, LS1 and LS2, that share a common magnetic core 635 and have a coupling factor of K12. Both inductors LS1 and LS2 are coupled together at the regulated voltage supply node designated Vreg3 in this embodiment.

[0053] A first instance of the pulse control circuit 601 of the power converter 240 includes a switch control circuit 602 operable to control the switching of a high-side switch HS1 and a low-side switch LS1. Both of these switches are coupled to a switching node LX1, which in turn is coupled to the inductor LS1 and further coupled to a feedback loop provided to the switching control circuit 602. The switching control circuit 602 can alternately activate the high-side switch HS1 (to couple LX1 to the input voltage Vreg1) and LS1 (to couple LX1 to ground). A second instance of the pulse control circuit 601 operates in the same manner as the first pulse control circuit 601.The second instance of the pulse control circuit 601 includes another instance of the switch control circuit 602, a high-side switch HS2 and a low-side switch LS2 coupled to the inductor L62 at the switch node LX2.

[0054] During operation, the switching control circuits 602 can cause their respective corresponding switches to operate in opposite phases to each other. Thus, HS2 is inactive when HS1 is active, and vice versa. Similarly, LS2 is inactive when LS1 is active.

[0055] The Fig. The coupled-inductor power converter 240 shown in Figure 6 represents one possible variation among a number of power converter possibilities used at the different levels of the power delivery system 100 and the various embodiments thereof. Embodiments in which bootstrapping occurs at the high-side switch (e.g., implemented using an NMOS device with additional circuitry to drive its gate voltage) are also possible and contemplated. As further noted, the disclosure contemplates the use of buck and boost converters, as well as the use of linear voltage regulators. Computer-readable medium and manufacturing system:

[0056] Fig. 7 is a block diagram of one embodiment of a manufacturing system 700. The system includes a non-transitory computer-readable medium 720 having stored thereon instructions / description 750 of a power delivery system of any embodiment falling within the scope of this disclosure. The computer-readable medium 720 may be any of a number of different types of non-transitory media, including disk storage, solid-state drive (e.g., using flash memory), optical storage (e.g., CD-ROM), various types of random access memory (RAM), and so forth, capable of providing persistent storage of information.

[0057] A computer system 740 is configured to read the circuit instructions / description 750 from the computer-readable medium 720. Furthermore, the computer system 740 may execute the various instructions and use the circuit description to cause the manufacturing system 745 to manufacture one or more instances of the circuit represented by the circuit instructions / description 750. The manufacturing system 745 may be any type of automated system capable of manufacturing electronic circuits. Example system:

[0058] Next, with reference to Fig. 8 shows a block diagram of one embodiment of a system 800 that may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 800 includes at least one instance of a system-on-chip (SoC) 806, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a data transfer fabric and interfaces to memory and input / output devices. In some embodiments, one or more processors within the SoC 806 include multiple execution lanes and an instruction issue queue. In various embodiments, the SoC 806 is coupled to external memory 802, peripherals 804, and a power supply 808.

[0059] A power supply 808 is also provided, which supplies the supply voltages to the SoC 806 and one or more supply voltages to the memory 802 and / or the peripherals 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery in a smartphone, a laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 806 is included (and more than one external memory 802 is also included).

[0060] The memory 802 is any memory type such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR, DDR2, DDR3, etc.) (including mobile versions of SDRAMs such as mDDR3, etc., and / or low-power versions of SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with an SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0061] Peripherals 804 include any desired circuitry depending on the type of system 800. For example, in one embodiment, peripherals 804 include devices for various types of wireless communication, such as WLAN, Bluetooth, cellular, global positioning system, etc. In some embodiments, peripherals 804 also include additional memory, including RAM, solid-state memory, or disk storage. Peripherals 804 include user interface devices, such as a display screen, including touch display screens or multi-touch display screens, keyboard or other input devices, microphones, speakers, etc.

[0062] As illustrated, system 800 is shown to have application in a wide range of fields. For example, system 800 may be utilized as part of the chips, circuitry, components, etc., of a desktop computer 810, laptop computer 820, tablet computer 830, cellular or mobile phone 840, or television 850 (or a set-top box coupled to a television). Also illustrated are a smartwatch and a health monitoring device 860. In some embodiments, a smartwatch 860 may include a variety of general computing-related functions. For example, a smartwatch may provide access to email, cellular service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality.For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for the purpose of epidemiological distancing, provide contact tracing, provide communication to emergency services in the event of a health emergency, and so on. In various embodiments, the aforementioned smartwatch may or may not include some or all of the health monitoring-related features. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, eyewear designed to provide an augmented and / or virtual reality experience, and so on.

[0063] The system 800 may further be used as part of a cloud-based service(s) 870. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 800 may be utilized in one or more household devices other than those previously mentioned. For example, devices within the home may monitor and detect conditions requiring attention. For example, various devices within the home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a repair facility) should a particular event be detected.Alternatively, a thermostat can monitor the temperature in the apartment and can automate settings of a heating / cooling system based on a history of responses to various conditions by the apartment owner. Also in . Fig. 8 illustrates the application of system 800 to various modes of transportation. For example, system 800 may be used in the control and / or entertainment systems of airplanes, trains, buses, rental cars, passenger vehicles, watercraft, from private boats to cruise ships, (rental or private) scooters, and so on. In various cases, system 800 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and others. Any of these many other embodiments are possible and are contemplated. It is noted that the Fig. The devices and applications illustrated in Figure 8 are illustrative only and are not intended to be limiting. Other devices are possible and are contemplated.

[0064] The present disclosure further contemplates the use of a common scalable computing architecture among some or all of the various devices disclosed in Fig.8. Thus, a computing element may be scaled according to the requirements of the particular system in which it is implemented. For example, smartwatch / health-related monitoring device 860 may use a first implementation of a computing element of a scalable architecture, while tablet computer 830 uses a second implementation and desktop computer 810 uses a third implementation. In this particular example, the implementation of the computing element in tablet computer 830 may be scaled up relative to smartwatch / health-related monitoring device 860. Similarly, the implementation of the computing element in desktop computer 810 may be scaled up relative to that of tablet computer 830.Thus, each of these devices may utilize a common computing architecture implemented at a scale appropriate to the requirements of their respective systems. In conjunction with the scalable architecture, a power delivery system according to this disclosure may be deployed in each of these applications and may scale with the computing element accordingly. Thus, while each of the examples discussed herein may utilize a power delivery system with a common design, the implementation for desktop computer 810 may have greater power delivery capacity than that of tablet computer 830, which in turn has greater power delivery capacity than that of smartwatch / health-related monitoring device 860.However, the common design of the power delivery system used among these various devices can significantly simplify their implementation, since the power delivery system can be configured for the particular application by enabling / disabling appropriate power converters therein.

Claims

[1] Facility comprising: a hierarchical power output circuit (100) including: a first level (102) of power converter circuitry configured to generate one or more regulated first level supply voltages (102) from an input voltage; a second level (104) of power converter circuitry configured to generate from corresponding ones of the first level (102) regulated supply voltages one or more second level regulated supply voltages (104) to a data processing element (110) comprising one or more integrated circuits configured to operate as a single logical computer system, the data processing element (110) being configured to operate in a plurality of power configurations having different numbers of load circuits; and wherein the hierarchical power delivery circuit (100) is configured to selectively activate different portions of the first and second power converter levels (102, 104) for corresponding ones of the plurality of power configurations of the data processing element (110). [2] The device of claim 1, wherein the first level (102) regulated supply voltages include a first regulated supply voltage and a second regulated supply voltage generated by a first power converter and a second power converter, respectively. [3] The device of claim 2, wherein the one or more regulated supply voltages of the second level (104) include a third regulated supply voltage and a fourth regulated supply voltage, wherein respective ones of a first plurality of power converters (204, 208, 240-250, 261-265) implemented in a first integrated circuit are configured to generate the third regulated supply voltage, and wherein respective ones of a second plurality of power converters (204, 208, 240-250, 261-265) implemented in a second integrated circuit are configured to generate the fourth regulated supply voltage. [4] The device of claim 1, wherein the second level (104) of power converter circuitry includes a plurality of power converters (204, 208, 240-250, 261-265), wherein a number of activated ones of the plurality of power converters (204, 208, 240-250, 261-265) depends on a particular one of the plurality of power configurations of the data processing element (110). [5] The device of claim 1, wherein the second level (104) of power converter (204, 208, 240-250, 261-265) includes a plurality of power converters (204, 208, 240-250, 261-265), wherein a number of activated ones of the plurality of power converters (204, 208, 240-250, 261-265) depend on a number of integrated circuits comprising the data processing element (110). [6] The device of claim 1, wherein the first level (102) of power converter circuitry includes at least one multi-phase power converter, wherein a number of enabled phases of the at least one multi-phase power converter depends on a number of load circuits supplied to the one or more integrated circuits of the data processing element (110) by the second level (104) of power converter circuitry. [7] The device of claim 1, wherein the second power converter level (104) includes a power converter (204, 208, 240-250, 261-265) having control circuitry configured to control turn-on and turn-off sequences for at least one power converter (204, 208, 240-250, 261-265) of the first power converter level (102) and one or more power converters (204, 208, 240-250, 261-265) of the second power converter level (104). [8] The device of claim 1, wherein the second power converter level (104) includes one or more buck converters with coupled inductors. [9] The device of claim 1, further comprising at least one control bus coupled between respective power converters (204, 208, 240-250, 261-265) of the first and second power converter levels (104). [10] The device of claim 1, wherein the first power converter level (102) includes at least one power converter (204, 208, 240-250, 261-265) configured to remain operational when the input voltage is present, and wherein the first and second power converter levels (104) further include respective power converters (204, 208, 240-250, 261-265) configured to enter a sleep mode. [11] System comprising: a data processing element (110) consisting of one or more integrated circuits configured to operate as a single logical computer system, the data processing element (110) being configured to operate in a plurality of power configurations having different numbers of load circuits; and a power delivery system (100) configured to provide power to the computing element, the power delivery system (100) comprising: a first power converter level (102) comprising first and second power converters configured to generate first and second regulated supply voltages from a common input voltage; and a second power converter level (104) comprising a first plurality of power converters (204, 208, 240-250, 261-265) and a second plurality of power converters (204, 208, 240-250, 261-265), wherein respective ones of the first plurality of power converters (204, 208, 240-250, 261-265) are configured to generate a third regulated supply voltage from the first regulated supply voltage, and wherein respective ones of the second plurality of power converters (204, 208, 240-250, 261-265) are configured to generate a fourth regulated supply voltage from the second regulated supply voltage; wherein the power delivery system (100) is configured to selectively activate different portions of the first and second power converter levels (104) for corresponding ones of the plurality of power configurations of the computing cluster. [12] The system of claim 11, wherein the computing element (110) comprises a computing architecture scalable from a first of the plurality of performance configurations comprising a single integrated circuit die to one or more additional ones of the plurality of performance configurations comprising two or more integrated circuit dies, the two or more integrated circuit dies being configured as a single system in which the presence of multiple integrated circuit dies is transparent to the software executing on the single system. [13] The system of claim 11, wherein the plurality of power configurations includes at least one configuration wherein a portion of a single integrated circuit is disabled. [14] The system of claim 11, wherein the first and second power converters are multi-phase power converters (204, 208, 240-250, 261-265), wherein a number of phases enabled for one of the first and second power converters depends on a selected one of the plurality of power configurations. [15] A non-transitory computer-readable medium storing instructions which, when executed on a computer system, are usable for manufacturing an electronic circuit, the electronic circuit comprising: a hierarchical power output circuit (100) including: a first level (102) of power converter circuitry configured to generate a first supply voltage and a second supply voltage from an input voltage; a second level (104) of power converter circuitry configured to generate, from corresponding ones of the first and second supply voltages, one or more instances of a third supply voltage and one or more instances of a fourth supply voltage to be provided to a data processing element (110) comprising one or more integrated circuits configured to operate as a single logical computer system, wherein the data processing element (110) is configured to operate in a plurality of power configurations having different numbers of load circuits; and wherein the hierarchical power delivery circuit (100) is configured to selectively activate different portions of the first and second power converter levels (104) for corresponding ones of the plurality of power configurations of the data processing element (110).

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