Semiconductor module and semiconductor unit

Abstract

Semiconductor module (10) comprising: a first chip (20) containing a main transistor (21) with an electron transit layer serving as the main drift layer (24); a second chip (30) containing at least part of an active clamping circuit (40) with a clamping transistor (41), the clamping transistor (41) operating on the basis of an increase in the drain-source voltage of the main transistor; a connecting element (50) electrically connecting the main transistor and the active clamping circuit; and a sealing resin (60) sealing the first chip, the second chip, and the connecting element. The clamping transistor has a subdrift layer (45) formed from a different material than the main drift layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor module and a semiconductor unit. BACKGROUND

[0002] A known discrete semiconductor device includes a power transistor as the main transistor (see, for example, Patent Literature 1). CITATION LISTPatent literature

[0003] Patent Literature 1: Japanese Laid-Open Patent Publication No. 2018-82011 (JP 2018- 82 011 A) SUMMARY OF THE INVENTIONTechnical problem

[0004] If the drain-source voltage of a main transistor changes significantly, the gate-source voltage of the main transistor increases. In this case, the main transistor may be mistakenly turned on, which is called spurious turn-on. Solution to the problem

[0005] One aspect of the present disclosure is a semiconductor module comprising: a first chip having a main transistor including a main drift layer; a second chip having at least a portion of an active clamp circuit including a sub-transistor configured to be activated based on an increase in a drain-source voltage of the main transistor; an interconnection element electrically connecting the main transistor and the active clamp circuit; and an encapsulation resin encapsulating the first chip, the second chip, and the interconnection element. The sub-transistor includes a sub-drift layer formed of a material different from that of the main drift layer.

[0006] One aspect of the present disclosure is a semiconductor device comprising: the semiconductor module described above; a third chip disposed in the encapsulating resin separately from the first chip and the second chip and including a driver circuit configured to drive the main transistor; and a control connector electrically connecting the third chip to the first chip and the second chip. Advantageous effects of the invention

[0007] The semiconductor module and the semiconductor unit described above prevent the occurrence of erroneous turning on of the main transistor when the drain-source voltage of the main transistor changes sharply. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view schematically showing the internal structure of a semiconductor module according to a first embodiment. Fig. 2 is a cross-sectional view of the semiconductor module taken along the line F2-F2 in Fig. 1. Fig. 3 is a cross-sectional view of the semiconductor module taken along the line F3-F3 in Fig. 1. Fig. 4 is a rear view of the Fig. 1 shown semiconductor module. Fig. 5 is a cross-sectional view schematically showing the cross-sectional structure of a main transistor in the semiconductor module. Fig. 6 is a cross-sectional view schematically showing the cross-sectional structure of a clamp transistor of an active clamp circuit of the semiconductor module. Fig. 7 is a cross-sectional view schematically showing the cross-sectional structure of a clamping capacitor of the active clamping circuit of the semiconductor module. Fig. 8 is a schematic cross-sectional view showing the cross-sectional structure of a pull-down resistor of the active clamp circuit of the semiconductor module. Fig. 9 is a circuit diagram of the semiconductor module. Fig. Figure 10 is a graph showing changes in the drain-source voltage and gate-source voltage of a main transistor and the gate-source voltage of a clamp transistor. Fig. 11 is a plan view schematically showing the internal structure of a semiconductor module according to a second embodiment. Fig. 12 is a plan view of the Fig. 11 shown semiconductor module. Fig. 13 is a cross-sectional view of the semiconductor module taken along line F13-F13 in Fig. 11. Fig. 14 is a plan view schematically showing the internal structure of a second chip of the semiconductor module. Fig. 15 is a cross-sectional view taken along line F15-F15 in Fig. 14, which schematically shows the cross-sectional structure of the second chip. Fig. 16 is a plan view schematically showing the internal structure of a semiconductor module according to a third embodiment. Fig. 17 is a cross-sectional view of the semiconductor module taken along line F17-F17 in Fig. 16. Fig. 18 is a cross-sectional view of the semiconductor module taken along line F18-F18 in Fig. 16. Fig. 19 is a plan view schematically showing the internal structure of a semiconductor unit according to a fourth embodiment. Fig. 20 is a plan view mainly showing the connection configuration of the Fig. 19 shows the semiconductor unit. Fig. 21 is a plan view of the semiconductor unit. Fig. 22 is a cross-sectional view of the semiconductor device taken along the line F22-F22 in Fig. 21. Fig. 23 is a cross-sectional view of the semiconductor device taken along the line F23-F23 in Fig. 21. Fig. 24 is a circuit diagram of the semiconductor unit. Fig. 25 is a cross-sectional view schematically showing the cross-sectional structure of a pull-down resistor of a semiconductor module according to a modified example. Fig. 26 is a cross-sectional view schematically showing the cross-sectional structure of a pull-down resistor of a semiconductor module according to a modified example. Fig. 27 is a circuit diagram of a semiconductor module according to a modified example. Fig. 28 is a cross-sectional view schematically showing the cross-sectional structure of a protection diode in the Fig. 27 shows the semiconductor module shown. Fig. 29 is a circuit diagram of a semiconductor module according to a modified example. Fig. 30 is a circuit diagram of a semiconductor module according to a modified example. Fig. 31 is a circuit diagram of a semiconductor unit according to a modified example. DESCRIPTION OF THE EMBODIMENTS

[0008] Embodiments of a semiconductor module and a semiconductor unit of the present disclosure are described below with reference to the drawings. For simplicity and clarity of illustration, the components in the drawings are not necessarily drawn to scale. In a cross-section, hatching may be omitted for clarity. The accompanying drawings only illustrate embodiments of the present disclosure and are not intended to limit the present disclosure.

[0009] The following detailed description shows exemplary embodiments of a device (apparatus), a system, and a method according to the present disclosure. The detailed description is for illustrative purposes and does not limit the embodiments of the present disclosure or the application and uses of the embodiments. First embodiment

[0010] The structure of a semiconductor module according to a first embodiment will now be described with reference to FIGS. 1 to 9. Fig. Figure 1 shows a schematic representation of the internal structure of the semiconductor module. For better illustration, Fig. 1 the components arranged in the semiconductor module are shown by solid lines. Schematic structure of a semiconductor module

[0011] As in Fig. 1, a semiconductor module 10 includes a first chip 20 having a main transistor 21, a second chip 30 having an active clamp circuit 40, a connecting element 50 electrically connecting the main transistor 21 and the active clamp circuit 40, and an encapsulating resin 60 encapsulating the first chip 20, the second chip 30, and the connecting element 50.

[0012] The encapsulation resin 60 is made of an insulating resin material. Such a resin material is, for example, an epoxy resin, an acrylic resin, or a phenolic resin. The encapsulation resin 60 defines the outer surfaces of the semiconductor module 10. In the present embodiment, the encapsulation resin 60 has the shape of a rectangular plate. The encapsulation resin 60 includes a resin front surface 61 and a resin back surface 62 (see Fig. 2) facing in opposite directions, and first to fourth resin side surfaces 63 to 66 intersecting with the resin front surface 61 and the resin back surface 62. In the present embodiment, the first to fourth resin side surfaces 63 to 66 are orthogonal to the resin front surface 61 and the resin back surface 62. The direction in which the resin front surface 61 and the resin back surface 62 are arranged is referred to as the "z direction." The thickness direction of the encapsulating resin 60 also refers to the z direction. A view of the semiconductor module 10 taken in the z direction is referred to as a "top view." In the following description, the term "top view" includes the meaning of "a view taken in the thickness direction of the encapsulating resin 60." Two directions that are orthogonal to each other and orthogonal to the z direction are referred to as the "x direction" and the "y direction."

[0013] In plan view, the encapsulating resin 60 is rectangular and has a long side direction (also referred to as the longitudinal direction or long side direction) and a short side direction (also referred to as the transverse direction or short side direction). In the present embodiment, the encapsulating resin 60 is arranged so that the long side direction coincides with the y-direction and the short side direction coincides with the x-direction. The first resin side surface 63 and the second resin side surface 64 form opposite end surfaces of the encapsulating resin 60 in the y-direction. The third resin side surface 65 and the fourth resin side surface 66 form opposite end surfaces of the encapsulating resin 60 in the x-direction.

[0014] The semiconductor module 10 further includes a first die pad 71 on which the first chip 20 is mounted, and a second die pad 72 on which the second chip 30 is mounted. The die pads 71 ​​and 72 are formed from a metal material such as copper (Cu), aluminum (Al), or the like. In plan view, the die pads 71 ​​and 72 are rectangular. The first die pad 71 and the second die pad 72 are aligned with each other in the short side direction (also referred to as the short side direction, x-direction) of the encapsulation resin 60 and separated from each other in the long side direction (also referred to as the long side direction, y-direction) of the encapsulation resin 60. In the present embodiment, as shown in Fig. 2, the die pads 71 ​​and 72 are aligned with each other in the z-direction. The die pads 71 ​​and 72 are separated from the resin backside 62 in the z-direction toward the resin frontside 61 and are therefore not exposed on the resin backside 62. Alternatively, the semiconductor module 10 can be configured such that at least one of the two pads, namely the first die pad 71 and the second die pad 72, is exposed from the resin backside 62.

[0015] As in Fig. As shown in Figure 2, the first chip 20 has a chip front side 20s and a chip back side 20r that are oppositely oriented in the z-direction. The chip front side 20s faces in the same direction as the resin front side 61. The chip back side 20r faces in the same direction as the resin back side 62. The chip back side 20r faces the first die pad 71. The first chip 20 is connected to the first die pad 71 by a first bonding material AD1. More specifically, the first bonding material AD1 connects the chip back side 20r and the first die pad 71. The first bonding material AD1 is, for example, a conductive bonding material such as solder paste or silver (Ag) paste.

[0016] As in Fig. As shown in Figure 1, a drain pad PD1, a source pad PS1, and a gate pad PG1 are formed on the chip front side 20s. In plan view, the drain pad PD1, the source pad PS1, and the gate pad PG1 are arranged separately from each other. In the present embodiment, the x-direction, i.e., the arrangement direction of the drain pad PD1 and the source pad PS1, corresponds to a "first direction." In the plan view, the arrangement direction of the first chip 20 and the second chip 30 is orthogonal to the arrangement direction (first direction) of the drain pad PD1 and the source pad PS1. In the present embodiment, the y-direction, i.e., the arrangement direction of the first chip 20 and the second chip 30, corresponds to a "second direction."

[0017] The drain pad PD1 is electrically connected to a drain electrode 21D (see Fig. 5) of the main transistor 21. The drain pad PD1 is located closer to the fourth resin side surface 66 than the source pad PS1 and the gate pad PG1.

[0018] The source pad PS1 is electrically connected to a source electrode 21S (see Fig. 5) of the main transistor 21. The source pad PS1 is located closer to the third resin side surface 65 than the drain pad PD1 and the gate pad PG1.

[0019] The gate pad PG1 is electrically connected to a gate electrode 21G (see Fig. 5) of the main transistor 21. The gate pad PG1 is located between the drain pad PD1 and the source pad PS1 in the x-direction. The arrangement of the drain pad PD1, the source pad PS1, and the gate pad PG1 can be changed as desired.

[0020] As in Fig. As shown in Figure 2, the second chip 30 includes a chip front side 30s and a chip back side 30r that are oppositely oriented in the z-direction. The chip front side 30s faces in the same direction as the resin front side 61. The chip back side 30r faces in the same direction as the resin back side 62. The chip back side 30r faces the second die pad 72. The second chip 30 is connected to the second die pad 72 by a second bonding material AD2. More specifically, the second bonding material AD2 connects the chip back side 30r and the second die pad 72. Like the first bonding material AD1, the second bonding material AD2 is also a conductive bonding material.

[0021] As in Fig. As shown in FIG. 1, a source pad PS2, a pad PG2, and a capacitor pad PCA are formed on the chip front side 30s. In plan view, the source pad PS2, the pad PG2, and the capacitor pad PCA are arranged separately from each other. In the present embodiment, the pads PS2, PG2, and PCA are arranged separately from each other in a plan view. In other words, the pads PS2, PG2, and PCA are arranged separately from each other in a direction orthogonal to the arrangement direction (y direction) of the first chip 20 and the second chip 30. The arrangement of the source pad PS2, the pad PG2, and the capacitor pad PCA can be arbitrarily changed.

[0022] The source pad PS2 is electrically connected to a source electrode 41 S of a clamping transistor 41 (see Fig. 6) of the active clamp circuit 40. The source pad PS2 is located closer to the third resin side surface 65 than the pad PG2 and the capacitor pad PCA.

[0023] The pad PG2 is electrically connected to the gate electrode 41G (see Fig. 6) of the clamping transistor 41. The capacitor pad PCA is electrically connected to a clamping capacitor 42 (see Fig. 6) of the active clamp circuit 40. Viewed in the y-direction, the pad PG2 and the capacitor pad PCA are arranged to overlap each other. The pad PG2 is located closer to the first resin side surface 63 than the capacitor pad PCA.

[0024] As in Fig. As shown in Figure 4, the semiconductor module 10 further includes a drain terminal 81, a source terminal 82, and a gate terminal 83, which serve as external terminals. The terminals 81 to 83 are exposed from the resin backing 62. The terminals 81 to 83 are formed, for example, from a plating layer of a conductive material. The conductive material may be, for example, Cu, Al, a CuAl alloy, or the like.

[0025] As in Fig. 3, the drain terminal 81 and the source terminal 82 are located closer to the resin backsheet 62 than the first die pad 71 and the second die pad 72 in the z-direction. Thus, the first die pad 71 and the second die pad 72 are not exposed from the resin backsheet 62. Viewed in the z-direction, the drain terminal 81 and the source terminal 82 are arranged to partially overlap the first die pad 71. Although not shown, the drain terminal 81 and the source terminal 82 are arranged to partially overlap the second die pad 72.

[0026] As in Fig. 1, the gate terminal 83 is integrated into the second die pad 72. The second die pad 72 has a mounting portion on which the second chip 30 is mounted. The mounting portion is located closer to the resin front side 61 (see Fig. 2) as the gate terminal 83. In one example, the fixing portion and the gate terminal 83 are connected by a joining portion extending toward the resin back surface 62 (see Fig. 2) is inclined in a direction from the mounting portion to the gate terminal 83. However, the joining portion need not be inclined. Alternatively, the gate terminal 83 and the second die pad 72 may be arranged separately and electrically connected to each other by a connecting element, e.g., a wire.

[0027] As in Fig. As shown in FIG. 1, the connecting member 50 includes a first connecting member 51, a second connecting member 52, and a third connecting member 53. In the present embodiment, the connecting members 51 to 53 may be formed, for example, from a metal plate. The metal plate may be formed, for example, from Cu, Al, a CuAl alloy, or the like. The connecting members 51 to 53 are not limited to a metal plate and may be formed, for example, from metal plating (metal coating). That is, the connecting members 51 to 53 may be formed from a plating layer.

[0028] The first connecting element 51 is configured to electrically connect the source terminal 82, the source pad PS1 of the first chip 20, and the source pad PS2 and the pad PG2 of the second chip 30. Thus, the source terminal 82, the source electrode 21S of the main transistor 21, and the source electrode 41S and the pull-down resistor 43 of the clamping transistor 41 are electrically connected.

[0029] The second connection element 52 is configured to electrically connect the drain terminal 81, the drain pad PD1 of the first chip 20, and the capacitor pad PCA of the second chip 30. Thus, the drain terminal 81, the drain electrode 21D of the main transistor 21, and the clamp capacitor 42 are electrically connected.

[0030] The third connecting element 53 is configured to electrically connect the gate pad PG1 of the first chip 20 and the second die pad 72. Thus, the gate electrode 21G of the main transistor 21 is electrically connected to the gate terminal 83.

[0031] The shape of the first connecting element 51 in the plan view is not based on the shape of the Fig. 1 and can be changed as desired. The shapes of the second connecting element 52 and the third connecting element 53 can also be changed as desired. Detailed structure of the first chip

[0032] Fig. 5 is a cross-sectional view schematically showing an example of the cross-sectional structure of the first chip 20. Some of the hatched lines are omitted for simplicity and clarity.

[0033] As in Fig. 5, the first chip 20 includes a semiconductor substrate 22. The semiconductor substrate 22 is rectangular and plate-shaped. The semiconductor substrate 22 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 22 may be a Si substrate. The semiconductor substrate 22 may, for example, have a thickness of 200 µm to 1500 µm. The main transistor 21 is formed on the semiconductor substrate 22. The main transistor 21 includes a buffer layer 23 formed on the semiconductor substrate 22, an electron transit layer 24 including a main drift layer formed on the buffer layer 23, and an electron supply layer 25 formed on the electron transit layer 24. The buffer layer 23, the electron transit layer 24 and the electron supply layer 25 each have a thickness in the z-direction.“Top view” therefore also means “view in the thickness direction of the main drift layer (electron transit layer)”.

[0034] Buffer layer 23 is disposed between semiconductor substrate 22 and electron transit layer 24 and is formed from any material that reduces the lattice mismatch between semiconductor substrate 22 and electron transit layer 24. Buffer layer 23 includes one or more nitride semiconductor layers. Buffer layer 23 may, for example, include at least one aluminum nitride (AlN) layer, one aluminum gallium nitride (AlGaN) layer, or a graded AlGaN layer with different aluminum compositions. Buffer layer 23 may, for example, include a single AlN layer, a single AlGaN layer, a layer with an AlGaN / GaN superlattice structure, a layer with an AlN / AlGaN superlattice structure, or a layer with an AlN / GaN superlattice structure.

[0035] In one example, the buffer layer 23 includes a first buffer layer, which is an AlN layer formed on the semiconductor substrate 22, and a second buffer layer, which is an AlGaN layer formed on the AlN layer. In one example, the first buffer layer is an AlN layer with a thickness of 200 nm. In one example, the second buffer layer has a structure in which multiple AlGaN layers are stacked on top of each other. To prevent leakage currents in the buffer layer 23, the buffer layer 23 may be partially doped with an impurity so that the buffer layer 23 is semi-insulating. In this case, the impurity is, for example, carbon (C) or iron (Fe). The concentration of the impurity may, for example, be greater than or equal to 4 × 10 16 cm -3 be.

[0036] The electron transit layer 24 may be formed from a nitride semiconductor and may, for example, be a GaN layer. The thickness of the electron transit layer 24 may, for example, be in the range of 300 nm to 2 µm, and preferably in the range of 300 nm to 400 nm. In one example, the thickness of the electron transit layer 24 is 350 nm. As described above, the main transistor 21 is a GaN transistor, in which the electron transit layer 24 is formed from GaN as the main drift layer.

[0037] To prevent leakage currents from the electron junction layer 24, the electron junction layer 24 can be partially doped with an impurity, so that the electron junction layer 24 is semi-insulating except for its surface region. In this case, the impurity is, for example, BC. The concentration of the impurity can, for example, be greater than or equal to 1 × 10 19 cm -3at a peak concentration. More specifically, the electron transit layer may contain 24 GaN layers with different impurity concentrations, e.g., a C-doped GaN layer and a non-doped GaN layer. The C concentration in the C-doped GaN layer may be in a range of 9×10 18 cm -3 up to 9×10 19 cm -3 lay.

[0038] The electron supply layer 25 may be formed from a nitride semiconductor with a larger band gap than the electron transit layer 24 and may, for example, be an AlGaN layer. The band gap increases with increasing Al composition. Therefore, the electron supply layer 25, which is an AlGaN layer, has a larger band gap than the electron transit layer 24, which is a GaN layer. In one example, the electron supply layer 25 may be made of Al z Ga 1-zN, where 0.1 < z < 0.4 and preferably 0.2 < z < 0.3. In one example, z = 0.25. The electron supply layer 25 has a thickness in the range of, for example, 5 nm to 20 nm. In one example, the electron supply layer 25 has a thickness in the range of 8 nm to 15 nm.

[0039] The electron transit layer 24 and the electron supply layer 25 can be formed from nitride semiconductors with different lattice constants. A lattice mismatch between the electron transit layer 24 and the electron supply layer 25 strains / strains the electron supply layer 25. The strain induces a two-dimensional electron gas 26 (2DEG) in the electron transit layer 24. The 2DEG 26 spreads in the electron transit layer 24 at a location near the heterojunction boundary between the electron transit layer 24 and the electron supply layer 25 (e.g., about a few nanometers from the boundary). The 2DEG 26 is used as a current path (channel) of the main transistor 21.

[0040] The main transistor 21 further includes a gate layer 27 formed on a portion of the electron supply layer 25, the gate electrode 21G formed on the gate layer 27, a passivation layer 28, the source electrode 21S, and the drain electrode 21D. The passivation layer 28 covers the electron supply layer 25, the gate layer 27, and the gate electrode 21G and includes a first opening 28A and a second opening 28B. The source electrode 21S is in contact with the electron supply layer 25 through the first opening 28A. The drain electrode 21D is in contact with the electron supply layer 25 through the second opening 28B.

[0041] The gate layer 27 may be formed from a nitride semiconductor containing an acceptor impurity. The gate layer 27 is formed, for example, from any material that has a smaller band gap than the electron supply layer 25, which is an AlGaN layer. In one example, the gate layer 27 is a GaN layer (p-type GaN layer) doped with an acceptor impurity. The acceptor impurity may contain at least one of the elements zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor impurity in the gate layer 27 is, for example, in a range of 7×10 18 cm -3 up to 1×10 20 cm -3The main transistor 21, which includes the gate layer 27 made of a nitride semiconductor with an acceptor impurity, depletes the 2DEG 26 in a region immediately below the gate layer 27. This allows the main transistor 21 to be used as a normally-off transistor. That is, the main transistor 21 is a normally-off transistor.

[0042] The gate layer 27 has a lower surface 27r in contact with the electron supply layer 25 and an upper surface 27s opposite the lower surface 27r. The gate electrode 21G is formed on the upper surface 27s of the gate layer 27.

[0043] In the present embodiment, the gate layer 27 has a ridge 27C including the upper surface 27s on which the gate electrode 21G is formed, and two extensions (first extension 27A and second extension 27B) extending outward from the ridge 27C in plan view.

[0044] In plan view, the first extension 27A extends from the web 27C toward the first opening 28A. The first extension 27A is separated from the first opening 28A.

[0045] In plan view, the second extension 27B extends from the web 27C toward the second opening 28B. The second extension 27B is separated from the second opening 28B.

[0046] The ridge 27C is located between the first extension 27A and the second extension 27B and is formed integrally with the first extension 27A and the second extension 27B. Since the gate layer 27 includes the first extension 27A and the second extension 27B, the lower surface 27r is larger in area than the upper surface 27s. In the present embodiment, the second extension 27B extends outward from the ridge 27C longer than the first extension 27A in plan view.

[0047] Fin 27C corresponds to a relatively thick portion of gate layer 27 and has a thickness in the range of, for example, 80 nm to 150 nm. The thickness of gate layer 27, in particular fin 27C, can be determined by considering parameters such as the gate threshold voltage. In one example, the thickness of gate layer 27 (fin 27C) is greater than 110 nm.

[0048] The first extension 27A and the second extension 27B each have a thickness less than the web 27C. In one example, the thickness of the first extension 27A and the second extension 27B is each less than or equal to half the thickness of the web 27C.

[0049] In the present embodiment, each of the extensions 27A and 27B is a flat portion having a substantially constant thickness. In this specification, the term "substantially constant thickness" refers to a thickness that is within a manufacturing variation range (e.g., 20%). Alternatively, each of the extensions 27A and 27B may include a tapered portion having a thickness that gradually decreases as the ridge 27C is further removed in a region adjacent to the ridge 27C. Each of the extensions 27A and 27B may include a flat portion having a substantially constant thickness in a region a predetermined distance away from the ridge 27C. In one example, the flat portion has a thickness in the range of 5 nm to 25 nm.

[0050] The gate electrode 21G formed on the fin 27C may be formed from one or more metal layers. The metal layer is, for example, a TiN layer. Alternatively, the gate electrode 21G may include a first metal layer made of Ti and a second metal layer made of TiN formed on the first metal layer. The gate electrode 21G has a thickness in a range of, for example, 50 nm to 200 nm. The gate electrode 21G may form a Schottky junction with the gate layer 27.

[0051] The first opening 28A and the second opening 28B of the passivation layer 28 are separated from the gate layer 27. The gate layer 27 is disposed between the first opening 28A and the second opening 28B. More specifically, the gate layer 27 is disposed between the first opening 28A and the second opening 28B at a position closer to the first opening 28A than to the second opening 28B. The passivation layer 28 extends along the top surface of the electron supply layer 25, the side surface and the top surface 27s of the gate layer 27, and the side surface and the top surface of the gate electrode 21G. Thus, the passivation layer 28 has a non-flat surface.

[0052] The source electrode 21S and the drain electrode 21D are formed from one or more metal layers. The metal layer can comprise any combination of, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 21S fills the first opening 28A. At least a portion of the drain electrode 21D fills the second opening 28B. The source electrode 21S is in ohmic contact with the 2DEG 26 located directly below the electron supply layer 25 through the first opening 28A. The drain electrode 21D is in ohmic contact with the 2DEG 26 located directly below the electron supply layer 25 through the second opening 28B.

[0053] The source electrode 21S includes a source contact 21SA filling the first opening 28A and a source field plate 21SB covering the passivation layer 28. The source field plate 21SB is formed integrally with the source contact 21SA. In plan view, the source field plate 21SB includes an end 21SC located between the second opening 28B and the gate layer 27 in plan view. The source field plate 21SB extends from the source contact 21SA to the end 21SC along the surface of the passivation layer 28 toward the drain electrode 21D, but is spaced apart from the drain electrode 21D. Since the source field plate 21SB extends along the non-planar surface of the passivation layer 28, the source field plate 21SB similarly has a non-planar surface. In a state where no gate voltage is applied to the gate electrode 21G, ieIn the zero bias state, when a drain voltage is applied to the drain electrode 21D, the source field plate 21SB reduces the concentration of the electric field near the end of the gate electrode 21G.

[0054] The drain electrode 21D and the source electrode 21S are covered by an interlayer insulation layer 29. The interlayer insulation layer 29 has an interconnection layer (not shown). The interconnection layer includes a drain interconnection connecting the drain electrode 21D and the drain pad PD1 (see Fig. 1) electrically connects a source interconnection connecting the source electrode 21S and the source pad PS1 (see Fig. 1) and a gate interconnection connecting the gate electrode 21G and the gate pad PG1 (see Fig. 1) electrically connects.

[0055] The first chip 20 therefore does not contain the active clamp circuit 40, but the main transistor 21. In the present embodiment, only the main transistor 21 is formed on the semiconductor substrate 22 in the first chip 20. Detailed structure of the second chip

[0056] As in Fig. 1, the active clamp circuit 40 is configured to prevent the occurrence of a faulty turn-on due to a sharp change in the drain-source voltage when the main transistor 21 is in a deactivated state. The active clamp circuit 40 includes the clamp transistor 41 (see Fig. 6), which is an example of a sub-transistor, the clamping capacitor 42 (see Fig. 7) and the pull-down resistor 43 (see Fig. 8). The clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 are electrically connected to each other in the second chip 30.

[0057] In the plan view, the pull-down resistor 43 is arranged to overlap the pad PG2. In the present embodiment, the clamping transistor 41 is formed in a main portion of the second chip 30. The clamping capacitor 42 is formed in a different region of the second chip 30 than the region where the clamping transistor 41 is formed. In one example, in the plan view, the region where the clamping capacitor 42 is formed and the region where the pull-down resistor 43 is formed are each approximately 1 / 100 of the area of ​​the pad PG2. Fig. For simplicity, the capacitor pad PCA is shown enlarged in Figure 1. The actual capacitor pad PCA is smaller than the pad PG2.

[0058] Fig. 6 is a cross-sectional view of an example of the schematic cross-sectional structure of the second chip 30, showing the cross-sectional structure of a portion of an active area 41T of the clamping transistor 41. Some of the hatched lines are omitted for simplicity and clarity. The active area 41T of the clamping transistor 41 refers to a region in which a transistor is formed.

[0059] As in Fig. 6, the second chip 30 includes a semiconductor substrate 44. The semiconductor substrate 44 is rectangular and plate-shaped. The semiconductor substrate 44 may be formed of Si, SiC, GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 44 may be a Si substrate. The semiconductor substrate 44 may, for example, have a thickness of 200 µm to 1500 µm. The clamping transistor 41 is formed on the semiconductor substrate 22. The clamping capacitor 42 (see Fig. 7) and the pull-down resistor 43 (see Fig. 8) are formed on the semiconductor substrate 44.

[0060] The clamping transistor 41 includes an n-type drift layer 45 formed on the semiconductor substrate 44. In other words, the semiconductor substrate 44 supports the drift layer 45. The drift layer 45 is an example of a sub-drift layer and may be formed of a material different from that of the electron transit layer 24 (see Fig. 5), which is a main drift layer. The drift layer 45 may be formed of a material such as Si. For example, N, phosphorus (P), arsenic (As), or the like is used as the n-type impurity of the drift layer 45. The impurity concentration of the drift layer 45 is, for example, in a range of 1×10 13 cm -3 up to 5×10 14 cm -3As described above, the clamping transistor 41 is a transistor in which the drift layer 45, including the sub-drift layer, is formed of a material containing Si. In the present embodiment, the clamping transistor 41 is an Si transistor in which the drift layer 45 is formed of Si. Alternatively, the clamping transistor 41 may also be an SiC transistor in which the drift layer 45 is formed of SiC.

[0061] A p-type base region 46 is formed on a surface of the drift layer 45. For example, boron (B), Al, or the like is used as a p-type dopant for the base region 46. The base region 46 has an impurity concentration in the range of, for example, 1×10 16 cm -3 up to 1×10 18 cm -3 lies.

[0062] Trenches 47 are arranged side by side in the surface of the base region 46. In one example, the trenches 47 extend in the y-direction and are separated from each other in the x-direction. The trenches 47 extend through the base region 46 in the z-direction to an intermediate region of the drift layer 45. The trenches 47 can be arranged in a grid pattern in plan view.

[0063] A n + -type source region 48 is formed on the surface of the base region 46 on opposite sides of the trench 47 in the x-direction. In other words, the source region 48 is formed on the surface of the drift layer 45. The impurity concentration of the source region 48 is higher than the impurity concentration of the base region 46 and is, for example, in the range of 1×10 19 cm -3 up to 5×10 20 cm -3 .

[0064] A p +-type base contact region 46A is formed on the surface of base region 46 in the x-direction adjacent to source region 48. Base contact region 46A is arranged in the x-direction between two source regions 48, which are located in the x-direction between the trenches 47 adjacent to each other in the x-direction. The impurity concentration of base contact region 46A is higher than that of base region 46 and is, for example, in the range of 5×10 18 cm -3 up to 1×10 20 cm -3 .

[0065] An insulating film 49A is integrally formed on the wall surface of each trench 47 and the surface of the base region 46. The insulating film 49A is made of a material containing, for example, SiO2. An electrode material, such as polysilicon, is embedded in each trench 47 with the insulating film 49A. This forms the gate electrode 41G.

[0066] An interlayer insulating film 49B is formed on the insulating film 49A located on the surface of the base region 46. The interlayer insulating film 49B is made of a material containing, for example, SiO2. The interlayer insulating film 49B is thicker than the insulating film 49A. The source electrode 41S is formed on the interlayer insulating film 49B.

[0067] The insulating film 49A and the intermediate insulating film 49B each include openings 49C that expose the base contact region 46A. The source electrode 41S is embedded in the openings 49C to contact the base contact region 46A.

[0068] A drain electrode 41D is formed on the backside of the semiconductor substrate 44, on a side opposite the drift layer 45 in the z-direction. The drain electrode 41D and the source electrode 41S are formed of a material containing, for example, titanium (Ti), tungsten (W), Al, Cu, or an Al-Cu alloy.

[0069] Fig. 7 is a cross-sectional view showing an example of the cross-sectional structure of the clamp capacitor 42.

[0070] As in Fig. As shown in Figure 7, the clamping capacitor 42 is arranged such that it overlaps the capacitor pad PCA in plan view. In plan view, the area of ​​the second chip 30 that overlaps the capacitor pad PCA differs from the active area of ​​the clamping transistor 41. As shown in Fig. 7, the region overlapping the capacitor pad PCA has a structure in which the insulating film 49A is formed on the semiconductor substrate 44.

[0071] The clamp capacitor 42 has a first electrode 42P and a second electrode 42Q. The first electrode 42P and the second electrode 42Q are separated from each other by the insulating film 49A. More specifically, two openings 49D and 49E are separated from each other and formed in the insulating film 49A to expose the semiconductor substrate 44. The first electrode 42P fills the opening 49D and extends to an edge extending around the opening 49D. The second electrode 42Q fills the opening 49E and extends to an edge extending around the opening 49E. The portion of the first electrode 42P protruding from the opening 49D and the portion of the second electrode 42Q protruding from the opening 49E are covered by the interlayer insulating film 49B. The insulation film 49A formed between the first electrode 42P and the second electrode 42Q, ieThe portion of the insulating layer 49A located between the opening 49D and the opening 49E contains a dielectric layer. The first electrode 42P is electrically connected to the capacitor pad PCA, for example, via a via 42V.

[0072] Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of the pull-down resistor 43.

[0073] As in Fig. As shown in the top view of Figure 8, the pull-down resistor 43 is arranged to overlap the pad PG2. The pull-down resistor 43 has a first terminal 43P, a second terminal 43Q, and a plate-shaped resistance portion 43R. The second terminal 43Q is electrically connected to the pad PG2 via a via 43V, for example.

[0074] The first terminal 43P and the second terminal 43Q are separated from each other by the insulating film 49A. More specifically, two openings 49F and 49G are separated from each other and formed in the insulating film 49A to expose the resistance part 43R. The first terminal 43P fills the opening 49F and reaches to an edge extending around the opening 49F. The second terminal 43Q fills the opening 49G and reaches to an edge extending around the opening 49G. The portion of the first terminal 43P protruding from the opening 49F and the portion of the second terminal 43Q protruding from the opening 49G are covered by the interlayer insulating film 49B.

[0075] Resistor portion 43R is formed on semiconductor substrate 44. Resistor portion 43R may be made of a material having a greater resistance than the material forming first terminal 43P and second terminal 43Q. In one example, resistor portion 43R is formed of polysilicon, for example.

[0076] The first terminal 43P and the second terminal 43Q are arranged on the resistance part 43R. The first terminal 43P and the second terminal 43Q are electrically connected to the resistance part 43R. More specifically, the terminals 43P and 43Q are in ohmic contact with the resistance part 43R. In the plan view, the first terminal 43P and the second terminal 43Q are formed separately at two ends of the resistance part 43R in the y-direction. Thus, the pull-down resistor 43 is formed on the insulation film 49A and covered by the interlayer insulation film 49B.

[0077] As in the Fig. 7 and Fig. 8, the first electrode 42P and the second electrode 42Q of the clamp capacitor 42, the vias 42V and 43V, and the first terminal 43P and the second terminal 43Q of the pull-down resistor 43 may be formed, for example, from any conductive material including at least one of the following materials: Cu, Al, an Al-Cu alloy, W, Ti, and TiN.

[0078] The second chip 30 does not contain the main transistor 21, but does contain the active clamp circuit 40. More specifically, the second chip 30 includes the clamp transistor 41, the clamp capacitor 42, and the pull-down resistor 43. In the present embodiment, the second chip 30 includes only the clamp transistor 41, the clamp capacitor 42, and the pull-down resistor 43. Circuit arrangement of a semiconductor module

[0079] Fig. 9 shows the circuit arrangement of the semiconductor module 10. As in Fig. As shown in Figure 9, the active clamp circuit 40 is connected to the main transistor 21. More specifically, the source electrode 41S of the clamp transistor 41 is connected to the source electrode 21S of the main transistor 21. The drain electrode 41D of the clamp transistor 41 is connected to the gate electrode 21G of the main transistor 21. The clamp capacitor 42 is connected between the drain electrode 21D of the main transistor 21 and the gate electrode 41G of the clamp transistor 41. The pull-down resistor 43 is connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41.

[0080] The drain electrode 21D of the main transistor 21 and the clamping capacitor 42 are connected to the drain terminal 81. The source electrode 21S of the main transistor 21, the source electrode 41S of the clamping transistor 41, and the pull-down resistor 43 are connected to the source terminal 82. The gate electrode 21G of the main transistor 21 and the drain electrode 41D of the clamping transistor 41 are connected to the gate terminal 83. How it works

[0081] The operation of the present embodiment will now be described. A semiconductor module that does not include the second chip 30 is referred to as a "reference semiconductor module." The reference semiconductor module includes only the first chip 20. The first chip 20 (main transistor 21) is used, for example, for a DC-DC converter.

[0082] As in Fig. As shown in Figure 10, in the comparative semiconductor module, the drain-source voltage of the main transistor 21 can change significantly during a period from t1 to t2 when the main transistor is turned off. This occurs, for example, through an element (e.g., a coil of the DC-DC converter) connected to the main transistor 21. At this time, the gate-source voltage (gate voltage) of the main transistor 21 is increased by the parasitic gate-drain capacitance of the main transistor 21, as shown by the dashed lines in the middle section of Figure 10. Fig. 10. When the gate-source voltage exceeds the threshold of the main transistor 21, the main transistor 21 is turned on. In other words, in the comparison semiconductor module, the main transistor 21 enters an activated state even when it should be in a deactivated state (erroneous turn-on).

[0083] In this context, in the present embodiment, the clamping transistor 41 is configured to be activated based on an increase in the drain-source voltage of the main transistor 21. More specifically, the clamping transistor 41 is configured to turn on earlier than the main transistor 21 in response to a sharp change in the drain-source voltage of the main transistor 21. In one example, the capacitance of the clamping capacitor 42 is set so that the voltage of the second electrode 42Q increases rapidly compared to the gate-source voltage of the main transistor 21. For example, the clamping capacitor 42 has a capacitance smaller than the gate-drain capacitance of the main transistor 21. The clamping capacitor 41 may have a threshold voltage set lower than the threshold voltage of the main transistor 21.

[0084] When the clamp capacitor 42 described above is connected to the gate electrode 41G of the clamp transistor 41, the gate-source voltage of the clamp transistor 41 is increased by a sharp change in the drain-source voltage of the main transistor 21. This activates the clamp transistor 41, and the gate electrode 21G and the source electrode 21S of the main transistor 21 can be connected via the clamp transistor 41. As a result, the gate-source voltage of the main transistor 21 changes from rising to falling before fully rising. As shown by the solid lines in the middle section in Fig. As indicated in Figure 10, an increase in the gate-source voltage of the main transistor 21 is thus limited. This prevents the main transistor 21 from being switched on incorrectly.

[0085] When the comparative semiconductor module is provided with the active clamp circuit 40 as a measure against erroneous power-on, the active clamp circuit 40 (second chip 30) may be disposed on a circuit substrate arranged outside the comparative semiconductor module. In this configuration, the main transistor 21 in the comparative semiconductor module is connected to the active clamp circuit 40 arranged on the circuit substrate via a conduction path such as interconnections arranged on the circuit substrate. If the conduction path is long, the conduction path has a high parasitic impedance. Furthermore, the conduction path may have a parasitic inductance that delays the activation of the active clamp circuit 40 in response to a sharp change in the drain-source voltage of the main transistor 21.Therefore, when the drain-source voltage of the main transistor 21 changes greatly, the gate-source voltage may increase, and the main transistor 21 may be mistakenly turned on.

[0086] In the present embodiment, the semiconductor module 10 includes the first chip 20 and the second chip 30. In other words, the semiconductor module 10 includes the main transistor 21 and the active clamp circuit 40. This allows the main transistor 21 and the active clamp circuit 40 to be electrically connected to each other in the semiconductor module 10. This shortens the conduction path between the main transistor 21 and the active clamp circuit 40 compared to a structure in which the active clamp circuit 40 (second chip 30) is arranged on a circuit substrate arranged outside the comparative semiconductor module. This reduces the parasitic impedance and parasitic inductance of the conduction path. This prevents the main transistor 21 from being erroneously turned on. Advantages

[0087] The first embodiment has the following advantages.

[0088] (1-1) The semiconductor module 10 includes the first chip 20, the second chip 30, the interconnection member 50, and the encapsulation resin 60 that encapsulates the first chip 20, the second chip 30, and the interconnection member 50. The first chip 20 includes the main transistor 21 with the electron transit layer 24 including a main drift layer. The second chip 30 includes at least a part of the active clamp circuit 40 with the clamp transistor 41 configured to be activated based on an increase in the drain-source voltage of the main transistor 21. The interconnection member 50 electrically connects the main transistor 21 and the active clamp circuit 40 to each other.

[0089] The clamping transistor 41 contains the drift layer 45 as a sub-drift layer, which is formed of a different material than the main drift layer (electron transit layer 24).

[0090] In this structure, when the drain-source voltage of the main transistor 21 changes sharply, the clamp transistor 41 limits an increase in the gate-source voltage of the main transistor 21. This prevents the main transistor 21 from being turned on erroneously.

[0091] The main transistor 21 and the active clamp circuit 40 are electrically connected to each other in the semiconductor module 10. This shortens the conduction path between the main transistor 21 and the active clamp circuit 40. This reduces the parasitic impedance and parasitic inductance of the conduction path, further preventing the main transistor 21 from being turned on incorrectly.

[0092] The electron transit layer 24, which serves as the main drift layer, and the drift layer 45, which serves as the sub-drift layer, are made of different materials. This allows a suitable material to be used for each application. For example, if the main transistor 21 is a power transistor such as a GaN transistor or a SiC transistor, the clamping transistor 41 can be a general-purpose transistor, which is different from a power transistor.

[0093] (1-2) The main transistor 21 is a GaN transistor in which the electron transit layer 24 is formed of GaN. The clamping transistor 41 is a Si transistor in which the drift layer 45 is formed of Si. This structure reduces the cost of the clamping transistor 41 compared to a configuration in which the clamping transistor 41 is a GaN transistor.

[0094] (1-3) The first chip 20 does not include the active clamp circuit 40, but includes the main transistor 21. The second chip 30 includes the clamp transistor 41, the clamp capacitor 42, and the pull-down resistor 43. The clamp transistor 41, the clamp capacitor 42, and the pull-down resistor 43 are electrically connected to each other in the second chip 30.

[0095] In this structure, the first chip 20 and the second chip 30 are electrically connected in a simple manner, compared to a structure in which the first chip 20 includes part of the active clamp circuit 40.

[0096] (1-4) The second chip 30 includes pad PG2. Pad PG2 is connected to the gate electrode 41G of clamp transistor 41 via pull-down resistor 43. In plan view, pull-down resistor 43 is arranged to overlap pad PG2. Pull-down resistor 43 is located closer to drift layer 45 than pad PG2.

[0097] This structure allows for an increase in the active area of ​​the clamping transistor 41 compared to a structure in which the pull-down resistor 43 and the pad PG2 are formed in different regions in plan view. If the active area is not increased, the area of ​​the second chip 30 can be reduced in plan view.

[0098] (1-5) The first connecting member 51, the second connecting member 52 and the third connecting member 53 are each formed of a metal plate.

[0099] With this configuration, the structure of the encapsulating resin 60 is simplified compared to a configuration in which the connecting elements 51 to 53 include interconnections and vias formed from, for example, plating layers. This reduces the number of steps for manufacturing the semiconductor module 100.

[0100] (1-6) The first chip 20 includes the drain pad PD1 electrically connected to the drain electrode 21D of the main transistor 21, and the source pad PS1 electrically connected to the source electrode 21S of the main transistor 21. In the plan view, the drain pad PD1 and the source pad PS1 are arranged separately from each other in the x-direction. In the plan view, the first chip 20 and the second chip 30 are arranged separately from each other in the y-direction.

[0101] This configuration simplifies the structure of the connecting element 50, which electrically connects the active clamp circuit 40 to the drain electrode 21D and the source electrode 21S of the main transistor 21.

[0102] (1-7) The active clamp circuit 40 includes the pull-down resistor 43 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41, and the clamp capacitor 42 connected between the drain electrode 21D of the main transistor 21 and the gate electrode 41G of the clamp transistor 41.

[0103] With this configuration, when the drain-source voltage of the main transistor 21 changes dramatically, the dramatic voltage change increases the gate-source voltage of the clamping transistor 41 and activates the clamping transistor 41. As a result, an increase in the gate-source voltage of the main transistor 21 is limited. As described above, the activation and deactivation of the clamping transistor 41 is controlled within the semiconductor module 10, rather than based on a signal from a circuit external to the semiconductor module 10. This eliminates the need to provide the semiconductor module 10 with an additional pad for the signal. This limits the addition of pads for the active clamping circuit 40 on the semiconductor module 10. Second embodiment

[0104] A second embodiment of a semiconductor module 100 will now be described with reference to the Fig. 11 to 15. The semiconductor module 100 of the present embodiment differs from the semiconductor module 10 of the first embodiment primarily in the configurations of the first chip 20 and the second chip 30. In the following description, the same reference numerals are used for components identical to the corresponding components of the first embodiment. These components will not be described in detail here. Schematic structure of a semiconductor module

[0105] The schematic structure of the semiconductor module 100 is shown in Fig. 11 to 13 described.

[0106] Fig. 11 is a plan view of the internal structure of the semiconductor module 100, mainly showing an example of the arrangement configuration and the connection configuration of the first chip 20 and the second chip 30. Fig. 12 is a plan view of the semiconductor module 100. Fig. 13 is a cross-sectional view of the semiconductor module 100 taken along the line F13-F13 in Fig. 11, which mainly shows the cross-sectional structure of the first chip 20 and the second chip 30. In Fig. 12, the openings 113 to 116, which will be described later, are marked by double dashed lines for the sake of simplicity.

[0107] As in Fig. 11, the semiconductor module 100 comprises the first chip 20, the second chip 30, and an encapsulation resin 110 that encapsulates the chips 20 and 30. In Fig. 11, the chips 20 and 30 located in the encapsulation resin 110 are shown by solid lines for clarity.

[0108] The semiconductor module 100 has the shape of a rectangular plate. The encapsulation resin 110 defines the outer surfaces of the semiconductor module 100. This means that the encapsulation resin 110 has the shape of a rectangular plate. The encapsulation resin 110 has a resin front side 110s and a resin back side 110r (see Fig. 13) facing in opposite directions, and first to fourth resin side surfaces 110a to 110d, which are four resin side surfaces that intersect the resin front surface 110s and the resin back surface 110r. In the present embodiment, the first to fourth resin side surfaces 110a to 110d are orthogonal to the resin front surface 110s and the resin back surface 110r. In the present embodiment, the thickness direction of the encapsulating resin 110 refers to the z-direction. Thus, in the description, "top view" means "viewed in the thickness direction of the encapsulating resin 110."

[0109] In plan view, the encapsulating resin 110 is rectangular and has a long side direction (longitudinal direction) and a short side direction (lateral direction). In the present embodiment, the encapsulating resin 110 is arranged so that the long side direction coincides with the y-direction and the short side direction coincides with the x-direction. In the present embodiment, the first resin side surface 110a and the second resin side surface 110b define opposite end surfaces of the encapsulating resin 110 in the long side direction (y-direction), and the third resin side surface 110c and the fourth resin side surface 110d define opposite end surfaces of the encapsulating resin 110 in the short side direction (x-direction). The encapsulating resin 110 is made of an insulating resin material. Such a resin material is, for example, an epoxy resin, an acrylic resin, or a phenolic resin.

[0110] As in Fig. As shown in Figure 13, the encapsulation resin 110 includes a first encapsulation portion 111 and a second encapsulation portion 112. The first encapsulation portion 111 is a support substrate supporting the first chip 20 and the second chip 30. The first encapsulation portion 111 includes the resin back surface 110r. The second encapsulation portion 112 is formed on the first encapsulation portion 111 and encapsulates the first chip 20 and the second chip 30 together with the first encapsulation portion 111. The second encapsulation portion 112 includes the resin front surface 110s. The first chip 20 is bonded to the first encapsulation portion 111 by the first bonding material AD1. The second chip 30 is bonded to the first encapsulation portion 111 by the second bonding material AD2. The bonding materials AD1 and AD2 can each be a conductive or an insulating bonding material.

[0111] As in Fig. As shown in Figure 11, the first chip 20 differs in shape from the first chip 20 of the first embodiment. In the present embodiment, the first chip 20 has the shape of a rectangular plate having a long side direction and a short side direction. The first chip 20 is arranged so that the long side direction (long side direction) of the first chip 20 is aligned with the long side direction of the encapsulating resin 110, and the short side direction of the first chip 20 is aligned with the short side direction of the encapsulating resin 110. In plan view, the first chip 20 is formed on a substantial portion of the encapsulating resin 110.

[0112] The first chip 20 contains a drain pad PD which is electrically connected to the drain electrode 21D (see Fig. 6) of the main transistor 21, a main source pad PSM and a sense source pad PSS, which are electrically connected to the source electrode 21S (see Fig. 6) of the main transistor 21, and a gate pad PG electrically connected to the gate electrode 21G (see Fig. 6) of the main transistor 21.

[0113] In the first chip 20, the drain pad PD is located closer to the third resin side surface 110c than the center of the encapsulation resin 110 in the x-direction. The main source pad PSM, the sense source pad PSS, and the gate pad PG are located closer to the fourth resin side surface 110d than the center of the encapsulation resin 110 in the x-direction. The gate pad PG is located closer to the first resin side surface 110a than the main source pad PSM and the sense source pad PSS.

[0114] The main transistor 21 has an active region 21T. The active region 21T is a region where a transistor is formed. In the present embodiment, the active region 21T is rectangular in plan view and has a long side direction and a short side direction. The active region 21T is arranged so that the long side direction of the active region 21T is aligned with the long side direction of the first chip 20, and the short side direction of the active region 21T is aligned with the short side direction of the first chip 20. The drain pad PD is located closer to the third resin side surface 110c than the active region 21T. The main source pad PSM, the sense source pad PSS, and the gate pad PG are located closer to the fourth resin side surface 110d than the active region 21T.

[0115] The second chip 30 differs in shape from the second chip 30 of the first embodiment. In the present embodiment, the second chip 30 has the shape of a rectangular plate having a long side direction and a short side direction. In plan view, the area (second area) of the second chip 30 is smaller than the area (first area) of the first chip 20. In one example, the second area is less than or equal to half (1 / 2) of the first area. In one example, the second area is less than or equal to 1 / 5 of the first area. In one example, the second area is less than or equal to 1 / 10 of the first area.

[0116] The second chip 30 is arranged such that the long side direction of the second chip 30 is aligned with the short side direction of the encapsulation resin 110, and the short side direction of the second chip 30 is aligned with the long side direction of the encapsulation resin 110. The second chip 30 is located closer to the first resin side surface 110a than the first chip 20. Thus, the first chip 20 and the second chip 30 are separated from each other in the long side direction (y-direction) of the encapsulation resin 110. The long side direction of the first chip 20 is aligned with the arrangement direction of the first chip 20 and the second chip 30. The long side direction of the second chip 30 is orthogonal to the arrangement direction of the first chip 20 and the second chip 30 in plan view.

[0117] In the present embodiment, the second chip 30 is located closer to the fourth resin side surface 110d than the center of the encapsulation resin 110 in the x-direction. In other words, the second chip 30 is located closer to the gate pad PG than the drain pad PD of the first chip 20.

[0118] The second chip 30 includes a first pad PA, a second pad PB, and a third pad PC. The pads PA to PC are aligned with each other in the short-side direction (y-direction) of the second chip 30 and separated from each other in the long-side direction (x-direction) of the second chip 30. The pads PA to PC are arranged in the center of the second chip 30 in the short-side direction (y-direction).

[0119] In the present embodiment, the first pad PA is arranged at one of the two ends of the second chip 30 in the x-direction that is closer to the third resin side surface 110c. In other words, the first pad PA is arranged closer to the drain pad PD in the x-direction than the second pad PB and the third pad PC.

[0120] The third pad PC is arranged at one of the two ends of the second chip 30 in the x-direction, which is closer to the fourth resin side surface 110d. In other words, the third pad PC is arranged closer to the gate pad PG in the x-direction than the first pad PA and the second pad PB. Viewed in the y-direction, the third pad PC is arranged to overlap the gate pad PG.

[0121] The second pad PB is arranged in the center of the second chip 30 in the x-direction. The first pad PA and the second pad PB are located closer to the third resin side surface 110c than the sense-source pad PSS and the gate pad PG. In other words, the first pad PA and the second pad PB are offset from the sense-source pad PSS and the gate pad PG in the y-direction toward the third resin side surface 110c.

[0122] The semiconductor module 100 includes a connecting element 120 that electrically connects the first chip 20 and the second chip 30. The connecting element 120 is formed from a conductive material. The conductive material may be, for example, Cu, Al, a CuAl alloy, or the like. In the present embodiment, the connecting element 120 is formed from a metal plate formed from a conductive material. The connecting element 120 is arranged on the first chip 20 and the second chip 30. Thus, the connecting element 120 extends over the first chip 20 and the second chip 30. The connecting element 120 is encapsulated by the second encapsulation portion 112 (encapsulation resin 110). In the present embodiment, the connecting element 120 includes a first connecting element 121, a second connecting element 122, a third connecting element 123, and a fourth connecting element 124.

[0123] The first connecting element 121 electrically connects the drain pad PD of the first chip 20 and the first pad PA of the second chip 30. In the present embodiment, the first connecting element 121 is connected to the entire surface of the drain pad PD. The first connecting element 121 is bonded to the drain pad PD and the first pad PA by ultrasonic bonding or the like.

[0124] The second connecting element 122 electrically connects the main source pad PSM of the first chip 20 and the second pad PB of the second chip 30. In plan view, the second connecting element 122 is shaped to bypass the SPSS. The second connecting element 122 is bonded to the main source pad PSM and the second pad PB.

[0125] The third connecting element 123 electrically connects the gate pad PG of the first chip 20 and the third pad PC of the second chip 30. The third connecting element 123 is bonded to the gate pad PG and the third pad PC.

[0126] The fourth connecting element 124 is electrically connected to the sense-source pad PSS of the first chip 20. The fourth connecting element 124 is bonded to the sense-source pad PSS. The fourth connecting element 124 can be integrated with the second connecting element 122.

[0127] As in Fig. As shown in Figure 12, the semiconductor module 100 includes a drain terminal 131, a main source terminal 132, a sense source terminal 133, and a gate terminal 134. The terminals 131 to 134 are formed on the resin front surface 110s. In plan view, the terminals 131 to 134 are arranged separately from each other.

[0128] In the plan view, the drain terminal 131 is arranged to overlap the drain pad PD of the first chip 20. In other words, in the plan view, the drain terminal 131 is arranged to overlap the first connecting element 121 (see Fig. 11). The drain terminal 131 is electrically connected to the drain pad PD via the first connecting element 121. In one example, a first opening 113 is formed in the encapsulating resin 110 at a location where the drain terminal 131 is formed to expose the first connecting element 121. The drain terminal 131 fills the first opening 113 and has a portion extending from the first opening 113 to the resin front surface 110s.

[0129] In the top view, the main source terminal 132 is arranged to overlap the main source pad PSM of the first chip 20. In other words, in the top view, the main source terminal 132 is arranged to overlap the second connection element 122. The main source terminal 132 is electrically connected to the main source pad PSM via the second connection element 122. In one example, as shown in Fig. 12 and Fig. As shown in Figure 13, a second opening 114 is formed in the encapsulating resin 110 at a location where the main source terminal 132 is formed to expose the second connecting element 122. The main source terminal 132 fills the second opening 114 and includes a portion extending from the second opening 114 to the resin front surface 110s.

[0130] In the top view, the sense source terminal 133 is arranged to overlap the sense source pad PSS of the first chip 20. The sense source terminal 133 is electrically connected to the sense source pad PSS. In an example, as shown in Fig. 12 and Fig. As shown in Figure 13, a third opening 115 is formed in the encapsulating resin 110 at a location where the sense-source terminal 133 is formed to expose the fourth connecting element 124. The third opening 115 is separated from the second opening 114 in the y-direction. The sense-source terminal 133 fills the third opening 115 and has a portion extending from the third opening 115 to the resin front surface 110s.

[0131] In the top view, the gate terminal 134 is arranged to overlap the gate pad PG of the first chip 20. The gate terminal 134 is electrically connected to the gate pad PG via the third connecting element 123. In an example, as shown in Fig. 12 and Fig. As shown in Figure 13, a fourth opening 116 is formed in the encapsulating resin 110 at a position where the gate terminal 134 is formed to expose the third connecting element 123. The gate terminal 134 fills the fourth opening 116 and has a portion extending from the fourth opening 116 to the resin front surface 110s.

[0132] A front insulating layer 135 is formed on the resin front surface 110s. The front insulating layer 135 is shaped to cover the peripheral edges of each terminal 131 to 134. In other words, the terminals 131 to 134 each have a portion exposed from the front insulating layer 135. Detailed structure of the second chip

[0133] The structure of the second chip 30 will now be described with reference to the Fig. 14 and Fig. 15 described in detail.

[0134] Fig. 14 is a plan view of the second chip 30, mainly showing an example of the planar structure of the active clamp circuit 40. Fig. 15 is a cross-sectional view of the second chip 30 along the line F15-F15 in Fig. 14, which mainly shows the schematic cross-sectional structure of the clamping transistor 41, the clamping capacitor 42 and the pull-down resistor 43, as well as the internal connection configuration of the active clamping circuit 40. In Fig. 14, the clamping transistor 41, the clamping capacitor 42 and the pull-down resistor 43 are shown by solid lines for better illustration.

[0135] As in Fig. 14, the second chip 30 has a first chip side surface 30a, a second chip side surface 30b, a third chip side surface 30c, and a fourth chip side surface 30d. The first chip side surface 30a and the second chip side surface 30b define two end surfaces of the second chip 30 in the short side direction (y-direction). The third chip side surface 30c and the fourth chip side surface 30d define two end surfaces of the second chip 30 in the long side direction (x-direction). The first chip side surface 30a faces in the same direction as the first resin side surface 110a (see Fig. 12). The second chip side surface 30b faces in the same direction as the second resin side surface 110b (see Fig. 12). The third chip side surface 30c faces in the same direction as the third resin side surface 110c (see Fig. 12). The fourth chip side surface 30d faces in the same direction as the fourth resin side surface 110d (see Fig. 12).

[0136] The clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 of the active clamping circuit 40 are arranged in different positions in the plan view. In the present embodiment, the clamping capacitor 42 and the pull-down resistor 43 are located closer to the third chip side surface 30c than the clamping transistor 41. The pull-down resistor 43 is located closer to the first chip side surface 30a than the clamping capacitor 42.

[0137] The clamping transistor 41 has an active region 41T in which a transistor is formed. In plan view, the active region 41T is rectangular and has a long side direction and a short side direction. In the present embodiment, the active region 41T is rectangular, so that the long side direction is aligned with the x-direction and the short side direction is aligned with the y-direction. The long side direction of the active region 41T is aligned with the long side direction of the second chip 30. Furthermore, in the plan view of the first chip 20 (see Fig. 12) the long side direction is aligned with the y-direction and the short side direction with the x-direction. The long side direction of the active region 41T is thus orthogonal to the long side direction of the first chip 20.

[0138] As in Fig. As shown in FIG. 15, the clamp transistor 41 in the present embodiment is a lateral structure MOSFET. Therefore, the drain electrode 41D, the source electrode 41S, and the gate electrode 41G of the clamp transistor 41 are exposed on a surface of the interlayer insulating film 49B. In the present embodiment, a drain region 46B is formed in a surface of the base region 46 and separated from the source region 48. The drain electrode 41D is in contact with the drain region 46B. The source electrode 41S is in contact with the source region 48. The clamp transistor 41 of the present embodiment differs from the clamp transistor 41 of the first embodiment in that the gate electrode 41G is formed on the base region 46 instead of a gate trench on the insulating film 49A. The gate electrode 41G is covered by the interlayer insulation film 49B.

[0139] As in Fig. 14, in the present embodiment, the first electrode 42P and the second electrode 42Q of the clamp capacitor 42 are formed of a plurality of wires.

[0140] The first electrode 42P has a plurality of first wires (two in the present embodiment) extending in the y-direction and a second wire extending in the x-direction. The two first wires are spaced apart from each other in the x-direction. The second wire connects the ends of the two first wires that are closer to the second chip side surface 30b in the x-direction.

[0141] The second electrode 42Q has a plurality of third wires (two in the present embodiment) extending in the y-direction and a fourth wire extending in the x-direction. The two third wires are spaced apart from each other in the x-direction. The third wires are opposite the first wires of the first electrode 42P in the x-direction. The first wires and the third wires are arranged alternately in the x-direction. The fourth wire is located closer to the first chip side surface 30a in the y-direction than the second wire of the first electrode 42P. The fourth wire connects the ends of the two third wires that are closer to the first chip side surface 30a in the x-direction. As shown in Fig. 15, the clamp capacitor 42 is formed on the insulating film 49A in the same manner as in the first embodiment and covered by the intermediate insulating film 49B.

[0142] As in the Fig. 14 and Fig. 15, the pull-down resistor 43 is configured in the same manner as the pull-down resistor 43 of the first embodiment.

[0143] As in Fig. 15, in the present embodiment, the clamp transistor 41, the clamp capacitor 42 and the pull-down resistor 43 are formed at the same position in the thickness direction (z-direction) of the semiconductor substrate 44 (see Fig. 6).

[0144] As in Fig. As shown in Figure 15, the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 are electrically connected to each other by an interconnect layer 140. The interconnect layer 140 includes a clamping drain interconnect 141, a clamping source interconnect 142, and a clamping gate interconnect 143.

[0145] The clamp-drain interconnect 141 is electrically connected to a plurality of drain electrodes 41D of the clamp transistor 41. In Fig. 14, the clamp-drain interconnect 141 is arranged closer to the second chip side surface 30b than the active region 41T for the sake of simplicity. In plan view, the clamp-drain interconnect 141 has the shape of a strip elongated in the x-direction. The clamp-drain interconnect 141 shown is a section that includes a plurality of clamp-drain interconnects 141 (see Fig. 15) formed on the active region 41T.

[0146] The clamp-source interconnect 142 is electrically connected to a plurality of source electrodes 41S of the clamp transistor 41. In Fig. 14, the clamp-source interconnect 142 has the shape of a strip elongated in the x-direction and, for the sake of simplicity, is arranged closer to the first chip side surface 30a than the active region 41T. The clamp-source interconnect 142 shown is a section comprising a plurality of clamp-source interconnects 142 (see Fig. 15) formed on the active region 41T.

[0147] The clamp gate interconnection 143 is electrically connected to a plurality of gate electrodes 41G of the clamp transistor 41. For simplicity, the clamp gate interconnection 143 in Fig. 14 has the shape of a small rectangle located adjacent to the active region 41T in the x-direction. However, the actual clamp gate interconnect 143 extends over the entire active region 41T.

[0148] As in Fig. 14 and Fig. 15, the interconnect layer 140 further includes a first interconnect 151, a second interconnect 152, a third interconnect 153, a fourth interconnect 154, and a fifth interconnect 155.

[0149] The first interconnection 151 electrically connects the clamp capacitor 42 and the first pad PA (see Fig. 11). More specifically, the first interconnection 151 connects the second wire of the first electrode 42P in the clamp capacitor 42 and the first pad PA. Since the first pad PA is connected by the Fig. While the first interconnection element 121 shown in Figure 11 is electrically connected to the drain electrode 21D of the main transistor 21, the first interconnection 151 is electrically connected to the drain electrode 21D. Thus, the first electrode 42P of the clamping capacitor 42 is electrically connected to the drain electrode 21D.

[0150] The second interconnection 152 electrically connects the gate electrode 41G of the clamping transistor 41 to the clamping capacitor 42 and the pull-down resistor 43. More specifically, the second interconnection 152 connects the gate electrode 41G to the fourth wire of the second electrode 42Q of the clamping capacitor 42 and the first terminal 43P of the pull-down resistor 43. In other words, the second interconnection 152 is a portion of the clamping gate interconnection 143 that is connected to the gate electrode 41G. That is, the clamping gate interconnection 143 includes the second interconnection 152.

[0151] As in Fig. As shown in Figure 14, the second interconnection 152 is located closer to the third chip side surface 30c than the active region 41T in plan view. The second interconnection 152 is formed between the clamping capacitor 42 and the pull-down resistor 43 in the y-direction.

[0152] The third interconnection 153 electrically connects the pull-down resistor 43 and the source electrode 41S of the clamping transistor 41. More specifically, the third interconnection 153 electrically connects the second terminal 43Q of the pull-down resistor 43 and the source electrode 41S. In other words, the third interconnection 153 is a portion of the clamping-source interconnection 142 that is connected to the source electrode 41S. That is, the clamping-source interconnection 142 includes the third interconnection 153. In plan view, the third interconnection 153 is located closer to the first chip side surface 30a and the third chip side surface 30c than the active region 41T.

[0153] The fourth interconnection 154 electrically connects the source electrode 41S of the clamping transistor 41 and the second pad PB. More specifically, the fourth interconnection 154 connects the clamping source interconnection 142 and the second pad PB (see Fig. 11). In the present embodiment, the fourth interconnect 154 is integrated with the clamp-source interconnect 142. In other words, the fourth interconnect 154 is a part of the clamp-source interconnect 142. That is, the clamp-source interconnect 142 includes the fourth interconnect 154. In the plan view, the fourth interconnect 154 is located closer to the first chip side surface 30a than the active area 41T. In the plan view, the fourth interconnect 154 is arranged to overlap the second pad PB. The position of the fourth interconnect 154 can be arbitrarily changed. For example, in the plan view, the fourth interconnect 154 may be arranged to overlap the active area 41T.

[0154] The fifth interconnection 155 electrically connects the drain electrode 41D of the clamping transistor 41 and the third pad PC (see Fig. 11). Since the third pad PC is electrically connected to the gate electrode 21G of the main transistor 21 through the third connecting element 123, the drain electrode 41D is electrically connected to the gate electrode 21G. The fifth interconnection 155 is located closer to the fourth chip side surface 30d than the active area 41T. In a plan view, the fifth interconnection 155 is arranged to overlap the third pad PC. The arrangement position of the fifth interconnection 155 can be arbitrarily changed. For example, in a plan view, the fifth interconnection 155 may be arranged to overlap the active area 41T.

[0155] The wires of the clamp capacitor 42, the terminals 43P and 43Q of the pull-down resistor 43, the interconnections 141 to 143, and the interconnections 151 to 155 can be formed of any conductive material, including at least one of Cu, Al, an Al-Cu alloy, W, Ti, and TiN, for example. The present embodiment has the same advantages as the first embodiment. Third embodiment

[0156] A third embodiment of a semiconductor module 200 will now be described with reference to the Fig. 16 to 18. The semiconductor module 200 of the present embodiment differs from the semiconductor module 100 of the second embodiment mainly in the configuration of the first chip 20 and the connection configuration of the first chip 20 and the second chip 30. In the following description, the same reference numerals are used for the components that are identical to the corresponding components of the second embodiment. These components will not be described in detail here.

[0157] Fig. 16 is a plan view of the semiconductor module 200. Fig. 17 is a plan view of the internal structure of the semiconductor module 200, mainly showing an example of the cross-sectional structure of the first chip 20 and its surroundings. Fig. 18 is a cross-sectional view of the internal structure of the semiconductor module 200, mainly showing an example of the cross-sectional structure of the first chip 20 and the second chip 30 and their surroundings.

[0158] As in Fig. 16, the semiconductor module 200 comprises the first chip 20, the second chip 30, and an encapsulation resin 110 that encapsulates the chips 20 and 30. In Fig. 16, the chips 20 and 30 located in the encapsulation resin 110 are indicated by double dashed lines for clarity.

[0159] In the present embodiment, the first chip 20 and the second chip 30 are aligned with each other in the short side direction (x-direction) of the encapsulation resin 110 and separated from each other in the long side direction (y-direction) of the encapsulation resin 110.

[0160] The first chip 20 differs from the first chip 20 of the second embodiment in its pad structure. In the present embodiment, the first chip 20 includes drain pads PD, a gate pad PG, and source pads PS. In the present embodiment, the first chip 20 does not include the sense source pad PSS of the second embodiment. The drain pads PD and the source pads PS are arranged alternately in the longitudinal direction (y-direction in the present embodiment) of the first chip 20. The gate pad PG is arranged at one of the two ends of the first chip 20 in the longitudinal direction, which is closer to the second chip 30.

[0161] The drain terminal 131, the main source terminal 132 and the gate terminal 134 are formed in the resin front side 110s (see Fig. 17). The present embodiment differs from the second embodiment in that the sense-source terminal 133 is not formed on the resin front surface 110s.

[0162] As in Fig. 16 and Fig. 17, the semiconductor module 200 includes a connecting element 210 that connects the first chip 20 and the second chip 30. As shown in Fig. 17, the connecting element 210 is arranged closer to the resin front side 110s than the chips 20 and 30. The connecting element 210 is encapsulated by the second encapsulation portion 112 (encapsulation resin 110). As shown in Fig. As shown in FIG. 18, the connecting member 210 is partially exposed from the second encapsulation portion 112 (encapsulation resin 110) to include the drain terminal 131, the main source terminal 132, and the gate terminal 134. In the same manner as in the second embodiment, the drain terminal 131, the main source terminal 132, and the gate terminal 134 are covered by the front insulating layer 135. In the same manner as in the second embodiment, the drain terminal 131, the main source terminal 132, and the gate terminal 134 are partially exposed from the front insulating layer 135.

[0163] As in Fig. As shown in Figure 16, the connecting element 210 includes a first connecting element 211, a second connecting element 212, and a third connecting element 213. The connecting elements 211 to 213 each include a first part connecting the chips 20 and 30, a second part exposed from the resin front surface 110s, and a third part connecting the first part and the second part. Since the second part is closer to the resin front surface 110s than the first part, the third part is bent in the z-direction.

[0164] The first connection element 211 connects the drain pads PD of the first chip 20 to the first pad PA of the second chip 30. The first connection element 211 includes a portion that protrudes from the encapsulation resin 110 and forms the drain terminal 131. In plan view, the first connection element 211 has a comb-tooth portion connected to the drain pads PD and an extension extending from an end of the comb-tooth portion closer to the second chip 30 toward the second chip 30. The extension is connected to the first pad PA.

[0165] The second connecting element 212 connects the source pads PS of the first chip 20 and the second pad PB of the second chip 30. The second connecting element 212 has a portion that protrudes from the encapsulation resin 110 and forms the main source terminal 132. In plan view, the second connecting element 212 has a comb-tooth portion connected to the source pads PS and an extension extending from an end of the comb-tooth portion located closer to the second chip 30 in the y-direction toward the second chip 30. The extension is connected to the second pad PB.

[0166] The third connecting element 213 connects the gate pad PG of the first chip 20 and the third pad PC of the second chip 30. The third connecting element 213 has a portion that protrudes from the encapsulation resin 110 and is electrically connected to the gate terminal 134. In plan view, the third connecting element 213 is crank-shaped to bypass the first connecting element 211.

[0167] As in Fig. As shown in Fig. 18, a first die pad 220 on which the first chip 20 is mounted and a second die pad 230 on which the second chip 30 is mounted are arranged on the first encapsulation portion 111. The die pads 220 and 230 are formed of, for example, a metal material such as Cu, Al, or a CuAl alloy. In the present embodiment, a Cu frame is used for the die pads 220 and 230. The first encapsulation portion 111 is shaped to cover the side surfaces of the die pads 220 and 230. In other words, the die pads 220 and 230 are exposed from the first encapsulation portion 111 (resin back surface 110r).

[0168] The first encapsulation section 111 includes a first heat dissipation structure 221 configured to dissipate heat from the first die pad 220 to the outside of the first encapsulation section 111. The first heat dissipation structure 221 includes vias and a thermally conductive pad formed on the resin backsheet 110r. The vias connect the thermally conductive pad and the first die pad 220.

[0169] The first encapsulation section 111 includes a second heat dissipation structure 231 configured to dissipate heat from the second die pad 230 to the outside of the first encapsulation section 111. The structure of the second heat dissipation structure 231 is the same as the structure of the first heat dissipation structure 221 and will therefore not be described in detail.

[0170] The first chip 20 is bonded to the first die pad 220 by the first bonding material AD1. The second chip 30 is bonded to the second die pad 230 by the second bonding material AD2. Each of the bonding materials AD1 and AD2 is a conductive bonding material such as solder paste or Ag paste.

[0171] A backside insulation layer 136 is formed on the resin backsheet 110r. The backside insulation layer 136 is formed of a material containing at least one of SiO2 and SiN. The backside insulation layer 136 is shaped to cover the peripheral edge of each of the heat dissipation structures 221 and 231. In other words, the heat dissipation structures 221 and 231 each have a portion exposed from the backside insulation layer 136. Advantages

[0172] The present embodiment has the following advantages in addition to the advantages of the first embodiment.

[0173] (3-1) The first chip 20 is mounted on the first die pad 220 exposed from the resin back surface 110r of the encapsulation resin 110. The first die pad 220 may be formed of a metal material.

[0174] With this structure, heat is easily dissipated from the first chip 20 to the outside of the semiconductor module 200 via the first die pad 220, compared to a structure in which the semiconductor module 200 does not include the first die pad 220. This prevents an excessive temperature rise of the first chip 20. Fourth embodiment

[0175] A fourth embodiment of a semiconductor module 300 and a semiconductor unit 400 will now be described with reference to the Fig. 19 to 24. The present embodiment differs from the third embodiment mainly in the number of first chips 20 and second chips 30, as well as the addition of a third chip 310. In the following description, the same reference numerals are used for components identical to the corresponding components of the third embodiment. These components will not be described in detail here. Structure of the semiconductor unit

[0176] The structure of the semiconductor unit 400 will be described with reference to Fig. 19 to 23 described.

[0177] Fig. 19 is a plan view of the internal structure of the semiconductor module 300, mainly showing an example of the arrangement of the first chip 20, the second chip 30, and the third chip 310, which will be described later. Fig. 20 is a plan view of the internal structure of the semiconductor module 300, mainly showing an example of the structure of an interconnection layer. Fig. 21 is a plan view of the semiconductor module 300. Fig. 22 is a cross-sectional view of an example of the cross-sectional structure of the semiconductor module 200 taken along the line F22-F22 in Fig. 21, which mainly shows the first chip 20 and its surroundings. Fig. 23 is a cross-sectional view of an example of the cross-sectional structure of the semiconductor module 200 taken along the line F23-F23 in Fig. 22, which mainly shows the third chip 310 and the first chip 20.

[0178] As in Fig. As shown in Figure 19, the semiconductor device 400 includes the semiconductor module 300 and the third chip 310. The third chip 310 is arranged separately from the first chip 20 and the second chip 30. The third chip 310 is encapsulated by an encapsulation resin 350 of the semiconductor module 300.

[0179] The present embodiment differs from the second embodiment in the structure of the semiconductor module 300. More specifically, the semiconductor module 300 includes a plurality of (in the present embodiment, two) first chips 20, a plurality of (in the present embodiment, two) second chips 30, and the encapsulation resin 350 that encapsulates the first chips 20 and the second chips 30. In Fig. In Figure 19, the chips 20, 30, and 310 located in the encapsulation resin 350 are shown by solid lines for clarity. In the following description, the first two chips 20 are referred to separately as "first chip 20A" and "first chip 20B" for simplicity. The second two chips 30 are referred to separately as "second chip 30A" and "second chip 30B."

[0180] The semiconductor module 300 has the shape of a rectangular plate. The encapsulation resin 350 defines the outer surfaces of the semiconductor module 300. This means that the encapsulation resin 350 has the shape of a rectangular plate. The encapsulation resin 350 has a resin front side 350s and a resin back side 350r (see Fig. 22) facing in opposite directions, as well as first to fourth resin side surfaces 350a to 350d, which are four resin side surfaces that intersect the resin front surface 350s and the resin back surface 350r. In the present embodiment, the first to fourth resin side surfaces 350a to 350d are orthogonal to the resin front surface 350s and the resin back surface 350r. In the present embodiment, the thickness direction of the encapsulating resin 350 refers to the z-direction. In the description, "top view" includes the meaning of "viewing in the thickness direction of the encapsulating resin 350."

[0181] In plan view, the encapsulating resin 350 is rectangular and has a long side direction and a short side direction. In the present embodiment, the long side direction of the encapsulating resin 350 is aligned with the y-direction. The short side direction of the encapsulating resin 350 is aligned with the x-direction. In the present embodiment, the first resin side surface 350a and the second resin side surface 350b form opposite end surfaces in the y-direction. The third resin side surface 350c and the fourth resin side surface 350d form opposite end surfaces in the x-direction. The encapsulating resin 350 is made of an insulating resin material. Such a resin material is, for example, an epoxy resin, an acrylic resin, or a phenolic resin.

[0182] The first chips 20A and 20B are aligned with each other in the long side direction (y-direction) of the encapsulating resin 350 and separated from each other in the short side direction (x-direction) of the encapsulating resin 110. In plan view, the first chips 20A and 20B are off-center in the y-direction relative to the encapsulating resin 350. In the present embodiment, in plan view, the first chips 20A and 20B are closer to the second resin side surface 350b of the encapsulating resin 350 than to the first resin side surface 350a. The first chips 20A and 20B are arranged such that the long side direction of the first chips 20A and 20B is aligned with the y-direction and the short side direction of the first chips 20A and 20B is aligned with the x-direction.In other words, the long side direction of each of the first chips 20A and 20B is aligned with the long side direction of the encapsulating resin 350, and the short side direction of each of the first chips 20A and 20B is aligned with the short side direction of the encapsulating resin 350.

[0183] In plan view, the third chip 310 is separated from the first chips 20A and 20B in a direction orthogonal to a direction in which the first chips 20A and 20B are arranged. Specifically, the third chip 310 is located closer to the first resin side surface 350a in the y-direction than the first chips 20A and 20B. The third chip 310 has the shape of a rectangular plate. In plan view, the third chip 310 is rectangular and has a long side direction and a short side direction. In the present embodiment, the third chip 310 is arranged so that the long side direction of the third chip 310 is aligned with the x-direction and the short side direction of the third chip 310 is aligned with the y-direction.Thus, in plan view, the long side direction of the third chip 310 is orthogonal to the long side direction of the encapsulating resin 350 and the long side direction of the first chips 20A and 20B, and the short side direction of the third chip 310 is orthogonal to the short side direction of the encapsulating resin 350 and the short side direction of the first chips 20A and 20B. Viewed in the y-direction, the third chip 310 is arranged to partially overlap each of the first chips 20A and 20B. In the present embodiment, the third chip 310 is arranged in the x-direction center of the encapsulating resin 350.

[0184] The third chip 310 has a chip front side 310s and a chip back side 310r, which are oppositely aligned in the z-direction (see Fig. 23). The chip front side 310s faces in the same direction as the resin front side 350s. The chip back side 310r faces in the same direction as the resin back side 350r.

[0185] The third chip 310 includes a semiconductor substrate, a driver circuit 311 formed on the semiconductor substrate and configured to separately drive the first chips 20A and 20B, and electrode pads 312 electrically connected to the driver circuit 311. The electrode pads 312 are visible from the chip front side 310s.

[0186] The second chips 30A and 30B are located closer to the first resin side surface 350a than the first chips 20A and 20B. The second chip 30A is arranged between the third chip 310 and the first chip 20A in the y-direction. The second chip 30B is arranged between the third chip 310 and the first chip 20B in the y-direction. The second chip 30A is located next to the first chip 20A in the y-direction. The second chip 30B is located next to the first chip 20B in the y-direction.

[0187] As in Fig. As shown in Figure 20, the semiconductor module 300 includes an interconnect layer 320. The interconnect layer 320 includes at least two types of interconnect layers. A first type of interconnect layer includes a via extending in the z-direction and an interconnect extending in a direction perpendicular to the z-direction. Another type of interconnect layer includes only a via extending in the z-direction. The interconnect layer 320 is configured to connect the first chips 20A and 20B, the second chips 30A and 30B, and the third chip 310.

[0188] The interconnect layer 320 includes a first interconnect 321, a second interconnect 322, a third interconnect 323, a fourth interconnect 324, and a fifth interconnect 325. The interconnect layer 320 also includes driver interconnects 326 connected to the third chip 310. The interconnects 321 to 325 and the driver interconnects 326 each extend in a direction orthogonal to the z-direction without bending in the z-direction. The interconnects 321 to 325 and the driver interconnects 326 may each be formed from a metal plating (metal coating).

[0189] The first interconnect 321 connects the source pads PS of the first chip 20A and the drain pads PD of the first chip 20B to the second pad PB of the second chip 30A and the first pad PA of the second chip 30B. In plan view, the first interconnect 321 has a combtooth portion, a first extension, and a second extension. The combtooth portion is electrically connected to the source pads PS of the first chip 20A and the drain pads PD of the first chip 20B, e.g., by vias. The first extension extends from an end of the combtooth portion closer to the second chip 30A toward the second chip 30A. The first extension is electrically connected to the second pad PB of the second chip 30A, e.g., by a via. The second extension extends from an end of the comb tooth portion closer to the second chip 30B toward the second chip 30B.The second extension is electrically connected to the first pad PA of the second chip 30B, e.g., by a via.

[0190] The second interconnection 322 connects the drain pads PD of the first chip 20A and the first pad PA of the second chip 30A. The second interconnection 322 includes a portion closer to the third resin side surface 350c than the first interconnection 321. In plan view, the second interconnection 322 has a comb-tooth portion electrically connected to the drain pads PD and an extension extending from an end of the comb-tooth portion closer to the second chip 30A toward the second chip 30A. The comb-tooth portion is electrically connected to each of the drain pads PD, for example, by vias. The extension is electrically connected to the first pad PA, for example, by a via.

[0191] The third interconnect 323 connects the source pads PS of the first chip 20B and the second pad PB of the second chip 30B. The third interconnect 323 includes a portion that is closer to the fourth resin side surface 350d than the first interconnect 321. The third interconnect 323 has a comb-tooth portion and an extension. The comb-tooth portion is electrically connected to the source pads PS, e.g., through vias. The extension is electrically connected to the second pad PB, e.g., through a via.

[0192] The fourth interconnect 324 connects the gate pad PG of the first chip 20A, the third pad PC of the second chip 30A, and one of the electrode pads 312 of the third chip 310. The fourth interconnect 324 is electrically connected to the gate pad PG and the electrode pad 312, e.g., by vias.

[0193] The fifth interconnect 325 connects the gate pad PG of the first chip 20B, the third pad PC of the second chip 30B, and one of the electrode pads 312 of the third chip 310. The fifth interconnect 325 is electrically connected to the gate pad PG and the electrode pad 312, e.g., by vias. The fourth interconnect 324 and the fifth interconnect 325 each correspond to a "control connection element."

[0194] The driver terminals 326 are each connected to the electrode pads 312 of the third chip 310. In plan view, each of the driver connections 326 extends beyond the third chip 310 toward one of the first resin side surface 350a, the third resin side surface 350c, and the fourth resin side surface 350d.

[0195] As in Fig. As shown in Figure 21, the semiconductor module 200 has a drain terminal 331, a source terminal 332, an output terminal 333, and driver terminals 334. The terminals 331 to 334 are formed on the resin front surface 350s. In Fig. 21, the portions of the drain terminal 331, the source terminal 332, and the output terminal 333 that are not exposed by the encapsulating resin 350 are indicated by dashed lines.

[0196] The drain terminal 331, the source terminal 332, and the output terminal 333 are aligned with each other in the y-direction and separated from each other in the x-direction. The drain terminal 331, the source terminal 332, and the output terminal 333 are located closer to the second resin side surface 350b than to the first resin side surface 350a in the y-direction. In the plan view, the drain terminal 331 is arranged to contact the second interconnection 322 (see Fig. 20), the source terminal 332 is arranged to connect the third interconnection 323 (see Fig. 20) and the output terminal 333 is arranged to connect the first interconnection 321 (see Fig. 20) overlaps.

[0197] The driver terminals 334 are located closer to the first resin side surface 350a than to the second resin side surface 350b in the y-direction. In plan view, the driver terminals 334 are arranged in a line along each of the first resin side surface 350a, the third resin side surface 350c, and the fourth resin side surface 350d.

[0198] The drain terminal 331 is electrically connected to the drain electrode 21D (see Fig. 20) of the main transistor 21 in the first chip 20A. In plan view, the drain terminal 331 has the same shape as the combtooth portion of the second interconnection 322. The drain terminal 331 is electrically connected to the second interconnection 322.

[0199] The source terminal 332 is electrically connected to the source electrode 21S (see Fig. 20) of the main transistor 21 in the first chip 20B. In plan view, the source terminal 332 has the same shape as the combtooth portion of the third interconnection 323. The source terminal 332 is electrically connected to the third interconnection 323.

[0200] The output terminal 333 is electrically connected to the source electrode 21S (see Fig. 20) of the main transistor 21 in the first chip 20A and the drain electrode 21D (see Fig. 20) of the main transistor 21 in the first chip 20B. The output terminal 333 is electrically connected to the first interconnection 321.

[0201] The drain terminal 331, the source terminal 332 and the output terminal 333 are on the resin front side 350s (see Fig. 22) and covered by a front insulating layer 370, such that the drain terminal 331, the source terminal 332, and the output terminal 333 are partially exposed from the front insulating layer 370. The portion of the drain terminal 331, the source terminal 332, and the output terminal 333 exposed from the front insulating layer 370 is rectangular in plan view, such that the long side direction is aligned with the y-direction and the short side direction is aligned with the x-direction. The front insulating layer 370 is formed of a material such as SiO2 or SiN.

[0202] The driver terminals 334 are electrically connected to the driver circuit 311. The driver terminals 334 are electrically connected to the respective driver connections 326. More specifically, each driver terminal 334 is connected to a second passage of the driver connection line 326.

[0203] As in Fig. 22 and Fig. As shown in Figure 23, the encapsulation resin 350 includes a first encapsulation portion 351, a second encapsulation portion 352, and a third encapsulation portion 353. The encapsulation portions 351 to 353 are made of, for example, the same material.

[0204] The first encapsulation section 351 is a support member that supports the chips 20A, 20B, 30A, 30B, and 310. The chips 20A, 20B, 30A, 30B, and 310 are bonded to the first encapsulation section 351, e.g., using the bonding materials AD1 to AD3. The first encapsulation section 351 has the resin backing 350r.

[0205] In the first encapsulation section 351, a first die pad 361 on which the first chip 20A is mounted, a second die pad 362 on which the first chip 20B is mounted, a third die pad 363 on which the second chip 30A is mounted, and a fourth die pad 364 on which the second chip 30B is mounted are formed. Although not shown, a fifth pad corresponding to the third chip 310 may also be formed.

[0206] The first encapsulation section 351 includes a first heat dissipation structure 365 configured to dissipate heat from the first die pad 361 to the outside of the encapsulation resin 350, and a second heat dissipation structure 366 configured to dissipate heat from the second die pad 362 to the outside of the encapsulation resin 350. The first encapsulation section 351 also includes a third heat dissipation structure (not shown) configured to dissipate heat from the third die pad 363 to the outside of the encapsulation resin 350, and a fourth heat dissipation structure 367 configured to dissipate heat from the fourth die pad 364 to the outside of the encapsulation resin 350.

[0207] The first heat dissipation structure 365 includes vias formed in portions overlapping the first die pad 361 in plan view, and a heat conduction pad formed on the resin backsheet 350r. The vias connect the first die pad 361 and the heat conduction pad. The structure of the second heat dissipation structure 366 and the fourth heat dissipation structure 367 is the same as that of the first heat dissipation structure 365 and will therefore not be described in detail. The die pads 361 and 362 and the heat dissipation structures 365, 366, and 367 are formed, for example, from the same material as the interconnection layer 320.

[0208] The resin backing 350r is covered with a backing insulation layer 380, which covers the peripheral edge of each thermal pad of the heat dissipation structures 365, 366, and 367. In other words, the thermal pad is exposed from the backing insulation layer 380.

[0209] The third chip 310 is mounted on the first encapsulation section 351. Specifically, the third chip 310 is bonded to the first encapsulation section 351 by the third bonding material AD3. The third bonding material AD3 can be a conductive or insulating bonding material. Thus, the third chip 310 is mounted directly on the first encapsulation section 351 without being mounted on a die pad.

[0210] The second encapsulation section 352 encapsulates the chips 20A, 20B, 30A, 30B and 310 together with the first encapsulation section 351.

[0211] The third encapsulation section 353 is arranged on the second encapsulation section 352. The third encapsulation section 353 has the resin front surface 350s. The drain terminal 331, the source terminal 332, the output terminal 333, and the driver terminals 334 are formed on the third encapsulation section 353.

[0212] The interconnection layer 320 is formed in the second encapsulation portion 352 and the third encapsulation portion 353.

[0213] As in Fig. 22, in the interconnect layer 320, the second interconnect 322 and the third interconnect 323 (see Fig. 20) is formed as follows. The interconnect layer 320 includes first vias that extend in the z-direction through portions of the second encapsulation section 352 covering the first chips 20A and 20B. The interconnect layer 320 has interconnects formed on the second encapsulation section 352. The interconnects are covered by the third encapsulation section 353. The interconnect section 320 includes second vias that extend in the z-direction through the third encapsulation section 353.In the interconnection layer 320, the second interconnection 322 and the third interconnection 323 include the vias extending in the z-direction through portions of the second encapsulation section 352 covering the first chips 20A and 20B, and the vias extending in the z-direction through the third encapsulation section 353.

[0214] As in Fig. 23, in the interconnect layer 320, the fourth interconnect 324 and the fifth interconnect 325 (see Fig. 20) is formed as follows. The interconnect layer 320 includes first vias extending in the z-direction through portions of the second encapsulation section 352 covering the first chips 20A and 20B. The interconnect layer 320 has interconnects formed on the second encapsulation section 352. The interconnects are covered by the third encapsulation section 353. The interconnect layer 320 has second vias extending in the z-direction through portions of the second encapsulation section 352 covering the third chip 310. Circuit arrangement of the semiconductor unit

[0215] The schematic circuit arrangement of the semiconductor unit 400 will now be described with reference to Fig. 24. For clarity, the circuit arrangement of the driver circuit 311 is not shown in detail. In the following description, the main transistor 21 of the first chip 20A is referred to as "main transistor 21A," and the main transistor 21 of the first chip 20B is referred to as "main transistor 21B." The active clamp circuit 40 of the first chip 20A is referred to as "active clamp circuit 40A," and the active clamp circuit 40 of the first chip 20B is referred to as "active clamp circuit 40B."

[0216] As in Fig. 24, the main transistor 21A is electrically connected to the active clamp circuit 40A in the same manner as in the first embodiment, and the main transistor 21B is electrically connected to the active clamp circuit 40B.

[0217] The drain electrode 21D of the main transistor 21A is connected to the drain terminal 331. The source electrode 21S of the main transistor 21B is connected to the source terminal 332.

[0218] The source electrode 21S of the main transistor 21A is connected to the drain electrode 21D of the main transistor 21B. The output terminal 333 is connected to a node N located between the source electrode 21S of the main transistor 21A and the drain electrode 21D of the main transistor 21B.

[0219] The gate electrode 21G of each of the main transistors 21A and 21B is connected to the driver circuit 311. The driver circuit 311 is connected to the driver terminals 334. The source electrode 21S of each of the main transistors 21A and 21B can be connected to the driver circuit 311.

[0220] In the semiconductor unit 400, when the driver terminals 334 receive a control signal for driving the main transistors 21A and 21B from an external device, the driver circuit 311 generates a drive signal for driving the main transistors 21A and 21B in accordance with the control signal supplied to the driver circuit 311 via the driver terminals 334. The driver circuit 311 transmits the drive signal to the gate electrodes 21G of the main transistors 21A and 21B. The main transistors 21A and 21B are turned on and off in a complementary manner based on the control signal supplied to the gate electrodes 21G. Advantages

[0221] The fourth embodiment has the following advantages in addition to the advantages of the first embodiment.

[0222] (4-1) The semiconductor unit 400 includes the first chips 20A and 20B, the second chips 30A and 30B, the third chip 310, and the encapsulation resin 350 that encapsulates the first chips 20A and 20B, the second chips 30A and 30B, and the third chip 310.

[0223] In this structure, the main transistors 21 of the first chips 20A and 20B are electrically connected to the driver circuit 311 of the third chip 310 within the semiconductor unit 400. This shortens the conduction path from the main transistors 21 of the first chips 20A and 20B to the driver circuit 311 compared to a structure in which the main transistors 21 of the first chips 20A and 20B are electrically connected to the driver circuit 311 on a circuit substrate arranged outside the semiconductor unit 400. This reduces parasitic impedances and parasitic inductances caused by the length of the conduction paths.

[0224] (4-2) In the plan view, the third chip 310 is separated from the first chips 20A and 20B in a direction orthogonal to the arrangement direction of the first chips 20A and 20B.

[0225] This structure limits the variations between the first chip 20A and the first chip 20B in the length of the conduction path extending from the gate electrode 21G of the main transistor 21 to the driver circuit 311, compared with a structure in which the third chip 310 is arranged adjacent to one of the first chips 20A and 20B in the arrangement direction of the first chips 20A and 20B. Modified examples

[0226] The above-described embodiments may be modified as follows. The above-described embodiments and the modified examples described below may be combined as long as the combined modifications are technically consistent with each other. Modified examples (variations) for the first chip

[0227] In the first embodiment, the drain pad PD1, the source pad PS1, and the gate pad PG1 of the main transistor 21 can be replaced with the drain pads PD, the source pads PS, and the gate pad PG of the main transistor 21 in the third and fourth embodiments. In the second embodiment, the pad terminal configuration of the main transistor 21 can be changed to the pad terminal configuration of the main transistor 21 in the third and fourth embodiments.

[0228] In each embodiment, a portion of the active clamp circuit 40 may be formed on the first chip 20. In one example, the clamp transistor 41 of the active clamp circuit 40 is formed on the first chip 20. In one example, the clamp capacitor 42 of the active clamp circuit 40 is formed on the first chip 20. In one example, the pull-down resistor 43 of the active clamp circuit 40 is formed on the first chip 20. In one example, the clamp transistor 41 and the clamp capacitor 42 are formed on the first chip 20. In one example, the clamp transistor 41 and the pull-down resistor 43 are formed on the first chip 20. In one example, the clamp capacitor 42 and the pull-down resistor 43 are formed on the first chip 20.

[0229] In any embodiment, the material forming the main drift layer (electron transit layer 24) of the first chip 20 can be changed in any way, as long as the material forming the main drift layer is different from the material forming the sub-drift layer (drift layer 45) of the second chip 30. In one example, the main drift layer can be formed as a drift layer made of a material containing Si. In this case, the sub-drift layer is formed of a different material than the Si-containing material (e.g., a material containing GaN). Modified examples for the second chip

[0230] In each embodiment, the structure of the pull-down resistor 43 can be changed as desired.

[0231] For example, when the main drift layer of the second chip 30 includes the electron transit layer 24 formed of GaN, the pull-down resistor 43 may be formed as in a first modified example according to Fig. 25 or a second modified example according to Fig. 26 be changed.

[0232] As in Fig. As shown in FIG. 25, the pull-down resistor 43 of the first modified example includes a serpentine-shaped conductive path 43A. In the present embodiment, the conductive path 43A is formed by the 2DEG 26. In other words, the 2DEG 26 of the pull-down resistor 43 is formed in a serpentine shape in plan view. Thus, the connection path 43A includes a serpentine-shaped portion. Thus, the pull-down resistor 43 includes a resistance component of the serpentine-shaped portion. The resistance component of the serpentine-shaped portion is adjusted depending on the length and width of the serpentine-shaped portion. The length and width of the serpentine-shaped portion are each adjusted depending on, for example, a desired resistance of the pull-down resistor 43.

[0233] The first terminal 43P and the second terminal 43Q of the pull-down resistor 43 define two ends of the serpentine section. The first terminal 43P is electrically connected to one end of the connection path 43A located toward the clamping capacitor 42. The second terminal 43Q is electrically connected to one end of the connection path 43A located toward the clamping transistor 41. The first terminal 43P and the second terminal 43Q are electrically connected to each other via the connection path 43A.

[0234] As in Fig. 25, the first terminal 43P and the second terminal 43Q are formed on the electron supply layer 25. More specifically, the first terminal 43P and the second terminal 43Q are formed on the electron supply layer 25 and are in ohmic contact with the electron supply layer 25.

[0235] As in Fig. As shown in FIG. 26, the pull-down resistor 43 in the second modified example is configured by a normally-on transistor and has an ON resistance of the normally-on transistor. Specifically, the pull-down resistor 43 includes the electron transit layer 24, the electron supply layer 25, and the passivation layer 28 in the same manner as the main transistor 21 in the embodiments. However, the pull-down resistor 43 does not include the gate layer 27, which is different from the main transistor 21 in the embodiments. The pull-down resistor 43 has the first terminal 43P corresponding to a drain electrode, the second terminal 43Q corresponding to a source electrode, a third terminal 43S corresponding to a gate electrode, and a connection path (not shown) electrically connecting the first terminal 43P and the second terminal 43Q.The connection path is formed by the 2DEG 26 and has a serpentine shape in plan view. The third terminal 43S is formed on the passivation layer 28. The third terminal 43S is arranged opposite the second terminal 43Q.

[0236] The pull-down resistor 43 includes a wire 43C connecting the first terminal 43P and the third terminal 43S. The wire 43C may be formed, for example, from any conductive material, including at least one of Cu, Al, an Al-Cu alloy, W, Ti, and TiN.

[0237] In the first embodiment, the clamping capacitor 42 may overlap the pad PG2 of the second chip 30 in plan view instead of the pull-down resistor 43. In this case, the clamping capacitor 42 is arranged closer to the drift layer 45 than the pad PG2.

[0238] In the first embodiment, the clamping capacitor 42 and the pull-down resistor 43 may overlap the pad PG2 of the second chip 30 in plan view. In this case, the clamping capacitor 42 and the pull-down resistor 43 are arranged closer to the drift layer 45 than the pad PG2.

[0239] In the first embodiment, the clamp capacitor 42 and the pull-down resistor 43 may be arranged at a position different from the pad PG2 of the second chip 30 in plan view. Circuit arrangement of the active clamp circuit in modified examples

[0240] In each embodiment, the circuit configuration of the active clamp circuit 40 can be arbitrarily modified. In one example, the active clamp circuit 40 can be modified as in the first to third modified examples described below.

[0241] Fig. 27 shows the circuit arrangement of the active clamp circuit 40 in the first modified example.

[0242] As in Fig. As shown in Fig. 27, the active clamp circuit 40 in the first modified example further includes a protection diode 500 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41. The protection diode 500 is, for example, a Zener diode. The protection diode 500 has an anode electrode 501 electrically connected to the source electrode 41S and a cathode electrode 502 electrically connected to the gate electrode 41G. The protection diode 500 is configured to prevent a voltage higher than the rated gate-source voltage from being applied to the gate electrode 41G of the clamp transistor 41. This makes it less likely that the gate-source voltage of the clamp transistor 41 will increase excessively.

[0243] Fig. 28 shows the schematic cross-sectional structure of the protection diode 500 in the first modified example.

[0244] As in Fig. 28, the protection diode 500 is arranged, for example, such that it overlaps the pad PG2 in the second chip 30 in plan view.

[0245] The protection diode 500 includes the anode electrode 501, the cathode electrode 502, the drift layer 45, which electrically connects the anode electrode 501 and the cathode electrode 502, and a well region 503, which differs in the type of conductivity from the drift layer 45. In the example shown, the well region 503 is a p-type semiconductor region. The anode electrode 501 is electrically connected to the pad PG2, for example, via a via 504. The anode electrode 501 and the cathode electrode 502 can be made of any conductive material, such as Cu, Al, an Al-Cu alloy, W, Ti, or TiN.

[0246] The anode electrode 501 and the cathode electrode 502 are separated from each other by the insulating film 49A. More specifically, two separate openings 49H and 49J are formed in the insulating film 49A to expose the drift layer 45. The anode electrode 501 fills the opening 49H and extends to an edge extending around the opening 49H. The cathode electrode 502 fills the opening 49J and extends to an edge extending around the opening 49J. The portion of the anode electrode 501 protruding from the opening 49H and the portion of the cathode electrode 502 protruding from the opening 49J are covered by the interlayer insulating film 49B.

[0247] A shunt resistor can also be used instead of the protective diode 500. The shunt resistor is designed to prevent the application of a voltage higher than the rated gate-source voltage to the gate electrode 41G (see Fig. 27) of the clamping transistor 41. With this configuration, the gate-source voltage of the clamping transistor 41 is less likely to rise excessively.

[0248] Fig. 29 shows the circuit arrangement of the active clamp circuit 40 in the second modified example.

[0249] As in Fig. 29, the active clamp circuit 40 in the second modified example further includes a capacitor 510 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41. The capacitor 510 has a first electrode 511 and a second electrode 512. The first electrode 511 is electrically connected to the gate electrode 41G of the clamp transistor 41 and the first terminal 43P of the pull-down resistor 43. The second electrode 512 is electrically connected to the source electrode 41S of the clamp transistor 41 and the second terminal 43Q of the pull-down resistor 43.

[0250] Capacitor 510 is configured to prevent a voltage higher than the rated gate-source voltage from being applied to gate electrode 41G of clamping transistor 41. This makes it less likely that the gate-source voltage of clamping transistor 41 will increase excessively.

[0251] The capacitor 510 can be formed in the same way as the clamping capacitor 42. For example, in the first embodiment, the capacitor 510 can be arranged to overlap the gate pad PG1 of the second chip 30. In the second to fourth embodiments, the capacitor 510 can be arranged at a different position in plan view than the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43.

[0252] Fig. 30 shows the circuit arrangement of the active clamp circuit 40 in the third modified example.

[0253] As in Fig. 30, the active clamp circuit 40 in the third modified example further includes a protection transistor 520 that prevents erroneous activation of the clamp transistor 41. The protection transistor 520 has a drain electrode 521, a source electrode 522, and a gate electrode 523. The protection transistor 520 is connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41. More specifically, the drain electrode 521 of the protection transistor 520 is connected to the gate electrode 41G of the clamp transistor 41, and the source electrode 522 of the protection transistor 520 is connected to the source electrode 41S of the clamp transistor 41. The gate electrode 523 of the protection transistor 520 is connected to the gate terminal 83. The protection transistor 520, like the main transistor 21, is a normally-on transistor.

[0254] When the main transistor 21 is in an activated state, the protection transistor 520 is in an activated state. The protection transistor 520 connects the gate electrode 41G of the clamping transistor 41 and the source electrode 41S of the clamping transistor 41. Thus, when the main transistor 21 is activated, the protection transistor 520 deactivates the clamping transistor 41. This prevents a situation in which the main transistor 21 is inadvertently turned off, even if noise or the like is applied to an interconnection connected to the gate electrode 41G of the clamping transistor 41.

[0255] When the main transistor 21 is in a deactivated state, the protection transistor 520 is in a deactivated state. This allows the clamping transistor 41 to be activated depending on the drain-source voltage of the main transistor 21. As described in the first embodiment, the clamping transistor 41 thus limits an increase in the gate-source voltage of the main transistor 21.

[0256] In at least one of the first and second examples, the active clamp circuit 40 may include the protection transistor 520 of the third modified example. With this configuration, the clamp transistor 41 is protected when the main transistor 21 is in a deactivated state, while erroneous activation of the clamp transistor 41 is prevented when the main transistor 21 is in an activated state.

[0257] In the fourth embodiment, at least a portion of the active clamp circuit 40 may be formed on the third chip 310. Specifically, a portion of the active clamp circuit 40 may be formed on the second chip 30, and elements of the active clamp circuit 40 not formed on the second chip 30 may be formed on the third chip 310.

[0258] The active clamp circuits 40A and 40B may be formed entirely on the third chip 310. In this case, as in Fig.31, the active clamp circuit 40 may be formed on the output side of the driver circuit 311 of the third chip 310. In one example, the driver circuit 311 includes a push-pull circuit (not shown) configured to transmit a gate signal to the gate of the main transistor 21. The active clamp circuit 40 is arranged between the push-pull circuit and an output terminal (electrode pad 312) of the driver circuit 311. If the active clamp circuit 40 is entirely formed on the third chip 310, the second chip 30 may be omitted from the semiconductor device 400. Modified examples of a semiconductor module

[0259] In the first to third embodiments, the number of first chips 20 and second chips 30 can be arbitrarily changed. The semiconductor modules 10, 100, and 200 may include a plurality of first chips 20. The semiconductor modules 10, 100, and 200 may include a plurality of second chips 30. The semiconductor modules 10, 100, and 200 may include a plurality of first chips 20 and a plurality of second chips 30. For example, when the semiconductor modules 10, 100, and 200 include a plurality of first chips 20 and a plurality of second chips 30, the first chips 20 and the second chips 30 are equal in number.

[0260] In the second and third embodiments, the position of the second chip 30 relative to the first chip 20 can be arbitrarily changed. In one example, the second chip 30 may be separated from the first chip 20 in the x-direction. In this case, the second chip 30 is arranged to overlap the first chip 20, viewed in the x-direction.

[0261] In each embodiment, the first chip 20 and the second chip 30 are electrically connected to each other by a metal plate or an interconnection layer consisting of a plating layer. However, the electrical connection structure between the first chip 20 and the second chip 30 is not limited thereto. In one example, the first chip 20 and the second chip 30 may be electrically connected to each other by wires. Modified examples of a semiconductor device

[0262] In the fourth embodiment, the number of third chips 310 can be arbitrarily changed. In one example, the number of third chips 310 can be changed depending on the number of first chips 20. For example, since the number of first chips 20A and 20B is two, the number of third chips 310 in the fourth embodiment can be two.

[0263] In the fourth embodiment, the arrangement of the second chips 30A and 30B can be arbitrarily changed. In one example, the second chips 30A and 30B can be arranged between the first chip 20A and the first chip 20B in the x-direction. In this case, the second chips 30A and 30B can be aligned with each other in the x-direction and separated from each other in the y-direction. In one example, the second chips 30A and 30B can be arranged separately on opposite sides of the third chip 310 in the x-direction.

[0264] In the fourth embodiment, the third chip 310, the first chips 20A and 20B, and the second chips 30A and 30B are electrically connected to each other through the interconnection layer formed of a plating layer. However, the electrical connection structure of the third chip 310, the first chips 20A and 20B, and the second chips 30A and 30B is not limited to this. In one example, the third chip 310, the first chips 20A and 20B, and the second chips 30A and 30B may be electrically connected to each other by wires.

[0265] In the fourth embodiment, the number of second chips 30 can be arbitrarily changed. In one example, a single second chip 30 may be used. In this case, the second chip 30 includes an active clamp circuit 40 electrically connected to the main transistor 21 of the first chip 20A and an active clamp circuit 40 electrically connected to the main transistor 21 of the first chip 20B. That is, the second chip 30 may include multiple active clamp circuits 40.

[0266] The semiconductor unit may include the semiconductor modules 10, 100, and 200 of the first to third embodiments and the third chip 310. The third chip 310 is encapsulated by the encapsulation resins 60 and 110 of the semiconductor modules 10, 100, and 200.

[0267] In the present disclosure, the term "on" includes the meaning "upon" as well as the meaning "above," unless the context clearly indicates otherwise. The phrase "first element formed on second element" is therefore intended to mean that, in one embodiment, the first element may be formed on the second element in contact with the second element, and that, in another embodiment, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first and second elements.

[0268] The z-direction referred to in the present disclosure does not necessarily have to be the vertical direction and does not necessarily have to be completely aligned with the vertical direction. In the structures according to the present disclosure, "up" and "down" in the z-direction referred to in the present description are not limited to "up" and "down" in the vertical direction. In one example, the x-direction may be aligned with the vertical direction. In another example, the y-direction may be aligned with the vertical direction.

[0269] In this description, “at least one of A and B” should be understood to mean “only A, only B, or both A and B”. Variants

[0270] The technical aspects resulting from the embodiment and the modified examples are described below. For ease of understanding, without any intention of limitation, the reference numerals of the elements in the embodiments are indicated with parentheses for the corresponding elements. The reference numerals are used as examples to facilitate understanding, and the components in each variant are not limited to those indicated by the reference numerals. [Variant 1]

[0271] Semiconductor module (10), comprising: a first chip (20) having a main transistor (21) having a main drift layer (24); a second chip (30) comprising at least a portion of an active clamp circuit (40) with a sub-transistor (41) configured to be activated based on an increase in a drain-source voltage of the main transistor (21); a connecting element (50) electrically connecting the main transistor (21) and the active clamping circuit (40); an encapsulating resin (60) encapsulating the first chip (20), the second chip (30) and the connecting element (50), wherein the sub-transistor (41) has a sub-drift layer (45) formed from a material different from a material from which the main drift layer (24) is formed. [Variant 2]

[0272] Semiconductor module according to variant 1, where the main transistor (21) is a GaN transistor in which the main drift layer (24) is formed from GaN, and wherein the sub-transistor (41) is a Si transistor in which the sub-drift layer (45) is formed of Si. [Variant 3]

[0273] Semiconductor module according to variant 1 or 2, wherein the main transistor (21) has a drain electrode (21D), a source electrode (21S) and a gate electrode (21G), and wherein the semiconductor module comprises: a drain terminal (81) electrically connected to the drain electrode (21D); a source terminal (82) electrically connected to the source electrode (21S); and a gate terminal (83) electrically connected to the gate electrode (21G). [Variant 4]

[0274] Semiconductor module according to one of variants 1 to 3, wherein the sub-transistor (41) has a drain electrode (41D), a source electrode (41S) and a gate electrode (41G), wherein the source electrode (41S) of the sub-transistor (41) is connected to a source electrode (21S) of the main transistor (21), wherein the drain electrode (41D) of the sub-transistor (41) is connected to a gate electrode (21G) of the main transistor (21), and wherein the active clamping circuit (40) comprises: a pull-down resistor (43) connected between the source electrode (41S) and the gate electrode (41G) of the sub-transistor (41), and a clamp capacitor (42) connected between a drain electrode (21D) of the main transistor (21) and the gate electrode (41G) of the sub-transistor (41). [Variant 5]

[0275] Semiconductor module according to variant 4, where the first chip (20) does not have the active clamp circuit (40) but contains the main transistor (21), and wherein the second chip (30) comprises the sub-transistor (41), the pull-down resistor (43) and the clamping capacitor (42). [Variant 6]

[0276] Semiconductor module according to variant 5, wherein the sub-transistor (41), the pull-down resistor (43) and the clamping capacitor (42) in the second chip (30) are electrically connected to one another. [Variant 7]

[0277] Semiconductor module according to one of variants 4 to 6, wherein the first chip (20) has: a drain pad (PD1) electrically connected to the drain electrode (21D) of the main transistor (21), and a source pad (PS1) electrically connected to the source electrode (21S) of the main transistor (21), wherein the drain pad (PD1) and the source pad (PS1) are arranged separately from each other in a first direction as seen in a thickness direction (z-direction) of the main drift layer (24), and wherein the first chip (20) and the second chip (30) are arranged separately from each other in a second direction orthogonal to the first direction, as seen in the thickness direction (z-direction) of the main drift layer (24). [Variant 8]

[0278] Semiconductor module according to one of variants 4 to 7, wherein the second chip (30) has a semiconductor substrate (44) carrying the sub-drift layer (45), wherein a source region (48) is formed on a front side of the sub-drift layer (45) and is electrically connected to the source electrode (41S) of the sub-transistor (41), and wherein the drain electrode (41D) of the sub-transistor (41) is formed on a back side of the semiconductor substrate (44) which is located on a side opposite to the sub-drift layer (45). [Variant 9]

[0279] Semiconductor module according to one of variants 4 to 7, wherein a drain region (46B) electrically connected to the drain electrode (41D) of the sub-transistor (41) and a source region (48) electrically connected to the source electrode (41S) of the sub-transistor (41) are separately arranged on a front side of the sub-drift layer (45). [Variant 10]

[0280] Semiconductor module according to one of variants 4 to 9, wherein the second chip (30) has a pad (contact area) (PG2) connected to the gate electrode (41G) of the sub-transistor (41) via the pull-down resistor (43), and wherein, viewed in a thickness direction (z-direction) of the sub-drift layer (45), the pull-down resistor (43) and / or the clamping capacitor (42) is formed at a position overlapping the pad (PG2) and closer to the sub-drift layer (45) than the pad (PG2). [Variant 11]

[0281] Semiconductor module according to one of variants 4 to 9, wherein the connecting element (50) comprises: a first connecting element (51) electrically connecting the source electrode (21S) of the main transistor (21) to the source electrode (41S) and the gate electrode (41G) of the sub-transistor (41), a second connecting element (52) electrically connecting the clamping capacitor (42) to the drain electrode (21D) of the main transistor (21), and a third connecting element (53) electrically connecting the gate electrode (21G) of the main transistor (21) and the drain electrode (41D) of the sub-transistor (41). [Variant 12]

[0282] Semiconductor module according to variant 11, wherein the first connecting element (51), the second connecting element (52) and the third connecting element (53) are each formed from a metal plate. [Variant 13]

[0283] Semiconductor module according to variant 11, wherein the first connecting element (51), the second connecting element (52) and the third connecting element (53) are each formed from a metal coating. [Variant 14]

[0284] Semiconductor module according to one of variants 11 to 13, wherein the second chip (30) has a capacitor pad (PCA) electrically connected to the clamp capacitor (42), and the second connecting element (52) is connected to the capacitor pad (PCA). [Variant 15]

[0285] Semiconductor module according to one of variants 1 to 14, wherein the first chip (20A, 20B) comprises first chips arranged separately from each other, and wherein the second chip (30A, 30B) is separated from the first chips (20A, 20B) in a direction orthogonal to an arrangement direction of the first chips (20A, 20B) as viewed in a thickness direction (z-direction) of the encapsulating resin (350). [Variant 16]

[0286] A semiconductor module according to variant 15, wherein the second chip (30A, 30B) comprises second chips arranged separately from each other in the arrangement direction of the first chips (20A, 20B). [Variant 17]

[0287] Semiconductor unit (400), comprising: the semiconductor module (300) according to one of variants 1 to 16; a third chip (310) arranged in the encapsulation resin (350) separately from the first chip (20) and the second chip (30) and having a driver circuit (311) configured to drive the main transistor (21); and a control connection element (324, 325) electrically connecting the third chip (310) to the first chip (20) and the second chip (30). [Variant 18]

[0288] Semiconductor unit according to variant 17, wherein the main transistor (21) and the sub-transistor (41) each have a drain electrode (21D, 41D), a source electrode (21S, 41S) and a gate electrode (21G, 41G), and the control connection element (324, 325) electrically connects the driver circuit (311), the drain electrode (41D) of the sub-transistor (41) and the gate electrode (21G) of the main transistor (21). [Variant 19]

[0289] Semiconductor module according to one of variants 2 to 14, further comprising: a capacitor (510) connected between a source electrode (41S) and a gate electrode (41G) of the sub-transistor (41). [Variant 20]

[0290] Semiconductor module according to one of variants 2 to 14, further comprising: a protection diode (500) having an anode electrode (501) electrically connected to a source electrode (41S) of the sub-transistor (41) and a cathode electrode (502) electrically connected to a gate electrode (41G) of the sub-transistor (41). [Variant 21]

[0291] Semiconductor module according to one of variants 2 to 14, 20 and 21, further comprising: a protection transistor (520) connected between a source electrode (41S) and a gate electrode (41G) of the sub-transistor (41) and having a gate electrode (523) electrically connected to a gate electrode (21G) of the main transistor (21). [Variant 22]

[0292] Semiconductor module according to one of variants 4 to 14, wherein the second chip (30) contains a semiconductor substrate (44), and the clamping capacitor (42) has: a first electrode (42P) and a second terminal (42Q) arranged separately on the semiconductor substrate (44), and a dielectric layer (49A) disposed on the semiconductor substrate (44) and located between the first electrode (42P) and the second terminal (42Q). [Variant 23]

[0293] Semiconductor module according to one of variants 4 to 14, further comprising: a connection path (43A) electrically connecting the drain electrode (41D) of the sub-transistor (41) and the source electrode (41S) of the sub-transistor (41), the connection path (43A) having a serpentine section, and the pull-down resistor (43) contains a resistance component of the serpentine section. [Variant 24]

[0294] Semiconductor module according to one of variants 4 to 14, wherein the second chip (30) contains a semiconductor substrate (44), and wherein the pull-down resistor (43) comprises: a first terminal (43P), a second terminal (43Q), and a plate-shaped resistance part (43R) formed on the semiconductor substrate (44) and having a greater resistance than the first terminal (43P) and the second terminal (43Q), and the first terminal (43P) and the second terminal (43Q) are arranged on the resistance part (43R) and electrically connected to the resistance part (43R). [Variant 25]

[0295] A semiconductor module according to any one of variants 4 to 14, wherein the pull-down resistor (43) is configured by a normally-on transistor and has an ON resistance of the normally-on transistor. [Variant 26]

[0296] Semiconductor module according to one of variants 1 to 16 and 19 to 24, wherein the sub-transistor (41) is arranged to be switched on earlier than the main transistor (21) in response to an increase in the drain-source voltage of the main transistor (21).

[0297] The above description provides only examples. One skilled in the art may recognize other possible combinations and substitutions of the elements and methods (manufacturing processes) in addition to those listed for the purpose of describing the techniques of the present disclosure. This disclosure is intended to encompass any substitutions, modifications, and changes that fall within the scope of the disclosure, including the claims and variations. LIST OF REFERENCE SYMBOLS 10, 100, 200, 300 semiconductor modules 20, 20A, 20B first chip 20s chip front 20r chip back 21, 21A, 21B main transistor 21D Drain electrode 21S source electrode 21SA Source Contact 21SB source field plate 21SC End 21G gate electrode 21T active area 22 Semiconductor substrate 23 buffers 24 Electron transit layer 25 Electron supply layer 26 2DEG 27 Gate layer 27s upper surface 27r lower surface 27A first extension 27B second extension 27C Bridge 28 Passivation layer 28A first opening 28B second opening 29 Interlayer insulation layer 30, 30A, 30B second chip 30a first chip side surface 30b second chip side surface 30c third chip side surface 30d fourth chip side surface 30s chip front 30r chip back 40, 40A, 40B active clamp circuit 41 clamping transistor 41D Drain electrode 41S source electrode 41G Gate electrode 41T active area 42 clamp capacitor 42P first electrode 42Q second electrode 42V through-hole plating (Via) 43 Pull-down resistor 43A connecting path 43C wire 43P first connection 43Q second connection 43R resistor part 43V through-hole plating (Via) 44 Semiconductor substrate 45 Drift layer 46 Basic area 46A base contact area 46B Drain area 47 Trench 48 Source area 49A Insulation film 49B Intermediate insulation film 49C, 49D, 49E, 49F, 49G, 49H, 49J opening 50 connecting element 51 first connecting element 52 second connecting element 53 third connecting element 60 encapsulation resin 61 resin front 62 resin back 63 first resin side surface 64 second resin side surface 65 third resin side surface 66 fourth resin side surface 71 first die pad 72 second die pad 81 Drain connection 82 Source connection 83 Gate connection 110 Encapsulation resin 110s resin front 110r resin back 110a first resin side surface 110b second resin side surface 110c third resin side surface 110d fourth resin side surface 111 first encapsulation section 112 second encapsulation section 113 first opening 114 second opening 115 third opening 116 fourth opening 120 connecting element 121 first connecting element 122 second connecting element 123 third connecting element 124 fourth connecting element 131 Drain connection 132 Main source connection 133 Sense-Source connection 134 Gate connection 135 front insulation layer 136 rear insulation layer 140 Interconnect layer 141 Clamp-drain intermediate connection 142 Clamp-source interconnect 143 Clamp gate interconnect 151 first intermediate connection 152 second intermediate connection 153 third intermediate connection 154 fourth intermediate connection 155 fifth intermediate connection 210 connecting element 211 first connecting element 212 second connecting element 213 third connecting element 220 first die pad 221 first heat dissipation structure 230 second die pad 231 second heat dissipation structure 310 third chip 310s chip front 310r chip back 311 driver circuit 312 Electrode Pad 320 Intermediate connection 321 first intermediate connection 322 second intermediate connection 323 third intermediate connection 324 fourth intermediate connection 325 fifth intermediate connection 326 driver connections 331 Drain connection 332 Source connection 333 Output connector 334 Driver connection 350 encapsulation resin 350s resin front 350r resin back 350a first resin side surface 350b second resin side surface 350c third resin side surface 350d fourth resin side surface 351 first encapsulation section 352 second encapsulation section 353 third encapsulation section 361 first die pad 362 second die pad 363 third die pad 364 fourth die pad 365 first heat dissipation structure 366 second heat dissipation structure 367 fourth heat dissipation structure 370 front insulation layer 380 rear insulation layer 400 semiconductor units 500 protection diode 501 anode electrode 502 cathode electrode 503 Well region 504 Through-hole plating (Via) 510 capacitor 520 protection transistor 521 Drain electrode 522 Source electrode 523 Gate electrode AD1 first bonding material AD2 second bonding material AD3 third bonding material PA first pad PB second pad PC third pad PD, PD1 drain pad PS, PS1, PS2 Source Pad PSM Main Source Pad PSS Sense-Source Pad PG, PG1 Gate Pad PG2 Pad PCA capacitor pad QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-82011

[0003] JP 2018-82 011 A

[0003]

Claims

[1] Semiconductor module, comprising: a first chip having a main transistor having a main drift layer; a second chip having at least a portion of an active clamp circuit with a sub-transistor configured to be activated based on an increase in a drain-source voltage of the main transistor; a connecting element that electrically connects the main transistor and the active clamping circuit; an encapsulating resin that encapsulates the first chip, the second chip and the connecting element, wherein the sub-transistor has a sub-drift layer formed of a material different from a material from which the main drift layer is formed. [2] Semiconductor module according to claim 1, wherein the main transistor is a GaN transistor in which the main drift layer is formed from GaN, and wherein the sub-transistor is a Si transistor in which the sub-drift layer is formed of Si. [3] A semiconductor module according to claim 1 or 2, wherein the main transistor has a drain electrode, a source electrode and a gate electrode, the semiconductor module further comprising: a drain terminal electrically connected to the drain electrode; a source terminal electrically connected to the source electrode; and a gate terminal electrically connected to the gate electrode. [4] Semiconductor module according to one of claims 1 to 3, wherein the sub-transistor has a drain electrode, a source electrode and a gate electrode, wherein the source electrode of the sub-transistor is connected to a source electrode of the main transistor, wherein the drain electrode of the sub-transistor is connected to a gate electrode of the main transistor, and where the active clamp circuit has: a pull-down resistor connected between the source electrode and the gate electrode of the sub-transistor, and a clamping capacitor connected between a drain electrode of the main transistor and the gate electrode of the sub-transistor. [5] Semiconductor module according to claim 4, wherein the first chip does not have the active clamp circuit, but contains the main transistor, and wherein the second chip comprises the sub-transistor, the pull-down resistor and the clamp capacitor. [6] The semiconductor module according to claim 5, wherein the sub-transistor, the pull-down resistor and the clamping capacitor in the second chip are electrically connected to each other. [7] Semiconductor module according to one of claims 4 to 6, wherein the first chip has: a drain pad electrically connected to the drain electrode of the main transistor, and a source pad electrically connected to the source electrode of the main transistor, wherein the drain pad and the source pad are arranged separately from each other in a first direction as seen in a thickness direction of the main drift layer, and wherein the first chip and the second chip are arranged separately from each other in a second direction orthogonal to the first direction as viewed in the thickness direction of the main drift layer. [8] Semiconductor module according to one of claims 4 to 7, wherein the second chip has a semiconductor substrate carrying the underdrift layer, wherein a source region is formed on a front side of the sub-drift layer and is electrically connected to the source electrode of the sub-transistor, and wherein the drain electrode of the sub-transistor is formed on a back side of the semiconductor substrate which is located on a side opposite to the sub-drift layer. [9] Semiconductor module according to one of claims 4 to 7, wherein a drain region electrically connected to the drain electrode of the sub-transistor and a source region electrically connected to the source electrode of the sub-transistor are separately arranged on a front side of the sub-drift layer. [10] Semiconductor module according to one of claims 4 to 9, wherein the second chip has a pad connected to the gate electrode of the sub-transistor via the pull-down resistor, and wherein, viewed in a thickness direction of the sub-drift layer, at least one of the pull-down resistor and the clamping capacitor is formed at a position overlapping the pad and closer to the sub-drift layer than the pad. [11] Semiconductor module according to one of claims 4 to 9, wherein the connecting element comprises: a first connecting element electrically connecting the source electrode of the main transistor to the source electrode and the gate electrode of the sub-transistor, a second connecting element electrically connecting the clamping capacitor to the drain electrode of the main transistor, and a third connecting element that electrically connects the gate electrode of the main transistor and the drain electrode of the sub-transistor. [12] The semiconductor module according to claim 11, wherein the first connecting member, the second connecting member and the third connecting member are each formed of a metal plate. [13] The semiconductor module according to claim 11, wherein the first connecting member, the second connecting member and the third connecting member are each formed of a metal plate. [14] Semiconductor module according to one of claims 11 to 13, wherein the second chip has a capacitor pad electrically connected to the clamp capacitor, and the second connecting element is connected to the capacitor pad. [15] The semiconductor module according to any one of claims 1 to 14, wherein the first chip comprises first chips arranged separately from each other, and wherein, viewed in a thickness direction of the encapsulating resin, the second chip is separated from the first chips in a direction orthogonal to an arrangement direction of the first chips. [16] The semiconductor module according to claim 15, wherein the second chip comprises second chips arranged separately from each other in the arrangement direction of the first chips. [17] Semiconductor device, comprising: the semiconductor module according to one of claims 1 to 16; a third chip arranged in the encapsulation resin separately from the first chip and the second chip and having a driver circuit configured to drive the main transistor; and a control connection element that electrically connects the third chip to the first chip and the second chip. [18] A semiconductor device according to claim 17, wherein the main transistor and the sub-transistor each have a drain electrode, a source electrode and a gate electrode, and wherein the control connection element connects the driver circuit, the drain electrode of the sub-transistor and the gate electrode of the main transistor.

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