ADJUSTABLE WINDOW FOR MONITORING TIMING OR TIME EVENTS

Abstract

A microelectronic circuit can include at least one timing or time-event detector circuit configured to generate a time-event monitoring signal in response to a change in a digital value at an input of an associated register circuit during a time-event monitoring window. The microelectronic circuit can further include a control input for setting at least one duration of the time-event monitoring window.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure generally relate to microelectronic circuit technology that includes internal monitoring for detecting timing events. Some embodiments relate to adjusting the duration or position of a timing event monitoring (TEM) window. BACKGROUND

[0002] Processing paths in the microelectronic circuit can be implemented with logic units and register circuits, for example, such that a register circuit stores the output value of a preceding logic unit on the rising, falling, or both edges of a trigger signal (if the register circuit includes a flip-flop) or at a high or low level of the trigger signal (if the register circuit includes a latch). A trigger edge or other control event of the trigger signal (e.g., a clock signal) can establish a permissible time limit before which a digital value should appear at a data input of the register circuit to be properly stored. The permissible time limit is not necessarily the exact time of the trigger edge, but is defined in some proportion to it due to physical effects such as the finite rate at which a voltage level can change.The time required for the data input to be stable before the trigger edge can be referred to as the setup time. On the other hand, in some applications, the data input should be stable for a certain time after the trigger edge. The minimum time required for the data input to be stable after the trigger edge can be referred to as the hold time. The logic units can also be referred to as parts of a combinational logic.

[0003] Monitoring circuits can be used to detect timing events. A monitoring circuit can include a timing event detector circuit. A monitoring circuit can include a circuit element or functionality added to or associated with a register circuit and configured to generate a timing event observation (TEO) signal in response to the detection of a timing event. A timing event can be, for example, a change in the digital value of the data input that occurred during the setup time after the allowable time limit. In addition to the monitoring circuitry itself, the microelectronic circuit can include an OR tree and / or other structures for collecting, processing, and analyzing the TEO signals from the monitoring circuitry.The monitoring circuits can also be used as standalone devices for other applications, for example as edge detectors in digital phase-locked loops.

[0004] The detection of timing events can trigger compensatory actions, which may include, for example, changes in the values ​​of other operating parameters of the circuit, such as the clock frequency, or a temporary change in the clock waveform. SUMMARY

[0005] This summary is intended to introduce, in simplified form, a selection of concepts described further below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit or delineate the scope of the claimed subject matter.

[0006] Exemplary embodiments of the present disclosure enable optimization of the detection of temporal events by providing a dynamically adjustable TEM window. These and other advantages can be achieved by the features of the independent claims. Further embodiments are included in the dependent claims, the description, and the drawings.

[0007] According to a first aspect, a microelectronic circuit comprises: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window; and a control input for setting at least a duration of the timing event monitoring window.

[0008] According to an embodiment of the first aspect, the window for monitoring time events is connected to a corresponding edge of a clock signal.

[0009] According to an exemplary embodiment of the first aspect, the microelectronic circuit further comprises a timing event monitoring window clock signal generation circuit for generating a timing event monitoring window clock signal indicating the duration of the timing event monitoring window and a position of the timing event monitoring window with respect to the respective edge of the clock signal.

[0010] According to an exemplary embodiment of the first aspect, the circuit for generating a time event monitoring window clock signal is configured to provide the time event monitoring window clock signal to a single time event detector circuit, a subset of time event detector circuits of the microelectronic circuit, or all time event detector circuits of the microelectronic circuit.

[0011] According to an exemplary embodiment of the first aspect, the circuit for generating a time event monitoring window clock signal comprises a tapped delay line for delaying the clock signal.

[0012] According to an exemplary embodiment of the first aspect, the time event monitoring window clock signal generation circuit is configured to: delay the clock signal to obtain a delayed clock signal; and generate the window time event monitoring clock signal based on a combination of the clock signal and the delayed clock signal.

[0013] According to an embodiment of the first aspect, the microelectronic circuit is configured to adjust the delay of the delayed clock signal based on the control input to set the duration of the window for monitoring time events.

[0014] According to an embodiment of the first aspect, the duration of the time event monitoring window is configured to be adjustable by selecting one of a plurality of tapped delay line outputs corresponding to a desired delay.

[0015] According to an embodiment of the first aspect, the combination of the clock signal and the delayed clock signal comprises a NOR operation.

[0016] According to an exemplary embodiment of the first aspect, the circuit for generating a timing event monitoring window clock signal is configured to delay the clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates the duration of the timing event monitoring window and the position of the timing event monitoring window with respect to the respective edge of the clock signal

[0017] According to an embodiment of the first aspect, the microelectronic circuit is configured to adjust a duty cycle of the delayed clock signal to set the duration of the monitoring window for time events.

[0018] According to an embodiment of the first aspect, the microelectronic circuit is configured to adjust the delay of the delayed clock signal to adjust the position of the timing event monitoring window with respect to the respective edge of the clock signal.

[0019] According to an exemplary embodiment of the first aspect, the timing window clock signal generation circuit comprises a time-to-digital converter configured to convert the plurality of tapped delay line outputs to a digital value to enable calibration of the timing window clock signal generation circuit, and the timing window clock signal generation circuit is further configured to: determine a current clock cycle length of the clock signal based on the digital value; and reselect one of the plurality of tapped delay line outputs based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal.

[0020] According to an exemplary embodiment of the first aspect, the time-to-digital converter comprises a capture register configured to capture the plurality of tapped delay line outputs, and wherein the timing event monitoring window clock signal generation circuit is configured to determine the current clock cycle length of the clock signal based on the captured plurality of tapped delay line outputs.

[0021] According to an embodiment of the first aspect, at least a part of the window for monitoring time events lies before the respective edge of the clock signal.

[0022] According to an embodiment of the first aspect, the window for monitoring time events is located before the respective edge of the clock signal, and the window for monitoring time events ends with the clock edge.

[0023] According to an exemplary embodiment of the first aspect, a second window for monitoring timing events is located after the edge of the clock signal.

[0024] According to an embodiment of the first aspect, a part of the window for monitoring time events lies after the edge of the clock signal.

[0025] According to an embodiment of the first aspect, the microelectronic circuit further comprises: a plurality of processing paths comprising logic units and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic units in synchronization with the clock signal; a emulation path simulating the operation of a critical path of the plurality of processing paths, wherein the emulation path comprises a one-bit counter with feedback via a delay line adapted to the critical path, and wherein the associated register circuit comprises the one-bit counter.

[0026] According to a second aspect, a method for operating a microelectronic circuit comprises the following steps: generating a timing event observation signal in response to detecting a change in a digital value at an input of an associated register circuit during a timing event monitoring window; and adjusting at least a duration of the timing event monitoring window.

[0027] According to an embodiment of the second aspect, the window for monitoring time events is connected to a corresponding edge of a clock signal.

[0028] According to an embodiment of the second aspect, the method further comprises: generating a clock signal for the time event monitoring window indicating the duration of the time event monitoring window and a position of the time event monitoring window with respect to the respective edge of the clock signal.

[0029] According to an exemplary embodiment of the second aspect, the method further comprises: providing the clock signal for the timing event monitoring window for a single timing event detector circuit, a subset of timing event detector circuits of the microelectronic circuit, or all timing event detector circuits of the microelectronic circuit.

[0030] According to an embodiment of the second aspect, the monitoring window for the time event is generated based on a tapped delay line configured to delay the clock signal.

[0031] According to an exemplary embodiment of the second aspect, the method further comprises: delaying the clock signal to obtain a delayed clock signal; and

[0032] Generating the time event monitoring window clock signal based on a combination of the clock signal and the delayed clock signal.

[0033] According to an embodiment of the second aspect, the method further comprises: adjusting the delay of the delayed clock signal based on a control input to adjust the duration of the timing event monitoring window.

[0034] According to an embodiment of the second aspect, the duration of the window for monitoring timing events is adjusted by selecting one of a plurality of outputs of the tapped delay line corresponding to a desired delay.

[0035] According to an embodiment of the second aspect, the combination of the clock signal and the delayed clock signal comprises a NOR operation.

[0036] According to an embodiment of the second aspect, the method further comprises: delaying the clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates the duration of the timing event monitoring window and the position of the timing event monitoring window with respect to the respective edge of the clock signal.

[0037] According to an embodiment of the second aspect, the method further comprises:adjusting a duty cycle of the delayed clock signal to adjust the duration of the monitoring window for time events.

[0038] According to an embodiment of the second aspect, the method further comprises: adjusting the delay of the delayed clock signal to adjust the position of the time event monitoring window with respect to the respective edge of the clock signal.

[0039] According to an exemplary embodiment of the second aspect, the timing event watch window clock signal is generated based on a time-to-digital converter configured to convert the plurality of tapped delay line outputs into a digital value to enable calibration of the timing event watch window clock generator circuit, and the method further comprises: determining a current clock cycle length of the clock signal based on the digital value; and reselecting one of the plurality of tapped delay line outputs based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal.

[0040] According to an exemplary embodiment of the second aspect, the time-to-digital converter comprises a capture register configured to capture the plurality of outputs of the tapped delay line, and the method further comprises: determining the current clock cycle length of the clock signal based on the plurality of captured outputs of the tapped delay line.

[0041] According to an embodiment of the second aspect, at least a part of the window for monitoring time events lies before the respective edge of the clock signal.

[0042] According to an embodiment of the second aspect, the window for monitoring time events is located before the respective edge of the clock signal, and the window for monitoring time events ends with the clock edge.

[0043] According to an embodiment of the second aspect, a second window is provided for monitoring timing events after the edge of the clock signal.

[0044] According to an embodiment of the second aspect, a part of the window for monitoring time events lies after the edge of the clock signal.

[0045] According to an exemplary embodiment of the second aspect, the microelectronic circuit comprises a plurality of processing paths comprising logic units and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic units in synchronism with the clock signal, and the method further comprises: simulating the operation of a critical path of the plurality of processing paths by a replication path, wherein the replication path comprises a one-bit counter with feedback via a delay line adapted to the critical path, and wherein the associated register circuit comprises the one-bit counter.

[0046] Each of the above-mentioned embodiments may be combined with one or more other embodiments. Many of the associated features will be better understood from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, help to explain the principles of the invention. In the drawings: Fig. 1 shows an example of a microelectronic circuit with monitoring of time events; Fig. 2 shows an example of a timing event monitoring clock generator circuit configured to generate a timing event monitoring clock signal based on a combination of a clock signal and a delayed clock signal; Fig. 3 shows an example of a timing diagram of signals associated with the generation of clock signals for monitoring timing events based on a NOR operation between a clock signal and a delayed clock signal; Fig. 4 shows an example of a timing event monitoring clock generator configured to generate a timing event monitoring clock signal based on a delayed clock signal; Fig. Figure 5 shows an example timing diagram of signals associated with generating clock signals for monitoring timing events based on a delayed clock signal; Fig. Figure 6 shows an example of a timing window monitoring clock generator circuit with calibration function; Fig. Figure 7 shows an example of a microelectronic circuit including a timing event monitoring circuit connected to a replication path including a one-bit counter; and Fig. Figure 8 shows an example of a method for operating a microelectronic circuit.

[0048] In the accompanying drawings, identical or similar parts are identified by identical reference numerals. DETAILED DESCRIPTION

[0049] The following describes microelectronic circuits and methods for their design and operation. A microelectronic circuit may include a plurality of processing paths with logic units and register circuits. A processing path may include a sequence of circuit elements through which digital data can pass, so that it is processed in logic units and temporarily stored in register circuits located between successive logic units on the processing paths. The register circuits may be configured to temporarily store the output values ​​of the logic units in synchronization with a clock signal. The software executing the microelectronic circuit can determine which processing paths are used at a particular time and in what manner.

[0050] Fig. 1 shows an example of a microelectronic circuit with temporal or time event monitoring. As described above, the microelectronic circuit 100 may include a plurality of processing paths. The microelectronic circuit 100 may include a register circuit 110, e.g., any suitable type of latch or flip-flop, optionally in combination with other components. The register circuit 110 may be associated with one of the processing paths of the microelectronic circuit 100 or with a replication path connected to one or more of the processing paths. The register circuit 110 may have a data input for receiving digital values ​​of a data signal (D) and a clock signal input for receiving a clock signal (CLK).The clock signal can be configured as a trigger signal for register circuit 110 to store the digital value (D) currently appearing at the data input, for example, upon a rising or falling edge of the clock signal. The clock signal CLK can also be referred to as the main clock signal or the data clock signal.

[0051] A replication path can be configured to simulate the operation of one or more processing paths, e.g., with known input data. If a timing event is detected on the replication path, it can be assumed with sufficient probability that timing events will also occur on the "actual" processing path(s) under the same operating conditions, e.g., under the influence of the same values ​​of operating parameters such as operating voltage, clock frequency, or the like. The operating parameters can be adjusted to avoid or at least reduce the probability of timing events on the processing path(s). For example, the operating voltage can be increased or the clock frequency can be decreased, at least in a corresponding part of the microelectronic circuit.

[0052] Register circuit 110 may be connected to a timing event monitoring (TEM) circuit 120. A data input of TEM circuit 120 may be connected to the data input of register circuit 110. TEM circuit 120 may therefore receive as input a copy of what enters the data input of register circuit 110. TEM circuit 120 may be configured to generate a timing event observation (TEO) signal, for example, in response to a change in a digital value at the data input (D) of register circuit 110 that occurred during a TEM monitoring window associated with a corresponding edge of the clock signal (CLK), for example, later than a permissible time limit before the edge of the clock signal (CLK).For example, the TEO signal may comprise a binary digital signal that is normally at a logic low level, but at the moment a timing event is detected (e.g., a data value change during the TEM window), the TEM circuit 120 may raise the TEO signal to a logic high level. The TEO signal may be maintained at the logic high level until the end of the clock cycle in which the timing event was observed, or optionally longer.

[0053] Each instance or occurrence of the TEM window can be associated with a specific edge of the clock signal (CLK). Therefore, a specific instance of the TEM window enables the monitoring of timing events associated with the respective clock edge. However, it is also possible to set up a clock edge-independent TEM window to monitor timing events that are not directly associated with a clock signal edge. The duration and position of the TEM window can be defined by a TEM window clock signal (TEM_CLK), which is received as another input to the TEM circuit 120. The TEM window can also be referred to as a timing event observation window (TEO). The TEM circuit 120 can also be referred to as a timing event or timing event detector circuit.

[0054] The microelectronic circuit 100 may further comprise a TEM window clock generator circuit 130, which may also be referred to as a TEM clock generator. The TEM window clock generator circuit 130 may be configured to generate the TEM window clock signal (TEM_CLK), for example, based on the (main) clock signal (CLK), and provide the generated TEM_CLK to the TEM circuit 120. The TEM window clock signal may indicate the duration of the TEM window and the position of the TEM window with respect to the respective clock edge. For example, a logic high or a logic low level of the TEM_CLK may define the position and duration of the TEM window. Examples of the TEM window clock generator circuit 130 are described with reference to Fig. 2 and Fig. 4 described.

[0055] The TEM window clock generator 130 can provide its output to one or more TEM circuits 120. In one example, TEM_CLK is provided to a single TEM circuit 120. This allows for register-circuit-specific configuration of the TEM window. Alternatively, TEM_CLK can be provided to a group of TEM circuits, e.g., a subset of TEM circuits of the microelectronic circuit 100. The subgroup can be defined, for example, by categorizing the TEM circuits according to how likely a timing event will occur in the register circuit they monitor. This probability can be estimated, for example, based on the length of a processing path preceding the respective TEM circuit without other TEM circuits. The same TEM_CLK signal can be provided to the TEM circuits within the same category.This makes it possible to reduce the TEM overhead in terms of silicon area while allowing a degree of TEM window optimization for different parts of the microelectronic circuit. It is also possible to provide TEM_CLK to all register circuits of the microelectronic circuit 100. This enables very low TEM overhead, since the microelectronic circuit 100 can comprise a single TEM window clock signal generator 130.

[0056] The microelectronic circuit 100 may have a control input for adjusting at least the duration of the TEM window. Optionally, the position of the TEM window relative to the respective clock edge may also be adjusted. The duration and / or position of the TEM window may be dynamically adjusted (e.g., during the runtime of the microelectronic circuit 100), e.g., based on various operating parameters, e.g., the current operating voltage or clock frequency, or a number of detected timing events.

[0057] In one example, the control input comprises the TEM window clock signal input of the TEM circuit 120. Alternatively, the control input may comprise a control input within the TEM window clock generator circuit 130, where the control input may be configured to modify the TEM window clock signal supplied to the TEM circuit 120, such as described with reference to Fig. 2. The adjustable TEM window enables optimization of the monitoring of timing events in the microelectronic circuit 100. Monitoring of timing events by the TEM circuit 120 consumes energy, and therefore, energy can be saved by shortening the duration of the TEM window whenever possible. Thus, the energy consumption of the microelectronic circuit 100 can be reduced.

[0058] Fig. Figure 2 shows an example of a TEM window clock generator circuit configured to generate a TEM clock signal based on a combination of a clock signal and a delayed clock signal. As mentioned above, the TEM window clock generator circuit, designated by reference numeral 130-1 in this example, may receive the clock signal CLK (main clock) as an input signal. The TEM window clock generator circuit 130-1 may include a plurality of delay elements 131-1, 131-2, ..., 131-n configured to delay the input clock signal. The delay elements may form or be part of a tapped delay line (TDL) 131. The outputs of the individual delay elements may be fed to a multiplexer (MUX) 132, for example, via an n-wide bus. The multiplexer 132 may be configured to connect one of its inputs (ieThe control input delay_sel selects the clock signal (CLK) corresponding to a desired delay and provides the selected signal (CPD) as the output of the multiplexer 132. CPD may therefore comprise a delayed version of the clock signal (CLK). The delayed clock signal (CPD) may be combined with the clock signal CLK, for example, by a suitable logic operation to generate the TEM window clock signal (TEM_CLK). The control input delay_sel enables dynamic adjustment of the duration of the TEM window. The microelectronic circuit 100 may therefore adjust the delay of the delayed clock signal (CPD) based on the control input. This may result in an adjustment of the duration of the TEM window.

[0059] Generating the TEM window clock signal based on the delayed clock signal (CPD), in this example in combination with the (non-delayed) clock signal (CLK), enables the TEM window to be linked to the respective clock edge. Therefore, fluctuations in the clock signal, e.g., due to non-idealities of the microelectronic circuit 100, cannot affect the position of the TEM window relative to the respective clock edge.

[0060] The clock signal (CLK) and the delayed clock signal (CDP) may be combined in any suitable manner, e.g., by a logic unit (e.g., a gate) such as a NOR gate 133, as in the example of Fig. 2. However, it is assumed that the functionality described here can also be implemented in practice with other circuit elements, as is common with digital circuits: After a desired functionality has been taught, the person skilled in the art can, for example, imagine several alternative implementations that differ, for example, in the polarity of the signals and the resulting need to use circuit elements such as inverters, properly selected logic gates or the like.

[0061] Fig. Figure 3 shows an example of a timing diagram of signals associated with clock signal generation for monitoring timing events based on a NOR operation between a clock signal and a delayed clock signal. This example is used for the Fig. 2. On the left, the clock signal (CLK) is delayed by the delay d1, which corresponds to a corresponding number of delay elements selected by the delay_sel control input to obtain the delayed clock signal (CPD). As defined by the NOR gate 133, the TEM_CLK signal goes high when both CLK and CPD are low. In this example, the logic high level of TEM_CLK defines the position of the TEM window. In this example, the TEM window is located before the respective clock edge. The TEM window ends at the clock edge. However, to be completely precise, the TEM window can also contain rising and falling times, so the actual extent of the TEM window generally depends on CLK and / or CPD and does not necessarily start and end at the exact times of the respective trigger edges.

[0062] On the right side, the clock signal (CLK) is delayed by a delay d2, which is greater than the delay d1. The duration of the TEM window is correspondingly shorter. However, it should be noted that the position of the end of the TEM window relative to the clock edge of CLK is maintained (it essentially coincides with the clock edge). Providing (at least part of) the TEM window before the clock edge enables the detection of timing events during the setup of the register circuit 110. Since the duration of the TEM window can be adjusted, dynamically adjustable setup monitoring is possible. The delays d1 and d2 can be selected from a range of 0 ≤ d < TCLK_LOW, where TCLK_LOW is the time in which the clock signal (CLK) reaches a certain level, which defines the TEM window in combination with the delayed clock signal (LOW in this example). The TEM window duration can therefore have values ​​from the range 0 < d ≤TCLK_LOW assume.

[0063] Additionally, a second TEM window can be provided after the respective clock edge. This allows for the detection of hold violations. The second TEM window can essentially start with the respective edge of the clock signal (CLK). The hold phase can be more susceptible to random fluctuations (e.g., due to shorter paths, less averaging) than the setup phase (e.g., due to longer paths, more averaging). Therefore, in some applications, the operating parameters (e.g., a minimum operating voltage, VDD_min) can only be derived based on setup monitoring. Hold cases can persist. However, for reliability, it is advantageous that setup and hold can be monitored separately.

[0064] Fig. Figure 4 shows an example of a TEM clock generator circuit configured to generate a TEM window clock signal based on a delayed clock signal. Similar to the example of Fig. 2, the TEM window clock generator circuit, designated in this example by reference numeral 130-2, may include an input for the (main) clock signal (CLK), a tapped delay line 131, and a multiplexer (MUX) 132. However, the output of the TEM window clock generator 130-2 may be the delayed clock signal (CPD) directly (TEM_CLK = CPD), rather than combining it with the clock signal (CLK). This allows the end of the TEM window to be decoupled from the respective edge of the clock signal (CLK). The delayed clock signal may therefore specify (e.g., define) both the duration of the TEM window and its position relative to the respective edge of the clock signal (CLK).

[0065] Furthermore, the TEM window clock generator 130-2 can be configured to adjust the duty cycle of the delayed clock signal (CPD), for example, by increasing or decreasing the time the delayed clock signal (CDP) remains at the logic high level. Since the TEM window can be defined by a specific level of the delayed clock signal, the duration of the TEM window can be adjusted by adjusting the duty cycle. Furthermore, the position of the TEM window with respect to the respective edge of the clock signal (CLK) can be adjusted by adjusting the delay of CPD, e.g., via the control input delay_sel.

[0066] Fig. Figure 5 shows an example of a timing diagram of signals associated with TEM clock signal generation based on a delayed clock signal. This example is used for the Fig. 4. On the left, the clock signal (CLK) is delayed by the delay d1 to obtain the delayed clock signal (CPD). The CPD, which in this case is the TEM_CLK signal, has a first duty cycle (duty_cycle_1) corresponding to the time CPD is at the logic high level. In this example, the TEM window is defined by the logic low level of CPD / TEM_CLK. Accordingly, a portion of the TEM window lies before the respective clock edge. A portion of the TEM window lies after the respective clock edge. The TEM window can extend beyond the respective clock edge.

[0067] On the right side, the clock signal (CLK) is delayed by a delay of d2 to obtain CPD / TEM_CLK. CPD / TEM_CLK has a second duty cycle (duty_cycle_2) that is longer than the first duty cycle. Since the TEM window is defined by the logic low level of CPD / TEM_CLK, the TEM window on the right side is shorter than the TEM window on the left side. The duration of the TEM window can therefore be adjusted by adjusting the duty cycle of the delayed clock signal (CPD).

[0068] In addition, the position of the TEM window relative to the respective edge of the clock signal (CLK) can be adjusted by delaying CPD. This also makes it possible to adjust the portion of the TEM window that precedes the clock edge. This allows the behavior of setup and hold monitoring to be dynamically configured. For reliability, it is advantageous that both setup and hold can be monitored.

[0069] In one example, the delay can be set so that the TEM window is completely before the clock edge, which provides similar functionality to Fig. 3. Thus, at least part of the TEM window, i.e., the entire TEM window or a part of it, can be located before the respective clock edge. Such a procedure can be referred to as advancing the TEM window (resulting in an advanced TEM window) or advancing the TEM window (resulting in an advanced TEM window). If the TEM window lies entirely before the respective clock edge, it can end on the respective clock edge.

[0070] The TEM window can be decoupled from a time borrowing window. Time borrowing in a microelectronic circuit can refer to allowing a circuit element to temporarily borrow time from a subsequent stage, e.g., to change a digital value later than expected, if the subsequent circuit element(s) on the same processing path can handle this without corrupting the processed data. In other words, a logic unit or other part of the processing path preceding this type of register circuitry is allowed to temporarily cause a timing event, e.g., a late change to a digital value, if the register circuitry 110 can handle it without corrupting the data being processed. To enable time borrowing, timing events detected during a time borrowing window can be ignored. The occurrence of a case of time borrowingTime borrowing can be recognized as a time event during the time borrowing window. As mentioned above, the time borrowing window can be separated (decoupled) from the time borrowing window.

[0071] Fig. Figure 6 shows an example of a circuit for generating a time event monitoring window clock signal with calibration function. Similar to the example of Fig. 2, the TEM window clock generation circuit, designated in this example by reference numeral 130-3, may include an input for the (main) clock signal (CLK), a tapped delay line 131, a multiplexer (MUX) 132, and a NOR gate 133 configured to combine the clock signal (CLK) and the delayed clock signal (CPD). However, it is possible for the TEM window clock generator or generator 130-3 to be similar to the example of Fig. 4, meaning that it directly provides the delayed clock signal at its output. The calibration methods described here can therefore be applied to the TEM clock generator circuits 130-1 and 130-2, as well as to other variants thereof.

[0072] Calibration may be performed, for example, because the sensitivity of the delay chain (e.g., TDL 131) to PVT (process, voltage, temperature) variations can lead to large fluctuations in the monitoring window, both in the sense of systematic and random fluctuation due to PVT. Continuous calibration of the delay chain makes it possible to maintain the TEM window size (duration) accurately even during PVT changes. Furthermore, by ensuring that small monitoring windows are reliable and accurate, the overall timing overhead in the system can be significantly reduced, allowing microelectronic circuits 100 to be used in more time-sensitive, faster applications.

[0073] To enable this, the TEM window clock generator 130-3 may further comprise a time-to-digital converter (TDC) configured to convert the outputs of TDL 131 into a digital value, for example, in response to enabling the calibration of the TEM window clock generator circuit 130-3. An example of such a TDC is the capture register 134, which may be configured to capture outputs of TDL 131, e.g., at least some outputs of the delay elements (buffers) 131-1, 131-2, ..., 131-n. Capturing the outputs may occur in response to enabling the calibration of the TEM window clock generator circuit 130-3, e.g. B. by providing a START signal to enable the clock signal (CLK) to propagate through the AND gate 135 to an enable input of the capture register 134.The clock cycle determination block 136 may be configured to determine a current clock cycle length (clock period) of the clock signal (CLK) based on the digital value provided by the TDC, e.g., the outputs of TDL 131 captured at the capture register 134. The capture register values ​​may be provided to the clock cycle determination block 136, for example, via an n-wide bus. The delay selection block 137 may be configured to (re-)select one of the TDL outputs based on the current clock cycle length so that the desired delay is (substantially) maintained relative to the current clock cycle length. For example, the TDL output that provides a delay closest to the desired delay may be selected. This calibration function is described further below.

[0074] The output of each delay element 131-1, 131-2, ..., 131-n can be routed to a corresponding flip-flop (134-1, 134-2, ..., 134-n) of the acquisition register 134 in addition to the multiplexer (MUX) 132. Whenever the system requires calibration, the clock signal (CLK) for the acquisition register 134 can be enabled for a clock pulse (unlocking the clock gate). In this way, the TDL outputs can be captured, for example, on the next positive edge of the clock signal (CLK) in the acquisition register 134. At this time, the acquisition register 134 can contain a pattern of digital values ​​(e.g., zeros and ones). By analyzing the captured pattern, the clock cycle determination block 136 can determine the clock period of the clock signal (CLK) relative to the number of delay buffers (delay elements of the TDL 131). The flip-flop in which the digital values ​​first change, e.g.From one to zero, the clock period can be determined to represent the clock period in terms of the number of delay elements. For example, if the value in flip-flop number 20 changes from one to zero, the clock period can be determined as 20 buffer delays. This value can be denoted by clock_period, or clock period.

[0075] Based on the clock period, the tap point to be selected in the delay buffer chain to generate a desired delayed version of the clock signal (CLK) can be easily and accurately calculated in delay selection block 137. In the case of the previous example, i.e., clock period = 20, delay selection block 137 can select the tap point after the second buffer if a delay of 10% of the clock period is desired. If a delay of 50% of the clock period is required, block 137 can select the tap point after the tenth buffer. The calculation of the desired tap point from the values ​​of capture register 134 can be performed, for example, using combinational logic or software. In one example, the output of the TDL 131 as well as the output of the acquisition register 131 are provided as multi-bit thermometer codes, where b(0), ..., b(m) = 1, b(m+1), ... , b(n) = 0, and where m < n.The parameter m changes depending on the delay.

[0076] Additionally, additional optimizations can be implemented to reduce the logic count. For example, not all buffer outputs can be included in the capture register 134. For example, the first few delay buffer outputs can be ignored if the system always has a watch window larger than half the clock period. Therefore, the clock cycle in the block can be determined based on the outputs of a subset of delay elements of the TDL 131.

[0077] The subset can be determined based on predefined clock cycle constraints or based on the previously determined clock cycle length. Calibrating the TEM clock generator allows a desired relative delay with respect to the clock cycle to be maintained, even when the microelectronic circuit 100 is subjected to non-ideal conditions, such as PVT changes. Combined with the dynamically adjustable TEM window duration, the calibration allows the currently configured TEM window to be kept stable.

[0078] Calibration of the TEM window clock generator circuit 130 can be performed in hardware, e.g., by the TEM window clock generator circuit 130 itself, as described above. Alternatively, calibration of this circuit can be initiated by software, whereby the measurement result (i.e., the clock period) is stored in memory. The configuration of the TEM window (e.g., the selection of a specific TDL output) can then be updated by software based on the stored measurement result.

[0079] However, it is possible to apply the calibration methods described here to fixed TEM windows.Therefore, according to one embodiment, a microelectronic circuit may comprise: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event watch window associated with a respective edge of a clock signal; and at least one timing event watch window clock signal generation circuit, wherein the timing event watch window clock generator circuit comprises a tapped delay line for delaying the clock signal, and wherein the timing event watch window clock generator circuit is configured to select one of a plurality of tapped delay line outputs according to a desired delay.The timing event monitoring window clock signal generation circuit may further include a time-to-digital converter configured to convert the tapped delay line outputs to a digital value (e.g., a capture register configured to capture the tapped delay line outputs) in response to enabling calibration of the timing event monitoring window clock generator circuit. The timing event monitoring window clock generator circuit may be further configured to: determine a current clock cycle length of the clock signal based on the digital value (e.g., the captured tapped delay line outputs); and reselect one of the plurality of tapped delay line outputs based on the current clock cycle length. This may be done to substantially maintain the desired delay.The desired delay can be fixed. Therefore, calibration of a fixed-configuration TEM window is provided. This allows a fixed-configuration TEM window to be kept stable regardless of PVT fluctuations.

[0080] Fig. Figure 7 shows an example of a microelectronic circuit with a TEM circuit connected to a emulation path with a one-bit counter. Direct monitoring of critical paths can be considered an accurate method for understanding real-time variations in circuit speed. This information can then be used for a variety of operations, such as adjusting the operating voltage to the circuit speed to ensure the circuit always operates at the lowest possible voltage. However, such methods may be less effective if it is difficult to ensure activity on the monitored critical path. Example embodiments of the present disclosure provide good alternatives for these types of paths.For example, TEM window-based critical path monitoring solutions can be combined with a one-bit counter-based critical path emulation, which can be activated, for example, by asserting the clock signal (CLK) for that circuit. A emulation path can be configured to simulate the operation of one or more critical paths of the processing paths of the microelectronic circuit 100.

[0081] Example embodiments of the present disclosure may address the following problems: - By combining monitoring with an easily activated replication path, it can be ensured that the system (e.g., the microelectronic circuit 100) can activate the replication path and check the time span on the critical path at any time without being dependent on unpredictable activities on the actual critical path. - In a solution based on direct monitoring of critical paths, the overall system solution can take the activation probability into account because activation occurs randomly. This means that the number of monitors (or monitored paths) can be higher than if activation were perfect (if the critical paths were always active). Example embodiments of the present disclosure allow the activation probability to be increased to 100% because the system has control over activation. This means that the number of monitoring devices can be significantly reduced. - Since it may be uncertain when a critical path will be active, the monitoring solution may be active most of the time to ensure it does not miss any activity on the critical path. This results in wasted energy while the monitor is active and waiting for activity in the critical path. Example embodiments of the present disclosure allow the system to control activation. This means that the emulation and monitoring may, for example, only be turned on for two clock cycles when the system wants to check the time period. This ensures that the energy overhead caused by monitoring is significantly lower than in a system where the critical paths are monitored directly.

[0082] The use of TEM circuits connected to register circuits, the use of replication paths, and other similar arrangements can generally be described as having monitoring units associated with the respective processing paths. Each such monitoring unit can be configured to generate a TEO signal in response to anomalous operation, e.g., a timing event, of the respective processing path. In the case of register circuits with a monitor, the monitoring unit can be the monitor circuit. In the case of replication paths, the monitoring unit can comprise the replication path along with the circuit element that analyzes its output (e.g., TEM circuit 120), and the observation signal can indicate that the output of the replication path was not as it should have been.

[0083] In the example of Fig. 7, the TEM window-based monitoring approach is combined with a system based on the replication path, where the replication path is implemented as a one-bit counter circuit. As before, the microelectronic circuit 100 may include a TEM circuit 120. However, the one-bit counter-based replication path may be provided as a register circuit 110. The one-bit counter may include a flip-flop 112, e.g., a D-flop, receiving a digital value at its data input (D), which may also be supplied to the TEM circuit 120. The flip-flop 112 may further receive the clock signal (CLK). The one-bit counter may further include an inverter 114 to provide inverted feedback to its data input (D).The feedback path may comprise a delay chain (delay line) containing one or more delay elements such that the delay of the delay chain is matched to the delay of the critical path.

[0084] The one-bit counter can be activated by activating the one-bit counter clock signal. The clock signal can be activated for two clock cycles, for example, one clock cycle for startup and one clock cycle for acquisition. By adjusting the delay of the one-bit counter's feedback path to the critical path to be monitored, the problem of activation unpredictability is solved, as both critical path replication and monitoring can be activated simultaneously for one clock cycle.

[0085] As an alternative to the one-bit counter of Fig. 7, other types of replication paths can also be used. For example, the TEM clock generator circuits 130-1 or 130-2 can be used to implement a replication path. In this case, these circuits can be configured with similar properties to the one-bit counter in Fig. 7. For example, the delay of these circuits can be adjusted to match the delay of the critical path(s). This offers the following advantages: - Since the system can directly activate the critical path replica at any time, the probability of activity is 100% (perfect activation). This means that the number of monitors (or monitored paths) required is significantly lower than in a system where activation is unpredictable. - Since the system can directly enable critical path replication at any time, there is no need to enable monitoring continuously. Therefore, monitoring can be enabled, for example, for two clock cycles at the same time as the replication path is enabled. This ensures that the power consumption of monitoring is significantly lower. - The critical path emulation based on a single-bit counter requires no settling time. This means no power is wasted waiting for the circuit to settle. Furthermore, the window-based monitoring can be completed in two clock cycles. This means that the measurement delay is minimal, and therefore no additional time is required to compensate for measurement or settling delays. - The performance (or time span) of the one-bit counter based replication path can be easily measured using a window-based monitoring solution.

[0086] Fig. Figure 8 shows an example of a method for operating a microelectronic circuit.

[0087] At 801, the method may include generating a time event watch signal in response to detecting a change in a digital value at an input of an associated register circuit during a time event watch window.

[0088] At 802, the method may include setting at least a duration of the time event monitoring window.

[0089] Further features of the method arise directly from the functions of the microelectronic circuit 100, as described in the specification and the appended claims, and are therefore not repeated here. Various variations of the methods can also be applied, as described in connection with the various embodiments.

[0090] A device, such as a microelectronic circuit 100, a component of a microelectronic circuit 100, or a device (e.g., a computer) including a microelectronic circuit 100, may be configured to perform or cause to be performed any aspect of the method(s) described herein. Furthermore, a device may include means for performing any aspect of the method(s) described herein. According to one embodiment, the means include the circuits described herein.

[0091] It will be apparent to those skilled in the art that, as technology advances, the example embodiments may be implemented in various ways. For example, logical functions may be replaced by structurally different but functionally equivalent functions by considering the possible inversions and logical conversions required. The present disclosure is therefore not limited to the examples described above, but may vary within the scope of the claims.

Claims

[1] A microelectronic circuit comprising: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window; and a control input for setting at least one duration of the monitoring window for time events. [2] A microelectronic circuit according to claim 1, wherein the window for monitoring timing events is connected or associated with a corresponding edge of a clock signal. [3] The microelectronic circuit of claim 2, further comprising a timing window clock signal generation circuit for generating a timing window clock signal indicative of the duration of the timing window and a position of the timing window with respect to the respective edge of the clock signal. [4] The microelectronic circuit of claim 3, wherein the timing event monitoring window clock signal generation circuit is configured to provide the timing event monitoring clock signal to a single timing event detector circuit, a subset of timing event detector circuits of the microelectronic circuit, or all timing event detector circuits of the microelectronic circuit. [5] A microelectronic circuit according to claim 3 or claim 4, wherein the circuit for generating a clock signal for a time event monitoring window comprises a tapped delay line for delaying the clock signal. [6] A microelectronic circuit according to any one of claims 3 to 5, wherein the circuit is configured to generate a clock signal for a time event monitoring window to: Delaying the clock signal to obtain a delayed clock signal; and Generating the clock signal for the time event monitoring window based on a combination of the clock signal and the delayed clock signal. [7] The microelectronic circuit of claim 6, wherein the microelectronic circuit is configured to adjust the delay of the delayed clock signal based on the control input to adjust the duration of the time event monitoring window. [8] A microelectronic circuit according to claim 5 and any one of claims 6 to 7, wherein the duration of the timing event monitoring window is configured to be adjustable by selecting one of a plurality of outputs of the tapped delay line corresponding to a desired delay. [9] A microelectronic circuit according to any one of claims 5 to 8, wherein the combination of the clock signal and the delayed clock signal comprises a NOR operation. [10] A microelectronic circuit according to any one of claims 3 to 5, wherein the circuit for generating a clock signal for a time event monitoring window is configured to delay the clock signal to obtain a delayed clock signal, the delayed clock signal indicating the duration of the time event monitoring window and the position of the time event monitoring window with respect to the respective edge of the clock signal [11] The microelectronic circuit of claim 10, wherein the microelectronic circuit is configured to adjust a duty cycle of the delayed clock signal to adjust the duration of the time event monitoring window. [12] The microelectronic circuit of claim 10 or claim 11, wherein the microelectronic circuit is configured to adjust the delay of the delayed clock signal to adjust the position of the timing event monitoring window with respect to the respective edge of the clock signal. [13] The microelectronic circuit of claim 5 and any one of claims 8 to 12, wherein the timing event monitoring window clock signal generation circuit comprises a time-to-digital converter configured to convert the plurality of tapped delay line outputs into a digital value in response to enabling calibration of the timing event monitoring window clock signal generation circuit, the timing event monitoring window clock signal generation circuit being further configured to: Determining a current clock cycle length of the clock signal based on the digital value; and Reselecting one of the plurality of outputs of the tapped delay line based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal. [14] The microelectronic circuit of claim 13, wherein the time-to-digital converter comprises a capture register configured to capture the plurality of tapped delay line outputs, and wherein the timing event monitoring window clock signal generation circuit is configured to determine the current clock cycle length of the clock signal based on the captured plurality of tapped delay line outputs. [15] Microelectronic circuit according to one of claims 2 to 14, wherein at least a part of the window for monitoring time events lies before the respective edge of the clock signal. [16] Microelectronic circuit according to claim 15, wherein the time event monitoring window is located before the respective edge of the clock signal and wherein the time event monitoring window ends with the respective edge of the clock signal. [17] A microelectronic circuit according to claim 16, wherein a second window for monitoring timing events is located after the respective edge of the clock signal. [18] A microelectronic circuit according to claim 15, wherein a part of the window for monitoring timing events lies after the respective edge of the clock signal. [19] Microelectronic circuit according to one of claims 1 to 18, further comprising: a plurality of processing paths comprising logic units and register circuits, the register circuits configured to temporarily store output values ​​of the logic units in synchronization with the clock signal; a emulation path simulating the operation of a critical path of the plurality of processing paths, wherein the emulation path comprises a one-bit counter with feedback via a delay line matched to the critical path, and wherein the associated register circuit comprises the one-bit counter. [20] A method of operating a microelectronic circuit, the method comprising: Generating a timing event watch signal in response to detecting a change in a digital value at an input of an associated register circuit during a timing event watch window; and Setting at least one duration of the time event monitoring window. [21] The method of claim 20, wherein the time event monitoring window is associated with a corresponding edge of a clock signal. [22] The method of claim 21 further comprising: Generating a time event watch window clock signal indicating the duration of the time event watch window and a position of the time event watch window with respect to the respective edge of the clock signal. [23] The method circuit or method according to claim 22, further comprising: Providing the time event monitoring window clock signal to a single time event detector circuit, a subset of time event detector circuits of the microelectronic circuit, or all time event detector circuits of the microelectronic circuit. [24] The method of claim 22 or claim 24, wherein the window for monitoring timing events is generated based on a tapped delay line configured to delay the clock signal. [25] A method according to any one of claims 22 to 24 further comprising: Delaying the clock signal to obtain a delayed clock signal; and Generating the time event monitoring window clock signal based on a combination of the clock signal and the delayed clock signal. [26] The method of claim 25 further comprising: Adjust the delay of the delayed clock signal based on a control input to set the duration of the monitoring window for timing events. [27] A method according to claim 24 and any one of claims 25 to 26, wherein the duration of the window for monitoring timing events is adjusted by selecting one of a plurality of outputs of the tapped delay line corresponding to a desired delay. [28] A method according to any one of claims 24 to 27, wherein the combination of the clock signal and the delayed clock signal comprises a NOR operation. [29] A method according to any one of claims 22 to 24, further comprising: Delaying the clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates the duration of the time event monitoring window and the position of the time event monitoring window with respect to the respective edge of the clock signal [30] The method of claim 29 further comprising: Setting a duty cycle of the delayed clock signal to adjust the duration of the time event monitoring window. [31] A method according to claim 29 or claim 30, further comprising: Adjust the delay of the delayed clock signal to set the position of the timing event monitoring window with respect to the respective edge of the clock signal. [32] The method of claim 24 and any one of claims 27 to 31, wherein the time event monitoring window clock signal is generated based on a time-to-digital converter configured to convert the multiple outputs of the tapped delay line into a digital value in response to enabling the calibration of the time event monitoring window clock generator circuit, the method further comprising: Determining a current clock cycle length of the clock signal based on the digital value; and reselecting one of the plurality of outputs of the tapped delay line based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal. [33] The method of claim 32, wherein the time-to-digital converter comprises a capture register configured to capture the plurality of outputs of the tapped delay line, the method further comprising: Determining the current clock cycle length of the clock signal based on the detected plurality of outputs of the tapped delay line. [34] Method according to one of claims 21 to 33, wherein at least a part of the time event monitoring window lies before the respective edge of the clock signal. [35] The method of claim 34, wherein the time event monitoring window is located before the respective edge of the clock signal and wherein the time event monitoring window ends with the respective edge of the clock signal. [36] The method of claim 35, wherein a second window for monitoring timing events is located after the respective edge of the clock signal. [37] The method of claim 34, wherein a portion of the window for monitoring timing events is located after the respective edge of the clock signal. [38] The method of any one of claims 21 to 37, wherein the microelectronic circuit comprises a plurality of processing paths comprising logic units and register circuits, the register circuits being configured to temporarily store output values ​​of the logic units synchronously with the clock signal, the method further comprising: Simulating the operation of a critical path of the plurality of processing paths by a replica path, wherein the replica path comprises a one-bit counter with feedback via a delay line matched to the critical path, and wherein the associated register circuit comprises the one-bit counter.

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