DISPLAY BOARD AND DISPLAY DEVICE

Abstract

Display panel and display device, wherein the display panel comprises a pixel driver circuit, the pixel driver circuit comprising a transistor, and wherein the display panel further comprises: a base substrate (90), a first active layer, and a shielding layer; the first active layer is located on one side of the base substrate (90), and at least a portion of the structure of the first active layer is configured to form a channel region of the transistor; the shielding layer is located between the base substrate (90) and the first active layer, and the shielding layer is a conductive layer; the shielding layer comprises more than one shielding portion, which is independently arranged, and at least partially different shielding portions are configured to receive different signals. The display panel has a high degree of integration.

Description

FIELD OF TECHNOLOGY

[0001] The present disclosure relates to the field of display technology and, more particularly, to a display panel and a display device. BACKGROUND

[0002] In the related art, circuit structures such as a pixel driving circuit, a gate driving circuit, and a detecting circuit must be integrated into the display panel, so that the display panel requires a relatively large layout space for arranging the above-mentioned circuit structures.

[0003] It should be noted that the information disclosed in the background section above is intended only to enhance the understanding of the background of the present disclosure and may contain information that does not constitute prior art known to those skilled in the art. SUMMARY

[0004] According to one aspect of the present disclosure, a display panel is provided, the display panel comprising a pixel driver circuit, the pixel driver circuit comprising a transistor, and the display panel further comprising a base substrate, a first active layer, and a shielding layer; the first active layer is located on one side of the base substrate, and at least a portion of the structure of the first active layer is configured to form a channel region of the transistor; the shielding layer is located between the base substrate and the first active layer, the shielding layer is a conductive layer, the shielding layer comprises more than one shielding portion arranged independently, and at least partially different shielding portions are configured to receive different signals.

[0005] In an exemplary embodiment of the present disclosure, the pixel driver circuit includes a driver transistor and a first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driver transistor; and the first initial signal line is included in the more than one shielding part.

[0006] In an exemplary embodiment of the present disclosure, the first active layer comprises a first active portion and a third active sub-portion; the first active portion is configured to form a channel region of the first transistor, the first active portion comprises a first active sub-portion and a second active sub-portion, and the third active sub-portion is connected between the first active sub-portion and the second active sub-portion; the first initial signal line comprises a first extension portion, and an orthographic projection of the first extension portion on the base substrate at least partially overlaps with an orthographic projection of the third active sub-portion on the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the display panel further comprises a first conductive layer located on a side of the first active layer facing away from the base substrate; the first conductive layer comprises a first reset signal line; an orthographic projection of the first reset signal line on the base substrate extends along a first direction and covers an orthographic projection of the first active part on the base substrate, and a part of the structure of the first reset signal line is configured to form a gate of the first transistor; the first initial signal line comprises a second extension part, and an orthographic projection of the second extension part on the base substrate at least partially overlaps with an orthographic projection of the first reset signal line on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the display panel further comprises a fourth conductive layer located on a side of the first active layer facing away from the base substrate, the fourth conductive layer comprising a first initial connection line; wherein an orthographic projection of the first initial signal line on the base substrate extends along a first direction and an orthographic projection of the first initial connection line on the base substrate extends along a second direction, the first direction intersects the second direction, and the first initial connection line is connected to the first initial signal line intersecting the orthographic projection of the first initial connection line on the base substrate through a through-hole.

[0009] In an exemplary embodiment of the present disclosure, the display panel further comprises a light-emitting unit, the pixel driving circuit includes a seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light-emitting unit; the second initial signal line is included in the more than one shielding part.

[0010] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a driver transistor and a sixth transistor, a first electrode of the sixth transistor is connected to a second electrode of the driver transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit; the first active layer comprises a sixth active part and a seventh active part, the sixth active part is configured to form a channel region of the sixth transistor, and the seventh active part is configured to form a channel region of the seventh transistor; the display panel further comprises a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate, and the first conductive layer comprises an enable signal line and a second reset signal line;an orthographic projection of the enable signal line on the base substrate extends along a first direction and covers an orthographic projection of the sixth active part on the base substrate, and a part of the structure of the enable signal line is configured to form a gate of the sixth transistor; an orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the seventh active part on the base substrate, and a part of the structure of the second reset signal line is configured to form a gate of the seventh transistor; wherein an orthographic projection of the second initial signal line on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the display panel further comprises a fourth conductive layer located on a side of the first active layer facing away from the base substrate; the fourth conductive layer comprises a second initial connection line; wherein an orthographic projection of the second initial signal line on the base substrate extends along a first direction and an orthographic projection of the second initial connection line on the base substrate extends along a second direction, the first direction intersects the second direction, and the second initial connection line is connected to the second initial signal line, which intersects the orthographic projection of the second initial connection line on the base substrate, through a through-hole.

[0012] In an exemplary embodiment of the present disclosure, the pixel driver circuit includes a driver transistor, the first active layer includes a third active portion, and the third active portion is configured to form a channel region of the driver transistor; a first shield portion is included in the more than one shield portion, the first shield portion is connected to a stable voltage source, and an orthographic projection of the first shield portion on the base substrate covers an orthographic projection of the third active portion on the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a capacitor, wherein a first electrode of the capacitor is connected to a gate of the driver transistor and a second electrode of the capacitor is connected to a power supply line; the display panel further comprises a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is configured to form the gate of the driver transistor and the first electrode of the capacitor;the power supply line forms the stable voltage source and the first shielding part is configured to form the second electrode of the capacitor.;

[0014] In an exemplary embodiment of the present disclosure, the display panel further comprises a fourth conductive layer located on a side of the first conductive layer facing away from the base substrate; the fourth conductive layer comprises the power supply line, and an orthographic projection of the power supply line on the base substrate extends along a second direction; the display panel comprises more than one pixel driving circuit distributed in an array in a first direction and the second direction, the first direction intersecting with the second direction, and the more than one first shielding part distributed in the first direction are connected to each other, and the power supply line is connected to the first shielding part through a through hole.

[0015] In an exemplary embodiment of the present disclosure, the power supply line includes a third extension part, a fourth extension part, and a fifth extension part connected between the third extension part and the fourth extension part; a size of an orthographic projection of the fifth extension part on the base substrate in the first direction is larger than a size of an orthographic projection of the third extension part on the base substrate in the first direction, the size of the orthographic projection of the fifth extension part on the base substrate in the first direction is larger than a size of an orthographic projection of the fourth extension part on the base substrate in the first direction, and the first direction intersects with the second direction;the orthographic projection of the fifth extension part on the base substrate at least partially overlaps with an orthographic projection of the first conductive part on the base substrate, and at least a part of the structure of the fifth extension part is configured to form a second electrode of the capacitor;

[0016] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor; the first active layer further comprises a second active portion and a sixth active sub-portion, wherein the second active portion is configured to form a channel region of the second transistor, the second active portion comprises a fourth active sub-portion and a fifth active sub-portion, and the sixth active sub-portion is connected between the fourth active sub-portion and the fifth active sub-portion;the shielding layer further comprises a second shielding part connected to the first shielding part, the first shielding part comprises a first edge, the second shielding part comprises a second edge, the first edge is connected to the second edge, an angle between an orthographic projection of the first edge on the base substrate and an orthographic projection of the second edge on the base substrate is less than 180°, and an orthographic projection of the second shielding part on the base substrate at least partially overlaps with an orthographic projection of the sixth active sub-part on the base substrate;

[0017] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a first initial signal line and a second electrode of the first transistor is connected to a gate of the driver transistor, a first electrode of the second transistor is connected to the gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor;the first active layer further comprises a first active part, a second active part, and an eighth active part, wherein the first active part is configured to form a channel region of the first transistor, the second active part is configured to form a channel region of the second transistor, and the eighth active part is connected between the first active part and the second active part;the shielding layer further comprises a third shielding part, the third shielding part is connected to the first shielding part, the first shielding part comprises a first edge, the third shielding part comprises a third edge, the first edge is connected to the third edge, an angle between an orthographic projection of the first edge on the base substrate and an orthographic projection of the third edge on the base substrate is less than 180°, and an orthographic projection of the third shielding part on the base substrate at least partially overlaps with an orthographic projection of the eighth active part on the base substrate;

[0018] In an exemplary embodiment of the present disclosure, the pixel driver circuit further comprises a first transistor and a second transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driver transistor, a first electrode of the second transistor is connected to the gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor;the first active layer further comprises a first active part, a second active part, a sixth active sub-part, and an eighth active part, the first active part is configured to form a channel region of the first transistor, the second active part is configured to form a channel region of the second transistor, the second active part comprises a fourth active sub-part and a fifth active sub-part, the sixth active sub-part is connected between the fourth active sub-part and the fifth active sub-part, and the eighth active part is connected between the first active part and the second active part;the display panel further comprises a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer comprises a first conductive part and a first gate line, an orthographic projection of the first conductive part on the base substrate covers an orthographic projection of the third active part on the base substrate, and an orthographic projection of the first gate line on the base substrate extends along a first direction and covers an orthographic projection of the second active part on the base substrate;the shielding layer further comprises a second shielding part, a third shielding part, and a first connecting part, the second shielding part is connected to the first shielding part, and an orthographic projection of the second shielding part on the base substrate at least partially overlaps with an orthographic projection of the sixth active sub-part on the base substrate; the third shielding part is connected to the first shielding part, and an orthographic projection of the third shielding part on the base substrate at least partially overlaps with an orthographic projection of the eighth active part on the base substrate;the first connection part is connected between the second shielding part and the third shielding part in adjacent pixel driver circuits in the first direction, and an orthographic projection of the first connection part on the base substrate is located on a side of an orthographic projection of the first gate line on the base substrate away from an orthographic projection of the first conductive part on the base substrate.;

[0019] In an exemplary embodiment of the present disclosure, the display panel further comprises a display area and a frame area around the display area, wherein a part of the shielding part is located in the display area and a part of the shielding part is located in the frame area.

[0020] In an exemplary embodiment of the present disclosure, the pixel driver circuit includes more than one transistor, and a constant-voltage shielding part corresponding to the transistor is included in the more than one shielding part, and an orthographic projection of the constant-voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the transistor corresponding to the constant-voltage shielding part on the base substrate; at least partially different constant-voltage shielding parts are configured to receive different power supply voltages.

[0021] In an exemplary embodiment of the present disclosure, the pixel driver circuit includes an N-type transistor and a P-type transistor; a positive voltage shielding part and a negative voltage shielding part are included in the more than one constant voltage shielding part, the positive voltage shielding part is configured to receive a positive power supply voltage, and the negative voltage shielding part is configured to receive a negative power supply voltage; an orthographic projection of the positive voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the P-type transistor on the base substrate, and an orthographic projection of the negative voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the N-type transistor on the base substrate.

[0022] In an exemplary embodiment of the present disclosure, the display panel further comprises a light-emitting unit, wherein the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor; a first electrode of the fifth transistor is connected to a first power supply end, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;a first electrode of the fifth transistor is connected to a first power supply side, and a second electrode of the fifth transistor is connected to the first electrode of the driver transistor; a first electrode of the sixth transistor is connected to a second electrode of the driver transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit; more than one positive voltage shielding part in which more than one constant-voltage shielding part is included, and the more than one positive voltage shielding part comprises a first positive voltage shielding part, a second positive voltage shielding part, and a third positive voltage shielding part; an orthographic projection of the first positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the driver transistor on the base substrate;An orthographic projection of the second positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the fifth transistor on the base substrate and an orthographic projection of a channel region of the sixth transistor on the base substrate; An orthographic projection of the third positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the fourth transistor on the base substrate and an orthographic projection of a channel region of the seventh transistor on the base substrate;wherein a positive voltage received by the first positive voltage shielding part is greater than a positive voltage received by the second positive voltage shielding part, and a positive voltage received by the third positive voltage shielding part is greater than a positive voltage received by the first positive voltage shielding part;

[0023] In an exemplary embodiment of the present disclosure, the display panel includes a high-density integration region and a low-density integration region, and a density of transistors in the high-density integration region is greater than a density of transistors in the low-density integration region; the high-density integration region includes a first high-density integration region and a second high-density integration region, and the second high-density integration region is located on a side of the first high-density integration region opposite to the low-density integration region;in constant-voltage shielding parts corresponding to a same transistor in the pixel driving circuit, an absolute value of the voltage received by a constant-voltage shielding part located in the first high-density integration region is greater than an absolute value of the voltage received by a constant-voltage shielding part located in the second high-density integration region;

[0024] According to one aspect of the present disclosure, a display device is provided including the above-mentioned display panel.

[0025] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are incorporated into the specification and illustrate embodiments consistent with the present disclosure and are used in conjunction with the specification to explain the principles of the present disclosure. Of course, the accompanying drawings in the following description are only some of the embodiments of the present disclosure, and other drawings may be obtained from these drawings by a person of ordinary skill in the art without creative effort. Fig. 1 is a schematic diagram of a circuit structure of a pixel driver circuit in a display panel according to an exemplary embodiment of the present disclosure; Fig. 2 is a timing diagram of signals at each node in a driving method for the Fig. 1 shows the pixel driver circuit; Fig. 3 is a structural layout of a display panel according to an exemplary embodiment of the present disclosure; Fig. 4 is the structural layout of the shielding layer in Fig. 3; Fig. 5 is a structural layout of the first active layer in Fig. 3; Fig. 6 is a structural layout of the first conductive layer in Fig. 3; Fig. 7 is a structural layout of the fourth conductive layer in Fig. 3; Fig. 8 is a structural layout of the fifth conductive layer in Fig. 3; Fig. 9 is a structural layout of the shielding layer and the first active layer in Fig. 3; Fig. 10 is a structural layout of the shielding layer, the first active layer and the first conductive layer in Fig. 3; Fig. 11 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 3; Fig. 12 is a partial cross-sectional view of the display panel along the Fig. 3 dashed line AA; Fig. 13 is a structural layout of a display panel according to another exemplary embodiment of the present disclosure; Fig. 14 is a structural layout of the shielding layer in Fig. 13; Fig. 15 is a structural layout of the barrier layer and the first active layer in Fig. 13; Fig. 16 is a structural layout of a display panel according to another exemplary embodiment of the present disclosure; Fig. 17 is a structural layout of the fourth conductive layer in Fig. 16; Fig. 18 is a structural layout of the fifth conductive layer in Fig. 16; Fig. 19 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 16; Fig. 20 is a structural layout of a display panel according to another exemplary embodiment of the present disclosure; Fig. 21 is a structural layout of the shielding layer in Fig. 20; Fig. 22 is a structural layout of the fourth conductive layer in Fig. 20; Fig. 23 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 20; Fig. 24 is a structural layout of a display panel according to another exemplary embodiment of the present disclosure; Fig. 25 is a structural layout of the fourth conductive layer in Fig. 24; Fig. 26 is a structural layout of the fifth conductive layer in Fig. 24; Fig. 27 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 24; Fig. 28 is a schematic structural diagram of a display panel according to another exemplary embodiment of the present disclosure; Fig. 29 is a schematic diagram of a circuit structure of a pixel driving circuit in a display panel according to another exemplary embodiment of the present disclosure; Fig. 30 is a timing chart of each node in a driving process of the pixel driving circuit in Fig. 29; Fig. 31 is a structural layout of a display panel according to another exemplary embodiment of the present disclosure; Fig. 32 is a structural layout of the shielding layer in Fig. 31; Fig. 33 is a structural layout of the first active layer in Fig. 31; Fig. 34 is a structural layout of the first conductive layer in Fig. 31; Fig. 35 is a structural layout of the second conductive layer in Fig. 31; Fig. 36 is a structural layout of the second active layer in Fig. 31; Fig. 37 is a structural layout of the third conductive layer in Fig. 31; Fig. 38 is a structural layout of the fourth conductive layer in Fig. 31; Fig. 39 is a structural layout of the fifth conductive layer in Fig. 27; Fig. 40 is a structural layout of the shielding layer and the first active layer in Fig. 31; Fig. 41 is a structural layout of the shielding layer, the first active layer and the first conductive layer in Fig. 31; Fig. 42 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the second conductive layer in Fig. 31; Fig. 43 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer and the second active layer in Fig. 31; Fig. 44 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer and the third conductive layer in Fig. 31; Fig. 45 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer and the fourth conductive layer in Fig. 31; Fig. 46 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in Fig. 31; Fig. 47 is a partial cross-sectional view taken along the dashed line BB in Fig. 31; Fig. 48 is a schematic structural diagram of a display panel according to another example of the present disclosure. DETAILED DESCRIPTION

[0027] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. However, exemplary embodiments may be implemented in various forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings designate the same or similar structures, and detailed descriptions thereof will be omitted.

[0028] The terms "a," "an," and "said" are used to indicate the presence of one or more elements / components / etc. The terms "include" and "have" are used to express the meaning of open inclusion and refer to the presence of other elements / components / etc. in addition to those listed.

[0029] As in Fig. 1 is a schematic diagram of the circuit structure of a pixel driver circuit in a display panel according to an exemplary embodiment of the present disclosure. The pixel driver circuit may include a first transistor T1, a second transistor T2, a driver transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the first transistor T1 is connected to the first initial signal end Vinit1, the second electrode is connected to the node N, and the gate is connected to the first reset signal end Re1; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driver transistor T3, and the gate is connected to the first gate driver signal end G1;the gate of the driver transistor T3 is connected to the node N; the first electrode of the fourth transistor T4 is connected to the data signal end Da, the second electrode is connected to the first electrode of the driver transistor T3, and the gate is connected to the first gate drive signal end G1; the first electrode of the fifth transistor T5 is connected to the first power supply end VDD, the second electrode is connected to the first electrode of the driver transistor T3, and the gate is connected to the enable signal end EM; the first electrode of the sixth transistor T6 is connected to the second electrode of the driver transistor T3, and the gate is connected to the enable signal end EM;The first electrode of the seventh transistor T7 is connected to the second initial signal end Vinit2, the second electrode is connected to the second electrode of the six transistors T6, and the gate is connected to the second reset signal end Re2. The capacitor C is connected between the gate of the driver transistor T3 and the first power supply end VDD. The pixel driver circuit can be connected to a light-emitting unit OLED, and the pixel driver circuit is configured to drive the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply end VSS. The first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.

[0030] As in Fig. 2 is a timing diagram of the signals at each node in a driving process for the Fig. 1. Among them, G1 represents the timing chart of the signal at the first gate drive signal end G1, Re1 represents the timing chart of the signal at the first reset signal end Re1, Re2 represents the timing chart of the signal at the second reset signal end Re2, EM represents the timing chart of the signal at the enable signal end EM, and Da represents the timing chart of the signal at the data signal end Da. The driving method for the pixel drive circuit may include a reset phase t1, a compensation phase t2, and a light emission phase t3. In the reset phase t1, the first reset signal end Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal end Vinit1 outputs a first initial signal to the node N.In the compensation phase t2, the second reset signal end Re2 and the first gate drive signal end G1 output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and the data signal end Da outputs a data signal to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the drive transistor T3. The second initial signal end Vini2 inputs the second initial signal to the second electrode of the sixth transistor T6. In the light-emitting phase t3, the enable signal end EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth of the node N. According to the formula for the output current of the driver transistor: I=(µWCox / 2L)(Vgs-Vth). 2, where µ is the charge carrier mobility, Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driver circuit of the present disclosure is I=(µWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driver circuit can avoid the influence of the threshold value of the driver transistor on its output current. It should be understood that in other exemplary embodiments, there may also be other driving methods for the pixel driver circuit; for example, both the first transistor T1 and the seventh transistor T7 may be turned on during the reset phase.

[0031] A display panel according to the exemplary embodiments is further provided, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially, wherein an insulating layer may be provided between the above-mentioned adjacent layers. As shown in Fig. 3 to Fig. 11 is shown Fig. 3 shows a structural layout of a display panel according to an exemplary embodiment of the present disclosure, Fig. 4 is a structural layout of the shielding layer in Fig. 3, Fig. 5 is a structural layout of the first active layer in Fig. 3, Fig. 6 is a structural layout of the first conductive layer in Fig. 3, Fig. 7 is a structural layout of the fourth conductive layer in Fig. 3, Fig. 8 is a structural layout of the fifth conductive layer in Fig. 3, Fig. 9 is a structural layout of the shielding layer and the first active layer in Fig. 3, Fig. 10 is a structural layout of the shielding layer, the first active layer and the first conductive layer in Fig. 3, and Fig. 11 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 3. The scoreboard can have more than one Fig. 1 shown pixel driver circuit.

[0032] As in Fig. 3, Fig. 4 and Fig. 9, the shielding layer may be a conductive layer, and the shielding layer may include more than one first initial signal line Vinit1, one second initial signal line Vinit2, one first shielding part 61, one second shielding part 62, and one third shielding part 63. Among them, both the orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate may extend along the first direction X. The first initial signal line Vinit1 may be used to form the first initial signal end in Fig. 1, and the second initial signal line Vinit2 can be used to provide the second initial signal end in Fig. 1. The first shielding part 61 is connected to the second shielding part 62 and the third shielding part 63, respectively. Furthermore, the first shielding parts 61, which are arranged at intervals in the first direction X, may be connected one after the other. The first shielding part 61 may have a first edge 611, the second shielding part 62 may have a second edge 622, and the third shielding part 63 may have a third edge 633. The first edge 611 is connected to the second edge 622, and the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the second edge 622 on the base substrate may be less than 180°. For example, the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the second edge 622 on the base substrate may be 90°.The first edge 611 is connected to the third edge 633, and the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the third edge 633 on the base substrate may be less than 180°. For example, the angle between the orthographic projection of the first edge 611 on the base substrate and the orthographic projection of the third edge 633 on the base substrate may be 90°.

[0033] As in Fig. 3, Fig. 5 and Fig. 9, the first active layer may include a first active part 71, a second active part 72, a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, and a seventh active part 77. Among them, the first active part 71 is used to form the channel region of the first transistor T1, the second active part 72 is used to form the channel region of the second transistor T2, the third active part 73 is used to form the channel region of the driver transistor T3, the fourth active part 74 is used to form the channel region of the fourth transistor T4, the fifth active part 75 is used to form the channel region of the fifth transistor T5, the sixth active part 76 is used to form the channel region of the sixth transistor T6, and the seventh active part 77 is used to form the channel region of the seventh transistor T7.The first active portion 71 may include a first active sub-portion 711 and a second active sub-portion 712, and the first active layer further includes a third active sub-portion 713 located between the first active sub-portion 711 and the second active sub-portion 712. The second active portion 72 may include a fourth active sub-portion 724 and a fifth active sub-portion 725, and the first active layer further includes a sixth active sub-portion 726 connected between the fourth active sub-portion 724 and the fifth active sub-portion 725. The first active layer may further include an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, a fourteenth active portion 714, a fifteenth active portion 715, and a sixteenth active portion 716.The eighth active part 78 is connected between the first active part 71 and the second active part 72, the ninth active part 79 is connected to one end of the fifth active part 75 and the third active part 73, the tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77, the sixteenth active part 716 is connected to an end of the fourth active part 74 facing away from the third active part 73, the fourteenth active part 714 is connected to an end of the seventh active part 77 facing away from the sixth active part 76, and the fifteenth active part 715 is connected to an end of the first active part 71 facing away from the second active part 72.The first active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin-film transistors.

[0034] As in Fig. 3, Fig. 6 and Fig. 10, the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive part 11. Among them, the orthographic projection of the first reset signal line Re1 on the base substrate, the orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate may all extend along the first direction X. In the exemplary embodiment, the orthographic projection of a certain structure on the base substrate extending along a certain direction may be understood to mean that the orthographic projection of the structure on the base substrate extends linearly or curvedly along the direction.The orthographic projection of the first reset signal line Re1 on the base substrate may cover the orthographic projection of the first active part 71 on the base substrate, a part of the structure of the first reset signal line Re1 may be used to form the gate of the first transistor T1, and the first reset signal line Re1 may be used to form the first reset signal end in the manner shown in . Fig. 1. The orthographic projection of the second reset signal line Re2 on the base substrate may cover the orthographic projection of the seventh active part 77 on the base substrate, a part of the structure of the second reset signal line Re2 may be used to form the gate of the seventh transistor T7, and the second reset signal line Re2 may be used to form the second reset signal end in the Fig. 1. The orthographic projection of the first gate line G1 on the base substrate may cover the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fourth active portion 74 on the base substrate. Part of the structure of the first gate line G1 may be used to form the gate of the second transistor T2, another part of the structure of the first gate line G1 may be used to form the gate of the fourth transistor T4, and the first gate line G1 may be used to form the first gate drive signal end in the Fig. 1. The orthographic projection of the enable signal line EM on the base substrate can cover the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate, a part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6, and the enable signal line EM can be used to form the enable signal end in the Fig. 1. The orthographic projection of the first conductive part 11 on the base substrate may cover the orthographic projection of the third active part 73 on the base substrate, and the first conductive part 11 may be used to form the gate of the driver transistor T3 and the first electrode of the capacitor C. Furthermore, the display panel may use the first conductive layer as a mask to perform a wiring treatment on the first active layer, that is, the region in the first active layer covered by the first conductive layer may form the channel region of the transistor, and the region in the first active layer not covered by the first conductive layer forms a wiring pattern.

[0035] In the exemplary embodiment as shown in Fig. 3, Fig. 4, Fig. 6, Fig. 9 and Fig. As shown in Figure 10, the orthographic projection of the first shielding part 61 on the base substrate may overlap with the orthographic projection of the third active part 73 on the base substrate. For example, the orthographic projection of the first shielding part 61 on the base substrate may cover the orthographic projection of the third active part 73 on the base substrate. The first shielding part 61 may be connected to a stable voltage source, for example, the first shielding part 61 may be connected to the first power supply end VDD, the first initial signal end Vinit1, the second initial signal end Vinit2, and the like. Fig. 1. The first shielding part 61 can be used to shield the influence of noise from other signals on the driver transistor T3. When the first shielding part 61 is connected to the first power supply end VDD, the first shielding part 61 can also be used to form the second electrode of the capacitor C. The orthographic projection of the second shielding part 62 on the base substrate at least partially overlaps with the orthographic projection of the sixth active sub-part 726 on the base substrate, and the second shielding part 62 can exert a voltage-stabilizing effect on the sixth active sub-part 726, thereby reducing the leakage current from the sixth active sub-part 726 to the source-drain of the second transistor due to the voltage fluctuation of the sixth active sub-part 726.The orthographic projection of the third shielding part 63 on the base substrate may at least partially overlap with the orthographic projection of the eighth active part 78 on the base substrate, and the third shielding part 63 may exert a voltage-stabilizing effect on the eighth active part 78, so that the voltage fluctuation of the gate of the driver transistor T3 can be reduced. As shown in FIG. Fig. 4, the first initial signal line Vinit1 includes a first extension part Vinit11 and a second extension part Vinit12. The orthographic projection of the first extension part Vinit11 on the base substrate may at least partially overlap with the orthographic projection of the third active sub-part 713 on the base substrate. The first extension part Vinit11 may exert a voltage-stabilizing effect on the third active sub-part 713, thereby reducing the leakage current from the third active sub-part 713 to the source-drain of the first transistor caused by the voltage fluctuation of the third active sub-part 713. The orthographic projection of the second extension part Vinit12 on the base substrate may at least partially overlap with the orthographic projection of the first reset signal line Re1 on the base substrate, thereby improving the transmittance of the display panel.

[0036] As in Fig. 3, Fig. 7 and Fig. 11, the fourth conductive layer may include a first initial connection line 4Vinit1, a power supply line VDD, a first bridge part 41, a second bridge part 42, a third bridge part 43, and a fourth bridge part 44. The orthographic projection of the first initial connection line 4Vinit1 on the base substrate and the orthographic projection of the power supply line VDD on the base substrate may both extend along the second direction Y, and the second direction Y may intersect with the first direction X, where the second direction Y may be, for example, a column direction and the first direction X may be a row direction. The first initial connection line 4Vinit1 may be connected to the first initial signal line Vinit1 and the fifteenth active part 715, respectively, through the through-hole H to connect the first initial signal end and the first electrode of the first transistor.The black block in the drawing indicates the position of the through-hole. In the exemplary embodiment, the first initial connection line 4Vinit1 and the first initial signal line Vinit1 may form a lattice structure, and the lattice structure may reduce the voltage difference between the first initial signal ends at different positions of the display panel. The power supply line VDD may provide the first power supply end, and the power supply line VDD may be connected to the first shield part 61 and the ninth active part 79 through the through-hole, respectively, to connect the second electrode of the capacitor, the first power supply end, and the first electrode of the fifth transistor. As shown in FIG. Fig. 3, Fig. 7 and Fig. 11, the power supply line VDD may include a third extension part VDD3, a fourth extension part VDD4, and a fifth extension part VDD5, and the fifth extension part VDD5 is connected between the third extension part VDD3 and the fourth extension part VDD4, the size of the orthographic projection of the fifth extension part VDD5 on the base substrate in the first direction X is larger than the size of the orthographic projection of the third extension part VDD3 on the base substrate in the first direction X, and the size of the orthographic projection of the fifth extension part VDD5 on the base substrate in the first direction X is larger than the size of the orthographic projection of the fourth extension part VDD4 on the base substrate in the first direction X.The orthographic projection of the fifth extension part VDD5 on the base substrate may also at least partially overlap with the orthographic projection of the first conductive part 11 on the base substrate, and the fifth extension part VDD5 may also be used to form the second electrode of the capacitor C. The area of ​​the orthographic projection of the first conductive part 11 on the base substrate is S1, and the overlap area of ​​the orthographic projection of the first conductive part 11 on the base substrate and the orthographic projection of the fifth extension part VDD5 on the base substrate is S2. S2 / S1 may be greater than or equal to 60%, for example, S2 / S1 may be equal to 60%, 70%, 80%, 90%, or 100%, etc.The power supply line VDD and the first shielding part 61 may also form a grid structure that can reduce the voltage difference between the first power supply ends at different positions of the display panel.

[0037] As in Fig. 3, Fig. 7 and Fig. As shown in Figure 11, the first bridge part 41 can be connected to the second initial signal line Vinit2 and the fourteenth active part 714 via the through-hole to connect the first electrode of the seventh transistor and the second initial signal end. The second bridge part 42 can be connected to the tenth active part 710 via a through-hole to connect the second electrode of the sixth transistor and the second electrode of the seventh transistor. The third bridge part 43 can be connected to the sixteenth active part 716 via a through-hole to connect the first electrode of the fourth transistor. The fourth bridge part 44 can be connected to the eighth active part 78 and the first conductive part 11 via through-holes to connect the first electrode of the second transistor T2, the second electrode of the first transistor T1, and the gate of the driver transistor T3.

[0038] As in Fig. 3 and Fig. 8, the fifth conductive layer may include a fifth bridge part 55 and a data line Da. The data line Da may be used to connect the data signal ends in Fig. 1. The fifth bridge part 55 can be connected to the second bridge part 42 through a through-hole to connect the second electrode of the sixth transistor. The fifth bridge part 55 can also be connected to the first electrode of the light-emitting unit. The orthographic projection of the data line Da on the base substrate can extend along the second direction Y, and the data line Da can be connected to the third bridge part 43 through a through-hole to connect the first electrode of the fourth transistor and the data signal end.

[0039] It should be noted that, as in Fig. 3 and Fig. As shown in Figure 11, the black blocks drawn on the side of the fourth conductive layer facing away from the base substrate indicate the through-holes through which the fourth conductive layer is connected to other layers facing the base substrate side. The black blocks drawn on the side of the fifth conductive layer facing away from the base substrate indicate the through-holes through which the fifth conductive layer is connected to other layers facing the base substrate side. The black blocks drawn on the side of the electrode layer facing away from the base substrate indicate the through-holes through which the electrode layer is connected to other layers facing the base substrate side.The black block only indicates the position of the through-hole, and different through-holes represented by black blocks at different positions can pass through different insulation layers.

[0040] As in Fig. 12 is a partial cross-sectional view of the display panel along the Fig. 3 dashed line AA. The display panel may further include a buffer layer 91, an insulating layer 92, a dielectric layer 93, a passivation layer 94, and a first flat layer 95. Among them, the base substrate, the shielding layer, the buffer layer 91, the first active layer, the insulating layer 92, the first conductive layer, the dielectric layer 93, the fourth conductive layer, the passivation layer 94, the first flat layer 95, and the fifth conductive layer are sequentially stacked. The buffer layer 91 may include a silicon oxide layer and a silicon nitride layer. The insulating layer 92 may be a single-layer structure or a multi-layer structure, and the material of the insulating layer 92 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The dielectric layer 93 may be a silicon nitride layer. The passivation layer 94 may be a silicon oxide layer.The material of the first flat layer 95 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), and other materials. The base substrate 90 may consist of a glass substrate, a barrier layer, and a polyimide layer stacked one after the other, and the barrier layer may be made of an inorganic material. The material of the first conductive layer may be made of an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum / titanium alloy or laminate. The material of the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum / titanium alloy or laminate, or it may be a titanium / aluminum / titanium laminate.The display panel may further comprise a second flat layer, an electrode layer, and a pixel definition layer, wherein the second flat layer is disposed on the side of the fifth conductive layer remote from the base substrate, the electrode layer is disposed on the side of the second flat layer remote from the base substrate, and the pixel definition layer is disposed on the side of the electrode layer remote from the base substrate.

[0041] It should be noted that the scale of the drawings in the present disclosure can be used as a reference for the actual process, but is not limited thereto. For example, the width-to-length ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of subpixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural diagrams. Furthermore, the first, second, and other qualifiers are only used to define various structural names and do not have a meaning of a particular order.

[0042] As in Fig. 13 to Fig. 15 is shown Fig. 13 shows a structural layout of a display panel according to another exemplary embodiment of the present disclosure, Fig. 14 is a structural layout of the shielding layer in Fig. 13, and Fig. 15 is a structural layout of the barrier layer and the first active layer in Fig. 13.

[0043] As in Fig. 14 and Fig. 15, the first active layer may further include a seventeenth active portion 717. The seventeenth active portion 717 is connected between the second active portion 72 and the sixth active portion 76, and the orthographic projection of the seventeenth active portion 717 on the base substrate extends along the second direction Y, wherein the seventeenth active portion 717 is an equipotential point of the second electrode of the driver transistor. The difference between the Fig. 13 and the scoreboard shown in Fig. 3 is that in the display panel shown in Fig. 13, a break D1 is present between the adjacent first shielding parts 61 in the first direction X, i.e., adjacent first shielding parts 61 in the first direction X are not directly connected. The orthographic projection of the break D1 on the base substrate intersects with the orthographic projection of the seventeenth active part 717 on the base substrate. This arrangement can reduce the parasitic capacitance between the seventeenth active part 717 and the shielding layer, thereby improving the problem of residual images on the display panel. As shown in Fig. 14, the shielding layer includes a first connection part 64, and the first connection part 64 is connected between the third shielding part 63 and the second shielding part 62 in adjacent pixel driver circuits in the same row. The orthographic projection of the first connection part 64 on the base substrate may be located on a side of the orthographic projection of the first gate line G1 on the base substrate that is opposite to the orthographic projection of the first conductive part 11 on the base substrate. That is, the orthographic projection of the first connection part 64 on the base substrate does not overlap with the orthographic projection of the seventeenth active part 717 on the base substrate. In the exemplary embodiment, two first shielding parts 61 adjacent in the first direction X may be connected by the first connection part 64. Furthermore, other structures of the type shown in Fig. 14 shall be the same as that shown in Fig. 3 shown scoreboard.

[0044] As in Fig. 16 to Fig. 19 is shown Fig. 16 shows a structural layout of a display panel according to another exemplary embodiment of the present disclosure, Fig. 17 is a structural layout of the fourth conductive layer in Fig. 16, and Fig. 18 is a structural layout of the fifth conductive layer in Fig. 16, Fig. 19 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 16.

[0045] The difference between the Fig. 16 and the scoreboard shown in Fig. 3 is that in the display panel shown in Fig. 16, the fifth conductive layer may further include a second initial connection line 5Vinit2. The orthographic projection of the second initial connection line 5Vinit2 on the base substrate may extend along the second direction Y. The second initial connection line 5Vinit2 may be connected to the first bridge part 41 through a through-hole to connect the second initial signal line Vinit2. The second initial connection line 5Vinit2 and the second initial signal line Vinit2 may form a grid structure, and the grid structure may reduce the voltage difference between the second initial signal ends at different positions of the display panel. Other structures of the Fig. 16 may be the same as those shown in Fig. 3 shown scoreboard.

[0046] As in Fig. 20 to Fig. 23 shown, is Fig. 20 shows a structural layout of a display panel according to another exemplary embodiment of the present disclosure, Fig. 21 is a structural layout of a shielding layer in Fig. 20, Fig. 22 is a structural layout of a fourth conductive layer in Fig. 20, and Fig. 23 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 20.

[0047] The difference between the Fig. 20 and the scoreboard shown in Fig. 3 is that in the display panel shown in Fig. 20, the fourth conductive layer further comprises a second initial connection line 4Vinit2. A first initial connection line 4Vinit1 and a second initial connection line 4Vinit2 may be provided thereunder, corresponding to two adjacent columns of pixel driver circuits. The fourth conductive layer may further include a sixth bridge part 46. The first initial connection line 4Vinit1 may be connected to the first initial signal line Vinit1 through a through-hole via the sixth bridge part 46, and the second initial connection line 4Vinit2 may be connected to the second initial signal line Vinit2 through a through-hole via the first bridge part 41. Other structures of the display panel shown in Fig. 20 may be the same as those shown in Fig. 3 shown scoreboard.

[0048] As in Fig. 24 to Fig. 27 is shown Fig. 24 shows a structural layout of a display panel according to another exemplary embodiment of the present disclosure, Fig. 25 is a structural layout of the fourth conductive layer in Fig. 24, Fig. 26 is a fifth conductive layer in Fig. 25, and Fig. 27 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the fourth conductive layer in Fig. 24.

[0049] The difference between the Fig. 24 and the scoreboard shown in Fig. 3 is that in the display panel shown in Fig. 24, the fourth conductive layer is not provided with a power supply line VDD, but the fourth conductive layer is provided with a seventh bridge part 47 which connects the first shielding part 61 through a through hole. In the display panel shown in Fig. In the display panel shown in Figure 24, a power supply line VDD and a second initial connection line 5Vinit2 are added to the fifth conductive layer. The power supply line VDD is connected to the seventh bridge part 47 via the through-hole to connect the second electrode of the capacitor. The orthographic projection of the power supply line VDD on the base substrate can further cover the orthographic projection of the fourth bridge part 44 on the base substrate, and the power supply line VDD can shield the noise interference of other signals on the fourth bridge part 44, thereby reducing the voltage fluctuation at the gate of the driver transistor T3. The second initial connection line 5Vinit2 is connected to the first bridge part 41 via a through-hole, so that the second initial connection line 5Vinit2 and the second initial signal line Vinit2 can form a lattice structure.The grid structure can reduce the voltage difference between the second initial signal ends at different positions on the display panel. Other structures of the type described in . Fig. 24 may be the same as those shown in Fig. 3 shown scoreboard.

[0050] In the exemplary embodiment, the shield layer is used to form part of the signal lines and device patterns in the display panel, thereby improving the integration of the display panel. Furthermore, since the second electrode of the capacitor is formed by the first shield part 61 and the fifth extension part VDD5, the display panel does not need to be provided with a second gate layer compared to the display panel in the related art. In the display panel, the second shield part 62 and the third shield part 63 are directly connected to the first shield part 61, and the second shield part 62 and the third shield part 63 are connected to the power supply lines without the need for via holes, thereby reducing the number of via holes.It should be understood that the shielding layer may also include other independently arranged shielding parts, and the shielding parts may also be used to form other signal lines and device structures.

[0051] In the related art, the PI (polyimide) layer in the base substrate tends to generate a negative electrostatic field, and the negative electrostatic field leads to a positive shift in the threshold of the transistor. For example, the negative electrostatic field can easily lead to a positive shift in the threshold of the driver transistor, and the positive shift in the threshold of the driver transistor leads to undesirable phenomena such as the greening of the copper bar test of the display panel. The above-mentioned first shielding part 61 can shield the influence of the above-mentioned negative electrostatic field on the threshold of the driver transistor T3. Moreover, the shielding layer can be a light-shielding structure, and the shielding layer can avoid the influence of light on the characteristics of the transistor.

[0052] In the prior art, the positive shift in the threshold of the driver transistor T3 leads to an increase in the driver current at the same gray scale, which easily results in a greenish display on the display panel. In the exemplary embodiment, the above-mentioned first shielding part 61 can receive a positive power supply voltage, and the positive electric field generated by the first shielding part 61 causes the threshold of the driver transistor to shift negatively, thereby reducing the risk of the display panel turning green.

[0053] It should be understood that in other exemplary embodiments, the threshold voltages of other transistors in the pixel driver circuit also exhibit threshold shifts, leading to problems such as transistor leakage current. Fig. 1, for example, the leakage current of the first transistor T1 and the second transistor T2 may cause defects such as flickering of the display panel, and the leakage current of the sixth transistor T6 may cause defects such as division of the display panel into four screens. In the exemplary embodiment, the shielding layer may further include other shielding parts, and the orthographic projections of the other shielding parts on the base substrate may each cover at least part of the patterns of the orthographic projections of the channel regions of other transistors on the base substrate. Other shielding parts may be arranged independently of each other or at least partially connected. Among them, the shielding part is provided independently, and it can be understood that the shielding part is not connected to other shielding parts.

[0054] More than one independently provided shielding part can receive different power supply voltages, and the magnitude of the power supply voltage received by the shielding parts can be influenced by the transistor type. For example, the shielding part below the P-type transistor can receive a positive power supply voltage, and the positive electric field formed by the shielding part can negatively shift the threshold value of the P-type transistor, thereby reducing the turn-off leakage current of the P-type transistor. The shielding part below the N-type transistor can be connected to a negative power supply voltage, and the negative electric field formed by the shielding part can positively shift the threshold value of the N-type transistor, thereby reducing the turn-off leakage current of the N-type transistor. For example, the first transistor and the second transistor can Fig. 1 may be N-type transistors, a shielding part may be provided under the first transistor and the second transistor, and the shielding part under the first transistor and the second transistor may receive a negative power supply voltage.

[0055] Furthermore, the magnitude of the power supply voltage received by the shielding part can be determined by the operating state of the transistor. For example, in the exemplary embodiment, since the fourth transistor T4 and the seventh transistor T7 are in the positive-shift state for a long time, the fifth transistor T5 and the sixth transistor T6 are in the negative-shift state for a long time, and the positive voltage received by the shielding part under the fourth transistor T4 and the seventh transistor T7 can be greater than the positive voltage received by the shielding part under the fifth transistor T5 and the sixth transistor T6.For example, the voltage received by the shielding part below the fourth transistor T4 and the seventh transistor T7 may be 6.6 V, and the voltage received by the shielding part below the fifth transistor T5 and the sixth transistor T6 may be 2.6 V.

[0056] Furthermore, the magnitude of the power supply voltage received by the shielding part can be influenced by the size of the transistor. For example, if the length-to-width ratio of the channel region of the driver transistor is greater than the length-to-width ratio of the channel region of the fifth transistor T5, the voltage received by the shielding part below the driver transistor may be greater than the voltage received by the shielding part below the fifth transistor T5. For example, the voltage received by the shielding part below the driver transistor may be 4.6 V.

[0057] In addition, the magnitude of the power supply voltage received by the shielding part can be affected by the position of the transistor. There are differences in the density of transistors in different areas of the display panel, and the threshold values ​​of transistors near low-density transistor areas tend to shift. Fig. 28 shows a schematic structural diagram of a display panel according to another exemplary embodiment of the present disclosure. The display panel may include a high-density integration region H and a low-density integration region L, wherein the density of transistors in the high-density integration region H is greater than the density of transistors in the low-density integration region L. The high-density integration region includes a first high-density integration region H1 and a second high-density integration region H2. The second high-density integration region H2 is located on a side of the first high-density integration region H1 facing away from the low-density integration region L.In the shielding part corresponding to the same transistor in the pixel driving circuit, the absolute value of the voltage received by the shielding part in the first high-density integration region H1 is larger than the absolute value of the voltage received by the shielding part in the second high-density integration region H2. For example, in the shielding part corresponding to the driving transistor in the pixel driving circuit, the positive power supply voltage to be received by the shielding part corresponding to the driving transistor in the first high-density integration region H1 is larger than the positive power supply voltage to be received by the shielding part corresponding to the driving transistor in the second high-density integration region H2. Another example: When the first transistor in . Fig. 1 is an N-type transistor, in the shielding part corresponding to the first transistor in the pixel driving circuit, the negative power supply voltage received by the shielding part corresponding to the first transistor in the first high-density integration region H1 is lower than the positive power supply voltage received by the shielding part corresponding to the first transistor in the second high-density integration region H2.

[0058] In the exemplary embodiment, the low-density integration region L may be a frame region of the display panel, an integration region of the camera under the screen, a light-transmitting region in the display area, and the like. The density of transistors in the low-density integration region L may be zero.

[0059] In the exemplary embodiment, the pixel driver circuit in the display panel may also have other structures. Fig. Figure 29 shows a schematic diagram of a circuit structure of a pixel driver circuit in a display panel according to another exemplary embodiment of the present disclosure. The pixel driver circuit may include: a driver transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The difference from the Fig. 1 is that the first transistor and the second transistor are arranged in the Fig. 29 are N-type transistors.

[0060] As in Fig. 30 is a timing diagram of each node in a driving process for the pixel driving circuit in Fig. 29. Among them, G1 represents the timing of the first gate drive signal end G1, G2 represents the timing of the second gate drive signal end G2, Re1 represents the timing of the first reset signal end Re1, Re2 represents the timing of the second reset signal end Re2, EM represents the timing of the enable signal end EM, and Da represents the timing of the data signal end Da. The driving method for the pixel drive circuit may include a first reset phase t1, a compensation phase t2, a second reset phase t3, and a light emission phase t4. In the first reset phase t1, the first reset signal end Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal end Vinit1 outputs an initial signal to the node N.In the compensation phase t2, the first gate drive signal end G1 outputs a high-level signal, the second gate drive signal end G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal end Da outputs a drive signal to write the voltage Vdata+Vth (ie, the sum of the voltages Vdata and Vth) to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the drive transistor T3. In the second reset phase t3, the second reset signal end Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal end Vinit2 outputs an initial signal to the second electrode of the sixth transistor T6.In the light emission phase t4, the enable signal end EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driver transistor T3 drives the light emission unit under the action of the voltage Vdata+Vth stored in the capacitor C to emit light.

[0061] The formula for the output current of the driver transistor is as follows: I=(μWcox / 2L)(Vgs−Vth)2.

[0062] Where I is the output current of the driver transistor, µ is the charge carrier mobility, Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor and Vth is the threshold voltage of the driver transistor.

[0063] According to the above formula for the output current of the driver transistor, the gate voltage Vdata+Vth and the source voltage Vdd of the driver transistor in the pixel driver circuit of the present disclosure are substituted into the above formula to obtain the output current I of the driver transistor in the pixel driver circuit of the present disclosure, I = (µWCox / 2L) (Vdata+Vth-Vdd-Vth) 2 . The pixel driver circuit can avoid the influence of the threshold value of the driver transistor on its output current.

[0064] A further display panel according to exemplary embodiments is further provided, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer, which are arranged in a sequentially stacked manner. An insulating layer may be arranged between the aforementioned layers. As shown in Fig. 31 to Fig. 46 shown, is Fig. 31 shows a structural layout of a display panel according to another exemplary embodiment of the present disclosure. Fig. 32 is a structural layout of the shielding layer in Fig. 31. Fig. 33 is a structural layout of the first active layer in Fig. 31. Fig. 34 is a structural layout of the first conductive layer in Fig. 31. Fig. 35 is a structural layout of the second conductive layer in Fig. 31. Fig. 36 is a structural layout of the second active layer in Fig. 31. Fig. 37 is a structural layout of the third conductive layer in Fig. 31. Fig. 38 is a structural layout of the fourth conductive layer in Fig. 31. Fig. 39 is a structural layout of the fifth conductive layer in Fig. 27. Fig. 40 is a structural layout of the shielding layer and the first active layer in Fig. 31. Fig. 41 is a structural layout of the shielding layer, the first active layer and the first conductive layer in Fig. 31. Fig. 42 is a structural layout of the shielding layer, the first active layer, the first conductive layer and the second conductive layer in Fig. 31. Fig. 43 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer and the second active layer in Fig. 31. Fig. 44 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer and the third conductive layer in Fig. 31. Fig. 45 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer and the fourth conductive layer in Fig. 31. Fig. 46 is a structural layout of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in Fig. 31. The scoreboard may contain more than one Fig. 29 shown pixel driver circuit. As shown in Fig. As shown in Figure 46, the more than one pixel driver circuit may include a first pixel driver circuit P1 and a second pixel driver circuit P2 arranged side by side in the row direction X, and the first pixel driver circuit P1 and the second pixel driver circuit P2 may be arranged mirror-symmetrically. The first pixel driver circuit P1 and the second pixel driver circuit P2 may form a repeating unit, and the display panel may include more than one repeating unit arranged in an array in the row direction X and the column direction Y.

[0065] As in Fig. 31, Fig. 32 and Fig. 40, the shielding layer may include a positive voltage shielding part BSM1 and a negative voltage shielding part BSM2. The positive voltage shielding part BSM1 is used to receive a positive power supply voltage, and the negative voltage shielding part BSM2 is used to receive a negative power supply voltage. The orthographic projection of the positive voltage shielding part BSM1 on the base substrate and the orthographic projection of the negative voltage shielding part BSM2 on the base substrate may both extend along the column direction Y. Among them, the adjacent negative voltage shielding parts BSM2 in the row direction X may be connected to each other or arranged independently of each other. The adjacent positive voltage shielding parts BSM1 in the row direction X may be connected to each other or arranged independently of each other. The shielding layer may be a conductive structure, e.g., a conductive layer.the shielding layer can be a molybdenum layer.

[0066] As in Fig. 31, Fig. 33, Fig. 40 and Fig. 41, the first active layer may include a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, a seventh active part 77, an eighth active part 78, a ninth active part 79, a tenth active part 710, and an eleventh active part 711.Among them, the third active part 73 can be used to form the channel region of the driver transistor T3; the fourth active part 74 can be used to form the channel region of the fourth transistor T4; the fifth active part 75 can be used to form the channel region of the fifth transistor T5; the sixth active part 76 can be used to form the channel region of the sixth transistor T6; the seventh active part 77 can be used to form the channel region of the seventh transistor T7; the eighth active part 78 is connected to the side of the fifth active part 75 facing away from the third active part 73, and the ninth active part 79 is connected between the eighth active part 78 in the first pixel driver circuit P1 and the eighth active part 78 in the second pixel driver circuit P2.The tenth active part 710 is connected between the sixth active part 76 and the seventh active part 77, and the eleventh active part 711 is connected between the sixth active part 76 and the third active part 73. The eighth active part 78 can be used to form the first electrode of the fifth transistor. In the exemplary embodiment, the eighth active parts in two adjacent pixel driver circuits are connected via the ninth active part 79, so that the voltage difference between the first power supply ends in the adjacent pixel driver circuits can be reduced. As shown in FIG. Fig. 40, the orthographic projection of the positive voltage shielding part BSM1 on the base substrate may at least partially overlap with the orthographic projection of the third active part 73 on the base substrate, the orthographic projection of the fourth active part 74 on the base substrate, the orthographic projection of the fifth active part 75 on the base substrate, and the orthographic projection of the seventh active part 77 on the base substrate. For example, the orthographic projection of the positive voltage shielding part BSM1 on the base substrate may cover the orthographic projection of the third active part 73 on the base substrate, the orthographic projection of the fourth active part 74 on the base substrate, the orthographic projection of the fifth active part 75 on the base substrate, and the orthographic projection of the seventh active part 77 on the base substrate.The first active layer may be made of polysilicon material. Accordingly, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be low-temperature P-type polysilicon thin-film transistors.

[0067] As in Fig. 31, Fig. 34 and Fig. 41, the first conductive layer may include: a first conductive part 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 may be used to connect the second gate drive signal end in Fig. 29; the enable signal line EM can be used to provide the enable signal end in Fig. 29; the second reset signal line Re2 can be used to provide the second reset signal end in Fig. 29. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate may all extend along the row direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active part 74 on the base substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the base substrate covers the orthographic projection of the fifth active part 75 on the base substrate and the orthographic projection of the sixth active part 76 on the base substrate, and part of the structure of the enable signal line EM may be used to form the gates of the fifth transistor T5 and the sixth active part 76, respectively.of the sixth transistor T6. The orthographic projection of the second reset signal line Re2 on the base substrate can cover the orthographic projection of the seventh active part 77 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive part 11 on the base substrate covers the orthographic projection of the third active part 73 on the base substrate, and the first conductive part 11 can be used to form the gate of the driver transistor T3 and the first electrode of the capacitor. As shown in FIG. Fig. As shown in Figure 41, the second gate line G2 in the current row of pixel driving circuits may be multiplexed as the second reset signal line Re2 in the previous row of pixel driving circuits. This arrangement can increase the degree of integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit. Furthermore, the display panel can use the first conductive layer as a mask to perform wiring treatment on the first active layer. That is, the region in the first active layer covered by the first conductive layer can form the channel region of the transistor, and the region in the first active layer not covered by the first conductive layer forms a wiring pattern.

[0068] As in Fig. 31, Fig. 35 and Fig. 42, the second conductive layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G1, and more than one second conductive part 22. Among them, the first initial signal line Vinit1 is used to form the first initial signal end in Fig. 29, the third reset signal line 2Re1 can be used to provide the first reset signal end in Fig. 29, and the third gate line 2G1 can be used to provide the first gate drive signal end in Fig. 29. The orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G1 on the base substrate may all extend along the row direction X. As shown in Fig. As shown in Figure 35, the second conductive layer may further include more than one third connecting portion 23, and in a same repeating unit, the third connecting portion 23 is connected between two adjacent second conductive portions 22 in the row direction. Furthermore, in other exemplary embodiments, adjacent second conductive portions 22 in adjacent repeating units in the row direction may also be connected to each other.

[0069] As in Fig. 31, Fig. 36 and Fig. As shown in Figure 43, the second active layer may include an active portion 81, and the active portion 81 may include a first active portion 811, a second active portion 812, and a twelfth active portion 813 connected to each other. The first active portion 811 may be used to form the channel region of the first transistor. The second active portion 812 may be used to form the channel region of the second transistor T2. The twelfth active portion 813 is connected to an end of the second active portion 812 facing away from the first active portion 811. The second active layer may be made of InGaZnO, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin-film transistors.The orthographic projection of the third gate line 2G1 on the base substrate may cover the orthographic projection of the second active portion 812 on the base substrate, and a portion of the structure of the third gate line 2G1 may be used to form the lower gate of the second transistor. The orthographic projection of the third reset signal line 2Re1 on the base substrate may cover the orthographic projection of the first active portion 811 on the base substrate, and a portion of the structure of the third reset signal line 2Re1 may be used to form the lower gate of the first transistor T1.The orthographic projection of the negative voltage shielding part BSM2 on the base substrate may overlap with the orthographic projection of the first active part 811 on the base substrate and the orthographic projection of the second active part 812 on the base substrate, for example, the orthographic projection of the negative voltage shielding part BSM2 on the base substrate may cover the orthographic projection of the first active part 811 on the base substrate and the orthographic projection of the second active part 812 on the base substrate.

[0070] As in Fig. 31, Fig. 37 and Fig. 44, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. Both the orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the first gate line 3G1 on the base substrate may extend along the row direction X. The first reset signal line 3Re1 may be used to form the first reset signal end in Fig. 29, and the orthographic projection of the first reset signal line 3Re1 on the base substrate may cover the orthographic projection of the first active part 811 on the base substrate. Part of the structure of the first reset signal line 3Re1 may be used to form the upper gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a through-hole located in the wiring area at the edge of the display panel. The first gate line 3G1 may be used to form the first gate drive signal end of Fig. 29, and the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active part 812 on the base substrate. Part of the structure of the first gate line 3G1 may be used to form the upper gate of the second transistor T2, and at the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a through-hole located in the wiring area at the edge of the display panel. As shown in Fig. 31 and Fig. 44, the orthographic projection of the first conductive part 11 on the base substrate may be arranged between the orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate; the orthographic projection of the first reset signal line 3Re1 on the base substrate may be arranged on a side of the orthographic projection of the first gate line 3G1 on the base substrate, opposite to the orthographic projection of the first conductive part 11 on the base substrate. The orthographic projection of the second gate line G2 on the base substrate may be arranged between the orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the first reset signal line 3Re1 on the base substrate.The orthographic projection of the second reset signal line Re2 on the base substrate may be located on a side of the orthographic projection of the enable signal line EM on the base substrate that faces away from the first conductive part 11 on the base substrate. Furthermore, the display panel may use the third conductive layer as a mask to perform a conductive treatment on the second active layer. That is, the region in the second active layer covered by the third conductive layer may form the channel region of the transistor, and the region in the second active layer not covered by the third conductive layer forms a conductive pattern.

[0071] As in Fig. 31, Fig. 38 and Fig. 45, the fourth conductive layer may include a first bridge part 41, a second bridge part 42, a third bridge part 43, a fourth bridge part 44, a fifth bridge part 45, a sixth bridge part 46, and a second initial signal line Vinit2. Among them, the first bridge part 41 may be connected to the third connection part 23 through two via holes H and to the ninth active part 79 through the via holes for connecting the first electrode of the fifth transistor and the second electrode of the capacitor C. It should be noted that the black blocks in the exemplary embodiment indicate the positions of the via holes, and only some of the via holes are marked in the exemplary embodiment. The first bridge part 41 may be mirror-symmetrical to the mirror-symmetrical plane of the first pixel driver circuit P1 and the second pixel driver circuit P2.The second bridge part 42 can be connected via a through-hole to the tenth active part 710 in order to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7. The third bridge part 43 can be connected via through-holes to the eleventh active part 711 and the twelfth active part 813, respectively, in order to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driver transistor T3. The fourth bridge part 44 can be connected via through-holes, respectively, to the second active layer located between the first active part 811 and the second active part 812 and to the first conductive part 11 in order to connect the first electrode of the second transistor T2 and the gate of the driver transistor. As shown in FIG. Fig. 35, an opening 221 is formed on the second conductive part 22, and the orthographic projection of the through-hole connected between the first conductive part 11 and the fourth bridge part 44 on the base substrate is located within the orthographic projection of the opening 221 on the base substrate, so that the conductive pattern in the through-hole and the second conductive part 22 are isolated from each other. The fifth bridge part 45 can be connected to the second active layer on the side of the first active part 811 facing away from the second active part 812 and the first initial signal line Vinit1 through a through-hole, respectively, to connect the second electrode of the first transistor and the first initial signal line Vinit1. In two adjacent repeating units in the row direction, two adjacent pixel driver circuits can share the same fifth bridge part 45.The sixth bridge portion 46 may be connected to the first active layer on a side of the fourth active portion 74 facing away from the third active portion 73 through a through-hole to connect to the first electrode of the fourth transistor. The second initial signal line Vinit2 may be used to connect the second initial signal end in . Fig. 29. The second initial signal line Vinit2 may be connected to the first active layer on the side of the seventh active part 77 facing away from the sixth active part 76 through a through-hole to connect the second electrode of the seventh transistor and the second initial signal end.

[0072] As in Fig. 31, Fig. 39 and Fig. 46, the fifth conductive layer may include more than one power supply line VDD, more than one data line Da, and a seventh bridge part 57. Among them, the orthographic projection of the power supply line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate may both extend along the column direction Y. The power supply line VDD may be used to connect the first power supply end in Fig. 29, and the data line Da can be used to connect the data signal end in Fig. 29. As in Fig. As shown in Figure 31, each column of pixel driver circuits can be provided with a power supply line, respectively. The power supply line VDD in the first pixel driver circuit P1 can be connected to the first bridge part 41 through a through-hole, and the power supply line VDD in the second pixel driver circuit P2 can be connected to the same first bridge part 41 through a through-hole, thereby connecting the first electrode of the fifth transistor and the first power supply end. The data line Da can be connected to the sixth bridge part 46 via a through-hole, thus connecting the first electrode of the fourth transistor and the data signal end. The seventh bridge part 57 can be connected to the second bridge part 42 via a through-hole, so as to be connected to the first electrode of the seventh transistor. As shown in Fig. 39, the power supply line VDD may include a first extension part VDD1, a second extension part VDD2, and a third extension part VDD3. The second extension part VDD2 is connected between the first extension part VDD1 and the third extension part VDD3. The size of the orthographic projection of the second extension part VDD2 on the base substrate in the row direction X may be larger than the size of the orthographic projection of the first extension part VDD1 on the base substrate in the row direction X, and the size of the orthographic projection of the second extension part VDD2 on the base substrate in the row direction X may be larger than the size of the orthographic projection of the third extension part VDD3 on the base substrate in the row direction X.The orthographic projection of the second extension part VDD2 on the base substrate can cover the orthographic projection of the first active part 811 on the base substrate and the orthographic projection of the second active part 812 on the base substrate. The second extension part VDD2 can reduce the influence of light on the characteristics of the first transistor T1 and the second transistor T2. In two adjacent repeating units in the row direction, the second extension parts VDD2 can be connected to each other in two adjacent pixel driver circuits, so that the power supply line VDD and the second conductive part 22 can form a grid structure, and the power supply line of the grid structure can reduce the voltage drop of the current signal thereon.

[0073] As in Fig. 31, the electrode layer may comprise more than one electrode part, and the more than one electrode part may comprise: more than one R electrode part R, more than one G electrode part G, and more than one B electrode part B.

[0074] As in Fig. 47 is a partial cross-sectional view along the dashed line BB in Fig. 31. The display panel may include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a first flat layer 97, and a second flat layer 98. The base substrate 90, the light-shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the first flat layer 97, the fifth conductive layer, the second flat layer 98, and the electrode layer are sequentially stacked.The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be a single-layer structure or a multi-layer structure, and the material of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 may be a silicon nitride layer. The material of the first flat layer 97 and the second flat layer 98 may be an organic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), and other materials.The base substrate 90 may consist of a glass substrate, a barrier layer, and a polyimide layer stacked one after the other, wherein the barrier layer may be made of an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer may be made of an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum / titanium alloy or lamination. The material of the fourth conductive layer and the fifth conductive layer may comprise a metallic material, e.g., it may be an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum / titanium alloy or lamination, etc., or it may be a titanium / aluminum / titanium lamination.

[0075] As in Fig.48 is a schematic structural diagram of a display panel according to another example of the present disclosure. The display panel may include a display area AA and a frame area B around the display area. The frame area B may be provided with the above-mentioned shielding part. For example, the frame area B may include a first frame area B1 for integrating gate drive circuits and a fan-out area B2 for fan-out data lines. The shielding part located in the first frame area B1 may form signal lines or device structures in the gate drive circuit, and the shielding part located in the fan-out area B2 may be used to form fan-out lines of data lines. Furthermore, the shielding part in the frame area B may be used to form signal lines or device structures in the detection circuit.This arrangement allows the shielding layer to be evenly distributed on the base substrate, so that problems such as uneven etching and poor control of process parameters do not occur during the process.

[0076] A display device according to an exemplary embodiment is further provided, which includes the above-mentioned display panel. The display device may be a display device such as a mobile phone, a tablet computer, or a television.

[0077] Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the present disclosure. This application is intended to cover any modifications, uses, or adaptations of the present disclosure which follow the general principles of the present disclosure and incorporate common knowledge or conventional technical means in the art not disclosed in the present disclosure. The specification and embodiments are to be considered as examples only, with a true scope and spirit of the disclosure being indicated by the appended claims.

[0078] It should be understood that the present disclosure is not limited to the precise constructions described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope of the disclosure. The scope of the present disclosure is limited only by the appended claims.

Claims

[1] A display panel, the display panel comprising a pixel driver circuit, the pixel driver circuit comprising a transistor, and the display panel further comprising: a base substrate; a first active layer located on one side of the base substrate, wherein at least a portion of the structure of the first active layer is configured to form a channel region of the transistor; and a shielding layer located between the base substrate and the first active layer, wherein the shielding layer is a conductive layer, the shielding layer comprises more than one independently arranged shielding part, and at least partially different shielding parts are configured to receive different signals. [2] The display panel according to claim 1, wherein the pixel driving circuit comprises a driving transistor and a first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driving transistor; and the first initial signal line is included in the more than one shielding part. [3] The display panel of claim 2, wherein the first active layer comprises a first active portion and a third active sub-portion; the first active portion is configured to form a channel region of the first transistor, the first active portion comprises a first active sub-portion and a second active sub-portion, and the third active sub-portion is connected between the first active sub-portion and the second active sub-portion; and the first initial signal line comprises a first extension portion, and an orthographic projection of the first extension portion on the base substrate at least partially overlaps with an orthographic projection of the third active sub-portion on the base substrate. [4] A display panel according to claim 2, wherein the display panel further comprises: a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line, an orthographic projection of the first reset signal line on the base substrate extending along a first direction and covering an orthographic projection of the first active portion on the base substrate, and a portion of the structure of the first reset signal line being configured to form a gate of the first transistor; the first initial signal line comprises a second extension part and an orthographic projection of the second extension part on the base substrate at least partially overlaps with an orthographic projection of the first reset signal line on the base substrate. [5] A display panel according to claim 2, wherein the display panel further comprises: a fourth conductive layer located on a side of the first active layer remote from the base substrate, the fourth conductive layer comprising a first initial interconnect line; wherein an orthographic projection of the first initial signal line on the base substrate extends along a first direction, and an orthographic projection of the first initial connection line on the base substrate extends along a second direction, the first direction intersecting the second direction, and the first initial connection line is connected to the first initial signal line intersecting the orthographic projection of the first initial connection line on the base substrate through a through-hole. [6] The display panel according to claim 1, wherein the display panel further comprises a light emitting unit, the pixel driving circuit comprises a seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit; and the second initial signal line is included in the more than one shielding part. [7] The display panel according to claim 6, wherein the pixel driving circuit further comprises a driving transistor and a sixth transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit; the first active layer comprises a sixth active part and a seventh active part, the sixth active part is configured to form a channel region of the sixth transistor, and the seventh active part is configured to form a channel region of the seventh transistor; and the display panel further comprises a first conductive layer, wherein the first conductive layer is arranged on a side of the first active layer facing away from the base substrate, and the first conductive layer comprises: an enable signal line, wherein an orthographic projection of the enable signal line on the base substrate extends along a first direction and covers an orthographic projection of the sixth active part on the base substrate, and a part of the structure of the enable signal line is configured to form a gate of the sixth transistor; and a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the seventh active part on the base substrate, and a part of the structure of the second reset signal line is configured to form a gate of the seventh transistor; wherein an orthographic projection of the second initial signal line on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate. [8] A display panel according to claim 6, wherein the display panel further comprises: a fourth conductive layer located on a side of the first active layer remote from the base substrate, the fourth conductive layer comprising a second initial interconnect line; wherein an orthographic projection of the second initial signal line on the base substrate extends along a first direction and an orthographic projection of the second initial connection line on the base substrate extends along a second direction, the first direction intersecting the second direction, and the second initial connection line is connected to the second initial signal line intersecting the orthographic projection of the second initial connection line on the base substrate through a through-hole. [9] The display panel of claim 1, wherein the pixel driver circuit comprises a driver transistor, the first active layer comprises a third active portion, and the third active portion is configured to form a channel region of the driver transistor; and a first shield portion in which more than one shield portion is included, the first shield portion is connected to a stable voltage source, and an orthographic projection of the first shield portion on the base substrate covers an orthographic projection of the third active portion on the base substrate. [10] The display panel according to claim 9, wherein the pixel driver circuit further comprises a capacitor, a first electrode of the capacitor is connected to a gate of the driver transistor, and a second electrode of the capacitor is connected to a power supply line; and the display panel further comprises: a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion being configured to form the gate of the driver transistor and the first electrode of the capacitor; the power supply line forms the stable voltage source, and the first shielding part is configured to form the second electrode of the capacitor. [11] A display panel according to claim 10, wherein the display panel further comprises: a fourth conductive layer located on a side of the first conductive layer facing away from the base substrate; wherein the fourth conductive layer comprises the power supply line and an orthographic projection of the power supply line extends on the base substrate along a second direction; the display panel comprises more than one pixel driving circuit distributed in an array in a first direction and the second direction, the first direction intersecting with the second direction, and the more than one first shielding part distributed in the first direction are connected to each other, and the power supply line is connected to the first shielding part through a through hole. [12] The display panel according to claim 11, wherein the power supply line comprises a third extension part, a fourth extension part, and a fifth extension part connected between the third extension part and the fourth extension part; a size of an orthographic projection of the fifth extension part on the base substrate in the first direction is larger than a size of an orthographic projection of the third extension part on the base substrate in the first direction, the size of the orthographic projection of the fifth extension part on the base substrate in the first direction is larger than a size of an orthographic projection of the fourth extension part on the base substrate in the first direction, and the first direction intersects with the second direction; and the orthographic projection of the fifth extension part on the base substrate at least partially overlaps with an orthographic projection of the first conductive part on the base substrate, and at least a part of the structure of the fifth extension part is configured to form a second electrode of the capacitor. [13] The display panel according to claim 9, wherein the pixel driver circuit further comprises a second transistor, a first electrode of the second transistor is connected to a gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor; the first active layer further comprises a second active portion and a sixth active sub-portion, wherein the second active portion is configured to form a channel region of the second transistor, the second active portion comprises a fourth active sub-portion and a fifth active sub-portion, and the sixth active sub-portion is connected between the fourth active sub-portion and the fifth active sub-portion; the shielding layer further comprises a second shielding part connected to the first shielding part, the first shielding part comprises a first edge, the second shielding part comprises a second edge, the first edge is connected to the second edge, an angle between an orthographic projection of the first edge on the base substrate and an orthographic projection of the second edge on the base substrate is less than 180°, and an orthographic projection of the second shielding part on the base substrate at least partially overlaps with an orthographic projection of the sixth active sub-part on the base substrate. [14] The display panel according to claim 9, wherein the pixel driver circuit further comprises a first transistor and a second transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driver transistor, a first electrode of the second transistor is connected to the gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor; the first active layer further comprises a first active part, a second active part, and an eighth active part, wherein the first active part is configured to form a channel region of the first transistor, the second active part is configured to form a channel region of the second transistor, and the eighth active part is connected between the first active part and the second active part; and the shielding layer further comprises a third shielding part, the third shielding part is connected to the first shielding part, the first shielding part comprises a first edge, the third shielding part comprises a third edge, the first edge is connected to the third edge, an angle between an orthographic projection of the first edge on the base substrate and an orthographic projection of the third edge on the base substrate is less than 180°, and an orthographic projection of the third shielding part on the base substrate at least partially overlaps with an orthographic projection of the eighth active part on the base substrate. [15] The display panel according to claim 9, wherein the pixel driver circuit further comprises a first transistor and a second transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driver transistor, a first electrode of the second transistor is connected to the gate of the driver transistor, and a second electrode of the second transistor is connected to a second electrode of the driver transistor; the first active layer further comprises a first active part, a second active part, a sixth active sub-part, and an eighth active part, the first active part is configured to form a channel region of the first transistor, the second active part is configured to form a channel region of the second transistor, the second active part comprises a fourth active sub-part and a fifth active sub-part, the sixth active sub-part is connected between the fourth active sub-part and the fifth active sub-part, and the eighth active part is connected between the first active part and the second active part; the display panel further comprises a first conductive layer, the first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer comprises a first conductive part and a first gate line, an orthographic projection of the first conductive part on the base substrate covers an orthographic projection of the third active part on the base substrate, and an orthographic projection of the first gate line on the base substrate extends along a first direction and covers an orthographic projection of the second active part on the base substrate; the shielding layer further comprises a second shielding part, a third shielding part and a first connecting part, the second shielding part is connected to the first shielding part, and an orthographic projection of the second shielding part on the base substrate at least partially overlaps with an orthographic projection of the sixth active sub-part on the base substrate; the third shielding part is connected to the first shielding part and an orthographic projection of the third shielding part on the base substrate at least partially overlaps with an orthographic projection of the eighth active part on the base substrate; and the first connection part is connected between the second shielding part and the third shielding part in adjacent pixel driver circuits in the first direction, and an orthographic projection of the first connection part on the base substrate is located on a side of an orthographic projection of the first gate line on the base substrate opposite to an orthographic projection of the first conductive part on the base substrate. [16] The display panel according to claim 1, wherein the display panel further comprises a display area and a frame area around the display area, a part of the shielding part is located in the display area, and a part of the shielding part is located in the frame area. [17] The display panel according to claim 1, wherein the pixel driving circuit includes more than one transistor, and a constant-voltage shielding part corresponding to the transistor in which more than one shielding part is included, and an orthographic projection of the constant-voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the transistor corresponding to the constant-voltage shielding part on the base substrate; and at least partially different constant-voltage shielding parts are configured to receive different power supply voltages. [18] The display panel of claim 17, wherein the pixel driver circuit comprises an N-type transistor and a P-type transistor; a positive voltage shielding part and a negative voltage shielding part in which more than one constant voltage shielding part is included, the positive voltage shielding part is configured to receive a positive power supply voltage, and the negative voltage shielding part is configured to receive a negative power supply voltage; and an orthographic projection of the positive voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the P-type transistor on the base substrate, and an orthographic projection of the negative voltage shielding part on the base substrate at least partially overlaps with an orthographic projection of a channel region of the N-type transistor on the base substrate. [19] The display panel according to claim 17, wherein the display panel further comprises a light-emitting unit, the pixel driving circuit comprises a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors; a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driver transistor; a first electrode of the fifth transistor is connected to a first power supply end, and a second electrode of the fifth transistor is connected to the first electrode of the driver transistor; a first electrode of the sixth transistor is connected to a second electrode of the driver transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit; a first electrode of the sixth transistor is connected to a second electrode of the driver transistor, and a second electrode is connected to a first electrode of the light emitting unit; and more than one positive voltage shielding part in which more than one constant voltage shielding part is contained, and which comprises more than one positive voltage shielding part: a first positive voltage shielding part, wherein an orthographic projection of the first positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the driver transistor on the base substrate; a second positive voltage shielding part, wherein an orthographic projection of the second positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the fifth transistor on the base substrate and an orthographic projection of a channel region of the sixth transistor on the base substrate; and a third positive voltage shielding part, wherein an orthographic projection of the third positive voltage shielding part on the base substrate covers an orthographic projection of a channel region of the fourth transistor on the base substrate and an orthographic projection of a channel region of the seventh transistor on the base substrate; wherein a positive voltage received by the first positive voltage shielding part is greater than a positive voltage received by the second positive voltage shielding part, and a positive voltage received by the third positive voltage shielding part is greater than a positive voltage received by the first positive voltage shielding part. [20] The display panel of claim 17, wherein the display panel comprises a high-density integration region and a low-density integration region, and a density of transistors in the high-density integration region is greater than a density of transistors in the low-density integration region; the high-density integration region comprises a first high-density integration region and a second high-density integration region, and the second high-density integration region is located on a side of the first high-density integration region facing away from the low-density integration region; and in constant-voltage shielding parts corresponding to a same transistor in the pixel driving circuit, an absolute value of the voltage received by a constant-voltage shielding part located in the first high-density integration region is greater than an absolute value of the voltage received by a constant-voltage shielding part located in the second high-density integration region. [21] A display device comprising the display panel according to any one of claims 1 to 20.

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