Driver backplate, display panel and display device

Abstract

A driver backplate, a display panel, and a display device pertain to the field of display technology. The driver backplate has a pixel area (AA) and a control area (WA), which includes a circuit area (CA) and a bus area (LA); the driver backplate comprises a substrate (SU) and a circuit layer (CL), wherein the circuit layer (CL) includes a plurality of pixel circuits.A row of pixel circuits is connected to at least one gate line (GAL); a gate driver circuit (GGOA) is located in the control area (WA) and comprises several cascaded gate shift register units (GGOAs); a bus (L) is located in the bus area (LA) and lies at least partially between the gate driver circuit (GGOA) and the pixel area (AA); a gate shift register unit (GGOAs) is connected to a gate interconnect line (GCL), wherein at least a portion of the gate interconnect line (GCL) is located on a different layer than the gate line (GAL) and is connected to at least one gate line (GAL) through a contact hole; the gate interconnect line (GCL) is isolated from the bus (L). The blocking capability of static electricity is increased, and display anomalies are prevented.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology and specifically relates to a driver backplate, a display panel, and a display device. STATE OF THE ART

[0002] OLED (organic electroluminescent diode) display panels have advantages such as self-illumination, a wide color range, high contrast, flexibility, high responsiveness, and flexibility, and have broad application prospects. However, existing display panels may experience abnormal display images such as black screens and flickering.

[0003] It should be noted that the information disclosed in the above prior art is merely intended to enhance the understanding of the background of the present disclosure and may therefore contain prior art information that is not known to a person of ordinary skill in the art. DISCLOSURE OF THE INVENTION

[0004] The present disclosure provides a driver backplate, a display panel, and a display device.

[0005] According to one aspect of the present disclosure, a driver backplane is provided comprising a pixel region and a control region outside the pixel region, wherein the control region comprises a circuit region and a bus region separated between the circuit region and the pixel region; the circuit layer comprises: multiple pixel circuits distributed in an array in the pixel area; a plurality of gate lines extending along a row direction and distributed along a column direction, wherein a row of the pixel circuit is connected to at least one of the gate lines; a gate drive circuit provided in the control region and comprising a plurality of gate shift register units cascaded along the column direction; a bus provided in the bus region and located at least partially between the gate driver circuit and the pixel region, the bus being located on a side of the gate line remote from the substrate; a plurality of gate connection lines, wherein one of the gate shift register units is connected to one of the gate connection lines, at least a portion of one of the gate connection lines is located in a different layer than the gate line and is connected to at least one of the gate lines through a contact hole; the gate connection line is provided in isolation from the bus.

[0006] In an exemplary embodiment of the present disclosure, the gate connection line includes a first connection part and a second connection part connected to each other, wherein the first connection part is connected to the gate shift register unit and passes through the bus region, the second connection part is distributed spaced apart from the bus and the pixel circuit and is connected to at least one of the gate lines; at least one of the first connection part and the second connection part and the gate line are on different layers.

[0007] In an exemplary embodiment of the present disclosure, the first connecting part and the gate line are arranged on one and the same layer, the second connecting part and the gate line are located on different layers.

[0008] In an exemplary embodiment of the present disclosure, the first connection part and the second connection part are arranged on one and the same layer, and are located on different layers than the gate line and the bus.

[0009] In an exemplary embodiment of the present disclosure, the circuit layer further comprises a power line, a data line, and a reset signal line, wherein both the power line and the data line extend along the column direction and are distributed along the row direction, the power line and the data line, and the bus are arranged on one and the same layer; the reset signal line extends along the row direction and is distributed along the column direction, the reset signal line and the gate line, and the bus are located on different layers; the gate line comprises a first gate line and a second gate line; the pixel circuit comprises a storage capacitor and a plurality of transistors, wherein the transistors comprise a driver transistor, a write transistor, a compensation transistor, and a first reset transistor; gate electrodes of the compensation transistor and the write transistor are connected to the first gate line; a first terminal of the driver transistor is connected to the power line, and a second terminal is connected to a light-emitting element; the compensation transistor is connected to the second terminal and the gate electrode of the driver transistor; a first terminal of the write transistor is connected to the data line, and a second terminal is connected to the first terminal of the driver transistor; a gate electrode of the first reset transistor is connected to the second gate line, a first terminal is connected to the reset signal line, and a second terminal is connected to the gate electrode of the driver transistor;a first electrode plate of the storage capacitor is connected to the gate electrode of the driver transistor and a second electrode plate is connected to the power line; a first gate line connected to the pixel circuit in the n-th row and a second gate line connected to the pixel circuit in the n+1-th row are connected to the same gate shift register unit via the same gate connection line.

[0010] In an exemplary embodiment of the present disclosure, the circuit layer comprises: a semiconductor layer provided on one side of the substrate and comprising a channel of one of the respective transistors; a first gate insulating layer covering the semiconductor layer; a first gate layer provided on the surface of the first gate insulating layer remote from the substrate and comprising the gate line, the first electrode plate, and the gate electrode of the respective transistor; a second gate insulating layer covering the first gate layer; a second gate layer provided on the surface of the second gate insulating layer remote from the substrate and including the second electrode plate and the reset signal line; a dielectric layer covering the second gate layer; a source-drain layer provided on a side of the dielectric layer remote from the substrate and comprising the bus, the power line and the data line.

[0011] In an exemplary embodiment of the present disclosure, when the first connection part is arranged on a same layer of the gate line and is located on a different layer than the second connection part, the first connection part is connected to the second gate line; and the second connection part is located on the source-drain layer and extends along the column direction, the second connection part is connected to the first gate line via a contact hole.

[0012] When, in an exemplary embodiment of the present disclosure, the first connecting part and the second connecting part are arranged on one and the same layer: the gate connection line is located on the second gate layer.

[0013] In an exemplary embodiment of the present disclosure, the first connection part is connected to the gate shift register unit and the second gate line through a contact hole; the second connection part extends along a column direction and is connected to the first connection part, the second connection part is connected to the first gate line via a contact hole.

[0014] In an exemplary embodiment of the present disclosure, the gate line further comprises a third gate line; wherein the pixel circuit further comprises a second reset transistor, a first light emission control transistor, and a second light emission control transistor; a gate electrode of the first light emission control transistor is connected to a third gate line, a first terminal is connected to the power line, and a second terminal is connected to the first terminal of the driver transistor; a gate electrode of the second light emission control transistor is connected to the third gate line, a first terminal is connected to the second terminal of the driver transistor, and a second terminal is connected to the light-emitting element; the gate electrode of the second reset transistor is connected to the first gate line, a first pole is connected to the reset signal line, and a second pole is connected to the second pole of the second light emission control transistor.

[0015] In an exemplary embodiment of the present disclosure, the circuit layer further comprises: a light emission control circuit provided in the control area and comprising: a plurality of light-emitting shift register units cascaded along the column direction; a plurality of light emission interconnections, wherein one of the light-emitting shift register units is connected to one of the light emission interconnections, at least a portion of the light emission interconnection is located on a different layer than the third gate line and is connected to the third gate line via a contact hole.

[0016] In an exemplary embodiment of the present disclosure, the light emission connection line is located on the second gate layer and is connected to the light emitting shift register unit and the third gate line via a contact hole.

[0017] In an exemplary embodiment of the present disclosure, the light emission interconnection line includes a third interconnection part and a fourth interconnection part, wherein the third interconnection part is disposed on a same layer as the gate line and is connected to the light-emitting shift register unit, the third interconnection part passes through the bus region along the direction; the fourth interconnection part is disposed on the source-drain layer or the second gate layer and is connected to the third interconnection part and the third gate line via a contact hole.

[0018] In an exemplary embodiment of the present disclosure, the second reset transistor of the pixel circuit of the n-th row is connected to the second gate line of the pixel circuit of the n+1-th row.

[0019] In an exemplary embodiment of the present disclosure, the bus includes a test bus, a reset bus, and a power bus located on the source-drain layer, and the power line is connected to the power bus, the reset signal line is connected to the reset bus.

[0020] In an exemplary embodiment of the present disclosure, the reset bus is located between the test bus and the pixel region, wherein the second connection part is located on a side of the reset bus remote from the test bus and is provided adjacent to the reset bus; a distance between the second connection part and the reset bus along the row direction is 3 µm-10 µm.

[0021] In an exemplary embodiment of the present disclosure, the width of the second connection part is 20-40% of the width of the reset bus.

[0022] In an exemplary embodiment of the present disclosure, the control region of the driver backplane includes an output region extending along the row direction and spaced apart from the pixel region along the column direction; the bus, the data line, and the power line are all connected to the output region; the bus region comprises: side bus regions distributed on two sides of the pixel region along the row direction, and a connection bus region connected between the two side bus regions; wherein the connection bus region is located between the output region and the pixel region; the power bus is located in the connecting bus area.

[0023] According to one aspect of the present disclosure, there is provided a display panel comprising a driver backplate according to any one of the above embodiments.

[0024] According to one aspect of the present disclosure, a display device is provided comprising a driver backplate according to any one of the above embodiments.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not limiting of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are incorporated in and constitute a part of the specification; they illustrate embodiments according to the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. Other drawings based on these drawings will be readily available to those of ordinary skill in the art without inventive effort. Fig. 1 is a schematic partial cross-sectional diagram of one embodiment of a display panel of the present disclosure. Fig. 2 is a schematic diagram of distribution of respective regions in one embodiment of the driver backplate of the present disclosure. Fig. 3 is a schematic diagram of the circuit distribution in one embodiment of the driver backplane of the present disclosure. Fig. 4 is a schematic diagram of a pixel circuit in one embodiment of the driver backplane of the present disclosure. Fig. 5 is a partial top view of a semiconductor layer in one embodiment of the driver backplate of the present disclosure. Fig. 6 is a partial top view of a first gate layer in one embodiment of the driver backplate of the present disclosure. Fig. 7 is a partial top view of a second gate layer in one embodiment of the driver backplate of the present disclosure. Fig. 8 is a partial top view of a source-drain layer in one embodiment of the driver backplate of the present disclosure. Fig. 9 is a partial top view of a pixel circuit in one embodiment of the driver backplane of the present disclosure. Fig. 10 is a schematic diagram of a gate shift register unit in one embodiment of the driver backplane of the present disclosure. Fig. 11 is a partial schematic diagram of a first embodiment of a first type of driver backplate of the present disclosure. Fig. 12 is a partial schematic diagram of a second embodiment of the first type of driver backplate of the present disclosure. Fig. 13 is a partial schematic diagram of a third embodiment of the first type of driver backplate of the present disclosure. Fig. 14 is a partial schematic diagram of a fourth embodiment of the first type of driver backplate of the present disclosure. Fig. 15 is a partial schematic diagram of a first embodiment of a second type of driver backplate of the present disclosure. Fig. 16 is a schematic diagram of the circuit distribution in another embodiment of the driver backplane of the present disclosure. Fig. 17 is a partial schematic diagram of one embodiment of a power bus of the driver backplane of the present disclosure. Fig. 18 is a partial schematic diagram of another embodiment of the driver backplane power bus of the present disclosure. EMBODIMENTS OF THE INVENTION

[0027] Example embodiments will now be described in more detail with reference to the accompanying drawings. However, example embodiments may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals throughout the drawings designate the same or similar structures, and therefore, detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic representations of this disclosure and are not necessarily drawn to scale.

[0028] The terms "a", "an", "this", "the", and "at least one" are used to represent the presence of one or more elements / components / or the like; the terms "comprise" and "comprising" are used to indicate a meaning of containing in the open sense, meaning that in addition to the listed elements / components / or the like, there may be further elements / components / or the like; they are used only as a marker, not a limitation on the number of its objects; the terms "first", "second", and "third" or the like are used merely as labels and do not serve as a limitation on the number of its objects.

[0029] In this text, the row direction X and the column direction Y are merely two mutually perpendicular directions. In the drawings of the present disclosure, the row direction X may be a transverse direction and the column direction Y a longitudinal direction, but are not limited thereto. When the display panel is rotated, the actual orientations in the row direction X and column direction Y may change.

[0030] "Overlap" of feature A and feature B in this text means that the orthographic projection of feature A on the substrate at least partially overlaps with the orthographic projection of feature B on the substrate. "Nonoverlap" of feature A and feature B in this text means that the area of ​​the overlap region of the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate is zero.

[0031] The term "on the same layer" of feature A and feature B in this text means that feature A and feature B can be formed simultaneously. The term "on different layers" of feature A and feature B means that feature A and feature B are distributed in a direction perpendicular to the substrate and separated by other film layers.

[0032] As in Fig. 2, the display panel of the present disclosure may include a driving back plate BP and a light-emitting element LD arranged on one side of the driving back plate BP. By a driving circuit in the driving back plate BP, the light-emitting element LD may be driven to emit light to display an image.

[0033] The light-emitting element LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a micro-LED or a mini-LED or the like, and may include a first electrode ANO and a second electrode CAT and a light-emitting layer EL located between the first electrode ANO and the second electrode CAT.

[0034] The display panel can be divided into at least a display area that can emit light and a peripheral area outside the display area that does not emit light. The drive circuit can include a pixel circuit arranged in the display area and a peripheral circuit arranged in the peripheral area. The peripheral circuit can be connected to the light-emitting element LD via the pixel circuit and supplies a first power supply signal VDD to the first electrode ANO of the light-emitting element LD; the peripheral circuit can also be connected to the second electrode CAT of the light-emitting element LD and supplies a second power supply signal VSS to the second electrode CAT. By controlling the pixel circuit, the current flowing through the light-emitting element LD can be controlled, thereby controlling the brightness of the light-emitting element LD.

[0035] As in Fig. 1 and Fig. 2, based on the above division of the display panel, the driver backplane BP of the present disclosure may accordingly be divided into at least a pixel region AA and a control region WA outside the pixel region AA. The pixel region AA is a region corresponding to the display region in the driver backplane BP, and the control region WA is a region corresponding to the peripheral region in the driver backplane BP. Furthermore, the control region WA may include a circuit region CA and a bus region LA separated between the circuit region CA and the pixel region AA.

[0036] As in Fig. 1-3 and Fig. As shown in Figures 11-15, the driver backplate BP of the present disclosure may include a substrate SU and a circuit layer CL provided on one side of the substrate SU. The substrate SU may be made of a flexible transparent material such as polyimide, or a hard transparent material such as glass, and the substrate SU may be multilayered or single-layered. The circuit layer CL may include the pixel circuits PC, gate lines, gate driver circuits, buses, and gate connection lines, where: A plurality of pixel circuits PC are provided and distributed in an array in the pixel area AA, resulting in multiple rows and columns of pixel circuits PC. A pixel circuit PC can be connected to at least one light-emitting element to drive the light-emitting element to emit light.

[0037] The gate lines GAL are located at least partially in pixel area AA, and multiple gate lines GAL are present. The respective gate lines GAL all extend along the row direction X and are distributed along the column direction Y. A row of pixel circuits PC is connected to at least one gate line GAL.

[0038] The gate driver circuit GGOA can be arranged in the control region WA and includes a plurality of gate shift register units GGOAs cascaded along the column direction Y. A plurality of gate interconnect lines GCL are provided, and a gate shift register unit GGOAs can be connected to a gate interconnect line GCL, allowing signals to be input to the pixel circuit PC via the gate interconnect line GCL and the gate line GAL. At the same time, at least a portion of a gate interconnect line GCL is located in a different layer than the gate line GAL and is connected to at least one gate line GAL via a contact hole.

[0039] The bus L is provided in the bus area LA and is located at least partially between the gate driver circuit GGOA and the pixel area AA. The bus L is isolated from the gate connection line GCL.

[0040] The driver backplate BP in the embodiment of the present disclosure can allow at least a portion of the gate interconnection line GCL, which connects the gate line GAL and the gate shift register unit GGOAs, and the gate line GAL to be located on different layers, requiring connection through a contact hole. The presence of the contact hole can increase the overall impedance of the gate interconnection line GCL, improve the ability to block static electricity, provide a certain protection function for other circuits, facilitate ensuring stable transmission of electrical signals, and prevent display anomalies such as black screens and flickering. In particular, for the gate line GAL, which transmits high-frequency pulse signals, signal interference caused by static electricity can be reduced.

[0041] The pixel circuit PC and the driver circuit are explained in detail below: The pixel circuit PC can comprise multiple transistors and capacitors, which can result in a pixel circuit PC of 3T1C, 7T1C, or the like. nTmC indicates that a pixel circuit PC comprises n transistors (denoted by the letter "T") and m capacitors (denoted by the letter "C").

[0042] As in Fig. 4, a pixel circuit PC in 7T1C structure is given as an example, which comprises a first reset transistor T1, a compensation transistor T2, a driver transistor T3, a write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst, where: A gate electrode of the first reset transistor T1 is provided for receiving a first reset control signal RE1, a first terminal is provided for receiving a reset signal VI, a second terminal is connected to a first electrode plate of the gate storage capacitor Cst of the driver transistor T3 at an N1 node, and a second electrode plate of the storage capacitor Cst is provided for receiving the first power supply signal VDD. A gate electrode of the compensation transistor T2 is provided for receiving a strobe signal GA, a first terminal is connected to a second terminal of the driver transistor T3 at an N2 node, and a second terminal is connected to the gate electrode of the driver transistor T3 at an N1 node. A gate electrode of the write transistor T4 is provided for receiving the strobe signal GA, a first terminal is provided for receiving a data signal DA, and a second terminal is connected to the first terminal of the driver transistor T3 at a node N3.A gate electrode of the first light-emitting control transistor T5 receives a light-emitting control signal EM, a first terminal receives the first power supply signal VDD, and a second terminal is connected to the first terminal of the driver transistor T3. A gate electrode of the second light-emitting control transistor T6 receives the light-emitting control signal EM, a first terminal is connected to the second terminal of the driver transistor T3 at the N2 node, and a second terminal is connected to the first electrode of the light-emitting element at an N4 node. A gate electrode of the second reset transistor T7 receives a reset control signal REL, a first terminal receives the reset signal VI, and a second terminal is connected to the second terminal of the second light-emitting control transistor T6 at the N4 node.

[0043] The working principle of the pixel circuit PC is explained below: Each transistor of the pixel circuit PC can be a P-type low-temperature polysilicon transistor. Since the P-type low-temperature polysilicon transistor has high carrier mobility, it facilitates the implementation of a display panel with high resolution, high response speed, high pixel density, and a high aperture ratio. A P-type low-temperature polysilicon transistor can be turned off when a high level signal is input to its gate electrode, and can be turned on when a low level signal is input. Of course, the transistor can also be an N-type low-temperature polysilicon transistor that is turned on at a high level. In this text, only a P-type low-temperature polysilicon transistor is explained as an example.

[0044] During a reset phase: The first reset control signal RE1 is low, the first reset transistor T1 is turned on, and the reset signal VI is written to the gate electrode of the driver transistor T3 and the first electrode plate of the storage capacitor Cst. As a result, the N1 node is reset to perform initialization and eliminate the influence of the image data of the last frame.

[0045] In a write phase: The sensing signal GA enables the write transistor T4 and the compensation transistor T2 to be turned on, the data signal DA is written to the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor Cst, i.e., the data signal DA is written to the N1 node via the N3 node and the N2 node until the potential reaches Vdata+vth. Vdata is the voltage of the data signal Da, and Vth is the threshold voltage of the driver transistor T3. The sensing signals GA of the write transistor T4 and the compensation transistor T2 can be the same signal.At the same time, the second reset control signal RE2 is a low level signal, which turns on the second reset transistor T7, writes the second reset signal VIN2 to the first electrode of the light-emitting element LD and the second pole of the second light-emitting control transistor T6, resets the N4 node to perform initialization and eliminates the influence of the data of the last frame image.

[0046] In a light emission phase: The light emission control signal EM is a low level signal, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, the driver transistor T3 is turned on under the action of the voltage Vdata + Vth stored in the storage capacitor Cst and the first power supply signal VDD, and the light-emitting element LD emits light.

[0047] Furthermore, as in Fig. 3 and Fig. 5-9, the circuit layer includes, in addition to the gate line GAL, a power line VDL, a data line DAL, a first reset signal line VIL1, and a second reset signal line VIL2 to facilitate the input of signals to the pixel circuit PC, where: The power line VDL can extend along the column direction Y and be distributed along the row direction X, and is connected to the first light-emitting control transistor T5 and the second electrode plate Cst2 of the storage capacitor Cst to transmit the first power supply signal VDD. The data line DAL can also extend along the column direction Y and is connected along the row direction X and to the first pole of the write transistor T4 to transmit the data signal DA.

[0048] The first reset signal line VIL1 and the second reset signal line VIL2 both extend along the row direction X and are distributed along the column direction Y. The first reset signal line VIL1 can be connected to the first pole of the first reset transistor T1 to transmit the reset signal VI. The second reset signal line VIL2 can be connected to the first pole of the second reset transistor T7 to transmit the reset signal VI. The two reset signals VI can be the same or different.

[0049] To simplify the structure, in some embodiments, the same reset signal line can be used to simultaneously input a reset signal to the second reset transistor T7 of the pixel circuit PC of the nth row and the first reset transistor T1 of the pixel circuit PC of the n+1st row. That is, the second reset signal line VIL2 connected to the pixel circuit PC of the nth row can be multiplexed into the first reset signal line VIL1 connected to the pixel circuit PC of the n+1st row. To this end, the first terminal of the second reset transistor T7 of the pixel circuit PC of the nth row can be connected to the first terminal of the first reset transistor T1 of the pixel circuit PC of the n+1st row and connected to the same reset signal line (the first reset signal line VIL1 and the second reset signal line VIL2). Thus, the number of reset signal lines can be reduced.

[0050] Multiple gate lines GAL may be provided, all extending along the row direction X and distributed along the column direction Y. The gate line GAL may be provided for transmitting the scanning signal GA, the first reset control signal RE1, the second reset control signal RE2, and the emission control signal EM, so that the switching on and off of other transistors besides the driver transistor T3 can be controlled. For example, the gate line GAL may include a first gate line GAL1, a second gate line GAL2, a third gate line GAL3, and a fourth gate line GAL4, where: The first gate line GAL1 may be simultaneously connected to the gate electrodes of the write transistor T4 and the compensation transistor T2, and simultaneously transmits the scan signal GA to the write transistor T4 and the compensation transistor T2. The second gate line GAL2 may be connected to the gate electrode of the first reset transistor T1 to transmit the first reset control signal RE1. The third gate line GAL3 may be simultaneously connected to the gate electrodes of the first light emission control transistor T5 and the second light emission control transistor T6 for the light emission control signal EM. The fourth gate line GAL4 may be connected to the gate electrode of the second reset transistor T7 to transmit the second reset control signal RE2.

[0051] Since the write transistor T4, the compensation transistor T2, and the second reset transistor T2 are all turned on during the light emission phase, the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC can receive a signal simultaneously; this signal can simultaneously serve as the scan signal GA and the second reset control signal RE2. At the same time, the first gate line GAL1 connected to n rows of pixel circuits PC can be connected to the second gate line GAL2 of the first reset transistor T1 connected to n+1 rows of pixel circuits PC, so that the pixel circuit PC of the nth row can be in the write phase and, at the same time, the pixel circuit PC of the n+1th row can be in the reset phase.

[0052] Then, the fourth gate line GAL4 connected to the second reset transistor T7 of the pixel circuit PC of the nth row and the second gate line GAL2 connected to the first reset transistor T7 of the pixel circuit PC of the n+1-th row may be a same gate line GAL, that is, the fourth gate line GAL4 connected to the pixel circuit PC of the n-th row is multiplexed as the second gate line GAL2 of the pixel circuit PC of the n+1-th row, thereby facilitating the simplification of the structure and shortening the refresh time.

[0053] Due to the above pixel circuit PC, the circuit layer CL comprises in some embodiments, as in Fig. 2, a semiconductor layer SEL, a first gate insulating layer GI1, a first gate layer GAT1, a second gate insulating layer GI2 and a second gate layer GAT2, a dielectric layer ILD, a source-drain layer SD and a planarization layer PLN, where: As in Fig. 5 and Fig. As shown in Figure 9, the semiconductor layer SEL may be provided on one side of the substrate SU and may include channels of the respective transistors. Low-temperature polysilicon or the like may be used as the material of the semiconductor layer SEL. The channel of the second reset transistor T7 of the pixel circuit PC of the nth row may be connected to the channel of the first reset transistor T1 of the pixel circuit PC of the n+1th row.

[0054] The first gate insulating layer GI1 may cover the semiconductor layer SEL and be made of insulating materials such as silicon nitride and silicon oxide, etc.

[0055] As in Fig. 6 and Fig. As shown in Figure 9, the first gate layer GAT1 may be disposed on a surface of the first gate insulating layer GI1 remote from the substrate SU. Metal, some metal oxides, or another conductive material may be used as the material of the first gate layer GAT1, and the first gate layer GAT1 may include the respective gate lines GAL and the first electrode plate Cst1 of the storage capacitor Cst.

[0056] The second gate insulating layer GI2 may cover the first gate layer GAT1 and be made of insulating materials such as silicon nitride and silicon oxide, etc., and the material of the second gate insulating layer GI2 may be the same as that of the first gate insulating layer GI1.

[0057] As in Fig. 7 and Fig. As shown in Figure 9, the second gate layer GAT2 may be disposed on a surface of the second gate insulating layer GI2 remote from the substrate SU. Metal, some metal oxides, or other conductive materials may be used as the material of the second gate layer GAT2, and the second gate layer GAT2 may include a first reset signal line VIL1, a second reset signal line VIL2, and a second electrode plate Cst2.

[0058] If the second reset signal line VIL2 connected to the pixel circuit PC of the n-th row is multiplexed into the first reset signal line VIL1 connected to the pixel circuit PC of the n+1-th row, the semiconductor layer SEL may be connected between the channel of the second reset transistor T7 of the pixel circuit PC of the n-th row and the channel of the first reset transistor T1 of the pixel circuit PC of the n+1-th row to the first reset signal line VIL1.

[0059] In some embodiments of the present disclosure, the compensation transistor T2 may be a dual-gate transistor and have two channels. The second gate layer GAT2 may also include a shielding portion SL, which may be provided between the first reset signal line VIL1 and the second electrode plate Cst2 and overlaps with the region between the two channels of the compensation transistor T2, thereby reducing the current leakage of the compensation transistor T2.

[0060] The dielectric layer ILD may cover the second gate layer GAT2, and the dielectric layer ILD may also be made of insulating materials such as silicon nitride and silicon oxide, etc.

[0061] As in Fig. 8 and Fig. As shown in Figure 9, the source-drain layer SD is provided on a surface of the dielectric layer ILD remote from the substrate SU. The source-drain layer SD may be made of metal, some metal oxides, or other conductive materials. The first source-drain layer SD may include a data line DAL and a power line VDL, and may also include a transmission part SDc. The transmission part SDc and the semiconductor layer SEL between the channel of the second reset transistor T7 of the pixel circuit PC of the nth row and the channel of the first reset transistor T1 of the pixel circuit PC of the n+1th row overlap and are connected via a contact hole.Meanwhile, the transmission part SDc is connected via a contact hole to the first reset signal line VIL1, which has been multiplexed into the second reset signal line VIL2 in the above text, so that a reset signal can be transmitted to the second reset transistor T7 of the n-th row and the first reset transistor T1 of the n+1-th row.

[0062] As in Fig. 3, Fig. 10, Fig. 13 and Fig. 14, the gate driver circuit GGOA may comprise a plurality of cascaded gate shift register units GGOAs and may provide signals to a plurality of rows of gate lines GAL to control the transistors connected to a plurality of rows of gate lines GAL to be turned on sequentially, while providing the data signals to the pixel circuits PC connected thereto through the data lines to generate the gray level voltages required by the respective gray levels for displaying images, thus controlling the brightness of the light-emitting element and further displaying a frame of the image.

[0063] The number of gate driver circuits GGOA may be one, and they are located on one side of the pixel area AA. The gate shift register unit GGOA may drive at least one row of pixel circuits PC, or the number of gate driver circuits GGOA may be two, and they are located on two sides of the pixel area AA. The gate shift register units GGOA of the two gate driver circuits GOA may be provided in a one-to-one correspondence, and the pixel circuits PC of the same row can simultaneously receive signals provided by the corresponding gate shift register units GGOA on both sides.

[0064] As in Fig. 10, the gate shift register unit GGOAs comprises eight transistors and two capacitors, including an input transistor T1, a first control transistor T2, a second control transistor T3, an output control transistor T4 and a gate output transistor T5, a first noise suppression transistor T6, a second noise suppression transistor T7, a voltage stabilizing transistor T8, a first capacitor C1 and a second capacitor C2.

[0065] The gate shift register units GGOAs are cascaded. A first terminal of the input transistor T21 in the first-stage gate shift register unit GGOAs is connected to an input terminal IN, which is connected to a trigger signal line GSTV to receive a trigger signal STV as an input signal; while a first terminal of the input transistor T1 in the gate shift register units GGOAs of the respective other stages is electrically connected to an output terminal of the last-stage gate shift register unit GGOAs to receive an output signal output from the output terminal GOUT of the last-stage gate shift register unit GGOAs as an input signal, thereby enabling a shift output to perform line-by-line scanning of the pixel circuits PC in the display area.

[0066] As in Fig. As shown in Figure 10, the gate electrode of the input transistor T1 is connected to a first clock signal terminal CK (the first clock signal terminal CK is connected to a first sub-clock signal line GCK) to receive the first clock signal, a second terminal of the input transistor is connected to the input terminal IN, and the first terminal of the input transistor T1 is connected to the first node N1. For example, when the gate shift register unit GGOAs is the first-stage gate shift register unit GGOAs, the input terminal IN is connected to the trigger signal line GSTV to receive the trigger signal; when the gate shift register unit GGOAs is a gate shift register unit GGOAs of the respective other stages except the first-stage gate shift register unit GGOAs, the input terminal IN is connected to the output terminal GOUT of the gate shift register unit GGOAs of its upper stage.

[0067] A gate electrode of the first control transistor T2 is connected to the first node N1, a second pole of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, a first pole of the first control transistor T2 and the second node N2 are connected, a gate electrode of the second control transistor T3 and the first clock signal terminal CK are connected to receive the first clock signal, a second pole of the second control transistor is connected to the second drive current line VGL to receive a second voltage, a first pole of the second control transistor T3 is connected to the second node N2.

[0068] A gate electrode of the output control transistor T4 is connected to the second node N2, a first pole of the output control transistor T4 is connected to the first drive current line VGH to receive a first voltage, a second pole of the output control transistor T4 is connected to the output terminal GOUT.

[0069] A first pole of the first capacitor is connected to the second node N2, a second pole of the first capacitor C1 is connected to the first driver current line VGH.

[0070] A gate electrode of the output transistor T5 is connected to the third node N3, a first pole of the output transistor T5 is connected to a second clock signal terminal CB, a second pole of the output transistor T5 is connected to the output terminal GOUT.

[0071] A first pole of the second capacitor C2 is connected to the third node N3, a second pole of the second capacitor C2 is connected to the output terminal GOUT.

[0072] A gate electrode of the first noise suppression transistor T6 is connected to the second node N2, a first pole of the first noise suppression transistor T6 is connected to the first drive power line VGH to receive the first voltage, a second pole of the first noise suppression transistor T6 is connected to a second pole of the second noise suppression transistor T7.

[0073] A gate electrode of the second noise suppression transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to a second sub-clock signal line GCB) to receive the second clock signal, a first pole of the second noise suppression transistor T7 is connected to the first node N1.

[0074] A gate electrode of the voltage stabilizing transistor T8 is connected to the second drive current line VGL to receive the second voltage, a second pole of the voltage stabilizing transistor T8 is connected to the first node N1, a first pole of the voltage stabilizing transistor T8 is connected to the third node N3.

[0075] For all the transistors in the gate shift register unit GGOAs in Fig. 10, P-type transistors are explained as an example. That is, the respective transistors are turned on when the gate electrode is connected to a low level; while they are turned off when connected to a high level. A first terminal of the transistor can be a source electrode, and a second terminal of the transistor can be a drain electrode.

[0076] Regarding the working principle of the gate scan gate shift register unit, reference can be made to the ideas in the field, which will not be explained in detail here.

[0077] It should be noted that the reference numerals (T1-T8) of the transistors and capacitors of the circuit of the above gate shift register unit GGOAs and the reference numerals (T1-T4) of the transistors of the pixel circuit PC are the same in the above text, only the same reference numerals are used for different circuits, and the same reference numerals of the transistors do not stand for the same transistors.

[0078] For the aforementioned gate drive circuit GGOA, the channels of their respective transistors may be located on the semiconductor layer SEL, the gate electrode of each transistor and one electrode plate of the capacitor may be located on the first gate layer GAT1, and another electrode plate of the capacitor may be located on the second gate layer GAT1. The first drive power line VGH, the second drive power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK, and the second sub-clock signal line GCB are located on the source-drain layer SD. And the first drive power line VGH, the second drive power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK, and the second sub-clock signal line GCB are all located on a side of the gate drive circuit GGOA remote from the display area.

[0079] As in Fig. 3, Fig. 16 to Fig. As shown in Figure 18, the bus L is located in the bus area LA and is connected to the output area BA. The bus L may include at least a power bus LVD and a reset bus LVI. Each power line VDL is connected to the power bus LVD to simultaneously transmit the first power supply signal VDD. The reset bus LVI may be connected to the first reset signal line VIL1 and the second reset signal line VIL2 to transmit the reset signal VI. At the same time, the bus L may also include a test bus LT that can transmit test signals for testing the display effect of the display panel. Accordingly, the peripheral area may also include a test unit connected to the test bus LT to send test signals. The test bus LT may be located on the side of the reset bus LVI remote from the display area.The number of test buses LT may be multiple, for example, two, and they may be spaced apart on the side of the reset bus LVI remote from the display area. The power bus LVD may be located on the side of the reset bus LVI close to the display area.

[0080] The space occupied by the LVD power bus can be reduced by shortening it, thus reducing the size of the peripheral area. For example, In some embodiments of the present disclosure, as in Fig. As shown in Figure 3, the control region WA of the driver backplane may include an output region BA extending along the row direction X and spaced apart from the pixel region AA along the column direction Y. The output region BA may be provided with a bonding region. The bus L, the data line DAL, the power line VDL, and the aforementioned first drive power line VGH, the second drive power line VGL, the trigger signal line GSTV, the sub-clock signal line GCK, and the second sub-clock signal line GCB may all be connected to the bonding region of the output region BA to be bonded to the flexible circuit board via the bonding region. The flexible circuit board may be provided with a control chip and bonded to a control board, whereby the display panel can be controlled via the control chip and the control board, and functions such as image display and testing can be realized.

[0081] Furthermore, the bus area LA, as in Fig. 3 and Fig. 17, in some embodiments of the present disclosure, include: side bus regions LA1 distributed on two sides of the pixel region AA along the row direction, and a connection bus region LA2 connected between the two side bus regions LA1, wherein the connection bus region LA2 may be located between the output region BA and the pixel region AA. Both the reset bus LVI and the test bus LT may extend from the one connection bus region LA2 to the two side bus regions LA1. The width of the reset bus LVI may be larger than the width of other buses L, and its power bus LVD may be the bus L of the respective buses L closest to the pixel region AA, i.e., no other bus L exists between the power bus LVD and the pixel region AA.The power bus LVD can only be located in the interconnect bus area LA2 and does not extend into the side bus area LA1, which benefits the reduction of the width of the peripheral area in the X-row direction, thereby increasing the picture-to-body ratio.

[0082] In other embodiments of the present disclosure, as in Fig. 13, Fig. 14 and Fig. As shown in Figure 17, the power bus LVD may extend into the side bus area LA1 and surround outside the pixel area AA.

[0083] As in Fig. 11 to Fig. 15, a plurality of gate interconnection lines GCL are provided, and a gate shift register unit GGOAs can be connected to one gate interconnection line GCL. One gate interconnection line GCL can be connected to at least one gate line GAL, so that signals can be input to the pixel circuit PC via the gate interconnection line GCL and the gate line GAL. At the same time, at least a portion of the gate interconnection line GCL is located on a different layer than the gate interconnection GAL and is connected to the gate line GAL via the contact hole. That is, during the connection of the gate interconnection line GCL to the gate line GAL, mediation through a contact hole is necessary, but the presence of the contact hole leads to the increase in the impedance of the gate interconnection line GCL, facilitating the enhancement of the static electricity shielding capability.In addition, the pulse signal transmitted by the gate connection line GCL, which is connected to the first gate line GAL1, the second gate line GAL2, and the fourth gate line GAL4, has a relatively high frequency to meet the different requirements of the reset stage, the write stage, and the light emission stage. However, these high-frequency pulse signals are easily affected by static electricity.

[0084] By increasing the resistance of at least part of the gate connection line GCL, the interference caused by static electricity can be reduced.

[0085] Due to the multiplexing approach of the gate line GAL in the above embodiment of the pixel circuit PC in the above text, for example, the first gate line GAL1 connected to the pixel circuit PC of the n-row and the second gate line GAL2 of the first reset transistor T1 connected to the pixel circuit PC of the n+1-row can be connected to the same gate shift register unit GGOAs through the same gate connection line GCL. This connection method can enable the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC to be connected to the same gate shift register unit GGOAs through the same gate connection line GCL. Based on this connection method, a specific implementation of the gate connection line GCL is exemplified as follows: As in Fig. 11 to Fig. As shown in Figure 15, the gate connection line GCL may include a first connection part GCL1 and a second connection part GCL2 that are connected to each other. The first connection part GCL1 may be connected to the gate shift register unit GGOAs (output terminal GOUT) and pass through the bus area LA. The second connection part GCL2 may be located in the pixel area AA or the bus area LA and connected to at least one gate line GAL. At least one of the first connection part GCL1 and the second connection part GCL2 is located in a different layer than the gate line GAL.

[0086] In embodiments of the first type of the present disclosure, as in Fig. 11 and Fig. As shown in Figure 14, the first connection part GCL1 and the gate line GAL are arranged on the same layer, while the second connection part GCL2 and the gate line GAL are arranged on different layers. For example, the first connection part GCL1 is arranged on the first gate layer GAT1; the second connection part GCL2 can be arranged on the source-drain layer SD or the second gate layer GAT2, provided it can be connected to the gate line GAL through a contact hole.

[0087] In a first embodiment of the first type, as in Fig. 11, Fig. 13 and Fig. As shown in Figure 14, the first connection part GCL1 may extend along the row direction X and be connected to the output terminal of the gate shift register unit GGOAs via a contact hole, and is connected to the second gate line GAL2. Since the first connection part GCL1 and the gate line GAL are arranged on the same layer, they can be formed into an integrated one-piece structure with the second gate line GAL2.

[0088] The second connection part GCL2 is located on the source-drain layer SD and extends along the column direction Y. The second connection part GCL2 can be connected to the first connection part GCL1 via the contact hole and is connected to the first gate line GAL1 through the contact hole. The second connection part GCL2 can be located in the display area and between the reset bus LVI and a column of pixel circuits PC closest to the bus area LA, i.e., the second connection part GCL2 is located on a side of the reset bus LVI remote from the test bus.

[0089] Furthermore, the first connection part GCL1 passes through the bus area LA along the row direction X and overlaps with the respective buses L. The second connection part GCL2 is arranged adjacent to the reset bus LVI, that is, there is no wiring between the reset bus LVI and the second connection part GCL. The distance between the second connection part GCL2 and the reset bus LVI along the row direction X can be 3 µm-10 µm, for example, the distance can be 4.5 µm. On the one hand, a parasitic capacitance can be prevented from increasing excessively, which results from too close a distance between the second connection part GCL2 and the reset bus LVI, thus facilitating the reduction of power consumption. On the other hand, the width of the peripheral area can be prevented from increasing excessively, which results from too large a distance and does not benefit the reduction of the frame width.

[0090] The width of the second connection part GCL2 is 20-40% of the width of the reset bus. For example, the width of the second connection part GCL2 is 3.5 µm, and the width of the reset bus is 10 µm.

[0091] In a second embodiment of the first type, as in Fig. As shown in Figure 12, the connection method of the first connection part GCL1 and the second connection part GCL2, and the film layer where they are located, are the same as in the above-mentioned first embodiment and will not be explained in detail here. The difference is that the second connection part GCL2 can be located in the bus area LA, but to avoid a short circuit with the bus L, it can be arranged at a distance from the bus L, e.g., between a test bus LT and the reset bus LVI.

[0092] In a third embodiment of the first type, as in Fig. As shown in Figure 15, the connection method of the first connection part GCL1 and the second connection part GCL2 is the same as that in the above-mentioned first and second embodiments and will not be explained in detail here. The difference is that the second connection part GCL2 is located on the second gate layer GAT2 and extends along the column direction Y, and the second connection part GCL2 can be connected to the first connection part GCL1 through a contact hole and to the first gate line GAL1 through a contact hole. Accordingly, the second connection part GCL2 can be located in the display area and between the reset bus LVI and a column of pixel circuits PC closest to the bus area LA; or it can be located in the bus area LA and spaced apart from the bus L.

[0093] In a third embodiment of the first type, as in Fig. As shown in Figure 15, the first connection part GCL1 may still be located on the second gate layer GAT2, while the second connection part GCL2 is located on a same layer as the gate line, i.e., on the first gate layer GAT1. The first connection part GCL1 may extend through the bus area LA along the row direction X and is connected to the gate shift register unit GOA through a contact hole, and is connected to the second connection part GCL2 and the second gate layer GAT2 through a contact hole. The second connection part GCL2 may be connected to the first gate line GAL1.

[0094] In a fourth embodiment of the first type, as in Fig. 14, based on the above-described first embodiment, two ends of the second connection part GCL2 may be connected to the first gate line GAL1 and the second gate line GAL2 through contact holes, respectively, and the second connection part GCL2 may be connected to the first connection part GCL1 through one contact hole, that is, the second connection part GCL2 is provided with at least three contact holes.

[0095] In a fifth embodiment of the first type, the circuit layer CL may further comprise a light-shielding layer, which may be disposed on one side of the substrate SU and covered by an insulating layer. The semiconductor layer SEL may be disposed on a side of the insulating layer remote from the substrate SU. The light-shielding layer may have a light-shielding portion for shielding an overlap with the channel of the driver transistor to prevent light from irradiating the driver transistor. The second connection part GCL2 may be located on the light-shielding layer.

[0096] In other embodiments of the first type, the gate connection line GCL may not be limited to the above-described structures of the first connection part GCL1 and the second connection part GCL2, and may include more sections, at least a part of which may be located on the first gate layer GAT1, and the others may be located on at least one of the second gate layer GAT2 and the source-drain layer SD, as long as the connection between the gate shift register unit GGOAs and the first gate line GAL1 and the second gate line GAL2 can be realized and no direct contact with the bus is made. This is not listed individually.

[0097] In embodiments of a second type of the present disclosure, the gate connection line GCL is located on a same layer. For example, its first connection part GCL1 and its second connection part GCL2 are provided on a same layer, but on different layers from the gate line and the bus, so they must be connected to the gate lines via contact holes.

[0098] In a first embodiment of the second type, as in Fig. As shown in Figure 15, the gate interconnection line GCL is located on the second gate layer GAT2, and its first interconnection part GCL1 may extend along the row direction X and pass through the bus area LA, and is connected to the gate shift register unit GGOAs, and is connected to the second gate line GAL2 via a contact hole. The second interconnection part GCL2 and the first interconnection part GCL1 are an integrated structure and extend along the column direction Y and are connected to the first gate line GAL1 via contact holes.

[0099] In a second embodiment of the second type, the circuit layer CL may further comprise a light-shielding layer, which may be arranged on one side of the substrate and covered by an insulating layer. The semiconductor layer SEL may be arranged on a side of the insulating layer remote from the substrate SU. The light-shielding layer may have a light-shielding portion for shielding an overlap with the channel of the driver transistor to prevent light from irradiating the driver transistor. The gate connection line GCL may be located on the light-shielding layer. Regarding its specific structure and connection method, reference can be made to the first embodiment of the second type, which will not be described in detail here.

[0100] Furthermore, as in Fig. 11, Fig. 12 and Fig. As shown in Figure 15, the circuit layer CL further includes a light emission control circuit EGOA, which may be provided in the control region WA to control the on / off timing of the light emission control transistor. The light emission control circuit EGOA includes a plurality of light emission shift register units EGOAs cascaded along the column direction Y. The structure and working principle of the light emission shift register units EGOAs are similar to the gate shift register units GGOAs; they can control the light emission control transistors of the respective rows of pixel circuits PC to be sequentially turned on and off. For example, the light emission shift register unit EGOAs may be connected to the third gate line GAL3 and output the light emission control signal EM to the third gate line GAL3.In some embodiments of the present disclosure, the light-emitting shift register unit EGOAs may be connected to the third gate line GAL3 connected to two rows of pixel circuits PC.

[0101] For example, in some embodiments, as shown in Fig. 3, the gate drive circuit GGOA is located on a side of the gate drive circuit GGOA remote from the pixel region AA, that is, an outer side of the gate drive circuit GGOA, and is distributed at a distance from the gate drive circuit GGOA. Furthermore, both the number of light emission control circuits EGOA and the number of gate drive circuits GGOA are two, and the gate drive circuits GGOA are separated on two sides of the pixel region AA, and the light emission control circuit EGOA is located on the outer side of the gate drive circuit GGOA. One row of pixel circuits PC can be connected to two light-emitting shift register units EGOAs and two gate shift register units GGOAs to prevent an excessive difference in response speeds of the same row of pixel circuits PC caused by signal attenuation.

[0102] In some embodiments, as in Fig. 16, both the number of the light emission control circuit EGOA and the number of the gate drive circuit GGOA may be one, and they may be separated on two sides of the pixel area AA as long as signals can be transmitted to each row of pixel circuits PC, so that the shortening of the width of the control area is facilitated and thus the frame is reduced.

[0103] In order to realize the connection between the light-emitting shift register unit EGOAs and the third gate line GAL3, the circuit layer CL may further comprise a plurality of light-emitting connection lines ECL, a light-emitting shift register unit EGOAs is connected to a light-emitting connection line ECL, at least a portion of the light-emitting connection line ECL is located on a different layer than the third gate line GAL3 and is connected to a third gate line GAL3 via a contact hole.

[0104] The inventor discovered that although the illumination time of the light-emitting element LD is longer than the reset and write times, and the frequency of the light-emitting control signal EM serving as a pulse signal is lower than the frequencies of the scanning signal GA and the reset control signals RE1 and RE2, the light-emitting control signal EM could still be affected by static electricity. Therefore, a contact hole can be introduced between the light-emitting shift register unit EGOAs and the third gate line GAL3 to increase the impedance and thus improve the anti-static capability.

[0105] Analogous to the structure of the aforementioned gate connection line GCL, at most a portion of the light-emitting connection line ECL is located on the same layer as the gate line GAL, so a contact hole is required before a connection to the third gate line can be made. Thus, by introducing a contact hole, the resistance can be increased and the ability to withstand static electricity is improved.

[0106] As in Fig. 11, Fig. 12 and Fig. As shown in Figure 15, the light-emitting interconnection line CGL may include a third interconnection part CGL1 and a fourth interconnection part CGL2. The third interconnection part CGL1 is provided on the same layer as the gate line GAL, that is, it is located on the first gate layer GAT1. The third interconnection part CGL1 is connected to the light-emitting shift register unit EGOAs and passes through the bus region LA in one direction. The fourth interconnection part CGL2 is located on the source-drain layer SD or the second gate layer GAT2 and is connected to the third interconnection part CGL1 and the third gate line GAL3 via a contact hole.

[0107] In addition, the light emission connection line ECL may be located on the second gate layer GAT2 and is connected to the light emitting shift register unit EGOAs and the third gate line GAL3 via the contact hole.

[0108] Regarding the structure and connection method of the light-emitting interconnection line ECL, refer to the gate interconnection line GCL in the above text. For the third interconnection part ECL1, refer to the first interconnection part GCL1. For the fourth interconnection part ECL2, refer to GCL2, as long as a contact hole can increase the resistance. No detailed examples are given here. However, it should be noted that the light-emitting interconnection line ECL must not be in direct contact with the bus L and the gate interconnection line GCL to avoid a short circuit.

[0109] Furthermore, in the above-described embodiments of the second type, the reset signal lines (the second reset signal line VIL2 connected to the pixel circuit PC of the n-th row and the first reset signal line VIL1 connected to the pixel circuit PC of the n+1-th row) extend along the direction X and are connected to the reset bus LVI through the reset connection line RCL. In order to avoid intersection of the fourth connection part CGL2 and the second connection part GCL2 with the reset connection line RCL, the reset connection line RCL may be located on the first gate layer GAT1, and the reset connection line RCL and the reset bus LVI are connected. The reset signal line may be located on the second gate layer GAT2 and is connected to the reset connection line RCL through a contact hole.The reset connection line RCL overlaps with the fourth connection part CGL2 and the second connection part GCL2 and can be maintained insulating therefrom.

[0110] Of course, the connection between the reset signal line and the reset bus LVI can also be made by means of a reset connection line RCL of another foil layer, as long as the short circuit with the fourth connection part CGL2 and the second connection part GCL2 can be avoided.

[0111] As in Fig. 2, an embodiment of the present disclosure provides a display panel that may include a driver backplate BP and a light-emitting element LD, wherein: The driver back plate BP may be a driver back plate BP in any of the above embodiments and its structure will not be described in detail here.

[0112] The light-emitting element LD can be arranged on a side of the circuit layer CL remote from the substrate SU and is connected to the pixel circuit PC. There may be multiple light-emitting elements LD, and each light-emitting element LD can be connected to a pixel circuit PC; the same pixel circuit PC can be connected to one or more light-emitting elements LD. The light-emitting element LD can be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a micro-LED, or a mini-LED, etc., and can include a first electrode ANO, a second electrode CAT, and a light-emitting layer EL located between the first electrode ANO and the second electrode CAT.

[0113] An OLED is cited as an example. A first electrode ANO may be arranged on a surface of the circuit layer CL remote from the substrate SU, e.g., a surface of a second planarization layer PLN2 remote from the substrate SU. The light-emitting layer EL may comprise: a cavity injection layer, a cavity transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer, which are stacked in a direction away from the driver backplate BP. The respective light-emitting elements LD may share a second electrode CAT, i.e.The second electrode CAT may be a continuous full-layer structure, and the second electrode CAT may extend to the peripheral region and receive the second power supply signal VSS. The first electrode ANO is distributed in an array to ensure that the respective light-emitting elements LD can emit light independently. To limit the light emission range of the light-emitting elements LD and prevent crosstalk, a pixel definition layer PDL may be further provided on the surface where the first electrode ANO is provided. The pixel definition layer PDL may be provided with an opening exposing the respective first electrodes ANO. The light-emitting layer EL is stacked with the first ANO within the opening.

[0114] The respective light-emitting elements LD can at least commonly use a light-emitting material layer so that the respective light-emitting elements LD emit light in the same color. To enable a multi-color display, a color film layer can be provided on a side of a light-emitting element LD remote from the substrate SU. The light filter portions in the color film layer associated with the respective light-emitting elements LD enable a multi-color display. Of course, the light-emitting material layers of the respective light-emitting elements LD can also be independent, so that the respective light-emitting elements LD can directly emit monochromatic light, and the light emission colors of different light-emitting elements LD can differ, thus enabling a multi-color display.

[0115] In addition, the display panel may also include an encapsulation layer covering each light-emitting element LD, and may further include other film layers such as a touch layer and a transparent cover plate disposed on a side of the encapsulation layer remote from the substrate SU. These will not be described in detail here.

[0116] The present disclosure also provides a display device that may include a display panel of any of the above-mentioned embodiments. The display panel is a display panel according to any of the above-mentioned embodiments. Regarding its specific structure and advantageous effects, reference may be made to the above-mentioned embodiments of the display panel in the foregoing text. This will not be described in detail here. The display device of the present disclosure may be an electronic device with a display function, such as a mobile phone, a tablet computer, or a television. This will not be listed individually.

[0117] Those skilled in the art, after considering the description and practicing the invention disclosed herein, can readily devise other implementations of the present application. This application is intended to cover all variations, uses, or adaptations of the disclosure that adhere to the general principles of the disclosure and incorporate common knowledge or conventional technical means not disclosed in the present disclosure. The description and embodiments are to be considered exemplary only; the true scope and spirit of the present disclosure is set forth in the appended claims.

Claims

[1] A driver backplane comprising a pixel region and a control region outside the pixel region, the control region comprising a circuit region and a bus region separated between the circuit region and the pixel region; the driver backplane comprising a substrate and a circuit layer provided on one side of the substrate, and the circuit layer comprising: multiple pixel circuits distributed in an array in the pixel area; a plurality of gate lines extending along a row direction and distributed along a column direction, wherein a row of the pixel circuit is connected to at least one of the gate lines; a gate drive circuit provided in the control region and comprising a plurality of gate shift register units cascaded along the column direction; a bus provided in the bus region and located at least partially between the gate driver circuit and the pixel region; a plurality of gate connection lines, wherein one of the gate shift register units is connected to one of the gate connection lines, at least a portion of one of the gate connection lines is located in a different layer than the gate line and is connected to at least one of the gate lines through a contact hole; the gate connection line is provided in isolation from the bus. [2] The driver backplate according to claim 1, wherein the gate connection line comprises a first connection part and a second connection part connected to each other, the first connection part is connected to the gate shift register unit and passes through the bus region, the second connection part is distributed spaced apart from the bus and the pixel circuit and is connected to at least one of the gate lines; at least one of the first connection part and the second connection part and the gate line are on different layers. [3] The driver backplate according to claim 2, wherein the first connecting part and the gate line are arranged on one and the same layer, the second connecting part and the gate line are arranged on different layers. [4] The driver backplate according to claim 2, wherein the first connecting part and the second connecting part are arranged on one and the same layer, and are located on different layers than the gate line and the bus. [5] The driver backplate according to any one of claims 2-4, wherein the circuit layer further comprises a power line, a data line, and a reset signal line, and both the power line and the data line extend along the column direction and are distributed along the row direction, the power line and the data line, and the bus are arranged on one and the same layer; the reset signal line extends along the row direction and is distributed along the column direction, the reset signal line and the gate line, and the bus are located on different layers; the gate line comprises a first gate line and a second gate line; the pixel circuit comprises a storage capacitor and a plurality of transistors, wherein the transistors comprise a driver transistor, a write transistor, a compensation transistor, and a first reset transistor; gate electrodes of the compensation transistor and the write transistor are connected to the first gate line; a first terminal of the driver transistor is connected to the power line, and a second terminal is connected to a light-emitting element; the compensation transistor is connected to the second terminal and the gate electrode of the driver transistor; a first terminal of the write transistor is connected to the data line, and a second terminal is connected to the first terminal of the driver transistor; a gate electrode of the first reset transistor is connected to the second gate line, a first terminal is connected to the reset signal line, and a second terminal is connected to the gate electrode of the driver transistor;a first electrode plate of the storage capacitor is connected to the gate electrode of the driver transistor and a second electrode plate is connected to the power line; a first gate line connected to the pixel circuit in the n-th row and a second gate line connected to the pixel circuit in the n+1-th row are connected to the same gate shift register unit via the same gate connection line. [6] The driver backplate of claim 5, wherein the circuit layer comprises: a semiconductor layer provided on one side of the substrate and comprising a channel of one of the respective transistors; a first gate insulating layer covering the semiconductor layer; a first gate layer provided on the surface of the first gate insulating layer remote from the substrate and comprising the gate line, the first electrode plate, and the gate electrode of the respective transistor; a second gate insulating layer covering the first gate layer; a second gate layer provided on the surface of the second gate insulating layer remote from the substrate and including the second electrode plate and the reset signal line; a dielectric layer covering the second gate layer; a source-drain layer provided on a side of the dielectric layer remote from the substrate and comprising the bus, the power line and the data line. [7] The driver backplate of claim 6, wherein when the first connecting part is arranged on a same layer of the gate line and is located on a different layer than the second connecting part: the first connecting part is connected to the second gate line; the second connecting part is located on the source-drain layer and extends along the column direction, the second connecting part is connected to the first gate line via a contact hole. [8] Driver backplate according to claim 6, wherein when the first connecting part and the second connecting part are arranged on one and the same layer: the gate connection line is located on the second gate layer. [9] The driver backplate according to claim 8, wherein the first connection part is connected to the gate shift register unit and the second gate line through a contact hole; the second connection part extends along a column direction and is connected to the first connection part, the second connection part is connected to the first gate line via a contact hole. [10] The driver backplate of claim 6, wherein the gate line further comprises a third gate line; the pixel circuit further comprises a second reset transistor, a first light emission control transistor, and a second light emission control transistor; a gate electrode of the first light emission control transistor is connected to a third gate line, a first terminal is connected to the power line, and a second terminal is connected to the first terminal of the driver transistor; a gate electrode of the second light emission control transistor is connected to the third gate line, a first terminal is connected to the second terminal of the driver transistor, and a second terminal is connected to the light-emitting element; the gate electrode of the second reset transistor is connected to the first gate line, a first pole is connected to the reset signal line, and a second pole is connected to the second pole of the second light emission control transistor. [11] The driver backplate of claim 10, wherein the circuit layer further comprises: a light emission control circuit provided in the control area and comprising: a plurality of light-emitting shift register units cascaded along the column direction; a plurality of light emission interconnections, wherein one of the light-emitting shift register units is connected to one of the light emission interconnections, at least a portion of the light emission interconnection is located on a different layer than the third gate line and is connected to the third gate line via a contact hole. [12] The drive backplane according to claim 11, wherein the light emission connection line is located on the second gate layer and is connected to the light emitting shift register unit and the third gate line via a contact hole. [13] The driver backplate according to claim 11, wherein the light emission connection line comprises a third connection part and a fourth connection part, the third connection part being arranged on a same layer of the gate line and connected to the light-emitting shift register unit, the third connection part passing through the bus region along the direction; the fourth connection part being arranged on the source-drain layer or the second gate layer and connected to the third connection part and the third gate line via a contact hole. [14] The driver backplate of claim 11, wherein the second reset transistor of the pixel circuit of the n-th row is connected to the second gate line of the pixel circuit of the n+1-th row. [15] The driver backplane of any of claims 6-13, wherein the bus comprises a test bus, a reset bus and a power bus located on the source-drain layer, and the power line is connected to the power bus, the reset signal line is connected to the reset bus. [16] The driver backplane according to claim 15, wherein the reset bus is located between the test bus and the pixel region, the second connection part is located on a side of the reset bus remote from the test bus and is provided adjacent to the reset bus; a distance between the second connection part and the reset bus along the row direction is 3 µm-10 µm. [17] The driver backplate of claim 15, wherein the width of the second connection part is 20-40% of the width of the reset bus. [18] The driver backplane of claim 15, wherein the control region of the driver backplane comprises an output region extending along the row direction and spaced apart from the pixel region along the column direction; the bus, the data line, and the power line are all connected to the output region; the bus region comprises: side bus regions distributed on two sides of the pixel region along the row direction, and a connection bus region connected between the two side bus regions; wherein the connection bus region is located between the output region and the pixel region; the power bus is located in the connection bus area. [19] A display panel comprising a driver backplate according to any one of claims 1-18. [20] A display device comprising the display panel according to claim 19.

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