METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE

Abstract

A metal-insulator-metal (MIM) capacitor comprises a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connector electrically connected to the top electrode, a vertically extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connector electrically connected to the vertically extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a cup opening in a dielectric region and comprises a laterally extending insulator cup base formed on the bottom electrode and a vertically extending insulator cup sidewall extending upward from the laterally extending insulator cup base.The top electrode connection element and the bottom electrode connection element are formed in an upper metal layer.

Description

RELATED PATENT APPLICATION

[0001] This application claims priority to commonly owned U.S. Provisional Patent Application No. 63 / 349,703, filed June 7, 2022, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD

[0002] The present disclosure relates to metal-insulator-metal (MIM) capacitors formed in integrated circuit devices, and more particularly to an MIM capacitor module formed in an integrated circuit device. BACKGROUND

[0003] A metal-insulator-metal (MIM) capacitor is a capacitor made up of a metal top electrode, a metal bottom electrode, and an insulator (dielectric) sandwiched between the two electrodes.

[0004] MIM capacitors are important components in many electrical circuits, including many analog, mixed-signal, and radio-frequency circuits using complementary metal oxide semiconductor (RF CMOS). MIM capacitors generally provide better performance than alternatives such as POP (poly-oxide-poly) and MOM (metal-oxide-metal lateral flux) capacitors due to lower resistance, better matching for analog circuits (e.g., matching device properties such as resistance and capacitance), and / or better signal-to-noise characteristics.

[0005] MIM capacitors are usually constructed between two connecting metal layers (e.g. aluminum layers) which are called metal layers M x and M x+1 For example, an MIM capacitor can be manufactured using an existing metal layer M xas a bottom electrode, whereby an insulator and a top electrode are formed above the bottom electrode and an overlying metal layer M x+1 is connected to the top and bottom electrodes by vias to form an MIM capacitor module. The top plate, which is sandwiched between the two metal layers M x and M x+1 formed, can be made of a different metal than the metal layers M x and M x+1 The metal layers M x and M x+1 can be made of aluminum, for example, while the upper plate can be made of titanium / titanium nitride (Ti / TiN), tantalum / tantalum nitride (Ta / TaN) or tungsten (W).

[0006] The top electrode typically has a higher resistance than the bottom electrode because the top electrode can be limited by, for example, thickness constraints and the selected material, which limits the performance of conventional MIM capacitors. MIM capacitors typically have very tight process margins, especially for the metal etch used to form the top electrode.

[0007] Conventional MIM capacitors are also typically expensive to manufacture. MIM capacitors typically require multiple additional mask layers and many additional process steps.

[0008] In addition, in MIM capacitors made of aluminum composite (i.e. where the metal layers M x and M x+1Aluminum interconnect layers), the aluminum bottom electrode may be prone to the formation of hillocks on top of the bottom electrode, e.g., as a result of high-temperature processing of aluminum, a metal with a low melting point. Hillocks formed on the bottom electrode can negatively or unpredictably affect the breakdown voltage of the MIM capacitor.

[0009] There is a need for MIM capacitors that can be manufactured at lower cost, with few or no additional mask layers and / or with improved breakdown voltage. SUMMARY

[0010] A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator can formed on the bottom electrode, a top electrode formed in an opening defined by the insulator can, a top electrode interconnection element electrically connected to the top electrode, a vertically extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode interconnection element electrically connected to the vertically extending bottom electrode contact. The bottom electrode is formed in a lower metal layer.The insulator cup is formed in a well opening in a dielectric region of a via layer and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode interconnection element and the bottom electrode interconnection element may be formed in an upper metal layer above the via layer.

[0011] As used herein, an "MIM capacitor module" includes the basic elements of an MIM capacitor, e.g., an insulator (dielectric) sandwiched between conductive electrodes (e.g., conductive plates), and may also include certain related elements, e.g., conductive elements that provide electrical contact to the conductive electrodes.

[0012] In some examples, the top electrode is capacitively coupled to the bottom electrode via the laterally extending insulator can base. The laterally extending sidewall of the insulator can may be surrounded in lateral directions by the dielectric region, which may substantially prevent capacitive coupling between the top electrode and other conductive structures (e.g., the bottom electrode and / or the vertically extending bottom electrode contact) through the vertically extending sidewall of the insulator can. Thus, the structure of the MIM capacitor module effectively defines a planar capacitor between the top electrode and the bottom electrode through the laterally extending insulator can base. This planar capacitor defined by the structure of the MIM capacitor module may be suitable or advantageous for certain applications, e.g., for use in analog circuits.

[0013] In some examples, a method of forming the MIM capacitor module includes depositing a dielectric region including a base dielectric component and a sacrificial dielectric component over the base dielectric component, wherein the sacrificial dielectric component enables the removal of non-planarized recessed regions (e.g., "plug recesses") on top of the respective metal structures (e.g., vertical tungsten structures) through a planarization process to thereby provide planarized top surfaces suitable for connection to the overlying metal structures.

[0014] In some examples, the vertically extending contact of the bottom electrode is laterally spaced from the top electrode by a sufficient distance such that both a top electrode interconnection element (e.g., formed on the top surface of the top electrode) and a bottom electrode interconnection element (e.g., formed on the top surface of the vertically extending contact of the bottom electrode) can be formed in a common (i.e., same) metal layer without the need for additional mask layers.

[0015] In some examples, the MIM capacitor module may be built simultaneously with an interconnect structure. In some examples, the MIM capacitor module may be built in a damascene process without additional photomask layers, compared to a background IC manufacturing process.

[0016] In some examples, the MIM capacitor module provides a consistent breakdown voltage. For example, the disclosed processes for forming the MIM capacitor module can avoid the presence of bumps on the bottom electrode. Furthermore, the thickness of the top electrode and the overlying electrode pad (both of which can be formed from aluminum, for example) can be large, providing a very low series resistance.

[0017] In some examples, the MIM capacitor module may be constructed between two metal interconnect layers or between a silicided polysilicon layer and a metal-1 metal layer.

[0018] One aspect provides an MIM capacitor module including a bottom electrode formed in a lower metal layer and an insulator can formed in a well opening in a dielectric region above the lower metal layer and including a laterally extending insulator can base formed on the bottom electrode and a vertically extending insulator can sidewall extending upwardly from the laterally extending insulator can base.The MIM capacitor module includes a top electrode formed in an opening defined by the insulator can, a vertically extending bottom electrode contact formed in the dielectric region and contacting the bottom electrode, and a top electrode interconnection element and a bottom electrode interconnection element formed in a top metal layer, wherein the top electrode interconnection element is electrically connected to the top electrode and the bottom electrode interconnection element is electrically connected to the vertically extending bottom electrode contact.

[0019] In some examples, the lower metal layer and the upper metal layer each include metal interconnect layers.

[0020] In some examples, the bottom metal layer comprises a silicided polysilicon layer, wherein the bottom electrode comprises a metal silicide formed on a polysilicon structure.

[0021] In some examples, the bottom electrode and the vertically extending bottom electrode contact are formed from different metals.

[0022] In some examples, the bottom electrode is formed of aluminum and the vertically extending bottom electrode contact is formed of tungsten.

[0023] In some examples, the laterally extending insulator cup base is formed directly on the bottom electrode.

[0024] In some examples, the vertically extending sidewall of the insulator can is formed directly on a vertically extending surface of the dielectric region.

[0025] Another aspect provides an IC device comprising an IC structure and a MIM capacitor module. The IC structure includes a lower metal element formed in a lower metal layer, an upper metal element formed in an upper metal layer, and a vertically extending metal element formed in a dielectric region and electrically connected between the lower metal element and the upper metal element, the dielectric region being formed between the lower metal layer and the upper metal layer.The MIM capacitor module includes a bottom electrode formed in the lower metal layer, an insulator can formed in a well opening in the dielectric region and having a laterally extending insulator can base formed on the bottom electrode, a top electrode formed in an opening defined by the insulator can and contacting the bottom electrode, and a top electrode interconnection element and a bottom electrode interconnection element formed in the upper metal layer, wherein the top electrode interconnection element is electrically connected to the top electrode and the bottom electrode interconnection element is electrically connected to the vertically extending bottom electrode contact.

[0026] In some examples, both the bottom metal layer and the top metal layer include metal via layers, and the vertically extending metal element includes a via.

[0027] In some examples, the bottom metal layer comprises a silicided polysilicon layer, the bottom metal element comprises a first metal silicide formed on a first polysilicon structure, and the bottom electrode comprises a second metal silicide formed on a second polysilicon structure.

[0028] In some examples, the vertically extending contact of the bottom electrode of the MIM capacitor module and the vertically extending metal element of the via of the IC structure are formed from a conformal metal.

[0029] In some examples, the lower metal layer is formed of a different metal than the conformal metal.

[0030] In some examples, the laterally extending insulator cup base is formed directly on the bottom electrode.

[0031] In some examples, the insulator can includes a vertically extending insulator can sidewall extending upwardly from the laterally extending insulator can base, the vertically extending insulator can sidewall formed on a vertically extending surface of the dielectric region.

[0032] Another aspect includes a method including forming a lower metal layer having a bottom electrode, forming a dielectric region over the lower metal layer, patterning and etching the dielectric region to form a well opening and an electrode opening in the dielectric region; depositing a conformal metal over the dielectric region, wherein the deposited conformal metal (a) fills the contact opening of the bottom electrode to form a bottom electrode contact opening and (b) partially fills the well opening; performing a metal etching process that removes (a) portions of the conformal metal over the dielectric region and (b) the conformal metal in the well opening;applying an insulator layer over the dielectric region and forming an insulator cup structure in the well opening, the insulator cup structure including a laterally extending insulator cup base formed on the bottom electrode and a vertically extending electrode sidewall; applying a top electrode metal over the insulator layer extending into an opening defined by the insulator cup structure; performing a planarization process to remove (a) upper portions of the top electrode metal, (b) upper portions of the insulator layer, (c) a partial vertical thickness of the dielectric region, and (d) an upper portion of the bottom electrode contact structure in the electrode opening;wherein, after the planarization process, a remaining portion of the insulator layer defines an insulator can, a remaining portion of the top electrode metal defines a top electrode, and a remaining portion of the vertically extending top electrode contact structure defines a vertically extending top electrode contact and forms a top metal layer including (a) a bottom electrode interconnection element electrically connected to the vertically extending top electrode contact, and (b) a top electrode interconnection element electrically connected to the top electrode;

[0033] In some examples, the metal etching process forms a recess in the upper part of the bottom electrode contact structure defining a recessed region of the bottom electrode contact structure, wherein the recessed region of the bottom electrode contact structure has a vertical depth and the planarization process extends vertically below the vertical depth of the recessed region of the bottom electrode contact structure.

[0034] In some examples, forming the dielectric region over the lower metal layer comprises forming the dielectric region including (a) a base component having a vertical thickness of the base component and (b) a sacrificial component over the base component and having a vertical thickness of the sacrificial component, and the planarization process removes the vertical thickness of the sacrificial component of the dielectric region.

[0035] In some examples, the deposited conformal metal forms a cup-shaped conformal metal structure in the well opening.

[0036] In some examples, the lower metal layer and the upper metal layer each include metal interconnect layers.

[0037] In some examples, the bottom metal layer comprises a silicided polysilicon layer, wherein the bottom electrode comprises a metal silicide formed on a polysilicon structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Exemplary aspects of the present disclosure are described below in conjunction with the following figures: Fig. 1A is a plan view and Fig. Figure 1B is a side cross-section of an exemplary MIM capacitor module; Fig. 2 is a side cross-sectional view showing an exemplary IC structure including an MIM capacitor module and an interconnect structure that may be formed simultaneously according to one example; The Fig. 3A-3J show an exemplary method for forming the Fig. 2, which includes an MIM capacitor module and an interconnect structure; and Fig. 4 is a side cross-sectional view showing an exemplary IC structure with a MIM capacitor module and an interconnect structure formed on a bottom metal layer including a silicided polysilicon layer.

[0039] It is to be understood that the reference numerals for any illustrated element appearing in a plurality of different figures have the same meaning in all figures, and that mention or discussion of an illustrated element in connection with a particular figure also applies to any other figure in which the same illustrated element is shown. DETAILED DESCRIPTION

[0040] The Fig. 1A and Fig. 1B show an example of an MIM capacitor module 100 according to the present disclosure. In particular, Fig. 1A is a top view of the MIM capacitor module 100, and Fig. Figure 1B shows a side cross-sectional view of the MIM capacitor module 100 through the Fig. 1A, section line 1B-1B. As shown, the MIM capacitor module 100 includes (a) a bottom electrode 102, (b) an insulator can 104 in a well opening formed in a dielectric region 106, (c) a top electrode 110 formed in an opening defined by the insulator can 104, and (e) a vertically extending bottom electrode contact 112 formed in the dielectric region 106 and electrically contacting the bottom electrode 102, (f) a top electrode interconnection element 114 electrically connected to the top electrode 110, and (g) a bottom electrode interconnection element 116 electrically connected to the vertically extending bottom electrode contact 112.

[0041] The bottom electrode 102 can be in a lower metal layer M xbe formed, e.g. a lower metal compound layer (e.g. an aluminum composite) or a silicided polysilicon layer, as explained in more detail below.

[0042] The insulator can 104 is formed in a well opening 120 formed in the dielectric region 106, e.g., an inter-metal dielectrics (IMD) region or a poly-metal dielectrics (PMD) region comprising one or more dielectric materials, e.g., silicon oxide, PSG (phosphosilicate glass), or FSG (fluorine-doped glass), or a combination thereof. The insulator can 104 includes (a) a laterally extending electrode cup base 122 formed on the bottom electrode 102, and (b) an insulator cup sidewall 124 extending upwardly from the laterally extending electrode cup base 122. In this example, the insulator cup sidewall 124 extends upwardly from a lateral peripheral edge of the laterally extending insulator cup base 122. In some examples, the insulator can 104 comprises silicon nitride (SiN), e.g., with a thickness in the range of 250-750Å.Alternatively, the insulator cup 104 can also be SiO2, Al2O3, ZrO2, HfO2, ZrSiO. x , HfSiO x , HfAlO x or Ta2O5 or other suitable capacitor insulator material.

[0043] In some examples, the vertically extending sidewall of the insulator can 124 has a closed circular circumference surrounded by the dielectric region 106 in the xy plane, e.g., as in Fig. 1A. In some examples, the vertically extending insulator can sidewall 124 is formed directly on a vertically extending surface 130 of the dielectric region 106 defined by the well opening 120.

[0044] The top electrode 110 may fill an opening 125 defined by the insulator cup 104 and may comprise Al, Ti, TiN, W or a combination thereof, e.g., a combination of TiN and Al, and may be deposited, e.g., by a physical vapor deposition (PVD) process.

[0045] The vertically extending bottom electrode contact 112 is formed in an electrode contact opening 121 in the dielectric region 106 and extends vertically through the dielectric region 106 to electrically connect the bottom electrode interconnect element 116 to the bottom electrode 102. In some examples, the vertically extending bottom electrode contact 112 is formed from tungsten (W) or another conformal metal. In some examples, the vertically extending bottom electrode contact 112 is formed over a liner 126 comprising, for example, TiN. As described further below with reference to Fig. 2 and the Fig. 3A-3J, in some examples, the vertically extending bottom electrode contact 112 is formed concurrently with at least one vertically extending metal element of a separate IC structure, for example, with at least one interconnect via of a separate interconnect structure.

[0046] As shown, the insulator cup 104, the top electrode 110 and the vertically extending bottom electrode contact 112 may be formed in a via layer V x between the lower metal layer M x and an upper metal layer M x+1 (see below). The via layer V x has a vertical thickness Tv x for example in the range of 5,000-8,000Ä.

[0047] The top electrode connecting element 114 and the bottom electrode connecting element 116 can be formed in the upper metal layer M x+1be formed, e.g. a metal connection layer (e.g. an aluminum composite layer) or a bond pad layer which is formed above the via layer V x The top electrode connecting element 114 and the bottom electrode connecting element 116 may have any suitable shapes and sizes. For example, the top electrode connecting element 114 and the bottom electrode connecting element 116 may have a square or rectangular shape in an x-y plane, as shown in Fig. 1A. In another example (not shown), the top electrode interconnect 114 and the bottom electrode interconnect 116 may each have a generally circular shape in the xy-plane. Another example is that the top electrode interconnect 114 and / or the bottom electrode interconnect 116 may be substantially elongated, i.e., extend further laterally across the wafer in a first of the x-direction or the y-direction than the lateral extent across a second of the x-direction or the y-direction. In some examples, the top electrode interconnect 114 and / or the bottom electrode interconnect 116 may be omitted and is thus optional. For example, the bottom electrode interconnect 116 may be omitted, wherein the bottom electrode 102 may be contacted from below or laterally from the side instead of from above.

[0048] The top electrode 110 is capacitively coupled to the bottom electrode 102 via the laterally extending insulator cup base 122. As already mentioned, the vertically extending insulator cup sidewall 124 may be surrounded by the dielectric region 106 in the xy plane (e.g., as shown in Fig. 1A), which can substantially prevent capacitive coupling between the top electrode 110 and other conductive structures (e.g., the bottom electrode 102 and / or the vertically extending bottom electrode contact 112) through the vertically extending insulator can sidewall 124. As a result, the structure of the MIM capacitor module 100 effectively defines a planar capacitor between the top electrode 110 and the bottom electrode 102 through the laterally extending insulator can base 122, generally indicated by the dashed line PC. This planar capacitor defined by the structure of the MIM capacitor module 100 may be suitable or advantageous for certain applications, e.g.,Compared to a 3D MIM capacitor, where the insulator can is formed within a conductive can, enabling both vertical capacitive coupling through the insulator can base and lateral capacitive coupling through the insulator can sidewall. A planar capacitor defined by the structure of the MIM capacitor module 100 may, for example, provide better matching for analog circuits (e.g., matching device properties such as resistance and capacitance) and / or a higher breakdown voltage without experiencing an enhanced electric field in the corners.

[0049] The transition from the laterally extending insulator can base 122 to the vertically extending insulator can sidewall 124 defines an upwardly directed corner that wraps around the bottom corner of the top electrode 110, which can reduce an electric field associated with the top electrode and thereby improve the breakdown voltage of the MIM capacitor module 100.

[0050] In some examples, the MIM capacitor module 100 is constructed using a damascene process that does not require additional photomask operations for integrated circuit fabrication, as described below.

[0051] In some examples, both the top electrode 110 and the bottom electrode 102 are thick, e.g., they have a vertical thickness of at least 2500Å in the z-direction, thus providing low resistance. In some examples (see Fig. 1B) the bottom electrode 102 is in a metal compound layer M xand thus has the vertical thickness of the metal interconnect layer, while the upper electrode 110 is formed in a via layer V x (e.g. between two metal compound layers M x and M x+1 ) and the vertical thickness of the via layer V x less the small vertical thickness of the laterally extending insulator cup base 122 (e.g. less 250-750Å).

[0052] Fig. Figure 2 is a side cross-sectional view showing an exemplary IC device 200 incorporating the Fig. 1A-1B and a separate IC structure 202 formed simultaneously, according to one example. As previously mentioned, the MIM capacitor module 100 may be constructed without adding photomask operations to the background integrated circuit manufacturing process (e.g., the background integrated circuit manufacturing process for forming the IC structure 202 and / or other IC elements).

[0053] As described above, the MIM capacitor module 100 (a) includes a lower metal layer M x connected top electrode 102, (b) a in the upper metal layer M x+1 formed top electrode connection element 114 and bottom electrode connection element 116 and (c) an insulator cup 104, a top electrode 110 and a vertically extending bottom electrode contact 112 formed in the via layer V x between the lower metal layer Mx and the upper metal layer M x+1 The insulator cup 104 includes a laterally extending insulator cup base 122 and an electrode sidewall 124 extending upwardly from the laterally extending insulator cup base 122, and a top electrode 110 formed in the opening 124 defined by the insulator cup 104. The insulator cup 104 and the vertically extending bottom electrode contact 112 may be formed in the respective contact openings in the dielectric region 106. In some examples, the vertically extending insulator cup sidewall 124 of the insulator cup 104 is formed directly on the vertically extending surface 130 of the dielectric region 106 defined by the well opening 120.

[0054] As previously mentioned, the structure of the MIM capacitor module 100 effectively defines a planar capacitor between the top electrode 110 and the bottom electrode 102 by the laterally extending insulator can base 122, generally indicated by the dashed line PC.

[0055] As in Fig. 2, the IC structure 202 may include a lower metal element 204 formed in a lower metal layer M x and an upper metal element 210 formed in an upper metal layer M x+1 and is connected to the lower metal element 204 by vertically extending metal elements 205 formed in the via layer V xwherein the vertically extending metal elements 205 may be formed by depositing a conformal via material, e.g., tungsten, into the respective via openings. In some examples, the vertically extending metal elements 205 are formed over the liner 126, which may comprise, e.g., TIN.

[0056] As used herein, a “metal layer”, e.g. in connection with the lower metal layer M x and the upper metal layer M x+1, any metal or metallized layer or layers, including (a) a metal interconnect layer, e.g. consisting of copper, aluminum or another metal, applied by a subtractive patterning process (e.g., applying, patterning and etching a metal layer) or formed by a damascene process, or (b) a silicided polysilicon layer, for example comprising a number of polysilicon regions each having a layer or region of metal silicide formed thereon.

[0057] In some examples, the lower metal layer M x be a silicided polysilicon layer and the upper metal layer M x+1 may have a first metal compound layer, often referred to as Metal-1. In such examples, x=0, so that the lower metal layer M x = M0 and the upper metal layer M x+1= M1 (ie, Metal-1). Furthermore, an "interconnect structure," eg, in the context of the IC structure 202 described below, may include any type or types of metal layers as defined above.

[0058] In some examples, for example, as described below with reference to the Fig. 3A-3J, the IC structure 202 may include an interconnect structure wherein (a) the lower metal layer M x has a lower interconnect metal layer and the lower metal element 204 has a lower interconnect element formed in the lower interconnect metal layer, (b) the upper metal layer M x+1 an upper interconnect metal layer and the upper metal element 210 comprises an upper interconnect element formed in the upper interconnect metal layer, and (c) the vertically extending metal elements 205 comprise vias formed in the via layer V xand electrically connect the lower connecting element to the upper connecting element.

[0059] In other examples, e.g. as described below with reference to Fig. 4, the lower metal layer M x a silicided polysilicon layer, the upper metal layer M x-1 a first metal interconnect layer (metal 1 interconnect layer), and the via layer V xa PMD region beneath the Metal 1 interconnect layer. In such examples, (a) the bottom metal element 204 and the bottom electrode 102 formed in the silicided polysilicon layer include a respective metal silicide formed on a respective polysilicon region, (b) the top metal element 210, the top electrode interconnect element 114, and the bottom electrode interconnect element 116 include metal elements formed in the Metal 1 interconnect layer, and (c) the vertically extending metal elements 205 include contacts electrically connected between the metal silicide of the bottom metal element 204 and the top metal element 210.

[0060] In some examples, the lower metal member 204 and the upper metal member 210 may include corresponding wires or other lateral elongated structures or discrete pads (e.g., having a square or substantially square shape in plan view), or any other suitable shape and structure.

[0061] The lower metal element 204 and the bottom electrode 102 can be formed simultaneously in the lower metal layer M x be designed, e.g. as described below with reference to Fig. 3A. The upper metal element 210, the top electrode connecting element 114 and the bottom electrode connecting element 116 can be formed simultaneously in the upper metal layer M x+1 be designed, e.g. as described below with reference to the Fig. 3I and Fig. 3J. The vertically extending metal elements 205, the insulator cup 104, the top electrode 110 and the vertically extending bottom electrode connection element 112 can be formed in the via layer V x between the lower metal layer M x and the upper metal layer M x+1 be formed, e.g. using a Damascene process, as described below with reference to the Fig. 3A-3H. In some examples, vertically extending metal elements 205 and vertically extending bottom electrode contacts 112 may be formed simultaneously, e.g., by depositing tungsten or another conformal metal in corresponding openings in the dielectric region 106, e.g., as described below with reference to FIGS. Fig. 3B-3C discussed.

[0062] The Fig. 3A-3J show an exemplary method for forming the Fig. 2, which includes an MIM capacitor module 100 and an IC structure 202. As mentioned above, in other examples, the IC structure 202 may be optional, so that the MIM capacitor module 100 may be formed without the elements of the IC structure 202 by the process described below.

[0063] As in Fig. 3A, the lower metal element 204 and the bottom electrode 102 are in the lower metal layer M x In this example, the lower metal layer M x a metal interconnect layer, wherein the lower metal element 204 and the bottom electrode 102 are each formed as metal elements (e.g., as aluminum interconnect elements). In another example, e.g., as shown in Fig. 4, the lower metal layer M xa silicided polysilicon layer, wherein the lower metal element 204 and the bottom electrode 102 each comprise a metal silicide formed on a corresponding polysilicon structure.

[0064] Above the lower metal element 204 and the bottom electrode 102, which are formed in the lower metal layer M x are formed, a dielectric region 206 (e.g., an Inter Metal Dielectrics (IMD) region or a Poly Metal Dielectrics (PMD) region) is formed. As shown, the dielectric region 206 can have a total thickness T total deposited and planarized, comprising (a) a dielectric base component 206a having a vertical thickness T base the base component and (b) a sacrificial dielectric component 206b over the base component 206a, wherein the sacrificial dielectric component 206b has a vertical thickness T sacof the sacrificial component. The base dielectric component 206a and the sacrificial dielectric component 206b may comprise the same dielectric material, e.g., deposited in a single process. Alternatively, the dielectric component 206a and the sacrificial dielectric component 206b may comprise different dielectric materials formed by respective deposition processes. The base dielectric component 206a and the sacrificial dielectric component 206b may each comprise any suitable dielectric material, e.g., silicon oxide, PSG (phosphosilicate glass), FSG (fluorine-doped glass), or a combination thereof, and may each be deposited by a PECVD (plasma-enhanced chemical vapor deposition) process, a HDP (high-density plasma) process, or another suitable deposition process.

[0065] As explained further below, the dielectric component 206b may then be removed (e.g., by a CMP process) so that the dielectric component 206a remains, which forms the dielectric region 106 of the Fig. 2 shown finished MIM module 100. Thus, the vertical thickness T base the dielectric base component 206a is equal to or slightly greater than the vertical thickness Tv x the via layer V x (e.g., up to 10% larger than this), which may be defined by the Process of Record (POR) or the base specifications for the IC device 200. For example, the vertical thickness T base the dielectric component 206a in the range of 5,000-8,000Å.

[0066] As described below, for example, with reference to the Fig. 3D-3H, the sacrificial dielectric component 206b may be provided to enable removal of the recessed regions 330 of a bottom electrode contact structure 314 and the vertically extending metal element structures 312 formed in the dielectric region 206, to thereby form the vertically extending bottom electrode contact 112 and the vertically extending metal elements 205 having planar, non-recessed top surfaces coplanar with a top surface of the resulting dielectric region 106, e.g., as shown in Fig. 2. Therefore, the vertical thickness T sac of the dielectric component 206b may be greater than the vertical depth of the deepest recessed region 330. In some examples, the vertical thickness T sac the sacrificial component is in the range of 500-1,000Å.

[0067] As in Fig. 3B, the openings 300 in the dielectric region, including the vertically extending metal element openings 302, the well opening 120, and the bottom electrode contact opening 121, may be patterned using a photomask and etched into the dielectric region 206, i.e., into the base dielectric component 206a and the sacrificial dielectric component 206b. The openings in the dielectric region 300 may be formed by masking with photoresist material and by a plasma etch or other suitable etching process, followed by a resist strip or other suitable process for removing the remaining portions of the photoresist material. The etching process for forming the openings in the dielectric region 300 may be a selective etch that ends on the bottom metal element 204 and the bottom electrode 102 (e.g., comprising aluminum or another metal).

[0068] In some examples, the vertically extending metal element openings 302 may be via openings having a width (or diameter or critical dimension (CD)) W via in both the x-direction and the y-direction in the range of, for example, 0.1-0.5 µm. The bottom electrode contact opening 121 may also be a via opening having, for example, a width W bec in both the x-direction and the y-direction in the range of 0.1-0.5 µm. In other examples, the width W bec the bottom electrode contact opening 121 may have other suitable dimensions.

[0069] In contrast, the tub opening 120 can have a much larger width in the x-direction (W tub_x ) and / or y-direction (W tub_y) than the vertically extending metal element openings 302 and the bottom electrode contact opening 121. The shape and dimensions of the well opening 120 can be selected based on various parameters, e.g., for effective manufacturing of the MIM capacitor module 100 (e.g., effective formation of the insulator can 104 and the top electrode 110 in the well opening 120) and / or for the desired performance characteristics of the resulting MIM capacitor module 100. In one example, e.g., as shown in Fig. As shown in Figure 3B, the tub opening 120 may have a square or rectangular shape in plan view. In other examples, the tub opening 120 may have a round or oval shape in plan view.

[0070] As already mentioned, the width of the tub opening 120 in the x-direction (W tub_x ), in the y-direction (W tub_y ) or both in the x-direction and in the y-direction (W tub_x and W tub_y) may be substantially greater than the width Wvia of the vertically extending metal element openings 302 in the x-direction, in the y-direction, or in both the x-direction and the y-direction. In some examples, for example, the width W tub_x and W tub_y the tub opening 120 is at least twice as large as the width Wvia of the vertically extending metal element openings 302. In particular examples, the width W tub_x and W tub_y the tub opening 120 is at least five times as large or at least ten times as large as the width Wvia of the vertically extending metal element openings 302. In some examples, W tub_x and W tub_y each in the range of 1-100 µm.

[0071] Furthermore, the tub opening 120 can be formed with a height to width ratio of less than or equal to 1.0 in both the x and y directions, e.g., to enable effective filling of the tub opening 120 with appropriate materials.

[0072] For example, the tub opening 120 with an aspect ratio H tub / W tub_x and H tub / W tub_y in the range of 0.01-1.0, for example in the range of 0.1-1.0. In some examples, the aspect ratios H tub / W tub_x and H tub / W tub_y less than or equal to 1.0, e.g., to effectively fill the tub opening 120 with the appropriate materials to form the insulator cup 104 and the top electrode 110 in the tub opening 120. The tub opening 120 may, for example, have an aspect ratio H tub / W tub_x or H tub / W tub_yin the range of 0.1 - 1.0 or in particular in the range of 0.5 - 1.0.

[0073] As in Fig. As shown in Figure 3C, a liner (or “adhesive layer”) 126, comprising, for example, TiN with a thickness in the range of 50Å-200Å, is applied to the structure and extends into the respective openings of the dielectric region 300.A conformal metal 310 is deposited over the liner 126 and extends into the respective via layer openings 300 to (a) fill the vertically extending electrode openings 302 to form the respective vertically extending metal element structures 312, (b) fill the bottom electrode via opening 121 to form the bottom electrode contact structure 314, and (c) form a bottom electrode cup structure 316 in the well opening 120, wherein the bottom electrode cup structure 316 includes a laterally extending electrode cup base 320 and a bottom electrode cup sidewall 322 extending upward (in the z-direction) from a lateral peripheral edge of the laterally extending electrode cup base 320. In one example, the conformal metal comprises 310 tungsten deposited to a thickness in the range of 1000Å-5000Å.In other examples, the conformal metal 310 may comprise Co, TiN, or another conformal metal. The conformal metal 310 may be deposited by a conformal chemical vapor deposition (CVD) process or another suitable deposition process.

[0074] As in Fig. 3D, a metal etching process is performed to remove portions of the conformal metal 310. For example, a metal etch (e.g., an isotropic wet etch or an isotropic dry etch (plasma)) may be performed to (a) remove the upper portions of the conformal metal 310 above the dielectric region 206 and (b) remove the bottom electrode cup structure 316 from the well opening 120. The depth of the metal etch to completely remove the bottom electrode cup structure 316 from the well opening 120 may result in an "over-etch" at the top of the structure, which may form a corresponding bulge 328 (e.g.,a "plug bulge") in the respective upper portions of the bottom electrode contact structure 314 and the respective vertically extending metal element structures 312, defining a corresponding recessed area 330 of the bottom electrode contact structure 314 and the respective vertically extending metal element structures 312. Each recess 328 has a corresponding vertical depth D. recess wherein the dielectric component 206b above the base component 206a is greater than the vertical depth D recess the deepest recess 328.

[0075] The recessed areas 330 of the bottom electrode contact structure 314 and the vertically extending metal element structures 312 have a non-planar top surface, which may be unsuitable for forming effective or reliable electrical contacts with overlying conductive elements, such as the later formed bottom electrode connection element 116 and the top metal element 210, as described below. As will be further described below with respect to the Fig. 3G and Fig. 3H, the recessed regions 330 of the bottom electrode contact structure 314 and the vertically extending metal element structures 312 may be removed by a planarization process that removes at least the sacrificial dielectric component 206b of the dielectric region 206.

[0076] As in Fig. 3E, an insulator layer 340 is deposited over the structure and extends downwardly into the well opening 120 to form an insulator cup structure 342 having a laterally extending insulator cup base 344 formed on the bottom electrode 102 and a vertically extending electrode sidewall 346 extending upwardly from the laterally extending insulator cup base 344. The insulator cup structure 342 defines the opening 125 in which the top electrode 110 is formed, as described further below. In the illustrated example, the vertically extending sidewall 346 of the insulator cup structure extends upwardly from a lateral peripheral edge of the laterally extending insulator cup base 344.In the illustrated example, the vertically extending sidewall 346 of the insulator cup structure is formed directly on the vertically extending surface 130 of the dielectric region 206 defined by the well opening 120.

[0077] In some examples, the insulator layer 340 comprises silicon nitride (SiN) deposited to a thickness in the range of 250Å-750Å by a plasma-enhanced chemical vapor deposition (PECVD) process. Alternatively, the insulator layer 340 may comprise Al2O3, ZrO2, HfO2, ZrSiO x , HfSiO x , HfAlO x or Ta2O5 or another suitable capacitor insulator material deposited using an ALD (Atomic Layer Deposition) process.

[0078] As in Fig. As shown in Figure 3F, a top electrode metal 350 is deposited over the insulator layer 340 and extends into and fills the opening 125 defined by the insulator cup structure 342. In some examples, the top electrode layer 340 may comprise Al, Ti, TiN, W, or a combination thereof, e.g., TiN and Al, and may be deposited by a physical vapor deposition (PVD) process.

[0079] As in Fig. 3G (top view) and Fig. 3H (lateral cross-sectional view through the Fig. 3G, a planarization process is performed to remove (a) upper portions of the top electrode metal 350 to define the top electrode 110, (b) upper portions of the insulator layer 340 to define the insulator can 104, (c) a partial upper thickness of the dielectric region 206, e.g., dielectric component 206b, to define the dielectric region 106, and (d) corresponding upper portions of the bottom electrode contact structure 314 and the vertically extending metal element structures 312 to define the bottom electrode contact 112 and the vertically extending metal elements 205. In some examples, the planarization process comprises a chemical mechanical planarization (CMP) process.

[0080] As described further below, the planarization process defines a planarized top surface 351 of the via layer V x, which includes (a) planarized, non-recessed top surfaces 352a and 352b of the vertically extending bottom electrode contact 112 and the respective vertically extending metal elements 205, (b) a planarized top surface 354 of the planarized dielectric region 106, and (c) a planarized top surface 356 of the top electrode 110.

[0081] A vertical depth (in the z-direction) of the planarization process may remove the recessed regions 330 of the bottom electrode contact structure 314 and the vertically extending metal element structures 312. Thus, the planarization process may extend to a depth that is below the vertical depth D recess the deepest depression is 328.

[0082] The vertical depth of the planarization process may be at least the sacrificial dielectric component 206b (ie, the total vertical thickness T sacthe sacrificial component) and optionally a partial upper thickness of the dielectric component 206a (ie, a partial thickness of the vertical thickness T basethe base component). For example, if the dielectric component 206b is formed in a single deposition process (i.e., if the base dielectric component 206a and the sacrificial dielectric component 206b comprise the same dielectric material), the planarization process removes the sacrificial dielectric component 206b, leaving the base dielectric component 206a. As another example, if the dielectric component 206b is formed by multiple deposition processes (e.g., by depositing a first dielectric material defining the base dielectric component 206a and then depositing a different second dielectric material defining the sacrificial dielectric component 206b), the planarization process may remove the sacrificial dielectric component 206b and a portion of the vertical thickness T base the underlying dielectric base component 206a.

[0083] The remaining thickness of the planarized dielectric region 206 defines the dielectric region 106 of the MIM capacitor module 100, which has a vertical thickness Tv x which is equal to or less than the vertical thickness T base of the base component (e.g. depending on whether a partial upper part of the part of the vertical thickness T base the base component is removed by the planarization process).

[0084] The remaining portions of the insulator layer 340 define the insulator cup 104, which includes the laterally extending electrode cup base 122 on the bottom electrode 102 and the insulator cup base 122 extending upward from the laterally extending electrode sidewall 124. The vertically extending insulator cup sidewall 124 includes a remaining portion of the vertically extending insulator cup sidewall 346 after the planarization process.

[0085] A remaining portion of the top electrode metal 350 defines the top electrode 110 in the insulator can 104, with the top electrode 110 having the planarized top surface 356.

[0086] As in Fig. 3G, the vertically extending sidewall 124 of the insulator can may have a closed rectangular perimeter in a horizontal plane (xy-plane) surrounding the top electrode 110 and surrounded by the dielectric region 106. As shown, the vertically extending contact of the bottom electrode 112 and the respective vertically extending metal elements 205 may have a circular shape in the xy-plane. In other examples, the vertically extending bottom electrode contact 112 and / or the respective vertically extending metal elements 205 may have any other shape in the xy-plane, e.g., a square or rectangular shape.

[0087] Next, as shown in the Fig. 3I and Fig. 3J, an upper metal layer (M x+1 -layer) on the planarized upper surface 351 of the via layer V x be trained. Fig. Figure 3I shows a top view of the resulting structure after formation of the upper metal layer M x+1 , and Fig. Figure 3J shows a side cross-sectional view through the Fig. Line 3J-3J shown in Figure 3I. In the upper metal layer M x+1Various metal elements are formed (e.g., by a metal deposition, patterning, and etching process), including (a) the upper metal element 210, which is electrically connected to the via layers 206, (b) the top electrode connecting element 114, which is electrically connected to the top electrode 110, and (c) the bottom electrode connecting element 116, which is electrically connected to the vertically extending bottom electrode contact 112. The upper metal layer M x+1 may contain aluminum or other suitable metal.

[0088] As shown, the top metal element 210 may be formed directly on the planar top surfaces 352a of the respective vertically extending metal elements 205, the top electrode interconnect element 114 may be formed directly on the planar top surface 356 of the top electrode 110, and the bottom electrode interconnect element 116 may be formed directly on the planar top surface 352b of the vertically extending bottom electrode contact 112. Thus, (a) the top metal element 210 may be mechanically and electrically connected to the vias 205, (b) the top electrode interconnect element 114 may be mechanically and electrically connected to the top electrode 110, and (c) the bottom electrode interconnect element 116 may be mechanically and electrically connected to the vertically extending bottom electrode contact 112. Fig.4 is a side cross-sectional view illustrating an exemplary IC device 400 including a MIM capacitor module 402 and an IC structure 404 formed on a bottom metal layer MO comprising a silicided polysilicon layer. In this example, a bottom metal element 408 of the IC structure 404 and a bottom electrode 406 of the MIM capacitor module 402 may each include a metal silicide formed on a corresponding polysilicon region. In particular, the bottom metal element 408 includes a first metal silicide 422a formed on a first polysilicon region 420a, and the bottom electrode 406 includes a second metal silicide 422b formed on a second polysilicon region 420b. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 349,703

[0001]

Claims

[1] Metal-insulator-metal (MIM) capacitor module, which has: a bottom electrode formed in a lower metal layer, an insulator cup formed in a well opening in a dielectric region above the lower metal layer, the insulator cup including: a laterally extending insulator cup base formed on the bottom electrode; and a vertically extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base; a top electrode formed in an opening defined by the insulator can; a vertically extending bottom electrode contact formed in the dielectric region and contacting the bottom electrode; and a top electrode interconnection element and a bottom electrode interconnection element formed in an upper metal layer, wherein the top electrode interconnection element is electrically connected to the top electrode and the bottom electrode interconnection element is electrically connected to the vertically extending bottom electrode contact. [2] The MIM capacitor module according to claim 1, wherein the lower metal layer and the upper metal layer each comprise metal interconnect layers. [3] The MIM capacitor module according to any one of claims 1 to 2, wherein the lower metal layer comprises a silicided polysilicon layer, wherein the bottom electrode comprises a metal silicide formed on a polysilicon structure. [4] The MIM capacitor module according to any one of claims 1 to 3, wherein the bottom electrode and the vertically extending bottom electrode contact are formed of different metals. [5] MIM capacitor module according to one of claims 1 to 4, wherein: the bottom electrode is made of aluminum; and the vertically extending bottom electrode contact is made of tungsten. [6] The MIM capacitor module according to any one of claims 1 to 5, wherein the laterally extending insulator can base is formed directly on the bottom electrode. [7] The MIM capacitor module according to any one of claims 1 to 6, wherein the vertically extending sidewall of the insulator can is formed directly on a vertically extending surface of the dielectric region. [8] Integrated circuit (IC) device comprising: an IC structure that has: a lower metal element formed in a lower metal layer; an upper metal element formed in an upper metal layer; and a vertically extending metal element formed in a dielectric region and electrically connected between the lower metal element and the upper metal element, the dielectric region being located between the lower metal layer and the upper metal layer; and one of the MIM capacitor modules according to claims 1 to 7. [9] The IC device of claim 8, wherein the vertically extending metal member comprises a via connection. [10] The IC device according to any one of claims 8 to 9, wherein the lower metal element comprises a first metal silicide formed on a first polysilicon structure. [11] The IC device according to any one of claims 8 to 10, wherein the vertically extending bottom electrode contact of the MIM capacitor module and the vertically extending metal element of the via of the IC structure via are formed of a conformal metal. [12] The IC device of claim 11, wherein the lower metal layer is formed of a different metal than the conformal metal. [13] The IC device of any one of claims 8 to 12, wherein the insulator can includes a laterally extending insulator can sidewall extending upwardly from the laterally extending insulator can base, the vertically extending insulator can sidewall being formed on a vertically extending surface of the dielectric region. [14] Method comprising: Forming a lower metal layer including a bottom electrode; Forming a dielectric region over the lower metal layer; Structuring and etching the dielectric region to form a well opening and a contact opening for the bottom electrode in the dielectric region; Applying a conformal metal over the dielectric region, wherein the applied conformal metal (a) fills the contact opening of the bottom electrode to form a bottom electrode contact opening, and (b) partially fills the well opening, Performing a metal etching process that removes (a) portions of the conformal metal over the dielectric region and (b) the conformal metal in the well opening; Applying an insulator layer over the dielectric region and forming an insulator cup structure in the well opening, the insulator cup structure including a laterally extending insulator cup base formed on the bottom electrode and a vertically extending electrode sidewall; Applying a top electrode metal over the insulator layer extending into an opening defined by the insulator cup structure; Performing a planarization process to remove (a) upper portions of the top electrode metal, (b) upper portions of the insulator layer, (c) a partial vertical thickness of the dielectric region, and (d) an upper portion of the bottom electrode contact structure in the electrode opening; wherein, after the planarization process, a remaining portion of the insulator layer defines an insulator can, a remaining portion of the top electrode metal defines a top electrode, and a remaining portion of the vertically extending top electrode contact structure defines a vertically extending top electrode contact; and Forming a top metal layer including (a) a bottom electrode interconnection element electrically connected to the vertically extending top electrode contact and (b) a top electrode interconnection element electrically connected to the top electrode. [15] The method of claim 14, wherein: the metal etching process forms a recess in the upper part of the bottom electrode contact structure, which defines a depressed region of the bottom electrode contact structure; the recessed region of the bottom electrode contact structure has a vertical depth; and the planarization process extends vertically below the vertical depth of the recessed region of the bottom electrode contact structure. [16] A method according to any one of claims 14 to 15, wherein: forming the dielectric region over the lower metal layer includes forming the dielectric region having (a) a base component with a vertical thickness of the base component and (b) a sacrificial component over the base component and with a vertical thickness of the sacrificial component; and the planarization process removes the vertical thickness of the sacrificial component of the dielectric region. [17] The method of any one of claims 14 to 16, wherein the deposited conformal metal forms a cup-shaped conformal metal structure in the well opening. [18] A method according to any one of claims 14 to 17, wherein the lower metal layer and the upper metal layer each comprise metal compound layers. [19] The method of any one of claims 14 to 18, wherein the lower metal layer comprises a silicided polysilicon layer, wherein the bottom electrode comprises a metal silicide formed on a polysilicon structure. [20] A device formed by one of the methods according to any one of claims 14 to 19.

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