Scoreboard and display device

Abstract

A display panel and a display device are provided, wherein the display panel comprises a display area, a non-display area, a first signal line, and a plurality of electrostatic discharge units, the display area comprising subpixels; the non-display area surrounds the display area and comprises an electrostatic discharge area; the first signal line extends from the display area to the electrostatic discharge area in a first direction and is configured to provide a first display signal to the subpixels;the plurality of electrostatic discharge units are arranged in the first direction, each electrostatic discharge unit comprises at least one electrostatic sub-discharge unit, each electrostatic sub-discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and charges on the first signal line move toward the first conductor; the plurality of electrostatic discharge units comprise two adjacent electrostatic discharge units in a second direction, the second direction is perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other, and on a plane parallel to the second direction at least partially overlap with each other.

Description

TECHNICAL FIELD

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. BACKGROUND

[0002] With the development of society, people's demands for life are becoming increasingly higher. Conventional screens are gradually becoming unable to meet the demands of customized screens, and irregular screens have the characteristic of customization and offer certain advantages. However, the irregular screen breaks with the design pattern of traditional screen shapes, which means more innovative designs are needed to adapt to the irregular screen.

[0003] In a display panel, an electrostatic discharge unit is crucial for the display circuit. When static electricity occurs, the electrostatic discharge unit can be set to discharge the static electricity in the display circuit to effectively protect the display circuit. Traditional displays, such as rectangular displays, have sufficient space on the bottom to arrange the electrostatic discharge unit. However, for some displays with smaller border sizes, such as irregular displays, the border shape of the irregular screen provides very little space for arranging the electrostatic discharge unit, which poses a challenge for changing the traditional layout of the electrostatic discharge unit. SUMMARY

[0004] At least one embodiment of the present disclosure provides a display panel comprising: a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region includes the subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole and is configured to provide a first display signal to the subpixels;and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor;the plurality of electrostatic discharge units comprise two adjacent electrostatic discharge units in a second direction, the second direction is perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other, and orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the second direction at least partially overlap with each other, or the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the first direction do not overlap and a distance between the two adjacent electrostatic discharge units in the second direction is less than 1 µm;

[0005] For example, in the display panel provided by at least one embodiment of the present disclosure, in the plurality of sub-electrostatic discharge units of the plurality of electrostatic discharge units, orthographic projections of at least two sub-electrostatic discharge units on the plane parallel to the first direction do not overlap with each other, and the orthographic projections of the at least two sub-electrostatic discharge units on the plane parallel to the second direction at least partially overlap with each other.

[0006] For example, in the display panel provided by at least one embodiment of the present disclosure, a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction.

[0007] For example, in the display panel provided by at least one embodiment of the present disclosure, the display panel includes a plurality of first signal lines, and the plurality of sub-static discharge units of the plurality of electrostatic discharge units are each electrically connected to the one first signal line of the plurality of first signal lines; at least one of the plurality of first signal lines includes a recess in the electrostatic discharge region, the recess forming a groove depressed toward one side in the second direction, and at least a part of a sub-electrostatic discharge unit adjacent to the groove is located in the groove.

[0008] For example, in the display panel provided by at least one embodiment of the present disclosure, at least one electrostatic discharge unit of the plurality of electrostatic discharge units includes two adjacent sub-electrostatic discharge units in the second direction, and two adjacent first signal lines both include a recess in the electrostatic discharge region, recesses of the two adjacent first signal lines form grooves recessed toward a same side in the second direction, and the two adjacent sub-electrostatic discharge units are each at least partially located in the grooves formed by the recesses of the two adjacent first signal lines.

[0009] For example, in the display panel provided by at least one embodiment of the present disclosure, the first signal line connected to the at least one sub-electrostatic discharge unit includes a first recess and a second recess.The first recess forms a first groove which is recessed in the second direction towards a first side; the second recess forms a second groove which is recessed in the second direction towards a second side opposite the first side and which is arranged in the second direction with the first recess, wherein the two adjacent electrostatic discharge units are each a first electrostatic discharge unit and a second electrostatic discharge unit, an orthographic projection of the first electrostatic discharge unit parallel to the first direction lies within an orthographic projection of the first groove parallel to the first direction, and an orthographic projection of the second electrostatic discharge unit parallel to the first direction lies within an orthographic projection of the second groove parallel to the first direction.

[0010] For example, in the display panel provided by at least one embodiment of the present disclosure, the plurality of electrostatic discharge units form a plurality of electrostatic discharge unit groups spaced apart from each other in the second direction, each of the plurality of electrostatic discharge unit groups includes M sub-groups of electrostatic discharge units, each of the M sub-groups of electrostatic discharge units includes N electrostatic discharge units, and each of the N electrostatic discharge units includes Q sub-electrostatic discharge units, where M and Q are positive integers greater than or equal to 1, and N is a positive integer greater than or equal to 2;at least a part of the groups of electrostatic discharge units of the plurality of groups of electrostatic discharge units are arranged in a periodic arrangement in the second direction, and the one group of electrostatic discharge units is a repeating unit in the periodic arrangement;

[0011] For example, in the display panel provided by at least one embodiment of the present disclosure, a number of sub-electrostatic discharge units included in one group of electrostatic discharge units is M * N * Q; in the case where M is 1, N is 2, and Q is 3, a width of the one group of electrostatic discharge units in the second direction is less than or equal to 129.5 μm; or in the case where M is 2, N is 3, and Q is 3, a width of the one group of electrostatic discharge units in the second direction is less than or equal to 294 μm.

[0012] For example, in the display panel provided by at least one embodiment of the present disclosure, a resolution of the display panel is X * Y, where X represents a number of rows of a pixel array in the display area, Y represents a number of columns of the pixel array in the display area, X is greater than or equal to 960, and Y is greater than or equal to 1440.

[0013] For example, in the display panel provided by at least one embodiment of the present disclosure, the M subgroups of electrostatic discharge units include a first subgroup of electrostatic discharge units and a second subgroup of electrostatic discharge units, the first subgroup of electrostatic discharge units and the second subgroup of electrostatic discharge units are symmetrical or asymmetrical with respect to an axis of symmetry extending in the first direction.

[0014] For example, in the display panel provided by at least one embodiment of the present disclosure, the first display signal is a data signal, and the first signal line transmits the data signal; each of the subpixels includes a pixel circuit, and the pixel circuit includes: a light-emitting device, a driving transistor, and a data writing transistor, wherein the data writing transistor is configured to transmit the data signal to the driving transistor under control of a first sensing signal; the driving transistor is configured to control an amplitude of a driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light.

[0015] For example, in the display panel provided by at least one embodiment of the present disclosure, the non-display region includes a supply region, a driving circuit is provided in the supply region, and the driving circuit is configured to supply the first display signal to the first signal line; the electrostatic discharge region is located between the supply region and the display region, and the plurality of sub-electrostatic discharge units connected to the first signal lines that supply the first display signal to all sub-pixels are located in the non-display region on the same side of the display region in the first direction.

[0016] For example, in the display panel provided by at least one embodiment of the present disclosure, the non-display region further includes an edge region, the edge region is located between the supply region and the display region, a first power supply line is provided in the edge region, and the first power supply line is configured to supply a first power supply voltage to the subpixels; the supply region includes a data selection region on a side of the edge region remote from the display region, a data selection unit is provided in the data selection region, and the electrostatic discharge region is located between the first power supply line and the data selection region.

[0017] For example, in the display panel provided by at least one embodiment of the present disclosure, a first end of the data selection unit proximate to the electrostatic discharge region is electrically connected to R first signal lines, and a second end of the data selection unit remote from the electrostatic discharge region is electrically connected to S data supply lines, where S and R are both positive integers, and S is smaller than R; the S data supply lines are electrically connected to the drive circuit, and the first display signal is provided by the drive circuit to the S data supply lines.

[0018] For example, in the display panel provided by at least one embodiment of the present disclosure, a width of a region where the driving circuit is located in the second direction is smaller than a width of the electrostatic discharge region in the second direction.

[0019] For example, in the display panel provided by at least one embodiment of the present disclosure, the electrostatic discharge circuit comprises: a first subcircuit having a driver end, a first end, and a second end, wherein the driver end and the first end of the first subcircuit are electrically connected to the first signal line, and the second end of the first subcircuit is electrically connected to the first conductor.

[0020] For example, in the display panel provided by at least one embodiment of the present disclosure, the sub-electrostatic discharge unit further includes a second conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the second conductor, and is configured to allow charges on the first signal line to move toward the second conductor; the electrostatic discharge circuit further includes: a second sub-circuit having a driving end, a first end, and a second end, wherein the first end of the second sub-circuit is electrically connected to the first signal line, and the driving end and the second end of the second sub-circuit are both connected to the second conductor; the first sub-circuit and the second sub-circuit are arranged in the first direction.

[0021] For example, in the display panel provided by at least one embodiment of the present disclosure, the first subcircuit includes a first transistor, and the second subcircuit includes a second transistor; a gate electrode and a first electrode of the first transistor are electrically connected to the first signal line, and a second electrode of the first transistor is electrically connected to the first conductor; a first electrode of the second transistor is electrically connected to the first signal line, and a gate electrode and a second electrode of the second transistor are both connected to the second conductor; the first transistor and the second transistor are arranged in the first direction, the first electrode and the second electrode of the first transistor are arranged in the first direction, and the first electrode and the second electrode of the second transistor are arranged in the first direction;the first transistor includes a first active layer, and the second transistor includes a second active layer; the first active layer and the second active layer both extend in the first direction, and a width of the first active layer in the second direction is smaller than a length of the first active layer in the first direction, and a width of the second active layer in the second direction is smaller than a length of the second active layer in the first direction.;

[0022] For example, in the display panel provided by at least one embodiment of the present disclosure, the first conductor and the second conductor are spaced apart from each other in the first direction, and the first conductor extends in the second direction; the sub-electrostatic discharge unit includes a first gate portion; the second conductor includes a main body portion extending in the second direction and a second gate portion connected to the main body portion and extending in the second direction; the first gate portion and the second gate portion are arranged at intervals in the first direction, and the first gate portion and the second gate portion are located between the first conductor and the main body portion of the second conductor;a portion of the first gate portion overlapping with the first active layer forms the gate electrode of the first transistor, a portion of the second gate electrode overlapping with the second active layer forms the gate electrode of the second transistor, and the first gate portion is electrically connected to the first signal line;

[0023] For example, in the display panel provided by at least one embodiment of the present disclosure, the first gate portion includes a first stripe portion extending in the first direction and a gate interconnection structure electrically connected to the first stripe portion, the gate interconnection structure protrudes from the first stripe portion in the second direction toward the first signal line, and the gate interconnection structure is electrically connected to the first signal line through a first through-hole; the first gate portion further includes a first protrusion portion electrically connected to the first stripe portion, the first protrusion portion protrudes from the first stripe portion in the second direction away from the first signal line, and a portion of the first protrusion portion overlapping with the first active layer forms the gate electrode of the first transistor;the second gate portion includes a second stripe portion extending in the first direction and a second protrusion portion electrically connected to the second stripe portion, the second protrusion portion protrudes from the second stripe portion in the second direction, and a portion of the second protrusion portion overlapping with the second active layer forms the gate electrode of the second transistor;

[0024] For example, in the display panel provided by at least one embodiment of the present disclosure, the second protrusion portion protrudes from the second stripe portion in a direction away from the first signal line in the second direction, the first stripe portion is substantially aligned with the second stripe portion in the first direction, and the first protrusion portion is substantially aligned with the second protrusion portion in the first direction.

[0025] For example, in the display panel provided by at least one embodiment of the present disclosure, the first active layer and the second active layer form an electrostatic discharge semiconductor layer that is continuous and integral, and the electrostatic discharge semiconductor layer is in a stripe shape as a whole extending in the first direction;the sub-electrostatic discharge unit further comprises a data connection structure, the data connection structure being electrically connected to the first signal line and projecting from the first signal line toward the electrostatic discharge semiconductor layer in the second direction, a first end of the data connection structure proximate to the first signal line in the second direction being electrically connected to the gate connection structure, and a second end of the data connection structure remote from the first signal line in the second direction being electrically connected to the electrostatic discharge semiconductor layer through a second through-hole, the second through-hole being located between the first projecting portion and the second projecting portion in the first direction;

[0026] For example, in the display panel provided by at least one embodiment of the present disclosure, the sub-electrostatic discharge unit further includes a first connection structure and a second connection structure; a first end of the first connection structure in the first direction is connected to the first conductor through a third through-hole, and a second end of the first connection structure in the first direction is connected to the first active layer through a fourth through-hole; a first end of the second connection structure in the first direction is connected to the main body portion of the second conductor through a fifth through-hole, and a second end of the second connection structure in the first direction is connected to the second active layer through a sixth through-hole.

[0027] For example, in the display panel provided by at least one embodiment of the present disclosure, the electrostatic discharge semiconductor layer has a straight stripe shape and is located on a side of the first stripe portion and the second stripe portion remote from the first signal line.

[0028] For example, the display panel provided by at least one embodiment of the present disclosure further includes a reset voltage line and a reset voltage supply line.the reset voltage line is configured to provide a reset voltage signal to the subpixels and includes a supply section in the non-display area, wherein the supply section of the reset voltage line is located between two adjacent electrostatic discharge units and extends in the first direction, and J adjacent supply sections are electrically connected by a reset connection line extending in the second direction; and wherein a first end of the reset voltage supply line is electrically connected to the reset connection line, a second end of the reset voltage supply line is electrically connected to the driver circuit, and the driver circuit is configured to provide the reset voltage signal.

[0029] For example, in the display panel provided by at least one embodiment of the present disclosure, a width of a region in the second direction in which the driving circuit is located is smaller than a width of the electrostatic discharge region in the second direction.

[0030] At least one embodiment of the present disclosure further provides a display panel comprising a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region comprises a plurality of subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole, and is configured to provide a first display signal to the subpixels.and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor; in the plurality of electrostatic discharge units, orthographic projections of any two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other.

[0031] At least one embodiment of the present disclosure further provides a display panel comprising a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region comprises a plurality of subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole, and is configured to provide a first display signal to the subpixels.and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor and is configured to allow charges on the first signal line to move toward the first conductor; the non-display region comprises a supply region, a driving circuit is provided in the supply region, and the driving circuit is configured to supply the first display signal to the first signal line;the electrostatic discharge region is located between the supply region and the display region, and all of the plurality of sub-electrostatic discharge units connected to the first signal lines that supply the first display signal to all sub-pixels are located on a same side of the display region in the first direction;

[0032] At least one embodiment of the present disclosure further provides a display panel comprising a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region comprises a plurality of subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole and is configured to provide a first display signal to the subpixels.and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor; a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction, and the second direction is perpendicular to the first direction; BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments are briefly described below; it is obvious that the described drawings relate only to some embodiments of the disclosure and thus are not limiting the disclosure. Fig. 1 is a schematic diagram of an arrangement mode of an electrostatic discharge unit in a display panel; Fig. 2 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure; Fig. 3 is a schematic diagram of subpixels of a part of the display area of Fig. 2; Fig. 4A is a schematic diagram of an arrangement of an electrostatic discharge unit in a display panel provided by an embodiment of the present disclosure; Fig. Figure 4B is an enlarged schematic diagram of a part containing an electrostatic discharge group in Fig. 4A includes; Fig. 4C is a schematic diagram of an arrangement of another electrostatic discharge unit in an electrostatic discharge region of the display panel provided by an embodiment of the present disclosure; Fig. 4D is a schematic diagram of an arrangement of another electrostatic discharge unit in an electrostatic discharge region of the display panel provided by an embodiment of the present disclosure; Fig. 4E is a schematic diagram of another arrangement of another electrostatic discharge unit in an electrostatic discharge region of the display panel provided by an embodiment of the present disclosure; Fig. 5A is a schematic diagram of an electrostatic discharge circuit of an electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure; Fig. 5B is a schematic diagram of a specific electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure; Fig. 6A is a schematic diagram of a pixel circuit of a subpixel provided by at least one embodiment of the present disclosure; Fig. 6B is a circuit diagram for a specific implementation example of the Fig. pixel circuit shown in Figure 6A; Fig. 6C is a signal timing diagram of a driving method for a pixel circuit provided by at least one embodiment of the present disclosure; Fig. 7A is a planar schematic diagram of a structure of an electrostatic discharge unit of a display panel provided by at least one embodiment of the present disclosure; Fig. Figure 7B is a schematic diagram of a semiconductor layer of the Fig. 7A shown electrostatic sub-discharge unit; Fig. Figure 7C is a schematic diagram of a first conductive layer of the Fig. 7A shown electrostatic sub-discharge unit; Fig. Figure 7D is a schematic diagram of an interlayer insulation of the Fig. 7A shown electrostatic sub-discharge unit; Fig. Figure 7E is a schematic diagram of a second conductive layer of the Fig. 7A shown electrostatic sub-discharge unit; Fig. Figure 7F is a schematic cross-sectional view taken along a line A1-A2 in Fig. 7A; Fig. 8 is a schematic diagram of several specially shaped display panels incorporating electrostatic discharge units provided by embodiments of the present disclosure; Fig. 9A is a schematic diagram of a Y-shaped display panel provided by embodiments of the present disclosure; Fig. 9B is a planar schematic diagram of a portion of a Y-shaped display panel including an electrostatic discharge region and a feed region; Fig. 9C is a schematic diagram of a semiconductor layer of the Fig. 9B; Fig. 9D is a schematic diagram of a first conductive layer of the Fig. 9B; Fig. 9E is a schematic diagram of an insulating interlayer of the Fig. 9B; Fig. 9F is a schematic diagram of a second conductive layer of the Fig. 9B; Fig. 10 is a schematic diagram of a data selection circuit of a display panel provided by embodiments of the present disclosure; Fig. 11 is a working time diagram of the Fig. 10 shown data selection circuit; Fig. 12A is a structural planar diagram of a data selection unit of a display panel provided by embodiments of the present disclosure; Fig. 12B is a schematic diagram of a semiconductor layer of the Fig. 12A shown data selection unit; Fig. 12C is a schematic diagram of a first conductive layer of the Fig. 12A shown data selection unit; Fig. 12D is a schematic diagram of an insulating interlayer of the Fig. 12A shown data selection unit; Fig. 12E is a schematic diagram of a second conductive layer of the Fig. 12A shown data selection unit; Fig. 13A is a schematic diagram of a heart-shaped display panel provided by embodiments of the present disclosure; Fig. 13B is a partially planar schematic diagram of a heart-shaped display panel including an electrostatic discharge region and a feed region; Fig. 14A is a schematic diagram of a D-shaped display panel provided by embodiments of the present disclosure; Fig. 14B is a planar schematic diagram of a portion of a D-shaped display panel including an electrostatic discharge region and a feed region; Fig. 15A is a schematic diagram of an O-shaped display panel provided by embodiments of the present disclosure; Fig. 15B is a planar schematic diagram of a portion of an O-shaped display panel including an electrostatic discharge region and a feed region; Fig. 16A is a schematic diagram of an I-shaped display panel provided by embodiments of the present disclosure; and Fig. Figure 16B is a planar schematic diagram of a portion of an I-shaped display panel including an electrostatic discharge region and a feed region. DETAILED DESCRIPTION

[0034] To clarify the objects, technical details, and advantages of the embodiments of the disclosure, the technical solutions of the embodiments are described clearly and comprehensibly in conjunction with the drawings of the embodiments of the disclosure. Obviously, the described embodiments are only a part, but not all, of the embodiments of the disclosure. Based on the embodiments described here, one skilled in the art can, without inventive activity, obtain other embodiments that should fall within the scope of the disclosure.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," etc., used in the specification and claims of this disclosure application are not intended to indicate order, amount, or importance, but to distinguish various components. Also, the terms "comprise," "contain," "include," "including," etc., are intended to indicate that the elements or items listed before these terms include the elements or items listed after these terms and their equivalents, but do not exclude the other elements or items. The terms "connect," "connected," etc.are not intended to define a physical or mechanical connection, but may directly or indirectly include an electrical connection. "Up," "below," "left," "right," and the like are used only to indicate a relative positional relationship, and if the position of the described object changes, the relative positional relationship may change accordingly.

[0036] The terms "fundamental alignment" and "substantially equal" used in the disclosure include certain errors that, taking into account errors in measurement and measurement of a certain amount (e.g., limitations of the measurement system), represent the acceptable range of deviation for a given value determined by persons of ordinary skill in the art. For example, "fundamental" can mean within one or more standard deviations, or, unless otherwise specified, within a range of 10% or 5% of the stated value.

[0037] The term "directly connected" in the disclosure refers to two structures that are connected to each other (for example, A and B are directly connected, etc.) that are in contact with each other, and there is no other structure between the two connected structures as a medium for their connection. For example, the two directly connected structures may be a continuous and integral structure in which the materials of the two directly connected structures are the same, and the two structures may be formed by the same patterning process to simplify the manufacturing process of the display substrate; alternatively, the materials of the two directly connected structures may be different.For example, the two structures that are directly connected are conductive signal lines, and the two structures can each use materials that match their functions to meet the requirements of different properties such as different conductivity.

[0038] The term "in a / the same layer" in the present disclosure refers to the relationship between a plurality of layers formed on the film made of the same material after performing the same step (e.g., the same patterning process). The term "in a / the same layer" here does not always mean that the plurality of layers have the same thickness or height in cross-section.

[0039] The transistors used in all examples of the present disclosure may be thin-film transistors, field-effect transistors, or other devices with the same properties. According to their role in the circuit, the transistors used in the examples of the present disclosure are primarily switching transistors. Due to the symmetrical source and drain electrodes of the switching transistor used here, the source and drain electrodes can be interchanged. To distinguish the two electrodes of a transistor other than the gate electrode, the source electrode is referred to as the first electrode and the drain electrode as the second electrode in the examples of the present disclosure.Furthermore, the switching transistor used in the examples of the present disclosure includes at least one P-type switching transistor and one N-type switching transistor, wherein the P-type switching transistor is turned on at a low gate level and turned off at a high gate level, and the N-type switching transistor is turned on at a high gate level and turned off at a low gate level.

[0040] In a display panel, charges can easily accumulate in the signal line. These accumulated charges can have various adverse effects during the display process and even cause unforeseeable problems that affect display quality. Therefore, electrostatic discharge is crucial for the display circuit. When an electrostatic discharge occurs, the charges on the signal line can be released by an electrostatic discharge unit to effectively protect the display circuit.

[0041] Fig. 1 is a schematic diagram of an arrangement mode of an electrostatic discharge unit in a display panel. Fig. 1, the display panel comprises a plurality of signal lines Data1, Data2... DataN, and is provided with a plurality of electrostatic discharge units, each of which is electrically connected to the plurality of signal lines Data1, Data2... DataN, ie the ESD units formed by the rectangular frames in Fig. 1 to discharge electrostatic discharge on the plurality of signal lines Data1, Data2... DataN. However, the plurality of electrostatic discharge units are arranged in the horizontal direction, for example, it is necessary to provide an electrostatic discharge unit for each signal line, and in order to achieve high resolution, in the case where the signal line density is high, the space left for setting additional electrostatic discharge units is limited. For example, the shape of the edge of some special-shaped screens is irregular, and the lower edge region of the special-shaped screen is very small, often without sufficient width like the edge region of an ordinary rectangular screen to be provided with a plurality of electrostatic discharge units, which makes it impossible to provide a large number of electrostatic discharge units.

[0042] At least one embodiment of the present disclosure provides a display panel, the display panel comprising: a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region includes subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole and is configured to provide a first display signal to the subpixels;and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor;the plurality of electrostatic discharge units comprise two adjacent electrostatic discharge units in a second direction, the second direction is perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other, and orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the second direction at least partially overlap with each other, or the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the first direction do not overlap and a distance between the two adjacent electrostatic discharge units in the second direction is less than 1 µm;

[0043] At least one embodiment of the present disclosure provides a display panel, the display panel comprising: a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region includes subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole, and is configured to provide a first display signal to the subpixels;and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor; in the plurality of electrostatic discharge units, orthographic projections of any two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other.

[0044] At least one embodiment of the present disclosure provides a display panel, the display panel comprising: a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region includes subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole, and is configured to provide a first display signal to the subpixels;and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor and is configured to allow charges on the first signal line to move toward the first conductor; the non-display region comprises a supply region, a driving circuit is provided in the supply region, and the driving circuit is configured to supply the first display signal to the first signal line;the electrostatic discharge region is located between the supply region and the display region, and all of the plurality of sub-electrostatic discharge units connected to the first signal lines that supply the first display signal to all sub-pixels are located on a same side of the display region in the first direction;

[0045] At least one embodiment of the present disclosure provides a display panel, the display panel comprising: a display region, a non-display region, a first signal line, and a plurality of electrostatic discharge units. The display region includes subpixels; the non-display region surrounds at least a portion of the display region and includes an electrostatic discharge region; the first signal line extends from the display region to the electrostatic discharge region in a first direction as a whole, and is configured to provide a first display signal to the subpixels;and the plurality of electrostatic discharge units are arranged in the first direction, wherein each of the plurality of electrostatic discharge units comprises at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprises an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the first conductor, and is configured to allow charges on the first signal line to move toward the first conductor; a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction, and the second direction is perpendicular to the first direction;

[0046] An example is Fig. 2 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, and Fig. 3 is a schematic diagram of subpixels of a part of the display area of Fig. 2. As in Fig. 2 - Fig. 3, the display panel 10 provided by at least one embodiment of the present disclosure includes a display area 1, a non-display area 2, a first signal line 01, and a plurality of electrostatic discharge units EU. The display area 1 includes a plurality of subpixels 100, for example, as shown in Fig. 3, the plurality of subpixels are arranged in an array; of course, Fig. 3 only an exemplary representation of the partial subpixels in the display area 1, and the specific arrangement of the plurality of subpixels is not limited to the Fig. 3. The non-display region 2 surrounds at least a part of the display region 1 and includes an electrostatic discharge region 20; the first signal line 01 extends from the display region 1 to the electrostatic discharge region 20 in the first direction D1 as a whole and is configured to provide a first display signal to the subpixels 100. Fig. 4A is a schematic diagram of an arrangement of an electrostatic discharge unit in a display panel provided by an embodiment of the present disclosure, Fig. Figure 4B is an enlarged schematic diagram of a part containing an electrostatic discharge group in Fig. 4A. As in Fig. 4A- Fig. 4B, the plurality of electrostatic discharge units EU are arranged in the first direction D1, and each electrostatic discharge unit EU includes at least one sub-electrostatic discharge unit SEU, wherein each of the at least one sub-electrostatic discharge unit SEU includes an electrostatic discharge circuit EC and a first conductor C1. The electrostatic discharge circuit EC is electrically connected to the first signal line O1 and the first conductor C1 and is configured to migrate charges on the first signal line O1 toward the first conductor C1, thereby reducing the charges on the first signal line O1. For example, each electrostatic discharge unit EU includes a plurality of sub-electrostatic discharge units, wherein each sub-electrostatic discharge unit is electrically connected to a first signal line O1 for electrostatic discharge.

[0047] In the present application, the feature "the first signal line extends in the first direction as a whole" refers to the extension of the first signal line extending along the first direction, which includes the following situations: for example, the first signal line may be a straight line extending in the first direction; alternatively, at least a part of the first signal line has a certain degree of bend or inclination with respect to the first direction, but the direction from the beginning of the first signal line to the end of the first signal line extends along the first direction.

[0048] It should be noted that the first signal line groups Data1, Data2, Data3, Data4... Data n-1 and Data n in Fig. 4A each represent one or more first signal lines electrically connected to an electrostatic discharge unit EU, and each may comprise a plurality of first signal lines 01 electrically connected to the plurality of sub-electrostatic discharge units SEU of the one electrostatic discharge unit EU.

[0049] For example, with reference to Fig. 4A, the plurality of electrostatic discharge units EU of the display panel 10 form a plurality of groups of electrostatic discharge units EUG spaced apart from each other in the second direction D2. Each group of electrostatic discharge units EUG includes M subgroups of electrostatic discharge units SEUG, each subgroup of electrostatic discharge units SEUG includes N electrostatic discharge units EU, each electrostatic discharge unit EU includes Q subelectrostatic discharge units SEU, M and Q are positive integers greater than or equal to 1, and N is a positive integer greater than or equal to 2.

[0050] As in Fig. As shown in Figure 4A, the plurality of electrostatic discharge units EU comprises two adjacent electrostatic discharge units in the second direction D2. The two adjacent electrostatic discharge units are, for example, a first electrostatic discharge unit EU1 and a second electrostatic discharge unit EU2, wherein the second direction D2 is perpendicular to the first direction D1. The orthographic projections of the two adjacent electrostatic discharge units onto the plane parallel to the first direction D1 do not overlap, and the orthographic projections of the two adjacent electrostatic discharge units onto the plane parallel to the second direction D2 at least partially overlap.Therefore, the first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2 are offset not only in the first direction D1 but also in the second direction D2, which can greatly reduce the space occupied by the plurality of electrostatic discharge units EU in the second direction D2, so as to achieve the adjustment of the plurality of electrostatic discharge units even in the case where the size of the electrostatic discharge region 20 in the second direction D2 is small. For example, the pixel array of the display region includes a plurality of sub-pixel columns extending in the first direction D1 and arranged in the second direction D2, and a plurality of sub-pixel rows extending in the second direction D2 and arranged in the first direction D1.The display panel 10 includes a plurality of first signal lines O1, wherein a first signal line O1 provides the first display signal to the corresponding sub-pixel column. In the case where the resolution of the display panel is high, the arrangement density of the sub-pixel columns is very high, so the arrangement density of the first signal lines O1 is also very high. In order to achieve an ideal electrostatic discharge effect and ensure that the static electricity on each first signal line O1 can be released in a timely manner, it is necessary to set electrostatic sub-discharge units SEU for each first signal line O1. In this case, there are a large number of electrostatic sub-discharge units SEU, and the electrostatic discharge area must have a sufficient size in the second direction D2 to accommodate so many electrostatic sub-discharge units SEU.However, in the case where there is limited space for providing more sub-electrostatic discharge units in the display panel 10, for example, in the case where the display panel 10 is an irregular display panel, the edge shape of the irregular display panel is irregular, the size of the edge region located at the bottom of the irregular display panel is very small, that is, the electrostatic discharge region 20 in . Fig. 2 in the second direction D2 is very small, the above technical solution provided by the present disclosure can still achieve a good electrostatic discharge effect by providing sub-electrostatic discharge units SEU on each first signal line O1 while achieving high resolution.

[0051] In the case that two adjacent electrostatic discharge units are the first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2, respectively, “the orthographic projections of two adjacent electrostatic discharge units onto the plane parallel to the second direction D2 are at least partially overlapped with each other” can be understood as follows: the orthographic projections of at least a part of the first electrostatic discharge unit EU1 and at least a part of the second electrostatic discharge unit EU2 onto the plane parallel to the second direction D2 overlap with each other, ieas long as the orthographic projections of two adjacent electrostatic discharge units on the plane parallel to the second direction D2 have an overlap portion, which includes the case that the orthographic projection of a part or the whole of the first electrostatic discharge unit EU1 on the plane parallel to the second direction D2 has an overlap portion with the orthographic projection of the second electrostatic discharge unit EU2 on the plane parallel to the second direction D2, or the case that the orthographic projection of a part or the whole of the second electrostatic discharge unit EU2 on the plane parallel to the second direction D2 has an overlap portion with the orthographic projection of the first electrostatic discharge unit EU1 on the plane parallel to the second direction D2.

[0052] Fig. 4B is an enlarged schematic diagram of a part in Fig. 4A, which includes an electrostatic discharge group.; as in Fig. 4B, the relationship between an electrostatic discharge group and the first signal line is explained using an electrostatic discharge group EUG as an example. For example, as shown in Fig. As shown in Figure 4B, one electrostatic discharge group EUG serves as one electrostatic discharge subgroup SEUG, that is, one electrostatic discharge group EUG includes only one electrostatic discharge subgroup SEUG. For example, each electrostatic discharge subgroup SEUG includes two electrostatic discharge units EU, and each electrostatic discharge unit EU includes three electrostatic discharge subgroup SEUs, namely M=1, N=2, Q=3; of course, this is only an example to introduce the structure of one electrostatic discharge group EUG, without limiting the values of M, N, and Q. For example, the plurality of electrostatic discharge subgroups SEU of the plurality of electrostatic discharge units EU are electrically connected to one of the first signal lines O1 to discharge static electricity on the first signal line O1. For example, as shown in Fig. 4B, the first electrostatic discharge unit EU1 includes three electrostatic sub-discharge units, namely a first electrostatic sub-discharge unit S1a, a second electrostatic sub-discharge unit S2a, and a third electrostatic sub-discharge unit S3a. These three electrostatic sub-discharge units S1a / S2a / S3a are respectively electrically connected to three first signal lines O1a / O1b / O1c arranged continuously in the second direction D2 to release static electricity on the three first signal lines O1a / O1b / O1c, that is, the first signal line group Data1 in Fig. 4A comprises three first signal lines 01a / 01b / 01c. The second electrostatic discharge unit EU2 comprises three electrostatic sub-discharge units, namely a first electrostatic discharge unit S1b, a second electrostatic sub-discharge unit S2b, and a third electrostatic sub-discharge unit S3b. These three electrostatic sub-discharge units S1b / S2b / S3b are each electrically connected to three first signal lines 01d / 01e / 01f arranged one behind the other in the second direction D2 to discharge the static electricity on the three first signal lines 01d / 01e / 01f, i.e., the first signal line group Data1 in Fig. 4A includes three first signal lines 01d / 01e / 01f.

[0053] For example, in combination with Fig. 4A and Fig. 4B, the orthographic projections of the second electrostatic discharge unit EU2 and the first electrostatic discharge unit EU1 on the plane parallel to the second direction D2 at least partially overlap with each other. For example, the orthographic projections of the plurality of sub-electrostatic discharge units in the second electrostatic discharge unit EU2 and the orthographic projections of the plurality of sub-electrostatic discharge units in the first electrostatic discharge unit EU1 on the plane parallel to the second direction D2 at least partially overlap with each other, thereby effectively reducing the space occupied by the plurality of electrostatic discharge units EU in the second direction D2.

[0054] For example, as in Fig. 4B, in the plurality of electrostatic sub-discharge units SEU of the plurality of electrostatic discharge units EU, the orthographic projections of at least two electrostatic sub-discharge units SEU, such as the third electrostatic sub-discharge unit S3a of the first electrostatic discharge unit EU1 and the second electrostatic sub-discharge unit S2b of the second electrostatic discharge unit EU2, do not overlap with each other on the plane parallel to the first direction D1, but the orthographic projections of the at least two electrostatic sub-discharge units SEU at least partially overlap with each other on the plane parallel to the second direction D2, so as to further reduce the space occupied by the plurality of electrostatic discharge units EU on the second direction D2.

[0055] For example, as in Fig. 4B, for each sub-electrostatic discharge unit SEU, the size of the electrostatic discharge circuit EC in the second direction D2 is smaller than the size of the electrostatic discharge circuit EC in the first direction D1.In this way, the layout of each component of the electrostatic discharge circuit EC can be designed to fully utilize the space in the first direction D2 while providing sufficient space for the adjustment of the electrostatic discharge circuit, reducing the space occupied by the electrostatic discharge circuit EC in the second direction D2, thereby facilitating the adjustment of more sub-electrostatic discharge units in the second direction D2, achieving electrostatic discharge for each first signal line, and meeting the electrostatic discharge requirements of the display panel with the electrostatic discharge area of a very small size in the second direction D2.

[0056] For example, as in Fig. 4B, at least one first signal line 01 has a recess in the electrostatic discharge region 20. For example, the first signal line 01d includes a recess P1 in the electrostatic discharge region 20, and the recess P1 forms a groove G1 that is recessed to one side in the second direction D2, wherein the sub-electrostatic discharge unit S3a adjacent to the groove G1, which is the third sub-electrostatic discharge unit S3a of the first electrostatic discharge unit EU1, is at least partially located in the groove G1 to achieve a staggered arrangement and reduce the space occupied by the plurality of sub-electrostatic discharge units in the second direction D2. In the Fig. In the embodiment shown in Figure 4B, the first signal line O1c electrically connected to the third sub-electrostatic discharge unit S3a located in the groove G1 is adjacent to the first signal line O1d including the groove G1; alternatively, in other embodiments, the sub-electrostatic discharge unit located in the groove is electrically connected to the first signal line including the groove.

[0057] For example, as in Fig. 4B, at least one electrostatic discharge unit of the plurality of electrostatic discharge units EU comprises two sub-electrostatic discharge units SEU that are adjacent in the second direction D2, and the two adjacent signal lines, such as the first signal line O1c and the first signal line O1d, both comprise a recess P0 / P1 located in the electrostatic discharge region 20, wherein the recess P0 of the first signal line O1c and the recess P1 of the first signal line O1d form grooves that are recessed toward the same side in the second direction D2, and the adjacent two sub-electrostatic discharge units S2a / S3a are each at least partially located in the groove G0 formed by the recess P0 of the first signal line O1c and the groove G1 formed by the recess P1 of the first signal line O1d,to further effectively reduce the overall width of the plurality of electrostatic discharge units in the second direction D2 and meet the requirements for a narrow electrostatic discharge area.

[0058] For example, as in Fig. 4A and Fig. As shown in Fig. 4B, the first signal line 01d electrically connected to the first sub-electrostatic discharge unit SEU of the first electrostatic discharge unit EU1 includes a first recess P1 and a second recess P2; the first recess P1 forms a first groove G1 recessed toward a first side in the second direction D2; the second recess P2 forms a second groove G2 recessed toward a second side opposite to the first side in the second direction D2, and the second groove G2 is arranged with the first second groove G1 in the second direction D2. The first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2 are two adjacent electrostatic discharge units.The orthographic projection of the first electrostatic discharge unit EU1 parallel to the first direction D1 is located in the orthographic projection of the first groove G1 parallel to the first direction D1, and the orthographic projection of the second electrostatic discharge unit EU2 parallel to the first direction D1 is located in the orthographic projection of the second groove G2 parallel to the first direction D1, to achieve a staggered separation of two adjacent electrostatic discharge units in the second direction D2, thereby reducing the space occupied by the plurality of electrostatic discharge units in the second direction D2. Furthermore, the third sub-electrostatic discharge unit S3a of the first electrostatic discharge unit EU1 and the first sub-electrostatic discharge unit S1b of the second electrostatic discharge unit EU2 are two adjacent sub-electrostatic discharge units.The orthographic projection of the third sub-electrostatic discharge unit S3a parallel to the first direction D1 is located in the orthographic projection of the first groove G1 parallel to the first direction D1, and the orthographic projection of the first sub-electrostatic discharge unit S1b parallel to the first direction D1 is located in the orthographic projection of the second groove G2 parallel to the first direction D1, in order to reduce the space occupied by adjacent electrostatic discharge units in the second direction D2. Furthermore, the first signal line O1c, which is adjacent to the first signal line O1d in the second direction D2, and the first signal line O1b also have a first recess and a second recess similar to those of the first signal line O1d.Orthographic projections of the first recesses and the second recesses of the plurality of first signal lines parallel to the first direction D1 overlap with each other to adjust the staggered arrangement of the adjacent electrostatic discharge units in the second direction and to reduce the overall width of the plurality of electrostatic discharge units and the plurality of first signal lines in the second direction D2.

[0059] For example, as in Fig. 4A, at least a part of the plurality of electrostatic discharge unit groups in a periodic arrangement in the second direction D2, and an electrostatic discharge unit group EUG is a repeating unit in the periodic arrangement to make the arrangement of the plurality of electrostatic discharge unit groups more regular, which contributes to establishing and maintaining the uniformity of routing of the plurality of first signal lines, thereby maintaining the uniformity of the first display signal transmitted through the plurality of first signal lines and the uniformity of the electrostatic discharge effect on the plurality of first signal lines.

[0060] The number of electrostatic sub-discharge units SEU comprising a group of electrostatic discharge units is M * N * Q. For example, in the Fig. 4A and Fig. 4B, M is 1, N is 2, and Q is 3. In this case, for example, the width of a group of electrostatic discharge units EUG in the second direction D2 is less than or equal to 129.5 µm. The higher the resolution, the more the total width of the plurality of electrostatic discharge units in the second direction D2 needs to be reduced. For example, the resolution of the display panel 10 is X * Y, where X represents the number of rows of the pixel array in the display area 1, Y represents the number of columns of the pixel array in the display area 1, X is greater than or equal to 960, and Y is greater than or equal to 1440; for example, X=960, Y=1920; alternatively, X=1920, Y=3840; alternatively, X=1440, Y=1440.For the display panel with such a high resolution, the above arrangement method provided by the embodiment of the present disclosure can also satisfy the requirement for the total width of the plurality of electrostatic discharge units in the second direction D2.

[0061] With reference to Fig. 2, for example, the non-display region 2 includes a feeding region 21, which is the usual bonding region. The feeding region 21 is provided with a COF (Chip On Flex or Chip On Film) comprising a flexible printed circuit (FPC) 23. For example, the flexible printed circuit 23 includes a driver circuit IC configured to provide the first display signal to the data line DL. The electrostatic discharge region 20 is located between the feeding region 21 and the display region 1. For example, in the display panel 10 provided by at least one embodiment of the present disclosure, the plurality of sub-electrostatic discharge units SEU connected to the first signal lines O1, which provide the first display signals to all sub-pixels 100, are all located in the non-display region 2 on the same side of the display region 1 in the first direction D1.That is, the sub-electrostatic discharge units SEU connected to the data lines DL that provide data signals to all sub-pixel columns are all located in the non-display area 2 on the same side of the display area 1, for example, they are all arranged along one edge of the display area 1, instead of having a portion of the sub-electrostatic discharge units SEU arranged on the first side of the display area 1 and the other portion of the sub-electrostatic discharge units SEU arranged on the second side opposite the first side of the display area 1. For example, the non-display area 2 also includes an edge area including a first edge area 2a and a second edge area 2b.The first edge region 2a is located on the first side of the display area 1, and the sub-electrostatic discharge units SEU, which are connected to the data lines DL and provide data signals to all sub-pixel columns, are all located in the first edge region 2a and not in the second edge region 2b. Therefore, the driver circuits only need to be arranged near the first edge region 2a, which reduces manufacturing difficulty and simplifies the structure.Even in this case, the arrangement of the sub-electrostatic discharge units SEU provided by the embodiments of the present disclosure can still meet the requirement of setting a large number of sub-electrostatic discharge units SEU by using the limited width in the second direction D2 of the area on the same side of the display area 1, even if the planar shape of the display panel is the above irregular shape of the display panel 10, a large number of sub-electrostatic discharge units SEU can also be set by using the limited width in the second direction D2 of a part of the irregular edge while taking the high PPI into account.

[0062] With reference to Fig. 2, for example, the first edge region 2a is located between the supply region 21 and the display region 1, and the second edge region 2b is located on the second side of the display region 1 opposite the first side. A first power supply line PL is provided in the first edge region 2a, and the first power supply line PL is configured to supply a first power supply voltage VDD to the subpixel 100; the supply region 21 includes a data selection region 22 located on a side of the edge region remote from the display region 1. The data selection region 22 is provided with a data selection unit, and the electrostatic discharge region 20 is located between the first power supply line PL and the data selection region 22.

[0063] Alternatively, the first power supply line PL is configured to supply a second supply voltage VSS to the subpixel 100. For example, the first power supply line PL is arranged in the same layer as the gate electrode T01g of the first electrostatic discharge transistor T01 and is connected via a via or directly to the cathode of the subpixel covering the entire display area 1 in the non-display area 2. For example, the material of the first power supply line PL, which provides the second power supply voltage VSS, is a transparent conductive material, such as indium zinc oxide (ITO), indium zinc oxide (IZO), etc.

[0064] Fig. 4C is a schematic diagram of an arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure. Fig. The embodiment shown in Figure 4C differs from Fig. 4A in the following aspects.

[0065] In the Fig. In the embodiment shown in Figure 4C, M is 2, N is 2, and Q is 3.

[0066] For example, as in Fig. As shown in Figure 4C, the M subgroups of electrostatic discharge units SEUG include a first subgroup of electrostatic discharge units SEUG1 and a second subgroup of electrostatic discharge units SEUG2. The first subgroup of electrostatic discharge units SEUG1 and the second subgroup of electrostatic discharge units SEUG2 are symmetrical with respect to the axis of symmetry extending in the first direction D1, so that the arrangement of the plurality of electrostatic discharge unit groups is more regular, which contributes to establishing and maintaining the uniformity of the routing of the plurality of first signal lines, thereby maintaining the uniformity of the first display signals transmitted by the plurality of first signal lines and the uniformity of the electrostatic discharge effect on the plurality of first signal lines.Alternatively, in other embodiments, the first electrostatic discharge unit group and the second electrostatic discharge unit group may also be asymmetric.

[0067] The other features of the Fig. 4C are the same as those shown in Fig. 4A and Fig. 4B, which may refer to the previous descriptions.

[0068] Fig. 4C is a schematic diagram of an arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure. Fig. The embodiment shown in Figure 4D differs from Fig. 4A in the following aspects. For example, for at least some electrostatic discharge units, such as two adjacent electrostatic discharge units, taking the second electrostatic discharge unit EU2 and the third electrostatic discharge unit EU3, which are adjacent to each other in the first electrostatic discharge unit group SEUG1 as an example, the orthographic projections of the two adjacent electrostatic discharge units are not overlapped with each other on the plane parallel to the first direction D1 and are spaced from each other in the second direction D2, iethe orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the second direction D2 are not overlapped with each other, in this case, for example, the distance between the two adjacent electrostatic discharge units in the second direction D2 is less than 1µm, and the distance between the adjacent edges of the two adjacent electrostatic discharge units in the second direction D2 is less than 1µm.

[0069] In the Fig. In the embodiment shown in Figure 4D, in the case where M is 2, N is 3, and Q is 3, the width of a group of electrostatic discharge units in the second direction D2 is less than or equal to 294 μm. That is, the total width of 18 sub-electrostatic discharge units included in a group of electrostatic discharge units in the second direction D2 is 294 μm to meet the requirement of providing sufficient space for setting additional electrostatic discharge units when the width of the electrostatic discharge area in the second direction D2 is narrower.

[0070] Fig. 4E is a schematic diagram of an arrangement of another electrostatic discharge unit in an electrostatic discharge region of the display panel provided by an embodiment of the present disclosure. Fig. The embodiment shown in Figure 4E differs from Fig. 4A by the fact that in the Fig. 4E, orthographic projections of two adjacent electrostatic discharge units, such as the first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2, on the plane parallel to the first direction D1 do not overlap with each other and the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the second direction D2 do not overlap with each other in order to reduce the plurality of electrostatic discharge units to a certain extent, for example in each subgroup of the electrostatic discharge units SEUG,the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the first direction D1 do not overlap with each other, and the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the second direction D2 do not overlap with each other. For example, in the display panel 10 provided by at least one embodiment of the present disclosure, in the plurality of electrostatic discharge units EU, the orthographic projections of each two adjacent electrostatic discharge units EU on the plane parallel to the first direction D1 do not overlap with each other. The other features of the display panel shown in , Fig. 4E are the same as those shown in Fig. 4A and Fig. 4B, which may refer to the previous descriptions.

[0071] Fig. 5A is a schematic diagram of an electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure. As shown in Fig. For example, as shown in Figure 5A, the electrostatic discharge circuit EC includes a first subcircuit 001, the first subcircuit 001 having a driving end, a first end, and a second end; the driving end and the first end of the first subcircuit 001 are electrically connected to the first signal line 01, and the second end of the first subcircuit 001 is electrically connected to the first conductor C1. In this way, the static electricity accumulated on the first signal line 01 can be transferred to the first conductor C1 through the first subcircuit 001, thereby reducing the charges on the first signal line 01 and preventing the accumulation of static electricity on the first signal line 01 from causing display errors.

[0072] As in Fig. 5A, for example, the sub-electrostatic discharge unit SEU includes a second conductor C2, and the electrostatic discharge circuit EC is electrically connected to the first signal line O1 and the second conductor C2 and is configured to migrate the charges on the first signal line O1 toward the second conductor C2, thereby reducing the charges on the first signal line O1. The electrostatic discharge circuit EC further includes a second sub-circuit O02, wherein the second sub-circuit O02 has a driving end, a first end, and a second end, the first end of the second sub-circuit O02 is electrically connected to the first signal line O1, and both the driving end and the second end of the second sub-circuit O02 are connected to the second conductor C2.In this way, the static electricity accumulated on the first signal line 01 can also be transferred to the second conductor C2 through the second subcircuit 002, thereby reducing the charges on the first signal line 01 and preventing the accumulation of static electricity on the first signal line 01 from causing display errors.

[0073] For example, in some embodiments, the electrostatic discharge circuit may include only the first subcircuit and not the second subcircuit mentioned above.

[0074] For example, in the electrostatic discharge area 20 of the display panel 10, the first sub-circuit 001 and the second sub-circuit 002 are arranged in the first direction D1 to reduce the total width of the first sub-circuit 001 and the second sub-circuit 002 in the second direction D2 by designing the arrangement method of the first sub-circuit 001 and the second sub-circuit 002, thereby reducing the total width of the static discharge unit in the second direction D2 to meet the requirement of arranging more sub-electrostatic discharge units in the limited space in the second direction D2.

[0075] Fig. 5B is a schematic diagram of a specific electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure. As shown in Fig. 5B, in the electrostatic discharge circuit EC, the first subcircuit 001 includes a first electrostatic discharge transistor T01, and the second subcircuit 002 includes a second electrostatic discharge transistor T02; the gate electrode T01g and the first electrode T01s of the first electrostatic discharge transistor T01 are electrically connected to the first signal line O1, and the second electrode T01d of the first electrostatic discharge transistor T01 is electrically connected to the first conductor C1; the first electrode T02s of the second electrostatic discharge transistor T02 is electrically connected to the first signal line O1, and the gate electrode T02g and the second electrode T02d of the second electrostatic discharge transistor T02 are both connected to the second conductor C2. The first conductor C1 is connected to a high-voltage terminal VGH and the second conductor C2 is connected to a low-voltage terminal VGL.For example, the polarity of the voltage supplied by the high-voltage terminal VGH is opposite to the polarity of the voltage supplied by the low-voltage terminal VGL. For example, the polarity of the first voltage Vh supplied by the high-voltage terminal VGH is positive, and the polarity of the second voltage Vl supplied by the low-voltage terminal VGL is negative.

[0076] Depending on the characteristics of the transistors, they can be divided into N-type transistors and P-type transistors. If the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0 V, -5 V, -10 V, or other suitable voltage), and the turn-off voltage is a high voltage (e.g., 5 V, 10 V, or other suitable voltage); if the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0 V, -5 V, -10 V, or other suitable voltage).

[0077] The operation of the electrostatic discharge circuit EC is as follows, where the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02 are N-type transistors, for example. When the first display signal (e.g., the data signal Vd described below) transmitted on the first signal line O1 is at a high level, the gate electrode T01g of the first electrostatic discharge transistor T01 responds to the high level, enabling the first electrostatic discharge transistor T01 to turn on. In this case, the second voltage Vl is at a low level, e.g., -8V, -6V, etc.The gate electrode T02g of the second electrostatic discharge transistor T02 responds to the low level and enables the second electrostatic discharge transistor T02 to be turned off, so that the charges on the first signal line O1 are transferred through the first electrostatic discharge transistor T01 to the first conductor C1; in the case where the first display signal transmitted on the first signal line O1 (such as the data signal Vd described below) is at a low level, such as-30V, -20V, -10V or another suitable voltage, the gate electrode T01g of the first electrostatic discharge transistor T01 responds to the low level and enables the first electrostatic discharge transistor T01 to be turned off, due to the fact that the second voltage Vl is a low level voltage and is higher than the low level voltage of the first display signal transmitted on the first signal line O1, that is, is higher than the low level voltage at the gate electrode T01g of the first electrostatic discharge transistor T01, for example, the second voltage Vl is -8V, -6V, etc., so that the gate-source voltage Vgs of the second electrostatic discharge transistor T02 satisfies: Vgs=Vg-Vs=Vl-Vd>Vth, and Vd in this calculation formula represents the low-level voltage of the first display signal transmitted on the first signal line O1, Vth represents the threshold voltage of the second electrostatic discharge transistor T02, therefore the second electrostatic discharge transistor T02 is turned on, and the charges on the first signal line O1 are transferred through the second electrostatic discharge transistor T02 to the second conductor C2. For example: Vl=-8V and Vd=-20V, Vgs=Vg-Vs=Vl-Vd=-8-(-20)=16V, Vgs is greater than the threshold voltage of a typical transistor.In this way, in the case where the first display signal transmitted on the first signal line 01 has a high level or a low level, the static charges accumulated on the first signal line 01 can be discharged by the electrostatic discharge circuit EC shown in . Fig. 5B shown.

[0078] For example, as in Fig. 3, the plurality of subpixels 100 in the display area 1. For example, in the display substrate 10 provided by some embodiments, some subpixels in the plurality of subpixels 100 are dummy subpixels 1000, and the dummy subpixels 1000 do not participate in the display work.

[0079] For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 may further include a plurality of scan lines and a plurality of data lines DL configured to provide scan signals (control signals) and data signals, respectively, for driving the plurality of subpixels. Depending on the requirements, the display substrate 10 may also include power lines, sense lines, etc.

[0080] Fig. 6A is a schematic diagram of a pixel circuit of a subpixel provided by at least one embodiment of the present disclosure. As shown in Fig. As shown in Figure 6A, a pixel circuit unit 100 includes a driver subcircuit 122, a compensation subcircuit 128, a data write subcircuit 126, a storage subcircuit 127, a first emission control subcircuit 123, a second emission control subcircuit 124, a first reset subcircuit 125, and a second reset subcircuit 129.

[0081] For example, the driver subcircuit 122 includes a control end 122a, a first end 122b, and a second end 122c, and is configured to be connected to a light-emitting device 121 and to control the drive current flowing through the light-emitting device 121. The control end 122a of the driver subcircuit 122 is connected to a first node N1, the first end 122b of the driver subcircuit 122 is connected to a second node N2 and configured to receive a first power supply voltage VDD, and the second end 122c of the driver subcircuit 122 is connected to a third node N3.

[0082] For example, the data write subcircuit 126 includes a control end 126a, a first end 126b, and a second end 126c. The control end 126a is configured to receive a first sensing signal Ga1, the first end 126b is configured to receive a data signal Vd, and the second end 126c is connected to the first end 122b of the driver subcircuit 122 (i.e., the second node N2). The data write subcircuit 126 is configured to write the data signal Vd to the first end 122b of the driver subcircuit 122 in response to the first sensing signal Ga1. For example, the first end 126b of the data write subcircuit 126 is connected to a data line DL for receiving the data signal Vd, and the control end 126a is connected to a gate line 11 serving as a sensing line for receiving the first sensing signal Ga1.For example, in a data writing and compensation stage, the data writing subcircuit 126 may be turned on in response to the first strobe signal Ga1, thereby writing the data signal to the first end 122b of the driving subcircuit 122 (the second node N2) and storing the data signal in the storage subcircuit 127 to generate a driving current that drives the light-emitting device 121 to emit light, for example, during a light emission stage.

[0083] For example, the compensation subcircuit 128 includes a control end 128a, a first end 128b, and a second end 128c. The control end 128a of the compensation subcircuit 128 is configured to receive a second sensing signal Ga2, and the first end 128b and the second end 128c of the compensation subcircuit 128 are electrically connected to the second end 122c and the control end 122a of the driver subcircuit 122, respectively. The compensation subcircuit 128 is configured to perform threshold compensation on the driver subcircuit 122 in response to the second sensing signal Ga2.

[0084] For example, the first scanning signal Ga1 may be the same as the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to the same signal output terminal. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted via the same scanning line.

[0085] In other examples, the first scanning signal Ga1 may also be different from the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to different signal output terminals. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted via different scanning lines.

[0086] For example, the memory subcircuit 127 includes a first end 127a and a second end 127b, wherein the first end 127a of the memory subcircuit is configured to receive the first supply voltage VDD, and the second end 127b of the memory subcircuit is electrically connected to the control end 122a of the drive subcircuit.

[0087] For example, the storage subcircuit 127 is electrically connected to the control terminal 122a of the driver subcircuit 122 and a first voltage terminal vdd and is configured to store the data signal written by the data write subcircuit 126. For example, in the data write and compensation stages, the compensation subcircuit 128 may be turned on in response to the second strobe signal Ga2, thereby storing the data signal written by the data write subcircuit 126 in the storage subcircuit 127. For example, during the data write and compensation phases, the compensation subcircuit 128 may electrically connect the control end 122a and the second end 122c of the driver subcircuit 122 so that the relevant threshold voltage information of the driver subcircuit 122 can also be stored in the storage subcircuit accordingly.For example, during the light emission phase, the stored data signal and the threshold voltage may be used to control the driver subcircuit 122 so that the output of the driver subcircuit 122 may be compensated.

[0088] For example, the first emission control subcircuit 123 is connected to the first end 122b of the driver subcircuit 122 (the second node N2) and the first voltage end vdd, and is configured to apply the first power supply voltage VDD of the first voltage end vdd to the first end 122b of the driver subcircuit 122 in response to a first emission control signal EM1. For example, as shown in Fig. 6A, the first emission control subcircuit 123 is connected to the first emission control terminal EM1, the first voltage terminal vdd and the second node N2.

[0089] For example, the second emission control subcircuit 124 is connected to a second emission control terminal EM2, the first end 134 of the light-emitting device 121, and the second end 122c of the driver subcircuit 122, and is configured to respond to the second emission control signal to allow the driver current to be applied to the light-emitting device 121.

[0090] For example, in the light-emitting stage, the second emission control subcircuit 124 is turned on in response to the second emission control signal EM2 provided from the second emission control terminal EM2, so that the driving subcircuit 122 can be electrically connected to the light-emitting device 121 via the second emission control subcircuit 124, thereby driving the light-emitting device 121 to emit light under the control of the driving current; in the non-light-emitting stage, the second emission control subcircuit 124 is turned off in response to the second emission control signal EM2, thereby avoiding the current flowing through the light-emitting device 121 and causing the light-emitting device to emit light to improve the contrast of the corresponding display device.

[0091] For example, during an initialization phase, the second emission control subcircuit 124 may also be turned on in response to the second emission control signal EM2, thereby combining it with a reset subcircuit to perform a reset operation on the driver subcircuit 122 and the light-emitting device 121.

[0092] For example, the second emission control signal EM2 and the first emission control signal EM1 may be the same, for example, the second emission control signal EM2 and the first emission control signal EM1 may be connected to the same signal output terminal, for example, the second emission control signal EM2 and the first emission control signal EM1 may be transmitted via the same emission control line.

[0093] In other examples, the second emission control signal EM2 and the first emission control signal EM1 may be different. For example, the second emission control signal EM2 and the first emission control signal EM1 may be connected to different signal output terminals. For example, the second emission control signal EM2 and the first emission control signal EM1 may be transmitted via different emission control lines.

[0094] For example, the first reset subcircuit 125 is connected to a first reset voltage terminal Vinit1 and the control terminal 122a of the driver subcircuit 122 (the first node N1) and is configured to apply a first reset voltage Vinit1 to the control terminal 122a of the driver subcircuit 122 in response to a first reset control signal Rst1.

[0095] For example, the second reset subcircuit 129 is connected to a second reset voltage terminal Vinit2 and the first end 134 of the light-emitting device 121 (a fourth node N4) and is configured to apply a second reset voltage Vinit2 to the first end 134 of the light-emitting device 121 in response to a second reset control signal Rst2.

[0096] For example, the first reset subcircuit 125 and the second reset subcircuit 129 may be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 may be applied to the first node N1 and the first reset voltage Vinit1 may be applied to the first end 134 of the light-emitting device 121, thereby resetting the driver subcircuit 122, the compensation subcircuit 128, and the light-emitting device 121 and eliminating the effect of the previous light-emitting stage.

[0097] For example, the second reset control signal Rst2 of each row of subpixels may be the same signal as the first scanning signal Ga1 of that row of subpixels, and the second reset control signal Rst2 and the first scanning signal Ga1 may be transmitted via the same gate line (such as the reset control line 220b in Fig. 3A). For example, the first reset control signal Rst1 of each row of subpixels may be the same signal as the first scanning signal Ga1 of the previous row of subpixels, and the first reset control signal Rst1 and the first scanning signal Ga1 may be transmitted via the same gate line (such as the reset control line 220a in Fig. 3A).

[0098] For example, as in Fig. 6A, the light-emitting device 121 includes a first end 134 and a second end 135. The first end 134 of the light-emitting device 121 is configured to be connected to the second end 122c of the control subcircuit 122, and the second end 135 of the light-emitting device 121 is configured to be connected to a second voltage terminal VSS. For example, in one example, as shown in Fig. 6A, the first end 134 of the light-emitting device 121 may be connected to the fourth node N4 via the second emission control subcircuit 124. The embodiments of the present disclosure also include this situation, but are not limited thereto.

[0099] It should be noted that in explaining the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but rather the connection points of the corresponding circuit connections in the circuit diagram.

[0100] It should be noted that in the description of embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first strobe signal and the second strobe signal end, as well as the first strobe signal terminal and the second strobe signal terminal. The symbol Rst1 can represent both the first reset control terminal and the first reset control signal, and the symbol Rst2 can represent both the second reset control terminal and the second reset control signal. The symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal, as well as the first reset voltage and the second reset voltage. The symbol VDD can represent both the first supply voltage and the first supply line.The symbol VSS can represent both the common supply voltage and the common supply line. The following embodiments are identical and will not be repeated.

[0101] Fig. 6B is a circuit diagram for a specific implementation example of the Fig. 6A. As shown in Fig. As shown in Figure 6B, the pixel circuit includes the first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst. For example, the first transistor T1 is used as a driver transistor, and the other second to seventh transistors are used as switching transistors.

[0102] For example, as in Fig. 6B, the driver subcircuit 122 can be implemented as a first transistor T1. The gate electrode of the first transistor T1 serves as the control terminal 122a of the driver subcircuit 122 and is connected to the first node N1; the first electrode of the first transistor T1 serves as the first end 122b of the driver subcircuit 122 and is connected to the second node N2; the second electrode of the first transistor T1 serves as the second end 122c of the driver subcircuit 122 and is connected to the third node N3.

[0103] For example, as in Fig. 6B, the data write subcircuit 126 may be implemented as a second transistor T2. The gate electrode of the second transistor T2 is connected to the first scan signal terminal Ga1 to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line DL (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first end 122b of the driver subcircuit 122 (the second node N2).

[0104] For example, as in Fig. 6B, the compensation subcircuit 128 can be implemented as a third transistor T3. The gate electrode, the first electrode, and the second electrode of the third transistor T3 serve as the control end 128a, the first end 128b, and the second end 128c of the compensation subcircuit, respectively. The gate electrode of the third transistor T3 is configured to be connected to the second scanning line (the second scanning signal terminal Ga2) to receive the second scanning signal. The first electrode T3s of the third transistor T3 is connected to the second electrode T1d of the first transistor T1 (the third node N3), and the second electrode T3d of the third transistor T3 is electrically connected to the gate electrode T1g of the first transistor T1 (the first node N1). For example, as shown in Fig. As shown in Figure 6B, the storage subcircuit 127 can be implemented as a storage capacitor Cst, wherein the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2. The first electrode plate Cst2 is electrically connected to the first voltage terminal vdd, and the second electrode plate Cst1 is electrically connected to the gate electrode T1g of the first transistor T1 (the first node N1).

[0105] For example, as in Fig. 6B, the first emission control subcircuit 123 may be implemented as a fourth transistor T4. The gate electrode of the fourth transistor T4 is connected to the first emission control line (the first emission control terminal EM1) to receive the first emission control signal, the first electrode of the fourth transistor T4 is connected to the first voltage terminal vdd to receive the first supply voltage, and the second electrode of the fourth transistor T4 is connected to the first end 122b of the driver subcircuit 122 (the second node N2).

[0106] For example, the light-emitting device 121 is specifically implemented as a light-emitting diode (LED), which may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, which may be a micro light-emitting diode (Micro LED) or a Micro OLED. For example, the light-emitting device 121 may be a top-emitting structure, a bottom-emitting structure, or a double-sided emitting structure. The light-emitting device 121 may emit red, green, blue, or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting device.

[0107] For example, the first end of the light-emitting device 121 includes a first electrode (such as an anode). The first electrode is connected to the fourth node and is configured to be connected to the second end 122c of the driver subcircuit 122 through the second emission control subcircuit 124. The second end of the light-emitting device 121 includes a second electrode (such as a cathode). The second electrode is configured to be connected to the common power supply voltage terminal VSS to receive the common power supply voltage VSS. The current flowing into the light-emitting device 121 from the second end 122c of the driver subcircuit 122 determines the brightness of the light-emitting device. For example, the common supply voltage terminal VSS may be grounded, which means that VSS may be 0 V.For example, the common power supply voltage VSS may be negative.

[0108] For example, the second emission control subcircuit 124 may be implemented as a fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the second emission control line (the second emission control end EM2) to receive the second emission control signal, the first electrode of the fifth transistor T5 is connected to the second end 122c of the driver subcircuit 122 (the third node N3), and the second electrode of the fifth transistor T5 is connected to the first end 134 of the light-emitting device 121 (the fourth node N4).

[0109] For example, the first reset subcircuit 125 may be implemented as a sixth transistor T6, and the second reset subcircuit may be implemented as a seventh transistor T7. The gate electrode of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N1.The gate electrode of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0110] It should be noted that the transistors used in the embodiments of the present disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, the case where all thin-film transistors are thin-film transistors is used as an example for explanation. The source electrode and drain electrode of the transistor used here may be structured symmetrically so that the source electrode and drain electrode are structurally indistinguishable. To distinguish the two electrodes of the transistor except for the gate electrode, one electrode is directly referred to as the first electrode and the other electrode as the second electrode in the embodiments of the present disclosure.

[0111] For example, as in Fig. As shown in Figure 6B, the first to seventh transistors T1-T7 are all P-type transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, the embodiments of the present disclosure do not limit the type of transistors. If the transistor type changes, the connection relationship in the circuit can be adjusted accordingly.

[0112] The functional principle of the Fig. 6B will be described below with reference to the Fig. 6C. As shown in Fig. As shown in Figure 6C, the display process of each image includes three stages, namely an initialization stage 1, a data writing and compensation stage 2, and a light emission stage 3.

[0113] As in Fig. 6C, in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 assume the same signal, and the first emission control signal EM1 and the second emission control signal EM2 assume the same signal; and the waveform of the second reset control signal Rst2 and the waveform of the first scanning signal Ga1 / the second scanning signal Ga2 are the same, that is, the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 can use the same signal; the waveform of the first reset signal Rst1 of the current row of sub-pixels is the same as the waveform of the first scanning signal Ga1 / the second scanning signal Ga2 of the previous row of sub-pixels, that is, the first reset signal Rst1 of the current row of sub-pixels and the first scanning signal Ga1 / the second scanning signal Ga2 of the previous row of sub-pixels assume the same signal.However, this does not constitute a limitation of the present disclosure. In other embodiments, different signals may be adopted as the first sensing signal Ga1, the second sensing signal Ga2, the first reset control signal Rst1 and the second reset control signal Rst2, respectively, and different signals may be adopted as the first emission control signal EM1 and the second emission control signal EM2, respectively.

[0114] In the initialization stage 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate electrode of the first transistor T1, thereby resetting the first node N1.

[0115] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2, and the data signal Vd are input. The second transistor T2 and the third transistor T3 are turned on, and the data signal Vd is written to the second node N2 by the second transistor T2. The first node N1 is charged by the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored in the storage capacitor Cst to be maintained, which means that the voltage information including the data signal and the threshold voltage Vth is stored in the storage capacitor Cst to provide grayscale display data and compensate the threshold voltage of the first transistor T1 during the subsequent emission stage.

[0116] In the data write compensation stage 2, the second reset control signal Rst2 may also be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4, thereby resetting the fourth node N4. For example, the resetting of the fourth node N4 may also be performed in the initialization stage 1; for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiments of the present disclosure are not limited in this aspect.

[0117] In emission stage 3, the first emission control signal EM1 and the second emission control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5, and the first transistor T1. The fifth transistor T5 applies the drive current to the OLED to illuminate the OLED. The value of the drive current Id flowing through the OLED can be determined by the following formula:

[0118] Id=K(VGS-Vth)2=K[(Vd+Vth-VDD)-Vth]2=K(Vd-VDD)2, where K is the conductivity of the first transistor.

[0119] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate electrode and the source electrode (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. From the above formula for calculating Id, it can be seen that the drive current Id flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1, thereby achieving compensation for the pixel circuit, solving the problem of threshold voltage drift caused by the drive transistor (the first transistor T1 in the embodiments of the present disclosure) due to the process and long-term operation, and eliminating its effect on the drive current Id, and therefore improving the display effect of the display device using the pixel circuit.

[0120] Referring to Fig. 3, the display substrate 10 includes a base substrate 200, a first signal line O1 extending entirely in the first direction D1 on the base substrate 200, and a second signal line O2 extending entirely in the second direction D2 on the base substrate 200. For example, the first signal line O1 intersects with the second signal line O2 to define a plurality of subpixels 100. Note that the boundaries of the plurality of subpixels do not necessarily have to be the first signal line O1 and the second signal line O2. When the first signal line O1 and the second signal line O2 intersect to define a plurality of subpixels, this means that the arrangement of the plurality of subpixels coincides with the arrangement of the plurality of regions defined by the intersection of the first signal line O1 and the second signal line O2, i.e.the plurality of subpixels corresponds one-to-one to the plurality of regions defined by the intersection point of the first signal line O1 and the second signal line O2.

[0121] For example, the first signal line O1 is the data line DL, and the second signal line O2 is the gate line serving as a scanning signal line. The first display signal is the data signal Vd, and the first signal line O1 transmits the data signal Vd; each of at least some sub-pixels 100 in the plurality of sub-pixels 100 includes the above-mentioned pixel circuit including the light-emitting device, the driving transistor T1, and the data writing transistor T2. The data writing transistor T2 is configured to transmit the data signal Vd to the driving transistor T1 under the control of the first scanning signal Ga1; the driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device based on the data signal Vd, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light.

[0122] In other embodiments, the first signal line may of course also consist of other types of signal lines. In the present disclosure, the first signal line is not limited to the aforementioned data line DL.

[0123] Fig. 7A is a planar schematic diagram of a structure of a sub-electrostatic discharge unit of a display panel provided by at least one embodiment of the present disclosure; Fig. Figure 7B is a schematic diagram of a semiconductor layer of the sub-electrostatic discharge unit used in Fig. 7A is shown; Fig. Figure 7C is a schematic diagram of a first conductive layer of the sub-electrostatic discharge unit shown in Fig. 7A shown electrostatic sub-discharge unit; Fig. 7D is a schematic diagram of an interlayer insulation layer of the Fig. 7A shown electrostatic sub-discharge unit; Fig. Figure 7E is a schematic diagram of a second conductive layer of the Fig. 7A shown electrostatic sub-discharge unit; and Fig. Figure 7F is a schematic cross-sectional diagram along a line A1-A2 in Fig. 7A.

[0124] With reference to Fig. 7A, for example, in the display panel 10 provided by at least one embodiment of the present disclosure, the size of the electrostatic discharge circuit EC in the second direction D2 is smaller than the size of the electrostatic discharge circuit EC in the first direction D1, and the second direction D2 is perpendicular to the first direction D1 to minimize the width of each sub-electrostatic discharge unit in the second direction D2 as much as possible, thereby greatly reducing the total width of the plurality of sub-electrostatic discharge units in the second direction D2.

[0125] Referring to Fig. 7A, for example, the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02 are arranged in the first direction D1, the first electrode T01s and the second electrode T01d of the first electrostatic discharge transistor T01 are arranged in the first direction D1, and the first electrode T01s and the second electrode T01d of the first electrostatic discharge transistor T01 are arranged in the first direction D1, and the first electrode T02s and the second electrode T02d of the second electrostatic discharge transistor T02 are arranged in the first direction D1, in order to reduce the total width in the second direction D2 of the whole formed by the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02 by designing the arrangement mode of the first electrostatic discharge transistor T01,of the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02, the source electrode and the drain electrode of the first electrostatic discharge transistor T01 and the source electrode and the drain electrode of the second electrostatic discharge transistor T02, thereby reducing the width in the second direction D2 of the electrostatic discharge circuit and reducing the width in the second direction D2 of the electrostatic discharge unit to meet the requirement of arranging more sub-electrostatic discharge units in the limited space in the second direction D2.

[0126] With reference to Fig. 7A and Fig. 7B, for example, the first electrostatic discharge transistor T01 includes a first active layer T01a, and the second electrostatic discharge transistor T02 includes a second active layer T02a; the first active layer T01a and the second active layer T02a both extend in the first direction D1.The width in the second direction D2 of the first active layer T01a is smaller than the length in the first direction D1 of the first active layer T01a, and the width in the second direction D2 of the second active layer T02a is smaller than the length in the first direction D1 of the second active layer T02a in order to utilize the space in the first direction to arrange the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02, and to further reduce the widths in the second direction D2 of the first electrostatic discharge transistors T01 and the second electrostatic discharge transistors T02 while considering the proper sizes of the first active layer and the second active layer and the performance of the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02.For example, the width in the second direction D2 of the first active layer T01a is smaller than the length in the first direction D1 of the first active layer T01a, and the width in the second direction D2 of the second active layer T02a is smaller than the length in the first direction D1 of the second active layer T02a, so as to further reduce the widths in the second direction D2 of the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02 while considering the proper sizes of the first second active layer and the second active layer as well as the performance of the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02.

[0127] With reference to Fig. 7A and Fig. 7B, for example, the electrostatic discharge semiconductor layer is located in the semiconductor layer ACT. The first active layer T01a and the second active layer T02a form a continuous, integral electrostatic discharge semiconductor layer, and the electrostatic discharge semiconductor layer has the shape of a stripe extending as a whole in the first direction D1.For example, the electrostatic discharge semiconductor layer is located in a straight stripe shape on a side remote from the data line DL of both the first stripe portion S1 and the second stripe portion S2 to further reduce the space occupied by the first gate portion GP1, the second gate portion GP2, and the electrostatic discharge semiconductor layer in the second direction D2, thereby further reducing the width in the second direction D2 of one sub-electrostatic discharge unit, which can effectively reduce the total width in the second direction D2 occupied by the plurality of sub-electrostatic discharge units.

[0128] With reference to Fig. 7A and Fig. 7C, for example, the first conductor C1 and the second conductor C2, the gate electrode T01g of the first electrostatic discharge transistor T01, and the gate electrode T02g of the second electrostatic discharge transistor T02 are all located in the first conductive layer 110. For example, the gate electrode T01g of the first electrostatic discharge transistor T01 and the gate electrode T02g of the second electrostatic discharge transistor T02 are both located in the same layer as the gate electrode of the driver transistor T1 of the pixel circuit, so that the gate electrode T01g of the first electrostatic discharge transistor T01 and the gate electrode T02g of the second electrostatic discharge transistor T02 can be formed using the same mask and patterning process as the gate electrode of the driver transistor T1 of the pixel circuit.which simplifies the production process and the layered structure of the display panel. The first conductor C1 and the second conductor C2 are spaced apart from each other in the first direction D1, and the first conductor C1 extends in the second direction D2. The sub-electrostatic discharge unit SEU includes a first gate portion GP1; the second conductor C2 includes a main body portion CM extending in the second direction D2, and a second gate portion GP2 connected to the main body portion CM and extending in the second direction D2.For example, the second gate portion GP2 forms a continuous and integral structure with the main body portion CM of the second conductor C2; the first gate portion GP1 and the second gate portion GP2 are spaced apart from each other in the first direction D1, and the first gate portion GP1 and the second gate portion GP2 are located between the first conductor C1 and the main body portion CM of the second conductor C2; the portion of the first gate portion GP1 that overlaps with the first active layer T01a forms the gate electrode T01g of the first electrostatic discharge transistor T01; the portion of the second gate portion GP2 that overlaps with the second active layer T02a forms the gate electrode T02g of the second electrostatic discharge transistor T02; and the first gate portion GP1 is electrically connected to the data line DL.

[0129] With reference to Fig. 7A and Fig. 7C, for example, the first gate portion GP1 includes a first stripe portion S1 extending in the first direction D1 and a gate interconnection structure CG electrically connected to the first stripe portion S1. The gate interconnection structure CG protrudes from the first stripe portion S1 toward the data line DL in the second direction D2, and the gate interconnection structure CG is electrically connected to the data line DL via a first via V1. The first gate portion GP1 further includes a first protrusion portion electrically connected to the first stripe portion S1, the first protrusion portion protruding from the first stripe portion S1 in the second direction D2 away from the data line DL. The part of the first protrusion portion that overlaps with the first active layer T01a forms the gate electrode T01g of the first electrostatic discharge transistor T01.For example, the first protrusion portion includes a first terminal block G1 and a second terminal block G2 arranged in the first direction D1 and spaced from each other. The second gate portion GP2 includes a second stripe portion S2 extending in the first direction D1 and a second protrusion portion electrically connected to the second stripe portion S2. The second protrusion portion protrudes from the second stripe portion S2 in the second direction D2, and the part of the second protrusion portion overlapping with the second active layer T02a forms the gate electrode T02g of the second electrostatic discharge transistor T02. For example, the second protrusion portion includes a third terminal block G3 and a fourth terminal block G4 arranged in the first direction D1 and spaced from each other.

[0130] With reference to Fig. 7A and Fig. 7C, for example, the second protrusion protrudes from the second stripe portion S2 in a direction away from the data line DL in the second direction D2. The first stripe portion S1 is substantially aligned with the second stripe portion S2 in the first direction D1, and the first protrusion portion and the second protrusion portion are substantially aligned in the first direction D1 to reduce the width of the second gate portion GP2 in the second direction D2, thereby reducing the width of one sub-electrostatic discharge unit in the second direction D2, which can effectively reduce the total width occupied by the plurality of sub-electrostatic discharge units in the second direction D2.

[0131] With reference to Fig. 7A and Fig. 7E, for example, the first signal line O1 is located in the second conductive layer 120. The sub-electrostatic discharge unit SEU further includes a data connection structure DL1 electrically connected to the data line DL and protruding from the data line DL toward the electrostatic discharge semiconductor layer in the second direction D2. The first end of the data connection structure DL1 near the data line DL in the second direction D2 is electrically connected to the gate connection structure CG via the first via V1, thereby achieving the electrical connection between the gate connection structure CG and the data line DL via the first via V1, that is, realizing the electrical connection between the gate electrode T01g of the first electrostatic discharge transistor T01 and the data line DL.The second end of the data connection pattern DL1, which is remote from the data line DL in the second direction D2, is electrically connected to the electrostatic discharge semiconductor layer through a second through-hole V2, thereby establishing the electrical connection between the first electrode T01s of the first electrostatic discharge transistor T01 and the data line DL, and the electrical connection between the first electrode T02s of the second electrostatic discharge transistor T02 and the data line DL. The second through-hole V2 is located between the first protrusion portion and the second protrusion portion in the first direction D1. For example, the data connection pattern DL1 is electrically connected to the recess of the above-mentioned first signal line O1 adjacent to the data connection pattern DL1, for example, the part of the first signal line O1 that is electrically connected to the electrostatic discharge semiconductor layer in . Fig. 7B is connected, a part of the recess.

[0132] With reference to Fig. 7A and Fig. 7E, for example, the sub-electrostatic discharge unit SEU further comprises a first interconnection structure 201 and a second interconnection structure 202. The first interconnection structure 201 and the second interconnection structure 202 are located in the second conductive layer 120. The first end of the first interconnection structure 201 in the first direction D1 is connected to the first conductor C1 via a third via V3, and the second end of the first interconnection structure 201 in the first direction D1 is connected to the first active layer T01a via a fourth via V4, thereby establishing the electrical connection between the second electrode T01d of the first electrostatic discharge transistor T01 and the first conductor C1.The first end of the second connection structure 202 in the first direction D1 is connected to the main body portion CM of the second conductor C2 via a fifth via V5, and the second end of the second connection structure 202 in the first direction D1 is connected to the second active layer T02a via a sixth via V6, thereby establishing the connection between the gate electrode T02g and the second electrode of the second electrostatic discharge transistor T02 and the second conductor C2.

[0133] Referring to Fig. 7D and Fig. 7F, for example, the display panel 10 further includes a first insulating layer GI1 between the semiconductor layer ACT and the first conductive layer 110, a second insulating layer GI2 between the first conductive layer 110 and the second conductive layer 120, and an interlayer insulating layer ILD;the first through-hole V1 penetrates through the second insulating layer GI2 and the interlayer insulating layer ILD, the second through-hole V2 penetrates through the first insulating layer GI1, the second insulating layer GI2 and the interlayer insulating layer ILD, the third through-hole V3 penetrates through the second insulating layer GI2 and the interlayer insulating layer ILD, the fourth through-hole V4 penetrates through the first insulating layer GI1, the second insulating layer GI2 and the interlayer insulating layer ILD, the fifth through-hole V5 penetrates through the second insulating layer GI2 and the interlayer insulating layer ILD, and the sixth through-hole V6 penetrates through the first insulating layer GI1, the second insulating layer GI2 and the interlayer insulating layer ILD.;

[0134] With reference to Fig. 7F, the display substrate 10 further includes a buffer layer Buffer on the base substrate 200, and the semiconductor layer ACT is located on the buffer layer Buffer. The buffer layer Buffer can prevent contamination and damage to the base substrate 200 during the manufacturing process and make other structures formed thereon cleaner and smoother.

[0135] For example, the base substrate 200 in the display substrate 10 provided by the embodiments of the present disclosure may be a rigid substrate such as a glass substrate, a silicon substrate, etc., or a flexible material having excellent heat resistance and durability such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose acetate (TAC), cyclic olefin polymer (COP), cyclic olefin copolymer (COC), and the like.

[0136] The material of the semiconductor layer ACT includes, for example, but is not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, polythiophene, etc.).

[0137] For example, the materials of the first conductive layer and the second conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), or alloy materials composed of the above-mentioned metals; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.

[0138] For example, the first insulating layer GI1, the second insulating layer GI2, and the interlayer insulating layer ILD are inorganic insulating layers whose materials include at least one of silicon oxide, silicon nitride, and silicon nitrogen oxide, such as silicon oxide, silicon nitride, or silicon nitrogen oxide, or include insulating materials containing metal nitrogen oxide, such as aluminum oxide, titanium nitride, or the like. However, the embodiments of the present disclosure are not limited in this aspect.

[0139] Fig. Figure 8 is a schematic diagram of several specially shaped display panels incorporating electrostatic discharge units provided by embodiments of the present disclosure. For example, as shown in (a) of Fig. As shown in Figure 8, the planar shape of the display panel provided by the embodiments of the present disclosure is Y-shaped, with a Y-shaped display region 1, and the electrostatic discharge region 20 located at the bottom of the Y-shaped display panel. The maximum width L1 of the Y-shaped display panel in the second direction D2 is larger than the width L2 of the non-display region that can be used to provide the electrostatic discharge region 20 at the bottom of the Y-shaped display panel in the second direction D2. For example: L1=156912 µm, L2=71640 µm, L2 / L1=0.46. The ratio of L2 to L1 is less than 0.5, which means that the size of the lower space available for setting the electrostatic discharge region in the second direction is much smaller than the size of the space traversed by the display region in the second direction.Therefore, for example, for various irregular display panels, especially for display panels with a ratio of L2 to L1 of less than 0.5, it is necessary to significantly reduce the total width of the plurality of electrostatic discharge units ESD in the second direction D2 because the width of the space available for adjusting the electrostatic discharge area in the second direction D2 is small to a certain extent.

[0140] Fig. 9A is a schematic diagram of a Y-shaped display panel provided by embodiments of the present disclosure; Fig. 9B is a planar schematic diagram of a portion of a Y-shaped display panel including an electrostatic discharge region and a feed region; Fig. 9C is a schematic diagram of a semiconductor layer of the Fig. 9B; Fig. 9D is a schematic diagram of a first conductive layer of the Fig. 9B; Fig. 9E is a schematic diagram of an interlayer insulating layer of the Fig. 9B; and Fig. 9F is a schematic diagram of a second conductive layer of the Fig. 9B shown part.

[0141] The Fig. The embodiment shown in Figure 9B takes over the Fig. 4A. The arrangement mode of the adjacent first electrostatic discharge unit group EUG1 and the second electrostatic discharge unit group EUG2 was shown. For example, in the Fig. In the embodiment shown in Figure 9B, M is 1, N is 2, and Q is 3.

[0142] With reference to Fig. 2 and Fig. For example, 9A is the width L ICof the area in which the driver circuit IC is located (ie the space occupied by the driver circuit IC) in the second direction D2 is smaller than the width L ESD of the electrostatic discharge area 20 in the second direction D2. Therefore, for example, with reference to Fig. 2 and Fig. 9B, the first end of the data selection unit MUXU near the electrostatic discharge area 20 is electrically connected to R data lines DL, and the second end of the data selection unit MUXU remote from the electrostatic discharge area 20 is electrically connected to S data supply lines, where S and R are both positive integers and S is smaller than R. The S data supply lines are electrically connected to the driver circuit, and the first display signal, namely the data signal Vd, is supplied to the S data supply lines via the driver circuit. In this way, the number of data supply lines can be reduced, thereby reducing the total width required for the plurality of data supply lines in the second direction D2 to adapt to the situation where the width L ICof the area in which the driver circuit IC is located in the second direction D2 is relatively small compared to the width L ESD of the electrostatic discharge area 20 in the second direction D2.

[0143] For example, with reference to Fig. 9B, R=2, S=1, that is, the first end of the data selection unit MUXU near the electrostatic discharge area 20 is electrically connected to two data lines DL, the two data lines being a first data line O1a and a second data line O1b, respectively, and the second end of the data selection unit MUXU remote from the electrostatic discharge area 20 is electrically connected to a data supply line O1c. Referring to Fig. 4B and Fig. 9B, for example, the first data line O1a is electrically connected to the first sub-electrostatic discharge unit S1a in the first electrostatic discharge unit EU1, and the second data line O1b is electrically connected to the first sub-electrostatic discharge unit S1b in the second electrostatic discharge unit EU2. For example, the three sub-electrostatic discharge units S1a / S2a / S3a of the first electrostatic discharge unit EU1 respectively supply data signals Vd to the three sub-pixels in the same pixel in the display area 1, such as supplying data signals Vd to the three sub-pixels of red, green, and blue.That is, the first end of the data selection unit MUXU near the electrostatic discharge area 20 is electrically connected to two data lines DL, and the two data lines DL are electrically connected to two subpixels of the same color of two adjacent pixels to supply the data signal Vd to the two subpixels of the same color; the second end of the data selection unit MUXU, remote from the electrostatic discharge area 20, is electrically connected to a data supply line O1c. Of course, R is not limited to being equal to 2, and S is not limited to being equal to 1; preferably, R is equal to 2 and S is equal to 1.In this way, while reducing the number of the plurality of data supply lines connected to the drive circuit IC, since the value of R is not particularly large, it will not cause too many data lines to share the same data selection circuit, and since the same data selection unit MUXU is connected to the data lines that provide data signals to the plurality of sub-pixels of the same color, it is relatively easy to control the selection of data signals, which hardly affects the display effect, and because the sub-pixels of the same color are adjacent and the value of R is not particularly large, the layout mode of these signal wires is simpler and the manufacturing difficulty is less.

[0144] With reference to Fig. 9B, Fig. 9D and Fig. 9F, the second data line 01b may be connected across layers, for example, the second data line 01b comprises a first part 01b1, a second part 01b2 and a third part 01b3. With reference to Fig. 9F, the first part O1b1 and the second part O1b2 are located in the second conductive layer 120, the third part O1b3 is located in the first conductive layer 110, and the first end of the third part O1b3 is electrically connected to the first part O1b1 via a through hole, the second end of the third part O1b3 is electrically connected to the second part O1b2 via a through hole. Since there is very little space for the arrangement of the electrostatic discharge units and the driving circuit IC in this irregular screen, in this way, the plurality of data lines DL connected to the plurality of data selection units MUXU can be arranged in the limited space.

[0145] The structure of a data selection unit MUXU is presented below. Fig. 10 is a schematic diagram of a data selection circuit of a display panel provided by embodiments of the present disclosure; Fig. 11 is a working time diagram of the Fig. 10 shown data selection circuit; and Fig. 12A is a structural area diagram of a data selection unit of a display panel provided by embodiments of the present disclosure.

[0146] With reference to Fig. 10 and Fig. 12A, the data selection unit MUXU includes a data selection circuit, the data selection circuit including a first data selection transistor T001 and a second data selection transistor T002. The gate electrode of the first data selection transistor T001 is electrically connected to a first data terminal to receive a first data drive signal MUXG1 from the first data terminal; the gate electrode of the second data selection transistor T002 is electrically connected to a second data terminal to receive a second data drive signal MUXG2 from the second data terminal.The first electrode of the first data selection transistor T001 is electrically connected to the first data line O1a to output a first output signal Output1 to the first data line O1a, and the first electrode of the second data selection transistor T002 is electrically connected to the second data line O1b to output a second output signal Output2 to the second data line O1b. The second electrode of the first data selection transistor T001 is electrically connected to the second electrode of the second data selection transistor T002 and is electrically connected to the data supply line O1c to receive the input data signal Input from the data supply line O1c.

[0147] Taking the case where the second electrode of the first data selection transistor T001 and the second data selection transistor T002 are both N-type transistors, the working process of the data selection circuit is presented. Referring to Fig. 10-11, in a first stage t1, the first data drive signal MUXG1 is at a high level and the second data drive signal MUXG2 is at a low level, so that the first data selection transistor T001 is turned on and the second data selection transistor T002 is turned off; in this case, the input data signal Input is the first data signal, and the first data signal Output1 is transmitted as the input data signal Input via the first data selection transistor T001 to the first data line O1a and then provided to the corresponding subpixel via the first data line O1a.In a second stage t2, the first drive signal MUXG1 has a low level and the second drive signal MUXG2 has a high level, so that the first data selection transistor T001 is turned off and the second data selection transistor T002 is turned on; in this case, the input data signal Input is a second data signal different from the first data signal, and the second data signal is transmitted as the second output signal Output2 via the second data selection transistor T002 to the second data line O1b and then provided to the corresponding subpixel via the second data line O1b.

[0148] Fig. 12B shows the active layer T001a of the first data selection transistor T001 and the active layer T002a of the second data selection transistor T002. For example, the active layer T001a and the active layer T002a each include a plurality of islands arranged in the first direction D1. Fig. 12C shows the gate electrode T001g of the first data selection transistor T001 and the gate electrode T002g of the second data selection transistor T002. Fig. 12D-12E, the first data line O1a is electrically connected to the active layer T001a of the first data selection transistor T001 via a first group of vias V01, the second data line O1b is electrically connected to the active layer T002a of the second data selection transistor T002 via the second group of vias V02, and the data supply line O1c is electrically connected to the active layer T001a and the active layer T002a via the third group of vias V03. For example, for each island, the part of the active layer T001a and the part of T002a encompassed by the respective island form a continuous and integral structure.The structure of the plurality of islands arranged in the first direction D1 contributes to increasing the width-to-length ratio of the gate electrode T001g of the first data selection transistor T001 and the second data selection transistor T002, thereby improving the performance of the transistor, and to reducing the width of the plurality of data selection units in the second direction D2, thereby meeting the requirements of the too limited width of the area for setting the plurality of data selections in the second direction D2.

[0149] With reference to Fig. 9B and Fig. 9F, the display panel 10 further comprises a reset voltage line RL and a reset voltage supply line RL0. For example, the reset voltage line RL and the reset voltage supply line RL0 are both located in the second conductive layer 120 and in the same layer as the data line DL. The reset voltage line RL is configured to provide a reset voltage signal to the subpixel 100 and includes supply sections RL1 / RL2 in the non-display area; the first supply section RL1 is located between two adjacent electrostatic discharge units EU1 and EU2 and extends in the first direction D1, and adjacent J supply sections are electrically connected by a reset connection line RLC extending in the second direction D2. For example, in the Fig. 9B, J=2, that is, the adjacent first supply section RL1 and the second supply section RL2 are electrically connected by the reset connection line RLC extending in the second direction D2. The first end of the reset voltage supply line RL0 is electrically connected to the reset connection line RLC, and the second end of the reset voltage supply line RL0 is electrically connected to the driver circuit IC, and the driver circuit IC is configured to provide the reset voltage signal. For example, the reset voltage signal includes the first reset voltage Vinit1 and the first reset voltage Vinit2 supplied to the pixel circuit. The first reset voltage Vinit1 and the first reset voltage Vinit2 may be the same, both provided by the driver circuit IC via the reset voltage line RL.

[0150] In another embodiment, for example, as in (d) of Fig. As shown in Figure 8, the planar shape of the display panel provided by the embodiments of the present disclosure is heart-shaped, with a heart-shaped display region 1, and the electrostatic discharge region 20 located at the bottom of the heart-shaped display panel. The maximum width L1 of the heart-shaped display panel in the second direction D2 is greater than the width L2, in the second direction D2, of the non-display region at the bottom of the heart-shaped display panel, which can be used to provide the electrostatic discharge region 20. For example: L1=231061 µm, L2=84651 µm, and L2 / L1=0.37.This means that the size of the lower space available for adjusting the electrostatic discharge area in the second direction is much smaller than the size of the space traversed by the display area in the second direction, and even the value of L2 / L1 is smaller than the value of L2 / L1 in the Y-shaped display panel. Therefore, for this heteromorphic display panel, for example, the width of the space available for adjusting the electrostatic discharge area in the second direction D2 is small to a certain extent, so it is necessary to significantly reduce the total width of the plurality of electrostatic discharge units ESD in the second direction D2.

[0151] Fig. 13A is a schematic diagram of a heart-shaped display panel provided by embodiments of the present disclosure; and Fig. Figure 13B is a partial planar schematic diagram of a portion of a heart-shaped display panel including an electrostatic discharge region and a feed region.

[0152] With reference to Fig. 2 and Fig. For example, 13A is the width L IC of the area in which the driver circuit IC is located (ie the space occupied by the driver circuit IC) in the second direction D2 is smaller than the width L ESD of the electrostatic discharge area 20 in the second direction D2. For example: L ESD =70560µm, L IC =47864µm. Therefore, the design of the data selection circuit and the reset voltage supply line can also affect the design of the Fig. 9B shown embodiment.

[0153] The Fig. The embodiment shown in Figure 13B takes the Fig. 4D shows the arrangement of the electrostatic discharge unit. Fig. 13B shows a group of electrostatic discharge units EUG comprising a first subgroup of electrostatic discharge units SEUG1 and a second subgroup of electrostatic discharge units SEUG2.

[0154] If the pitch of a pixel is defined as δ, the width of the edges is L=edges on both sides+resolution*δ. For example, the resolution of the heart-shaped display panel is 1440*1440. According to the arrangement of two groups of ESD units in the vertical direction, namely M=1, N=2, Q=3, six sub-electrostatic discharge units form an electrostatic discharge group EUG. The total width of an electrostatic discharge group EUG in the second direction is 129.5µm. Therefore, the space required for all the ESD units =[(3*1440) / 6]*129.5=93528µm, but the bottom space of the heart-shaped display panel is only 84651µm, obviously the space is not enough. Therefore, the arrangement mode of the electrostatic discharge units in the heart-shaped display panel must adopt the arrangement of three vertically staggered groups of electrostatic discharge units arranged in Fig. 13B, namely M=2, N=3, Q=3, and 18 electrostatic discharge units form an electrostatic discharge group EUG. The second-direction width D2 of one electrostatic discharge group EUG is 294µm, and the total second-direction width D2 of all electrostatic discharge units required for the heart-shaped display panel is [(3 * 1440) / 18] * 294 = 70560µm. Compared with the Y-shaped display panel, this design can further reduce the total width of all electrostatic discharge units in the second direction while meeting the requirements for a higher PPI. It can also meet the requirement that the smaller L2 / L1 value in the heart-shaped display panel requires a smaller total width of all electrostatic discharge units in the second direction.

[0155] The others in Fig. 13B, such as the structures of each electrostatic sub-discharge unit, data selection circuit, etc., can be found in the description of the Fig. 9B shown embodiment.

[0156] In another embodiment, for example, as in (c) of Fig. As shown in Figure 8, the planar shape of the display panel provided by the embodiments of the present disclosure is D-shaped, and the electrostatic discharge region 20 is located at the bottom of the D-shaped display panel. The maximum width L1 of the D-shaped display panel in the second direction D2 is larger than the width L2 of the non-display region at the bottom of the D-shaped display panel, which can be used to adjust the electrostatic discharge region 20 in the second direction D2. For example: L1=156912 µm, L2=97900 µm, and L2 / L1=0.62.

[0157] Fig. 14A is a schematic diagram of a D-shaped display panel provided by embodiments of the present disclosure; and Fig. Figure 14B is a planar schematic diagram of a portion of a D-shaped display panel including an electrostatic discharge region and a feed region.

[0158] For example, the Fig. 14B illustrated embodiment in Fig. 4A shows the arrangement of the electrostatic discharge unit. Fig. 14B shows a group of electrostatic discharge units EUG consisting of an adjacent first subgroup of electrostatic discharge units SEUG1 and a second subgroup of electrostatic discharge units SEUG2. For example, in the Fig. In the embodiment shown in Figure 14B, the resolution of the D-shaped display panel is 960 x 1920. According to the arrangement of two groups of ESD units offset in the vertical direction, namely M=1, N=2, and Q=3, six electrostatic discharge units form one electrostatic discharge group EUG, and the total width of one electrostatic discharge group EUG in the second direction is 129.5 µm. Therefore, the total width required for all electrostatic discharge units of the D-shaped display panel in the second direction is [(3 * 960) / 6] * 129.5 = 62160 µm. It can be seen that the arrangement of the two groups of ESD units offset in the vertical direction can meet the requirements of the D-shaped display panel, and the electrostatic discharge units of the Y-shaped display panel have the same footprint as the D-shaped display panel. Fig. The embodiment shown in Figure 14B is similar to the case of the Y-shaped display panel, and this construction can also reduce the total width of all electrostatic discharge units in the second direction, thereby meeting the requirement of the smaller value of L2 / L1 in the heart-shaped display panel for the smaller total width of all electrostatic discharge units in the second direction. Of course, the Fig. 4C or Fig. The arrangement of electrostatic discharge units shown in Figure 4D can also be used to further reduce the overall width of all electrostatic discharge units in the second direction. The other Fig. 14B, such as the structure of each electrostatic sub-discharge unit, the data selection circuit, etc., can be found in the description of the Fig. 9B shown embodiment.

[0159] In another embodiment, for example, as in (e) of Fig. As shown in Figure 8, the planar shape of the display panel provided by the embodiments of the present disclosure is O-shaped, and the electrostatic discharge region 20 is located at the bottom of the O-shaped display panel. The maximum width L1 of the O-shaped display panel in the second direction D2 is larger than the width L2 of the non-display region at the bottom of the O-shaped display panel, which can be used to adjust the electrostatic discharge region 20 in the second direction D2. For example: L1=307835 μm, L2=164400 μm, and L2 / L1=0.53.

[0160] Fig. 15A is a schematic diagram of an O-shaped display panel provided by embodiments of the present disclosure; and Fig. Figure 15B is a planar schematic diagram of a portion of an O-shaped display panel including an electrostatic discharge region and a feed region.

[0161] With reference to Fig. For example, in Figure 15A, the resolution of the O-shaped display panel is 1920*3840, which is relatively high. Therefore, the O-shaped display panel has two COFs, and the total width required for all electrostatic discharge units in the second direction D2 is twice that of setting one COF. It is also necessary to minimize the total width of each group of electrostatic discharge units and all electrostatic discharge units in the second direction D2 as much as possible.

[0162] The Fig. The embodiment shown in Figure 15B takes over the Fig. 4C shows the arrangement of the electrostatic discharge unit. Fig. Figure 15B shows a group of electrostatic discharge units EUG consisting of a first subgroup of electrostatic discharge units SEUG1 and a second subgroup of electrostatic discharge units SEUG2 that are adjacent to each other. For example, in the Fig. In the embodiment shown in Figure 15B, the total width required for all electrostatic discharge units of the O-shaped display panel in the second direction D2 is twice that of the D-shaped display panel, i.e., M=2, N=2, and Q=3, and 12 electrostatic discharge units form the electrostatic discharge group EUG. Therefore, the required total width for all electrostatic discharge units of the O-shaped display panel in the second direction D2 is 2 * [(3 * 960) / 6] * 129.5 = 124320µm. Similar to the Y-shaped display panel, this construction can also reduce the total width of all electrostatic discharge units in the second direction to meet the requirement that the smaller value of L2 / L1 in the heart-shaped display panel requires a smaller total width of all electrostatic discharge units in the second direction. Of course, the Fig. The arrangement of electrostatic discharge units shown in Figure 4D can also be used to further reduce the overall width of all electrostatic discharge units in the second direction. The other Fig. 15B, such as the structures of each electrostatic sub-discharge unit, data selection circuit, etc., can be found in the description of the Fig. 9B shown embodiment.

[0163] In another embodiment, for example, as in (b) of Fig. As shown in Figure 8, the planar shape of the display panel provided by the embodiments of the present disclosure is I-shaped, and the electrostatic discharge region 20 is located at the bottom edge of the I-shaped display panel.

[0164] Fig. 16A is a schematic diagram of an I-shaped display panel provided by embodiments of the present disclosure; and Fig. Figure 16B is a planar schematic diagram of a portion of an I-shaped display panel including an electrostatic discharge region and a feed region.

[0165] For example, the Fig. 16B illustrated embodiment in Fig. 4A shows the arrangement of the electrostatic discharge units. Fig. 16B shows a group of electrostatic discharge units EUG consisting of an adjacent first subgroup of electrostatic discharge units SEUG1 and a second subgroup of electrostatic discharge units SEUG2. For example, the maximum width L1 of the I-shaped display panel in the second direction D2 is equal to the width of the non-display area at the bottom of the I-shaped display panel, which can be used to set the electrostatic discharge area 20 in the second direction D2, i.e., L2 / L1=1. For example: L1=156912 µm and L2=156912 µm. It can be seen that the width of the area used to set the electrostatic discharge units at the bottom of the I-shaped panel in the second direction D2 is relatively sufficient compared to the width of the display area in the second direction D2. Therefore, for example, with reference to Fig. 16B, the orthographic projections of the adjacent first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2 on the plane parallel to the second direction D2 do not overlap with each other, and the orthographic projections of the adjacent first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2 on the plane parallel to the first direction D1 are overlapped with each other, such as substantially completely overlapped with each other, in order to maintain an orderly arrangement and reduce manufacturing difficulties.

[0166] For example, the resolution of the I-shaped display panel is 960 * 1920. When arranging Fig. 16B, the total width of the three electrostatic sub-discharge units at the beginning and end in the second direction is 260µm. For the middle electrostatic sub-discharge units, six electrostatic sub-discharge units form a group of electrostatic discharge units; the total width of a group of electrostatic discharge units in the second direction is 280µm. The total width of all electrostatic discharge units in the second direction is [(3 * 960-6) / 6] * 280 + 260 = 134380µm. The width of the lower area of the I-shaped display panel in the second direction is 156912µm, and there is sufficient space for the electrostatic discharge units.

[0167] Of course, in the I-shaped display panel, the orthographic projections of two adjacent electrostatic discharge units on the plane parallel to the second direction D2 may also overlap at least partially. For example, the Fig. 4C or Fig. The arrangement of electrostatic discharge units shown in Figure 4D can be used to reduce the overall width of all electrostatic discharge units in the second direction and to adapt to smaller I-shaped panels.

[0168] With reference to Fig. 2 and Fig. For example, 16A is the width L IC of the area in which the driver circuit IC is located (ie the space occupied by the driver circuit IC), in the second direction D2 smaller than the width L ESD of the electrostatic discharge area 20 in the second direction D2. For example: L ESD =134383µm and L IC =47864µm. Therefore, the design of the data selection circuit and the reset voltage supply line can also refer to the design of the Fig. 9B shown embodiment.

[0169] The others in Fig. 16B, such as the structures of each electrostatic sub-discharge unit, data selection circuit, etc., can be found in the description of the Fig. 9B shown embodiment.

[0170] At least one embodiment of the present disclosure provides a display device comprising any display substrate provided by the embodiments of the present disclosure. The display device may be an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other types of devices with display functions. The embodiments of the present disclosure are not limited in this aspect.

[0171] The structures, functions, and technical effects of the display device provided by the embodiments of the present disclosure can be found in the corresponding descriptions of the display substrate 10 provided by the embodiments of the present disclosure and will not be repeated here.

[0172] For example, the display device provided by at least one embodiment of the present disclosure may be any product or component having display functions, such as a display panel, a mobile phone, a tablet, a television, a monitor, a laptop, a digital photo frame, a navigation device, etc. The embodiments of the present disclosure are not limited in this respect.

[0173] What has been described above are only specific implementations of the present disclosure, the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be based on the scope of the claims.

Claims

[1] Scoreboard, comprising: a display area comprising subpixels; a non-display area surrounding at least a portion of the display area and including an electrostatic discharge area; a first signal line extending from the display region to the electrostatic discharge region in a first direction as a whole and configured to provide a first display signal to the subpixels; and a plurality of electrostatic discharge units arranged in the first direction, each of the plurality of electrostatic discharge units comprising at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprising an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit being electrically connected to the first signal line and the first conductor, and being configured to allow charges on the first signal line to move toward the first conductor; the plurality of electrostatic discharge units comprise two adjacent electrostatic discharge units in a second direction, the second direction is perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other, and orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the second direction at least partially overlap with each other, or the orthographic projections of the two adjacent electrostatic discharge units on the plane parallel to the first direction do not overlap and a distance between the two adjacent electrostatic discharge units in the second direction is less than 1µm. [2] The display panel according to claim 1, wherein, in the plurality of sub-electrostatic discharge units of the plurality of electrostatic discharge units, orthographic projections of at least two sub-electrostatic discharge units on the plane parallel to the first direction do not overlap with each other, and the orthographic projections of the at least two sub-electrostatic discharge units on the plane parallel to the second direction at least partially overlap with each other. [3] The display panel according to claim 1, wherein a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction. [4] The display panel according to claim 1, wherein the display panel comprises a plurality of first signal lines, and the plurality of sub-static discharge units of the plurality of electrostatic discharge units are each electrically connected to the one first signal line of the plurality of first signal lines; at least one of the plurality of first signal lines includes a recess in the electrostatic discharge region, the recess forming a groove depressed toward one side in the second direction, and at least a part of a sub-electrostatic discharge unit adjacent to the groove is located in the groove. [5] The display panel according to claim 4, wherein at least one electrostatic discharge unit of the plurality of electrostatic discharge units comprises two adjacent sub-electrostatic discharge units in the second direction, and two adjacent first signal lines both comprise a recess in the electrostatic discharge region, recesses of the two adjacent first signal lines form grooves recessed toward a same side in the second direction, and the two adjacent sub-electrostatic discharge units are each at least partially located in the grooves formed by the recesses of the two adjacent first signal lines. [6] A display panel according to claim 5, wherein the first signal line connected to the at least one sub-electrostatic discharge unit comprises: a first recess forming a first groove recessed toward a first side in the second direction; a second recess forming a second groove which is recessed in the second direction toward a second side opposite the first side, and which is arranged in the second direction with the first recess, wherein the two adjacent electrostatic discharge units are each a first electrostatic discharge unit and a second electrostatic discharge unit, an orthographic projection of the first electrostatic discharge unit parallel to the first direction lies within an orthographic projection of the first groove parallel to the first direction, and an orthographic projection of the second electrostatic discharge unit parallel to the first direction lies within an orthographic projection of the second groove parallel to the first direction. [7] The display panel according to claim 1, wherein the plurality of electrostatic discharge units form a plurality of electrostatic discharge unit groups spaced apart from each other in the second direction, each of the plurality of electrostatic discharge unit groups comprises M sub-groups of electrostatic discharge units, each of the M sub-groups of electrostatic discharge units comprises N electrostatic discharge units, and each of the N electrostatic discharge units comprises Q sub-electrostatic discharge units, M and Q are positive integers greater than or equal to 1, and N is a positive integer greater than or equal to 2;at least a part of the groups of electrostatic discharge units of the plurality of groups of electrostatic discharge units are arranged in a periodic arrangement in the second direction, and the one group of electrostatic discharge units is a repeating unit in the periodic arrangement; [8] A display panel according to claim 7, wherein a number of sub-electrostatic discharge units included in said one electrostatic discharge unit group is M * N * Q; in the case where M is 1, N is 2, and Q is 3, a width of the one group of electrostatic discharge units in the second direction is less than or equal to 129.5µm; or, in the case where M is 2, N is 3, and Q is 3, a width of the one group of electrostatic discharge units in the second direction is less than or equal to 294µm. [9] The display panel according to claim 8, wherein a resolution of the display panel is X * Y, X represents a number of rows of a pixel array in the display area, Y represents a number of columns of the pixel array in the display area, X is greater than or equal to 960, and Y is greater than or equal to 1440. [10] A display panel according to claim 7, wherein the M subgroups of electrostatic discharge units comprise a first subgroup of electrostatic discharge units and a second subgroup of electrostatic discharge units, the first subgroup of electrostatic discharge units and the second subgroup of electrostatic discharge units being symmetrical or asymmetrical with respect to an axis of symmetry extending in the first direction. [11] A display panel according to any one of claims 1-10, wherein the first display signal is a data signal, and the first signal line transmits the data signal; each of the subpixels comprises a pixel circuit, and the pixel circuit comprises: a light-emitting device, a driver transistor, and a data write transistor, wherein the data write transistor is configured to transmit the data signal to the driver transistor under control of a first sensing signal; the driving transistor is configured to control an amplitude of a driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. [12] The display panel according to any one of claims 1 to 11, wherein the non-display region includes a supply region, a driving circuit is provided in the supply region, and the driving circuit is configured to supply the first display signal to the first signal line; the electrostatic discharge region is located between the supply region and the display region, and the plurality of sub-electrostatic discharge units connected to the first signal lines that supply the first display signal to all sub-pixels are located in the non-display region on the same side of the display region in the first direction. [13] The display panel according to claim 12, wherein the non-display region further comprises an edge region, the edge region is located between the supply region and the display region, a first power supply line is provided in the edge region, and the first power supply line is configured to supply a first power supply voltage to the sub-pixels; the supply region comprises a data selection region on a side of the edge region remote from the display region, a data selection unit is provided in the data selection region, and the electrostatic discharge region is located between the first power supply line and the data selection region. [14] A display panel according to claim 12 or 13, wherein a first end of the data selection unit close to the electrostatic discharge region is electrically connected to R first signal lines, and a second end of the data selection unit remote from the electrostatic discharge region is electrically connected to S data supply lines, S and R are both positive integers, and S is smaller than R; the S data supply lines are electrically connected to the drive circuit, and the first display signal is provided by the drive circuit to the S data supply lines. [15] The display panel according to any one of claims 12-14, wherein a width of a region in which the driving circuit is located in the second direction is smaller than a width of the electrostatic discharge region in the second direction. [16] A display panel according to any one of claims 1-15, wherein the electrostatic discharge circuit comprises: a first subcircuit having a driver end, a first end, and a second end, wherein the driver end and the first end of the first subcircuit are electrically connected to the first signal line, and the second end of the first subcircuit is electrically connected to the first conductor. [17] The display panel according to claim 16, wherein the sub-electrostatic discharge unit further comprises a second conductor, the electrostatic discharge circuit is electrically connected to the first signal line and the second conductor, and is configured to allow charges on the first signal line to move toward the second conductor; the electrostatic discharge circuit further comprises: a second subcircuit having a driver end, a first end, and a second end, wherein the first end of the second subcircuit is electrically connected to the first signal line, and the driver end and the second end of the second subcircuit are both connected to the second conductor; the first subcircuit and the second subcircuit are arranged in the first direction. [18] The display panel according to claim 17, wherein the first subcircuit comprises a first transistor, and the second subcircuit comprises a second transistor; a gate electrode and a first electrode of the first transistor are electrically connected to the first signal line, and a second electrode of the first transistor is electrically connected to the first conductor; a first electrode of the second transistor is electrically connected to the first signal line, and a gate electrode and a second electrode of the second transistor are both connected to the second conductor; the first transistor and the second transistor are arranged in the first direction, the first electrode and the second electrode of the first transistor are arranged in the first direction, and the first electrode and the second electrode of the second transistor are arranged in the first direction; the first transistor comprises a first active layer, and the second transistor comprises a second active layer; the first active layer and the second active layer both extend in the first direction, and a width of the first active layer in the second direction is smaller than a length of the first active layer in the first direction, and a width of the second active layer in the second direction is smaller than a length of the second active layer in the first direction. [19] The display panel according to claim 18, wherein the first conductor and the second conductor are spaced apart from each other in the first direction, and the first conductor extends in the second direction; the sub-electrostatic discharge unit comprises a first gate portion; the second conductor comprises a main body portion extending in the second direction and a second gate portion connected to the main body portion and extending in the second direction, the first gate portion and the second gate portion are arranged at intervals in the first direction, and the first gate portion and the second gate portion are located between the first conductor and the main body portion of the second conductor;a portion of the first gate portion that overlaps with the first active layer forms the gate electrode of the first transistor, a portion of the second gate electrode that overlaps with the second active layer forms the gate electrode of the second transistor, and the first gate portion is electrically connected to the first signal line; [20] The display panel according to claim 19, wherein the first gate portion comprises a first stripe portion extending in the first direction and a gate connection structure electrically connected to the first stripe portion, the gate connection structure projects from the first stripe portion in the second direction toward the first signal line, and the gate connection structure is electrically connected to the first signal line through a first through-hole; the first gate portion further comprises a first protrusion portion electrically connected to the first stripe portion, the first protrusion portion protrudes from the first stripe portion in the second direction away from the first signal line, and a portion of the first protrusion portion overlapping with the first active layer forms the gate electrode of the first transistor; the second gate portion includes a second stripe portion extending in the first direction and a second protrusion portion electrically connected to the second stripe portion, the second protrusion portion protrudes from the second stripe portion in the second direction, and a portion of the second protrusion portion overlapping with the second active layer forms the gate electrode of the second transistor. [21] The display panel according to claim 20, wherein the second protruding portion protrudes from the second stripe portion in a direction away from the first signal line in the second direction, the first stripe portion is substantially aligned with the second stripe portion in the first direction, and the first protruding portion is substantially aligned with the second protruding portion in the first direction. [22] A display panel according to claim 20, wherein the first active layer and the second active layer form an electrostatic discharge semiconductor layer which is continuous and integral, and the electrostatic discharge semiconductor layer is in a stripe shape as a whole extending in the first direction;the sub-electrostatic discharge unit further comprises a data connection structure, the data connection structure being electrically connected to the first signal line and projecting from the first signal line toward the electrostatic discharge semiconductor layer in the second direction, a first end of the data connection structure proximate to the first signal line in the second direction being electrically connected to the gate connection structure, and a second end of the data connection structure remote from the first signal line in the second direction being electrically connected to the electrostatic discharge semiconductor layer through a second through-hole, the second through-hole being located between the first projecting portion and the second projecting portion in the first direction; [23] The display panel according to claim 22, wherein the sub-electrostatic discharge unit further comprises a first connection structure and a second connection structure; a first end of the first connection structure is connected in the first direction to the first conductor through a third through-hole, and a second end of the first connection structure is connected in the first direction to the first active layer through a fourth through-hole; a first end of the second connection structure in the first direction is connected to the main body portion of the second conductor through a fifth through-hole, and a second end of the second connection structure in the first direction is connected to the second active layer through a sixth through-hole. [24] The display panel according to claim 22, wherein the electrostatic discharge semiconductor layer has a straight stripe shape and is located on a side of the first stripe portion and the second stripe portion remote from the first signal line. [25] A display panel according to any one of claims 1 to 24, further comprising: a reset voltage line configured to provide a reset voltage signal to the subpixels and comprising a supply section in the non-display area, wherein the supply section of the reset voltage line is located between two adjacent electrostatic discharge units and extends in the first direction, and J adjacent supply sections are electrically connected by a reset connection line extending in the second direction; and a reset voltage supply line, wherein a first end of the reset voltage supply line is electrically connected to the reset connection line, a second end of the reset voltage supply line is electrically connected to the driver circuit, and the driver circuit is configured to provide the reset voltage signal. [26] The display panel according to claim 25, wherein a width of a region in the second direction in which the driving circuit is located is smaller than a width of the electrostatic discharge region in the second direction. [27] Scoreboard, comprising: a display area comprising subpixels; a non-display area surrounding at least a portion of the display area and including an electrostatic discharge area; a first signal line extending from the display region to the electrostatic discharge region in a first direction as a whole and configured to provide a first display signal to the subpixels; and a plurality of electrostatic discharge units arranged in the first direction, each of the plurality of electrostatic discharge units comprising at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprising an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit being electrically connected to the first signal line and the first conductor, and being configured to allow charges on the first signal line to move toward the first conductor; in the plurality of electrostatic discharge units, orthographic projections of each two adjacent electrostatic discharge units on a plane parallel to the first direction do not overlap with each other. [28] Scoreboard, comprising: a display area comprising subpixels; a non-display area surrounding at least a portion of the display area and including an electrostatic discharge area; a first signal line extending from the display region to the electrostatic discharge region in a first direction as a whole and configured to provide a first display signal to the subpixels; and a plurality of electrostatic discharge units arranged in the first direction, each of the plurality of electrostatic discharge units comprising at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprising an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit being electrically connected to the first signal line and the first conductor and being configured to allow charges on the first signal line to move toward the first conductor; the non-display region comprises a supply region, a driver circuit is provided in the supply region, and the driver circuit is configured to provide the first display signal to the first signal line; the electrostatic discharge region is located between the supply region and the display region, and all of the plurality of sub-electrostatic discharge units connected to the first signal lines that supply the first display signal to all sub-pixels are located on a same side of the display region in the first direction. [29] Scoreboard, comprising: a display area comprising subpixels; a non-display area surrounding at least a portion of the display area and including an electrostatic discharge area; a first signal line extending from the display region to the electrostatic discharge region in a first direction as a whole and configured to provide a first display signal to the subpixels; and a plurality of electrostatic discharge units arranged in the first direction, each of the plurality of electrostatic discharge units comprising at least one sub-electrostatic discharge unit, each of the at least one sub-electrostatic discharge unit comprising an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit being electrically connected to the first signal line and the first conductor, and being configured to allow charges on the first signal line to move toward the first conductor; a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction, and the second direction is perpendicular to the first direction. [30] A display device comprising the display panel according to any one of claims 1-29.

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