STORAGE SYSTEM AND METHOD FOR OPTIMIZING PROCESSES FOR HOST-ACTIVATED DEFRAGMENTATION AND PROACTIVE STORAGE CLEANUP

Abstract

A storage system is provided that, based on a command from a host, performs a defragmentation operation or proactive cleanup of its memory. The command specifies which blocks in memory should be included in the defragmentation process by defining a maximum amount of valid data a block can contain to qualify for defragmentation. In this way, the storage system defragments only those blocks that meet the validity criteria provided by the host. This can help improve the performance of the storage system while reducing the level of negative trade-offs that can accompany defragmentation or proactive cleanup.

Description

REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit of U.S. Non-Provisional Patent Application No. 17 / 874,555, entitled “Storage System and Method for Optimizing Host-Activated Defragmentation and Proactive Garbage Collection Processes,” filed July 27, 2022, and hereby incorporates by reference the entire contents of which it is incorporated herein for all purposes. BACKGROUND

[0002] A challenge for the mobile phone and consumer industries, which many original equipment manufacturers (OEMs) and data storage device vendors are trying to address, is maintaining consistently high data storage device performance as the host (e.g., phone or laptop) is used and ages (e.g., after more than a year of use). One of the main reasons for the degradation of data storage device performance observed over time is physical fragmentation of memory, which can be the result of continuous use of the memory, with many files being written and some of them being deleted. This use leads over time to a state where memory blocks are occupied by only partially valid data, and no free blocks remain in memory.In this situation, significant performance degradation can occur with each host write command if memory block relocation occurs in the foreground during the host write operation. This problem can be addressed through host-activated defragmentation and proactive garbage collection processes, where the storage device can perform defragmentation during idle times to relocate valid data and ensure that there are enough free blocks in memory to accommodate incoming host writes. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram of a non-volatile storage system of one embodiment. Fig. 1B is a block diagram illustrating a storage module of one embodiment. Fig. Figure 1C is a block diagram illustrating a hierarchical storage system of one embodiment. Fig. Figure 2A is a block diagram showing components of the controller of the Fig. 1A, according to one embodiment. Fig. Figure 2B is a block diagram showing components of the Fig. 1A, according to one embodiment. Fig. 3 is a block diagram of a host and storage system of one embodiment. Fig. 4 is a diagram of various fragmentation levels of one embodiment. Fig. 5 is a diagram of various fragmentation levels of one embodiment. Fig. 6 is a flowchart of a method of one embodiment for optimizing host-activated defragmentation and proactive garbage collection processes. DETAILED DESCRIPTION

[0003] The following embodiments generally relate to a storage system and method for optimizing host-activated defragmentation and proactive garbage collection processes. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a command from a host to perform proactive defragmentation of the memory, the command specifying a maximum block valid count threshold; and to perform the defragmentation only for those blocks in the memory whose amount of valid data does not exceed the maximum block valid count threshold.In another embodiment, a method is provided, comprising: receiving, from a host, a command to perform proactive defragmentation of the memory, the command specifying a valid score criterion; and performing the defragmentation only on the blocks in the memory that meet the valid score criterion. In yet another embodiment, a storage system is provided, comprising: a memory; means for receiving, from a host, a command to perform proactive defragmentation of the memory, the command specifying a maximum block valid score threshold; and means for performing the defragmentation only on the blocks in the memory whose amount of valid data does not exceed the maximum block valid score threshold. Other embodiments are provided, which may be used alone or in combination.

[0004] Now referring to the drawings, in Fig. 1A to 1C show storage systems suitable for implementing aspects of these embodiments. Fig. 1A is a block diagram illustrating a non-volatile storage system 100 (sometimes referred to herein as a storage device, data storage device, or merely a device) according to one embodiment of the subject matter described herein. Referring to Fig. 1A, the non-volatile storage system 100 (sometimes referred to herein as a data storage device) includes a controller 102 and a non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to the collection of non-volatile memory cells and associated circuitry for managing the physical operation of these non-volatile memory cells formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory die 104.

[0005] The controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (Re-RAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM)) may, for example, take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. The controller 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts.Furthermore, some of the components shown as being within the controller may also be stored outside the controller, and other components may be used. Additionally, the phrase "operatively in communication with" could mean directly in communication with or indirectly (wired or wirelessly) in communication with through one or more components that may or may not be shown or described herein.

[0006] As used herein, a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory controller may have various functionalities in addition to the specific functionality described herein. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory operates properly, map defective non-volatile memory cells, and allocate spare cells to replace future faulty cells. A portion of the spare cells may be used to contain firmware to operate the non-volatile memory controller and implement other features.During operation, when a host needs to read or write data to non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to which data should be read / written, the non-volatile memory controller can convert the logical address received from the host into a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.)) The non-volatile memory controller may also perform various memory management functions, such as, but not limited to, wear leveling (spreading out writes to avoid wearing out certain blocks of memory cells that would otherwise be repeatedly written to) and garbage collection (after a block is full, only the valid data pages are moved to a new block so that the full block can be erased and reused). In addition, the structure for the "means" recited in the claims may, for example, include some or all of the controller structures described herein, programmed or fabricated as appropriate to cause the controller to operate to perform the recited functions.

[0007] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state memory cells (e.g., flash memory cells) and may be single-level, multi-level, or multi-level programmable. The memory cells may also be single-level cells (one bit per cell) (SLC) or multiple-level cells (MLC), such as two-level cells, triple-level cells (TLC), quad-level cells (QLC), or use other memory cell-level technologies now known or later developed. Furthermore, the memory cells may be fabricated in a two-dimensional or three-dimensional manner.

[0008] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as a toggle mode 200, 400, or 800. In one embodiment, the storage system 100 may be a card-based system, such as a Secure Digital (SD) card or a Micro Secure Digital (Micro SD) card (or USB, SSD, etc.). In an alternative embodiment, the storage system 100 may be part of an embedded storage system.

[0009] Although in the Fig. 1A, the non-volatile storage system 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104, the subject matter described herein is not limited to a single memory channel. For example, in some storage system architectures (such as those shown in Fig. 1B and Fig. 1C), depending on controller capabilities, 2, 4, 8, or more memory channels may be present between the controller and the memory device. In any of the embodiments described herein, more than a single channel may be present between the controller and the memory die, even if a single channel is shown in the drawings.

[0010] Fig. 1B illustrates a storage module 200 including multiple non-volatile storage systems 100. Therefore, the storage module 200 may include a storage controller 202 connected to a host and to a storage system 204 including a plurality of non-volatile storage systems 100. The interface between the storage controller 202 and the non-volatile storage systems 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interface Express (PCIe) interface, or a Double Data Rate (DDR) interface. The storage module 200, in one embodiment, may be a solid state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as found in a server PC or in portable computing devices such as laptop computers and tablet computers.

[0011] Fig. Figure 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding storage system 204. Host systems 252 can access storage within the storage system via a bus interface. In one embodiment, the bus interface can be a Non-Volatile Memory Express (NVMe) interface or a Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the Fig. The system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as might be found in a data center or other location where mass storage is required.

[0012] Fig. Figure 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front-end module 108 connected to a host, a back-end module 110 connected to the one or more non-volatile memory dies 104, and various other modules that perform functions that will now be described in detail. A module may take the form, for example, of a packaged functional hardware unit designed for use with other components, a section of program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that typically performs a particular function of related functions, or a standalone hardware or software component connected to a larger system.The controller 102 may sometimes be referred to herein as a NAND controller or a flash controller, but it should be understood that the controller 102 may be used with any suitable memory technology, examples of some of which are provided below.

[0013] Referring again to modules of controller 102, a buffer manager / bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102. A read-only memory (ROM) 118 stores system boot code. Although in Fig. 2A as being located separately from the controller 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located both within the controller 102 and external to the controller.

[0014] The front-end module 108 includes a host interface 120 and a physical layer (PHY) interface 122, which provide the electrical interface with the host or the next-level storage controller. The choice of host interface 120 type may depend on the type of storage used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serially Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 typically supports the transfer of data, control signals, and clock signals.

[0015] The backend module 110 includes an error correction code (ECC) engine 124, which encodes the data bytes received from the host and decodes and corrects errors in the data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, for transmission to the non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of corrupted data. RAID parity can be used as an additional level of integrity protection for the data written to the storage device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides the command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104.In one embodiment, the memory interface 130 may be a Double Data Rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of the backend module 110.

[0016] The storage system 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may be connected to the controller 102. In alternative embodiments, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer manager / bus controller 114 are optional components that are not required in the controller 102.

[0017] Fig. 2B is a block diagram illustrating components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional device. The non-volatile memory die 104 further includes a data cache 156 that temporarily stores data. The peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102.

[0018] Referring again to Fig. 2A, the flash control layer 132 (referred to herein as the flash translation layer (FTL) or more generally as the "media management layer" because the memory may not be flash memory) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internal operations of memory management and translates writes from the host into writes to memory 104. The FTL may be required because memory 104 may have limited durability, may only be written in multiples of pages, and / or may not be written to unless erased as a block of memory cells. The FTL is aware of these potential limitations of memory 104, which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from the host into writes to memory 104.

[0019] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or a data structure) and an allocated cache memory. In this way, the FTL translates logical block addresses ("LBAs") from the host into physical addresses in memory 104. The FTL may include other features, such as, but not limited to, power-off recovery (so that the FTL data structures can be restored in the event of a sudden power loss) and wear leveling (so that wear is even across memory blocks to prevent certain blocks from experiencing excessive wear, which would result in a greater likelihood of failure).

[0020] Referring again to the drawings, Fig. 3 is a block diagram of a host 300 and a storage system (sometimes referred to herein as a device) 100 of one embodiment. The host 300 may take any suitable form, including, but not limited to, a computer, a mobile phone, a digital camera, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 includes a processor 330 configured to send data (e.g., initially stored in the host's memory 340 (e.g., DRAM)) to the storage system 100 for storage in the memory 104 of the storage system (e.g., non-volatile memory die). While the host 300 and the storage system 100 in Fig. 3 as separate boxes, it should be noted that the storage system 100 may be integrated with the host 300, the storage system 100 may be removably connected to the host 300, and the storage system 100 and the host 300 may communicate over a network. It should also be noted that the memory 104 may be integrated with the storage system 100 or removably connected to the storage system 100.

[0021] As mentioned above, a challenge for the mobile phone and consumer industries that many original equipment manufacturers (OEMs) and data storage device vendors are trying to address is maintaining consistently high data storage device performance as the host (e.g., phone or laptop) is used and ages (e.g., after more than a year of use). One of the main reasons for the observed degradation in data storage device performance over time is physical fragmentation of memory, which can be the result of continuous use of the memory, with many files being written and some of them being deleted. This use leads, over time, to a state where memory blocks are occupied by only partially valid data and no free blocks remain in memory.In this situation, significant performance degradation can occur with each host write command if memory block relocation occurs in the foreground during the host write operation. Host-activated defragmentation and proactive garbage collection processes can be used to address this issue. These processes allow the storage device to perform defragmentation to proactively relocate valid data during idle times and ensure that there are enough free blocks in memory to accommodate incoming host writes.

[0022] However, proactive relocation can be detrimental to the write amplification factor (WAF) and storage lifetime if triggered excessively frequently. For example, one approach initiates memory defragmentation at every block / storage / media state to optimize storage for maximum performance benefit until the storage reaches (or approaches) its "end of life" threshold, after which the defragmentation feature is permanently disabled. However, this approach can wear out memory very quickly and permanently deprive the host of any optimization options, without giving the host the option to gradually refine the behavior and control the scenarios where performance optimization is actually needed / required.As another example, the defragmentation feature can be configured to trigger a move only at very specific block states with a minimum threshold to maximize and protect storage lifetime. However, in this case, the performance benefit of this feature may not be noticeable or significant enough.

[0023] The following embodiments provide a command and method that enable the host to dynamically control the block states / threshold involved in memory defragmentation, thus optimizing performance, WAF, and lifetime goals. The term "defragmentation" is used herein to refer to any proactive relocation process that involves moving valid data from one physical location to another physical location in memory. Therefore, the term "defragmentation" can be used to refer generally to reducing the logical randomness of data in physical memory space, or more specifically, to scatter-gather copying of valid data to consolidate free memory space ("garbage collection"). That is, "defragmentation" can refer to processes for defragmentation and / or proactive garbage collection.In one embodiment, the block health threshold is defined and controlled by a block valid number (block VC), where VC = % valid data within a physical data block. (While the valid number is commonly used in garbage collection and may or may not generally indicate logical fragmentation, the valid number, as used herein, is relevant to defragmentation.) As described in . Fig. As shown in Figure 4, the "zero / no free blocks" state can be the result of different block VC states. One example is where VC = 10%. From the user's perspective, the free space is 90%, but there are no free blocks internally in physical memory. Another example is where VC = 90%. From the user's perspective, the free space is 10%, but there are also no free blocks in physical memory.

[0024] In the example with VC = 90%, the amount of data that would need to be moved to free a new memory block would be nine times greater than with VC <= 10%. Therefore, initiating the memory defragmentation process with VC <= 10% can significantly reduce the lifetime of the memory and the WAF. However, if the defragmentation process is limited only to blocks with VC <= 10%, there may be many scenarios and media states that are not covered by this process. For example, with a threshold of VC <= 90%, almost all possible scenarios and media states can be covered, optimizing the data storage device to provide the best performance experience. However, in this situation, the memory can become worn out. Therefore, the higher the VC, the more data is moved during defragmentation, resulting in a higher WAF.Also, the higher the VC, the more scenarios / media states are optimized, which can lead to better performance and a guaranteed user experience.

[0025] In one embodiment, the block valid number (VC) state for defragmentation can be set and dynamically configured (indicating which blocks are involved in the defragmentation process). The thresholds / levels can be set by the host 300 via a dedicated command (hereinafter referred to as the "set VC threshold for host-activated defragmentation command") and can vary from 0 VC (meaning no defragmentation occurs regardless of the state) to a maximum size supported by the data storage device (e.g., up to a VC of 90%). The higher the VC% threshold, the greater the expected potential performance improvement, as more blocks are involved in the host-activated defragmentation and proactive garbage collection processes, with the drawback of a higher WAF and a reduction in memory lifetime.

[0026] In one embodiment, the controller 102 of the storage system 100 provides the host 300 with an attribute indicating support for the command to set a VC threshold for host-activated defragmentation, and optionally, an attribute reflecting the amount of maximum VC% threshold support that can be set by the host 300 via the command. Additional attributes may reflect the storage system's recommendation for a VC% threshold based, for example, on internal lifetime, utilization, and pattern statistics collected by the controller 102. Additional attributes may be provided regarding the number of blocks / payload expected to be moved in the defragmentation process per possible VC value, which may enable the host 300 to predict the potential impact of each of the possible VCs on the WAF.

[0027] Based on this attribute(s), the host 300 sends the dedicated command to set a VC threshold for host-activated defragmentation to the storage system 100 to set the maximum VC% value of blocks that can participate in the defragmentation function. The resolution of the set VC can be very precise (e.g., at the resolution of 1%), but can also be set with larger ranges / levels (e.g., supporting only three VC levels, such as <= 10%, <= 50%, <= 90%). Additional parameters in the command can specify an internal storage pool to which the VC threshold should be applied (assuming more than one storage pool is used).

[0028] In response to receiving the command, the controller 102 of the storage system 100 performs storage defragmentation during idle time only if enabled by the host 300, and selects the blocks for the proactive defragmentation process that meet the specified VC criteria. The dedicated command to set a VC threshold for host-activated defragmentation can be sent multiple times during the storage lifetime and dynamically change the VC threshold. As shown in Fig. 5, the VC threshold command and mechanism for host-activated defragmentation may be implemented by a host-activated defragmentation control module 500 in the host 300 and a host-activated defragmentation control module 510 in the controller 102 of the storage system 100. These modules 500, 510 may be used to implement the process illustrated in the flowchart 600 in Fig. 6. As shown in Fig. 6, a dedicated VC threshold command and method are provided for host-activated defragmentation, supported by both the host 300 and the controller 102 of the storage system 100 (action 610). The VC threshold is set by the host 300 (action 620). The controller 102 then selects only those blocks that meet the VC criteria during the proactive relocation process (action 630). Thereafter, the host 300 can dynamically update the VC threshold, for example, based on lifetime, integrity, counter, utilization, or performance statistics measured by the host 300 or the controller 102 of the storage system 100 (action 640).

[0029] In one embodiment, host 300 may apply simple pattern and system behavior learning techniques and update or modify the VC threshold for host-activated defragmentation accordingly. In one example, host 300 may set a very aggressive threshold at the beginning of the memory's lifetime and then gradually reduce this threshold as the memory's lifetime progresses. In another example, host 300 may set this threshold to a higher value based on a specific application usage that has a higher priority for performance optimization.

[0030] It should be noted that the mechanism described above for dynamically setting the VC threshold for selecting potential blocks for relocation may be applicable to features in addition to or instead of the host-activated defragmentation feature. For example, these embodiments may be used to dynamically set VC thresholds applied to the general garbage collection operations / flows performed by storage system 100 or to other features that utilize proactive relocation. These embodiments may also be used to define different VC thresholds for each of the internal storage pools in storage system 100.For example, lower VC thresholds may be applied to a single-level cell pool (SLC pool) managed internally within storage system 100, compared to a higher VC threshold that would be applied to a triple-level cell pool (TLC pool). Dynamic per-pool setup may be useful when storage system 100 internally manages several different pools and the lifetime of one pool is more limited than that of one or more others. To support this, the dedicated threshold setup command may include another parameter that may specify the pool number (e.g., "1" for the SLC pool and "2" for the TLC pool).

[0031] These embodiments provide numerous benefits. For example, these embodiments can help improve the performance versus WAF / lifetime tradeoffs for a host-activated defragmentation feature or other features that involve garbage collection / proactive relocation, and dynamically adjust them based on demand or use case.

[0032] Finally, as mentioned above, any suitable type of memory may be used. Semiconductor memory devices include volatile memory devices, such as Dynamic Random Access Memory ("DRAM" devices) or Static Random Access Memory ("SRAM" devices), non-volatile memory devices, such as ReRAM, Electrically Erasable Programmable Read Only Memory ("EEPROM"), Flash memory (which can also be considered a subset of EEPROM), Ferroelectric Random Access Memory ("FRAM"), and MRAM, and other semiconductor elements capable of storing information. Each type of memory device may comprise different devices. For example, Flash memory devices may be implemented in a NAND or NOR device.

[0033] The memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element, such as an anti-fuse, phase-change material, etc., and optionally a steering element, such as a diode, etc. Further, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements including a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric material for charge storage.

[0034] Multiple storage elements may be configured to be connected in series or such that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND device (NAND memory) typically include storage elements connected in series. A NAND memory array may be configured such that the array is composed of multiple memory chains, in which a chain is composed of multiple storage elements that share a single bit line and are accessed as a group. Alternatively, storage elements may be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured differently.

[0035] The semiconductor memory elements located in and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional (2D) memory structure or a three-dimensional (3D) memory structure.

[0036] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a 2D memory structure, memory elements are arranged in a plane (e.g., an xz-direction plane) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer over or within which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0037] The memory elements may be arranged in an ordered array at the individual memory device level, such as in a plurality of rows and / or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0038] A 3D memory array is arranged so that memory elements occupy multiple levels or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the y direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate).

[0039] As one non-limiting example, a 3D memory structure may be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements in each column. The columns may be arranged in a 2D device, e.g., in an xz-plane, resulting in a 3D array of memory elements with elements on multiple vertically stacked memory levels. Other devices of memory elements in three dimensions may also form a 3D memory array.

[0040] As a non-limiting example, the storage elements in a 3D NAND memory array may be coupled together to form a NAND chain within a single horizontal (e.g., xz) memory device level. Alternatively, the storage elements may be coupled together to form a vertical NAND chain spanning multiple horizontal memory device levels. Other 3D devices may be contemplated, with some NAND chains containing storage elements in a single memory level, while other chains containing storage elements spanning multiple memory levels. 3D memory arrays may also be configured as a NOR device and as a ReRAM device.

[0041] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory levels at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layers forming each memory device level of the array are typically formed on top of the layers of the array's underlying memory device levels. However, layers of adjacent memory device levels of a monolithic 3D memory array may be shared or have intermediate layers between memory device levels.

[0042] Then, in turn, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory levels. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels before stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic 3D memory arrays. Furthermore, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0043] Dedicated circuitry is typically required for the operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may include circuitry used to control and drive memory elements to perform functions such as programming and reading. This dedicated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory write / read operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0044] One skilled in the art will recognize that this invention is not limited to the described 2D and 3D structures, but covers all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one skilled in the art.

[0045] It is intended that the foregoing detailed description be construed as an illustration of selected forms the invention may take, rather than as a definition of the invention. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be understood that each aspect of each of the embodiments described herein may be used alone or in combination with one another. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 17 / 874,555

[0001] Cited non-patent literature

[0000] Storage System and Method for Optimizing Host-Activated Defragmentation and Proactive Garbage Collection Processes,” filed July 27, 2022

[0001]

Claims

[1] Storage system comprising: a memory and a controller coupled to the memory and configured to: Receiving, from a host, a command to perform host-activated defragmentation of the memory, the command specifying a maximum block valid number threshold; and Defragment only those blocks in memory whose amount of valid data does not exceed the maximum block valid count threshold. [2] The storage system of claim 1, wherein the controller is further configured to inform the host that the storage system supports the command. [3] The storage system of claim 1, wherein the controller is further configured to provide the host with an indication of a maximum block valid number threshold supported by the storage system. [4] The storage system of claim 1, wherein the controller is further configured to provide a recommendation for the maximum block valid number threshold to the host. [5] The storage system of claim 1, wherein the controller is further configured to provide the host with an indication of a number of storage blocks expected to be moved in each of a plurality of maximum block valid count thresholds. [6] The storage system of claim 1, wherein the defragmentation is performed during an idle time of the storage. [7] The storage system of claim 1, wherein the controller is further configured to receive a plurality of commands from the host, each command having a different maximum block valid number threshold. [8] The storage system of claim 1, wherein the command further specifies a storage pool in memory for which the defragmentation operation is to be performed. [9] The storage system of claim 1, wherein the maximum block valid count threshold is based on statistics of memory lifetime, memory integrity, a counter value, memory utilization, and / or performance. [10] The storage system of claim 1, wherein the memory comprises a three-dimensional memory. [11] A method in a storage system having a memory, comprising: Receiving, from a host, a command to perform host-activated defragmentation of the memory, the command specifying a validity count criterion; and Defragment only those blocks in memory that meet the valid count criteria. [12] The method of claim 11, further comprising informing the host that the storage system supports the command. [13] The method of claim 11, further comprising providing to the host an indication of a validity count criterion supported by the storage system. [14] The method of claim 11, further comprising providing a recommendation of the validity count criterion to the host. [15] The method of claim 11, further comprising providing the host with an indication of a number of memory blocks expected to be moved in each of a plurality of validity count criteria. [16] The method of claim 11, wherein the defragmentation is performed during an idle time of the memory. [17] The method of claim 11, further comprising receiving a plurality of commands from the host, each command having a different validity count criterion. [18] The method of claim 11, wherein the command further specifies a storage pool in memory for which the defragmentation operation is to be performed. [19] The method of claim 11, wherein the validity count criterion is based on statistics of memory lifetime, memory integrity, a counter value, memory utilization, and / or performance. [20] Storage system comprising: a memory; Means for receiving, from a host, a command to perform host-activated defragmentation of the memory, the command specifying a threshold of the maximum block valid number; and Means for performing defragmentation only on the blocks in memory, whose amount of valid data does not exceed the threshold of the maximum block validity number.

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