FEEDFORWARD EQUALIZER NOISE REDUCTION

Abstract

According to one aspect of an embodiment, a decision feedback equalizer (DFE) can be configured for noise reduction slicing. The DFE can be configured to receive an output signal with a received (Rx) symbol from a feedforward equalizer. The DFE can be configured to initialize the parameters of the noise reduction slicer (NSS parameters), including one or more initial NSS coefficients and one or more initial slicer-delayed decision (SDD) threshold offsets. The DFE can be configured to determine one or more updated NSS coefficients. The DFE can be configured to determine one or more updated SDD threshold offsets.The DFE can be configured to update the NSS parameters of a processing register based on one or more updated NSS coefficients and one or more updated SDD threshold offsets.

Description

RELATED APPLICATION

[0001] This application claims the benefits of US Provisional Application No. 63 / 362,887, filed on April 12, 2022, the disclosure of which is incorporated herein by reference in full. AREA OF TECHNOLOGY

[0002] The embodiments discussed in the present disclosure relate to noise reduction in feedforward equalizers and, in some embodiments, to noise reduction using a noise reduction slicer or a maximum likelihood sequence estimator (MLSE). BACKGROUND

[0003] Unless otherwise stated herein, the content described herein is not prior art within the meaning of the claims of the present application and is not recognized as prior art by its inclusion in this section.

[0004] An equalizer can compensate for or eliminate signal distortion and / or interference. In some cases, an equalizer can flatten the frequency response (e.g., the power spectral density) of a signal transmitted over a channel. After equalization, the frequency characteristics of a signal can be transmitted more reliably from the transmitting to the receiving end.

[0005] The subject matter claimed in the present disclosure is not limited to embodiments that eliminate any disadvantages or function only in environments such as those described above. Rather, this background is intended only to illustrate an exemplary technological field in which some embodiments described in the present disclosure may be practiced. SUMMARY

[0006] In some embodiments, a decision-feedback equalizer (DFE) can be implemented for noise reduction slicing. The DFE can be configured to receive an output signal with a received (Rx) symbol from a feedforward equalizer. The DFE can be configured to initialize parameters of the noise reduction slicer (NSS parameters), including one or more initial NSS coefficients and one or more threshold offsets for an initial slicer-delayed decision (SDD threshold offsets). The DFE can be configured to determine one or more updated NSS coefficients. The DFE can be configured to determine one or more updated SDD threshold offsets.The DFE can be configured to update the NSS parameters of a processing register based on one or more updated NSS coefficients and one or more updated SDD threshold offsets.

[0007] In some embodiments, a DFE can be configured for noise reduction. The DFE can include a feedforward equalizer configured to output a signal with an Rx symbol and a processing device. The processing device can be configured to receive the Rx symbol from the feedforward equalizer. The processing device can be configured to calculate an SDD range to identify a slicer-deferred decision (SDD). The processing device can be configured to apply the SDD to the Rx symbol if the Rx symbol value lies within the SDD range. The processing device can be configured to apply a hard slicer decision to the Rx symbol if the Rx symbol value lies outside the SDD range.

[0008] In some embodiments, a DFE can be configured for noise reduction. The DFE can include a feedforward equalizer configured to output a signal with an Rx symbol, and a processing device. The processing device can be configured to estimate a slicer error correlation based on a slicer error from a slicer input. The processing device can be configured to calculate one or more NSS coefficients based on the slicer error correlation. The processing device can be configured to apply noise reduction to the slicer input based on the one or more NSS coefficients. The processing device can be configured to estimate the Rx symbol after the noise reduction has been applied.

[0009] The objectives and advantages of the embodiments are realized and achieved at least through the elements, features and combinations particularly highlighted in the claims.

[0010] Both the preceding general description and the following detailed description are to be understood as examples and serve to illustrate, and not to limit, the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Exemplary embodiments are described and explained in more detail with reference to the accompanying drawings in which they are depicted: Fig. Figure 1 shows an example of a predictive decision-feedback equalizer (DFE). Fig. Figure 2 shows a flowchart for the noise reduction of a feedforward equalizer (FFE) using noise reduction slicer logic. Fig. Figure 3 shows a flowchart for decision-making in an exemplary equalization system. Fig. Figure 4 shows an example of a decision scheme for the FFE and the DFE. Fig. Figure 5 shows an example of an equalizer with an example noise reduction block. Fig. Figure 6 shows a block diagram of an example of a slicer with noise reduction. Fig. Figure 7 shows a block diagram of an example of a slicer with noise reduction. Fig. Figure 8 shows the process flow of a DFE device. Fig. Figure 9 shows the process flow of a DFE device. Fig. Figure 10 illustrates a process flow for a computer-readable medium used for a DFE device. Fig. Figure 11 shows an example of a communication system. Fig. Figure 12 shows a schematic representation of a computer in the exemplary form of a computer device in which a set of instructions can be executed to cause the computer to perform one or more of the procedures discussed here. Fig. Figure 13A shows exemplary results using FFE and noise expression. Fig. Figure 13B shows exemplary results using FFE and noise expression. Fig. Figure 14A shows exemplary results using FFE and noise expression. Fig. Figure 14B shows exemplary results using FFE and noise expression. Fig. Figure 15 shows exemplary results using FFE and noise expression. DESCRIPTION OF THE EXECUTION FORMS

[0012] Equalizers can be used in digital communications to reduce distortion and interference in a signal. Feedforward equalizers (FFEs) can be used to reduce distortion and / or interference in a channel of a communication signal. Equalizers can also be used to reduce intersymbol interference (ISI). A decision feedback equalizer (DFE) can use nonlinear equalization to correct precursor symbols, reducing noise and / or interference that can distort a currently received symbol. Various digital equalizers can be used to reduce intersymbol interference, including linear equalizers (e.g., MMSE equalizers and zero-forcing equalizers), blind equalizers (which estimate the transmitted signal without knowledge of the channel statistics), adaptive equalizers, and similar types.

[0013] In some scenarios, noise amplification in lossy channels by a feedforward equalizer (FFE) and / or a continuous-time linear equalizer (CTLE) can generate correlated noise. That is, the noise for a current symbol may be correlated with the noise of neighboring symbols. However, the correlated noise generated in neighboring symbols may not be reliably estimated.

[0014] Furthermore, the use of an FFE can lead to a deterioration of the bit error rate (BER). This means the bit error rate can increase and may not approach a theoretical lower limit. Additionally, the deterioration of the BER can be associated with increased power consumption.

[0015] A DFE can offer some degree of trailing noise mitigation, but at the cost of increased power consumption. If the feedforward equalizer (FFE) and feedback filter (FBF) of a DFE are implemented on separate lines, power consumption can increase. Furthermore, combining an FBF with an FFE may require additional components that can introduce further noise into the communication system. Therefore, reducing the BER degradation associated with an FFE by using a DFE can come at a cost.

[0016] In some embodiments, implementing noise suppression within the FFE line can improve performance and reduce resource consumption, such as energy. For example, power efficiency and performance can be improved compared to a conventional DFE with separate lines and no noise suppression. Furthermore, the systems and methods presented here can include a DFE that applies noise suppression to a small subset of Rx symbols based on one or more precursor and post-tap points, which can further improve performance and reduce energy consumption.

[0017] In some embodiments, a DFE can be configured for noise reduction. The DFE can be configured to receive an output signal with a received (Rx) symbol from a feedforward equalizer. The DFE can be configured to initialize the parameters of the noise reduction slicer (NSS), including one or more initial NSS coefficients and one or more threshold offsets for the initial slicer delayed decision (SDD). The DFE can be configured to determine one or more updated NSS coefficients. The DFE can be configured to determine one or more updated SDD threshold offsets. The DFE can be configured to update the NSS parameters of a processing register based on the one or more updated NSS coefficients and the one or more updated SDD threshold offsets.

[0018] The embodiments of the present disclosure are explained with reference to the accompanying drawings.

[0019] In some embodiments, such as in Fig. As shown in Figure 1, an example of a predictive decision-feedback equalizer (DFE) 100 can be provided. The DFE 100 may be a nonlinear channel equalizer to reduce intersymbol interference (ISI). The DFE 100 may contain two filters: (i) a feedforward filter (FFF) 102 and (ii) a feedback filter (FBF) 106. The DFE may contain one or more of the following elements: a decision device 104, one or more subtractors 112, 114, 116, or similar.

[0020] In some embodiments, the FFF 102 can receive an input signal with additive white Gaussian noise (AWGN) 122. In some examples, the FFF 102 can include a fractional equalizer (FSE). The FBF 106 can be used to remove some or all of the ISI from current symbols that may be caused by previous symbols.

[0021] In some embodiments, the feedforward filter 102 can be configured to output a signal 124 containing one or more desired symbols, ISI, and AWGN. The signal 124 can be routed to a subtractor 112, which can be configured to output a desired symbol and a prediction error signal 126 (i.e., including one or more desired symbols and a prediction error) to one or more of the decision devices 104 and the subtractor 136. Alternatively or additionally, the signal 124 can be routed to the subtractor 116, which can be configured to subtract a desired symbol signal 128 from the signal 124 (containing one or more of the desired symbol, ISI, and AWGN) and generate a signal 132, which is routed to the FBF 106. Alternatively or additionally, the signal 132 can also be routed to the FFF 102.

[0022] In some embodiments, the FBF 106 may include a linear predictor (e.g., using noise reduction slicing or minimum likelihood sequence estimation (MLSE)). In some DFEs 100, any suitable number of taps (e.g., infinite) may be used. In some DFEs 100, the FFF 102 may have an infinite number of taps.

[0023] In some embodiments, the FBF 106 can be configured to direct an output prediction signal 134 to the subtractor 112. The output prediction signal 134 can be subtracted from the signal 124 (i.e., using one or more of the desired symbol, ISI, and AWGN elements) to output the desired symbol and the prediction error signal 126 to the decision device 104 and the subtractor 114.

[0024] In some embodiments, the subtractor 114 can be configured to subtract the desired symbol and the prediction error signal 126 from the desired symbol signal 128 (which can be output by the decision device 104) to generate an error signal 136 that can be fed to the feedback filter 106. In some embodiments, the desired symbol signal 128 can be configured to provide an output decision signal 138.

[0025] In some embodiments, when the DFE 100 is implemented in an FFE line, the power output can be increased and the power consumption reduced compared to the baseline. In some examples, the reduction in power consumption compared to the baseline (where the DFE 100 is not implemented in an FFE line) can be greater than one or more of the following: 50%, 60%, 70%, 80%, 90%, 95%, 98%, or 99% compared to the baseline.

[0026] In some embodiments, the DFE 100 may use different taps, including n ± 1 taps (i.e., 1 ten Precursors and 1 ten Follower taps) that can be used for a subset of symbols that can be assigned for slicer-delayed decisions. Alternatively or additionally, the DFE might use n ± 2 taps (i.e., 2 ten Precursors and 2 tenFollower taps) can be used for a subset of symbols that can be assigned for slicer-delayed decisions. In some examples, using a combination of n ± 1 taps and n ± 2 taps can increase performance, measured in decibels, compared to a baseline where the combination of n ± 1 and n ± 2 taps is not used (e.g., the n ± 1 taps are used, but the n ± 2 taps are not). In some examples, the performance increase can be greater than one or more of the following criteria: 5%, 10%, 15%, 20%, 25%, 30%, or 50% compared to the baseline.

[0027] In some embodiments illustrated Fig. 2. A process flow diagram 200 for DFE noise reduction using noise reduction slicing or MLSE. The process flow diagram 200 can be executed by processing logic that may include hardware (circuits, dedicated logic, etc.), software (e.g., firmware or software running on a computer system or dedicated machine), or a combination of both, the processing logic being located in the processing device 1202. Fig. 12, the communication system 1100 of Fig. 11 or any other device, combination of devices or systems.

[0028] In some embodiments, the processing logic can be configured to receive from an FFE a signal containing a desired symbol (e.g., a received (Rx) symbol) and a prediction error (e.g., E). p(ω)). In one example, the processing logic can be designed to initialize the noise reduction slicer parameters (NSS parameters), including the initial NSS coefficients and the initial slicer-delayed decision (SDD) thresholds (e.g., threshold offsets), as can be implemented in Block 210. Alternatively or additionally, the processing logic can be designed to determine updated NSS coefficients, as can be implemented in Block 220. Alternatively or additionally, the processing logic can be designed to determine updated SDD thresholds (e.g., updated SDD threshold offsets), as can be implemented in Block 240.Alternatively or additionally, the processing logic can be designed to update the NSS parameters of a processing register based on the updated NSS coefficients and the updated SDD thresholds (e.g., updated SDD threshold offsets), as can be implemented in Block 250.

[0029] In some embodiments, the NSS parameters may include all suitable parameters that can be used to reduce noise during noise-reducing slicing or MLSE. The NSS parameters may include one or more of the following: (i) NSS coefficients, (ii) SDD thresholds (e.g., SDD threshold offsets), (iii) slicer error minimum limits (e.g., outer slicer error minimum limits), (iv) slicer error maximum limits (e.g., outer slicer error maximum limits), or similar parameters.

[0030] In some embodiments, such as those that can be implemented in Block 210 using Operation 212, the processing logic can be configured to initialize the noise reduction slicer (NSS) parameters by setting them to a hardware optimum. That is, the NSS parameters can be configured for a specific hardware implementation.

[0031] In some embodiments, the processing logic, as implemented in Block 220 using one or more of Operations 222, 224, 226, 228, 230, 232, or similar, can be configured to determine updated NSS coefficients. As shown in Operation 222, the processing logic can be configured to capture an FFE output. As shown in Operation 224, the processing logic can be configured to extract a slicer error from the captured FFE output. As shown in Operation 226, the processing logic can be configured to estimate a slicer error correlation (e.g., a slicer error autocorrelation). As shown in Operation 228, the processing logic can be configured to compute NSS coefficients. The NSS coefficients can be computed instantaneously in an example.As shown in Operation 230, the processing logic can be configured to pass the NSS coefficients to an infinite impulse response (IIR) filter. As shown in Operation 232, the processing logic can be configured to update the NSS coefficients (e.g., as calculated in Block 210 and / or Operation 212) so that they represent the outputs of the IIR filter.

[0032] In some embodiments, the slicer error correlation can be estimated based on a slicer error calculated from the slicer input (e.g., the slicer data acquisitions in signal 126) and the slicer thresholds and outputs, which may have been estimated a priori from the waveform at the FFE output. The error correlation can be based on the slicer data acquisitions, which can be used to extract the slicer error and calculate the slicer error autocorrelation. In one example, the slicer error correlation (e.g., the slicer error autocorrelation) can be used to determine the NSS coefficients.

[0033] In some embodiments, the error correlation (e.g., cross-correlation and / or autocorrelation) can alternatively or additionally be estimated based on the channel noise of a signal 122, which is fed, for example, from the output of an analog-to-digital converter (ADC) to the FFE. The channel noise may include: (i) AWGN introduced at the ADC output; (ii) non-independently and identically distributed (IID) (i.e., correlated) errors introduced by a continuous-time linear equalizer (CTLE); (iii) other (e.g., non-linear) distortions. Ignoring the non-linear distortions, the error correlation at the slicer input can be estimated based on (a) the second-order statistics of the channel noise components and (b) the FFE tap values. Consequently, the NSS coefficients can be estimated based on the second-order statistics of the channel noise components (a) and (b) and the FFE tap values.

[0034] In some embodiments, the slicer error correlation (e.g., cross-correlation and / or autocorrelation) can be estimated based on the correlated noise of neighboring symbols at a proximity chosen to reduce the slicer error in the slicer input. For example, the neighboring symbols might include one or more of the following: the n ± 1 taps; the n ± 2 taps; the n ± 3 taps; the n ± 4 taps; the n ± 5 taps, and so on.

[0035] In some embodiments, the processing logic, as shown in Block 228, can be configured to calculate noise reduction slicer coefficients (NSS coefficients) based on the slicer error correlation. The NSS coefficients can be sent to one or more IIR filters, as shown in Block 230, and the NSS coefficients can be updated based on IIR outputs of the IIR filters, as shown in Block 232.

[0036] In some embodiments, the NSS coefficients can be calculated using various methods, including one or more of the following: (i) Wiener-Hopf calculation, (ii) time-domain correlation, (iii) frequency-domain correlation, (iv) fast Fourier transform calculation, (v) discrete Fourier transform calculation, (vi) power spectral density calculation. For example, Wiener-Hopf calculation can be used to determine NSS coefficients that can be designed to combine the noise samples of a precursor sample and a postcursor sample to suppress a selected portion of the noise of a desired symbol.

[0037] In some embodiments, after the NSS coefficients have been determined, the processing logic can be configured to update the NSS parameters of a processing register based on the updated NSS coefficients, as can be implemented in Block 250. Block 250 can be implemented by setting the NSS parameters (e.g., the NSS coefficients) to the optimum for the specific hardware, as shown in Operation 252, and by writing the NSS parameters (e.g., the NSS coefficients) to a register of the processing device, as shown in Operation 254. In one example, the NSS parameters (e.g., NSS coefficients) can be programmed into the hardware of the noise reduction slicer block (e.g., into the registers of a processing device) to apply a hardware noise reduction algorithm to incoming signal samples.

[0038] In some embodiments, once the NSS coefficients have been written to the processing device register, the processing logic can be configured to apply noise reduction to the slicer input based on the NSS coefficients. The processing logic can then be configured to estimate the Rx symbol after the noise reduction has been applied (e.g., by applying a hard slicer decision to the Rx symbol).

[0039] In some embodiments, such as those that can be implemented in Block 240, the processing logic can be configured to determine updated thresholds for the delayed slicer decision (SDD) (e.g., 402aa, 402ab, 402ba, 402bb, 402ca and 402cb, as in Fig. 4 shown). The processing logic can be configured to calculate a signal-to-noise ratio (SNR) or a signal-to-noise ratio and distortion (SNDR) of a signal (e.g., an FFE output signal) around a slicer threshold (e.g., 410a, 410b, 410c, as shown in Fig. 4 shown).

[0040] In some embodiments, as shown in Operation 242, the processing logic can be configured to map the SNR to the SDD range as a fraction of the slicer output spacing (e.g., mapping the calculated SNR or SNDR to the width of an SDD range that optimizes the bit error probability after noise reduction). Such a mapping can be computed a priori by applying statistical signal processing techniques—assuming certain second-order channel statistics—or estimated empirically for a given channel and then stored in a lookup table. For some bandwidth-constrained channels, higher SNR or SNDR values ​​can be mapped to narrower SDD ranges to achieve an optimal bit error rate.For storage in a lookup table, the width of an SDD range can be expressed as a fraction of the distance between the slicer outputs around a slicer threshold (e.g., the width of SDD range 402a can be expressed as a fraction of the distance between slicer outputs 406a and 406b around the slicer threshold 410a, as in ). Fig. 4 shown). Alternatively, the width of an SDD area (e.g., SDD area 402a in Fig. 4) as the distance between a first location (in a signal amplitude domain) defined by a first SDD threshold (e.g. SDD threshold 402aa in Fig. 4) is identified, and a second location (in the signal amplitude domain) identified by a second SDD threshold offset (e.g. SDD threshold 402ab in Fig. 4) is identified, expressed.

[0041] In some embodiments, the processing logic can be configured to calculate SDD threshold offsets, as shown in Operation 244. The SDD threshold offsets can be one or more of a first SDD threshold offset (e.g., 412aa, 412ba, 412ca in Fig. 4) and a second SDD threshold offset (e.g. 412ab, 412bb or 412cb in Fig. 4) with respect to the same slicer threshold (e.g. 410a, 410b, 410c in Fig. 4) include. That is, SDD threshold offsets (412aa and 412ab in Fig. 4) can be relative to a slicer threshold (410a in Fig. 4) be defined. The first SDD threshold offset (e.g., 412aa in Fig. 4) identifies an initial SDD threshold (e.g. 402aa in Fig. 4), while the second SDD threshold (e.g. 412ab in Fig. 4) a second SDD threshold (e.g. 402ab in Fig. 4) identified. The SDD range can be the range between the first SDD threshold (e.g., 402aa in Fig. 4) and the second SDD threshold (e.g. 412ab in Fig. 4) The SDD range can be used to identify a delayed slicer decision or a hard slicer decision for an Rx symbol. In one example, the processing logic can be configured to apply the slicer delayed decision to the Rx symbol if the Rx symbol value is within the SDD range. In another example, the processing logic can be configured to apply the slicer hard decision to the Rx symbol if the Rx symbol value is outside the SDD range. In some examples, the SDD range can be calculated based on one or more test cases to determine values ​​for the SDD threshold offsets.

[0042] In some embodiments, the processing logic can be configured to provide an outer slicer error minimum limit (e.g., 414a in Fig. 4) and an outer slicer error limit (e.g. 414b in Fig. 4) calculated as shown in Operation 246. The outer slicer minimum error limit (e.g., 414a in Fig. 4) can be expressed as the negative of the distance between the lowest slicer output (e.g. 406a in Fig. 4) and the lowest SDD threshold (e.g. 402aa in Fig. 4) can be calculated. The outer slicer maximum error limit can be defined as the distance between the highest slicer output (e.g., 406d in Fig. 4) and the highest SDD threshold (e.g. 402cb in Fig. 4) are calculated. These limits can be applied to limit the slicer error of an Rx symbol that is below the lowest slicer output (e.g., 406a in ). Fig. 4) or above the highest slicer output (e.g. 406d in Fig. 4) before the slicer error is used for noise suppression of a preceding or subsequent Rx symbol that lies within an SDD region. In some embodiments, limiting the value of the outer slicer errors used in noise suppression can improve the accuracy of the noise estimation of an Rx symbol within an SDD region, resulting in improved hard decision and bit error performance.

[0043] In some embodiments, the processing logic can be configured to apply noise reduction to the slicer input. After the noise reduction has been applied, an updated SDD range can be calculated based on the updated SDD threshold offsets. The processing logic can be configured to apply an updated slicer hard decision to the Rx symbol if the Rx symbol value is outside the updated SDD range. The processing logic can also be configured to apply an updated SDD to the Rx symbol if the Rx symbol value is within the updated SDD range.

[0044] In some embodiments, the processing logic, as implemented in Block 250, can be configured to update the registers of a processing device. In one embodiment, the processing logic can be configured to set the SDD threshold offsets, the outer slicer minimum error limit, the outer slicer maximum error limit, or a combination thereof, based on the hardware configuration, as shown in Procedure 252. In other embodiments, the processing logic can be configured to write the SDD threshold offsets to the hardware (e.g., to the registers of a processing device), as shown in Procedure 254. In one example, the SDD threshold offsets can be programmed into the hardware of the noise reduction slicer block (e.g., to the registers of a processing device) to apply a hardware noise reduction algorithm to incoming signal samples.

[0045] In some embodiments, the order of calculating NSS coefficients and SDD threshold shifts can be reversed. In one example, block 240 can be calculated before block 220. In another example, operation 244 can be performed before operation 228.

[0046] In some embodiments, operations 244 and 246 (identified by box 260) can be combined with 602a in Fig. 6 marked operations correspond to the relationship between the NSS hardware in Fig. 6 and the process flow in Fig. 2 to illustrate.

[0047] In some embodiments, the SDD area can be integrated into the hardware of Fig. 6. The SDD range can be calculated and set without updating the SDD range. Alternatively or additionally, the processing logic can be configured to write the first SDD threshold offset and the second SDD threshold offset to a register of the processing device. The processing logic can be configured to calculate the SDD range either in real time or on demand.

[0048] In some embodiments, the processing logic can be configured to write the slicer error minimum limit (e.g., the outer slicer error minimum limit) and the slicer error maximum limit (e.g., the outer slicer error maximum limit) to a register of the processing device.

[0049] In some embodiments, operations 230 and 232 (identified by box 270) can be used in conjunction with 640a and 642a in Fig. The 6 marked operations correspond to the relationship between the NSS hardware in Fig. 6 and the process flow in Fig. 2 to illustrate.

[0050] In some embodiments, the NSS coefficients can be calculated periodically, in real time, and / or on demand, and stored in the hardware of Fig. 6. In one example, the processing logic can be configured to write the NSS coefficients into a register of the processing device.

[0051] In some embodiments, Fig. 3. A process flow diagram 300 for decision-making in an exemplary equalization system. The processing logic for an FFE can be designed as shown in Operation 310. A comparator can be used to determine whether a symbol is in a hard decision area of ​​the slicer (e.g., using the example in Fig. 4) or in an area with delayed slicer decision-making (e.g., also in Fig. (as shown in Figure 4). The comparator operation 320 must not cause any additional processing overhead compared to the basic FFE processing without the inclusion of comparator operation 320.

[0052] In some embodiments, the processing logic can be configured such that when comparator operation 320 detects that a symbol is within a slicer hard decision area, it calculates the slicer error, as shown in operation 330, and outputs a decision, as shown in operation 340. In some examples, the processing logic can be configured to interrupt the processing of the Rx symbol after the hard slicer decision has been applied to the Rx symbol. Interrupting symbol processing can enable a reduction in power consumption compared to basic FFE processing, where symbol processing is not interrupted after symbol processing.

[0053] In some embodiments, when the comparison operation 320 determines that an Rx symbol is not in a slicer-hard decision region or that the symbol is in a slicer-delayed decision region, the processing logic can be configured to apply noise suppression using the slicer error of precursor and postcursor symbols (e.g., hard-sliced ​​Rx symbols), as shown in operation 350. In some examples, the slicer error of the precursor and postcursor symbols can be used to form a slicer error estimator or predictor (i.e.,to compute a noise reduction term for the current Rx symbol(s), which may be based on a weighted combination of one or more of the following: slicer errors from an (n-1) symbol and an (n+1) symbol; slicer errors from an (n-2) symbol and an (n+2) symbol; slicer errors from an (n-3) symbol and an (n+3) symbol; slicer errors from an (n-4) symbol and an (n+4) symbol, or the like. In some examples, the combination of the weights of the slicer errors may yield the NSS coefficients obtained by Operation 220 in . Fig. 2. In some embodiments, when noise reduction has been applied (e.g., using the slicer error estimator or predictor), the processing logic can be designed to provide an output decision, as shown in Operation 360.

[0054] In some embodiments, the additional processing (e.g., calculating the slicer error of a hard-sliced ​​Rx symbol or using it for noise reduction) can be made dependent on the input of the slicer-delayed decision; therefore, the additional processing can be controlled. The probability that an Rx symbol is processed using a slicer-delayed decision may be small (e.g., less than 1 in 1000). Consequently, the performance impact resulting from process flow 300 may be less than, for example, 3% of the FFE power consumption.

[0055] In some embodiments, Fig. 4 An Example 400 for determining the slicer delayed decision and slicer hard decision for FFE and DFE in the case of a quadrature pulse amplitude modulated (PAM4) Rx signal. For lossy channels, for example, a symbol-wise equalization technique may not be sufficient to achieve reliable slicer hard decisions at the slicer output. In some examples, an Rx symbol that is in a slicer delayed decision region (i.e., close to a slicer threshold between different symbol values) can be re-evaluated after noise reduction. The noise reduction can be performed with processing logic designed to match the slicer input based on correlated noise from neighboring hard-decision symbols. In one example, a first precursor symbol (i.e., n-1) and a first follower symbol (i.e.,The neighboring symbols (n+1) can be used to compute an estimator or predictor (e.g., a slicer error estimator) to suppress the noise in the current Rx symbol (i.e., n). In some examples, the neighboring symbols can include any number of precursor or follower symbols that can reduce the noise of the Rx symbol to a suitable level to facilitate a slicer-hard decision.

[0056] In some embodiments, if a rectified Rx symbol lies in a hard decision area, i.e., in the area along the histogram 404a, 404b, 404c, 404d, which is not in the area 402a, 402b, 402c with slicer-delayed decision, a hard slicer decision can be applied to the symbol based on the slicer thresholds 410a, 410b, 410c to assign it to one of the slicer outputs 406a, 406b, 406c or 406d. If, on the other hand, the symbol is located in a range 402a, 402b, 402c, i.e. in the range around a slicer threshold of 410a, 410b or 410c, then a slicer-delayed decision can be applied to the symbol.

[0057] In some embodiments, the slicer-delayed decision range can be defined by a first SDD threshold (e.g., 402aa, 402ba, 402ca) and a second SDD threshold (e.g., 402ab, 402bb, 402cb). A first SDD threshold and a second SDD threshold can define a range on axis 408 (e.g., 402a, 402b, 402c) between which a symbol waveform can be processed using a delayed slicer decision instead of a hard slicer decision. In some examples, the first SDD threshold can be expressed as a negative offset (e.g., 412aa, 412ba, 412ca) from a slicer threshold (e.g., 410a, 410b, 410c) and the second SDD threshold as a positive offset (e.g., 412ab, 412bb, 412cb) from the same slicer threshold along axis 408.

[0058] In some embodiments, a slicer error may not be recorded if the waveform of a symbol is in a delayed slicer decision region. In some embodiments, a slicer error may be recorded if the waveform of the symbol is in a hard slicer decision region and a hard slicer decision has been applied to the symbol.

[0059] In some embodiments, Fig. Figure 5 shows an exemplary system 500 comprising a DFE 510 with a noise reduction block 520. The DFE 510 may include one or more feedforward filters 502, subtractors 504, feedback filters 512, noise reduction blocks 520, and hard slicers 508. The input signal 501 may contain additive Gaussian noise (AGN) (e.g., AWGN) and may be fed to the feedforward filter 502. The feedforward filter 502 may output a signal 503 comprising a desired symbol, ISI, and AGN (e.g., AWGN). The signal 503 can be passed to a subtractor 504, which can be configured to subtract an output prediction received from the feedback filter 512 from the signal 503 in order to generate a signal 505 with the desired symbol and a prediction error.The signal 505 can be output to the noise reduction block 520, which can be configured to generate a signal 521 containing the desired symbol with suppressed error, and which is passed to the hard slicer 508. The hard slicer 508 can apply a hard decision to the signal 521 to provide an input signal 509 for the feedback filter 512 and an output decision signal 511. The feedback filter 512 can be configured to provide a feedback signal 513 to the subtractor 504.

[0060] In some embodiments, the DFE 510 may include data path equalization and be used in FFE mode. If a least mean square (LMS) circuit is not configured to estimate FFE coefficients, the FFE coefficients can be estimated in the firmware by tracking channel updates in some examples. A parallel FFE implementation may be used in some examples, where multiple slices of Rx signal samples are processed by FFE in each data path clock cycle. In such examples, noise reduction may be applied to more than one or more of the following: 90% of the FFE slices, 95% of the FFE slices, or 99% of the FFE slices.

[0061] In some embodiments, the noise suppression block 520 can comprise one or more soft slicers 522, a subtractor 524, a mux 526, an arithmetic logic block 528 with data storage, a mux 530, a multiplier 532, a subtractor 534, or a delay block 536. The noise suppression block 520 can be configured to receive the signal 505 from the subtractor 504. The signal 505 can be routed to the soft slicer 522, which can be configured to route a signal 523 to the subtractor in order to supply an error signal 525 containing the slicer error to the mux 526. The mux 526 can be configured to receive a control signal 539a for a delayed decision of the slicer from block 538a.

[0062] In some embodiments, the Mux 526 can be configured to output a signal 527 that is selected as: (i) a “0” signal 525 when a delayed slicer decision is detected, and (ii) the error signal 525 (e.g., e n ), when a hard slicer decision is detected. The arithmetic logic block 528, which includes a data memory, can be configured to compute an estimator or predictor of a symbol slicer error (e.g., a slicer error estimator) using the correlated error of neighboring symbols. The arithmetic logic block 528 can be configured to forward the signal 529 to the mux 530. The mux 530 can be configured to receive a control signal 539b for a delayed slicer decision from block 538b.

[0063] In some embodiments, the Mux 530 can be configured to output a signal 531 which can be selected as: (i) a “0” signal when a hard slicer decision is detected, or (ii) as the signal 529 (e.g., c n), when a slicer-delayed decision is detected. The signal 531 can be passed to the multiplier 532, which can be configured to generate a signal 533 based on the signal 529 and a noise reduction factor 540 (e.g., α / (1 + β)) (which can be estimated in the firmware based on data path equalizer updates) sent via 541. In some cases, the signal 533 can be calculated using a lookup table in addition to or as an alternative to the multiplier 532. The resulting signal 533 can be passed to the subtractor 534, which can be configured to remove the signal 533 from the time-delayed signal 537 (which was calculated in the time-delay block 536 based on the input signal 505). The output signal 521 from the noise reduction block 520 can be output to the hard slicer 508 to generate an output decision signal 511.

[0064] In some embodiments, such as in Fig. As shown in Figure 6, a noise-suppression slicer 600 can be configured to receive a signal 601 from an FFE. The signal 601 can be passed to the soft slicer 602 and the character extender 606. The soft slicer can be configured to receive a signal 605 from the multiplexer 604. The multiplexer 604 can be configured to receive slicer thresholds and slicer outputs from the slicer data output signal 617. The soft slicer 602 can be configured to receive a software-defined configuration setting from 602a, which may include: (i) an instruction to enable the noise-suppression slicer, (ii) an outer slicer maximum error limit, (iii) an outer slicer minimum error limit, and (iv) SDD threshold offsets. In some implementations, SDD threshold offsets can be used to determine when slicer-delayed decisions are made.An error estimator or predictor (e.g., Block 644) can be used to suppress the correlated noise of one or more antecedent symbols and one or more runner symbols to enable a hard decision in a subsequent cycle.

[0065] In some embodiments, the soft slicer 602 can be directly connected to a switch 622 via 621 and receive inputs from an OR gate 620. The OR gate 620 can be configured to close the switch when it receives one or more enable signals for a slicer-delayed decision for one or more of the following signals: 2 ten Precursor, 1 ten Precursor, 1 ten Follower, 2 ten Follow-up signals or similar of the signal at the soft slicer input 601. The enable signals for the delayed decision of the slicer can be received from the output signal of the soft slicer 602, which is the 2ten Precursor, the 1 ten Precursor, the 1 ten Follower, the 2 ten This corresponds to trailing signals. The soft slicer can be configured to output a signal 603, which can be used to set the enable signal for the slicer's delayed decision for the current symbol via 603a to the signal 619 of an adjacent symbol.

[0066] In some embodiments, passing the output signal 603 via 603a to the signal 619 can result in a power reduction compared to a baseline slicer with noise suppression. The signal 603 can pass the SDD enable signals 619 to the OR gate 620, thus avoiding power consumption if none of the adjacent symbols (e.g., n-1, n-2, n+1, n+2) are in an SDD region (i.e., if they are all sufficiently reliable because they are in a slicer-hard decision region). If the adjacent symbols are sufficiently reliable, they do not benefit from the suppression of the correlated noise of the current symbol.By avoiding these calculations, the NSS can have a power consumption that can be reduced by more than 90%, 95% or 99% compared to a basic NSS where the slicer enable signals for delayed decision of adjacent symbols are not used to control the propagation of the slicer error signal 621 at the output of the soft slicer 602.

[0067] In some embodiments, when switch 622 is closed (when OR gate 620 has the truth value "1"), the slicer error of the current symbol can be routed via connection 623 to block 624, and then via connection 625 to the summation block 626 (for the 1 ten Precursors and the 1 ten Followers) and to the total block 628 (for the 2 ten Precursors and the 2 ten to be guided to the trailing symbol) of a neighboring symbol.

[0068] In some embodiments, the 1 ten Precursor and 1ten Trailing slicer errors from summation block 626 are routed to amplification by block 642, using NSS coefficients 642a calculated using software-defined configuration settings. Similarly, the 2 ten Precursor and 2 tenFollower slicer errors from summing block 628 are routed to block 640 for amplification, using NSS coefficients 640a calculated using software-defined configuration settings. The amplified signal from 642 and 640 can be routed to multiplexer 634 and multiplexer 636, respectively. Multiplexer 634 can be controlled by an NSS coefficient enable signal 634a, and multiplexer 636 by an NSS coefficient enable signal 636a, each of which can have software-defined configuration settings. The output of multiplexer 634 and multiplexer 636 can be routed to summing block 638. The entirety of block 644 can be controlled by an enable signal 644a. The output of the summing block 638 can be forwarded as signal 639 to the summing block 610.

[0069] In some embodiments, the summing block 610 can be selected by the multiplexer 608 (using the control signal 603 received from the soft slicer 602), which can receive a signal 607a from the character extender 606, which can receive the signal 601.

[0070] In some embodiments, signal 601 can be routed to sign extension 606 and then, as signal 607a, to the demultiplexer 608. The demultiplexer can be configured, via the soft slicer output signal 603 (i.e., the enable signal for the slicer's delayed decision), to route signal 607a to the summing block 610 via 609a, or it can be configured to route signal 607a directly to the multiplexer 614 via 609b. When the demultiplexer 608 routes signal 609a to the summing block 610, the resulting signal 611 may contain suppressed noise based on signal 639. The signal 611 can be routed to the RNS block 612, which can use a rounding and saturation block, and the RNS block 612 can route a signal 613 to the multiplexer 614.The multiplexer 614 can be controlled by the output signal 603 of the soft slicer 602 to select an output that includes signal 613 or signal 609b. Signal 615 from the multiplexer 614 can be routed to the hard slicer 618 or to the multiplexer 616.

[0071] In some embodiments, the hard slicer 618 can provide a decision output signal 651. The hard slicer 618 can be controlled by the block 618a, which may contain a modulation selection type (e.g., PAM4).

[0072] In some embodiments, the multiplexer 616 can receive signal 615 from the multiplexer 614 and signal 607b from the character extender 606. The multiplexer 614 can be controlled by a slicer data multiplexer selector for noise reduction to provide an output signal to one or more histogram calculation logics, memory acquisition logics, slicer threshold estimation logics, or SNR estimation logics.

[0073] In some embodiments, the configuration settings determined by the software in block 602a may correspond to field 260 in flowchart 200. In some embodiments, the configuration settings determined by the software in blocks 640a and 642a may correspond to box 270 in flowchart 200.

[0074] In some embodiments, the in Fig. In the noise reduction slicer 700 shown in Figure 7, a demultiplexer 702 is configured to receive a signal 701. The signal 701 can comprise one or more slices with a selected number of bits. The output signal 703 from the demultiplexer 702 can be routed to a hard slicer 704, which can be configured to send a decision output signal 705 to the multiplexer 706, which is output as signal 751.

[0075] In some embodiments, e.g., when a symbol is not present in a slicer hard decision area, the output signal 707 can be routed from the demultiplexer 702 to the soft slicer 708, which can receive one or more control signals with SDD thresholds (e.g., SDD threshold offsets). The soft slicer 708 can be configured to output a signal 709a to one or more of the following elements: (i) a demultiplexer 736; or (ii) an enable gate for one or more multiplexers 720, 722, 724 or 726. The enable gate for the one or more multiplexers 720, 722, 724 or 726 may be configured to enable noise suppression using one or more precursor symbols or one or more post-precursor symbols based on the reliability of the one or more precursor symbols or the one or more post-precursor symbols.

[0076] In some 1 tenIn certain embodiments, each of the multiplexers 720, 722, 724, 726 can receive a slicer error if the multiplexers 720, 722, 724, 726 are activated (e.g., for the 1 received via 729). ten Precursor 728, the one received via 731 ten Follower 730, the 2 received via 733 ten Precursor 732, the one received via 735 2 ten(e.g., follower 734 or similar). The output of multiplexers 720, 722 (e.g., the first precursor and the first follower) can be routed via connections 721 and 723 to a summing and scaling block 716. The output signal of multiplexers 724, 726 (e.g., the second precursor and the second follower) can be routed via connections 725 and 727 to a summing and scaling block 718. The output associated with the first precursor and follower can be routed via connection 717 to a summing block 710, and the output associated with the second precursor and follower can be routed via connection 719 to the summing block 710.

[0077] In some embodiments, the summing block 710 can be configured to receive an output signal from the demultiplexer 736. The summing block can output a signal 711 to the hard slicer 712, which can provide a decision output signal 713 that is routed via the multiplexer 714 to the multiplexer 706 via the connection 715. Therefore, when noise suppression is enabled, the path between the demultiplexer 702, the hard slicer 704, and the multiplexer 706 can be replaced by the path between the demultiplexer 702, the soft slicer 708, the demultiplexer 736, the summing block 710, the hard slicer 712, the multiplexer 714, and the multiplexer 706 to generate a decision output signal 751.

[0078] In some embodiments, a noise reduction slicer can be configured to estimate one or more NSS coefficients based on channel noise of the output signal. For example, y(n), the slicer input, can be calculated using the following formula: y(n)=∑k=kminkmaxx(n−k)h(k) where x(n) is the received signal at the output of the analog-to-digital converter and h(n) is the composite equalizer impulse response. Consequently, x(n) can be calculated as follows: x(n)=x0(n)+e(n) where e(n) is the noise term, which can be independent and identically distributed (IID) according to Gaussian characteristics, such as AWGN. Furthermore, y(n), the slicer input, can be calculated as follows: y(n)=y0(n)+ε(n) where ε(n) is an error term that is not independent and identically distributed (i.e., not IID). Furthermore, the error term for y(n) can be calculated as follows: ε(n)=∑k=kminkmaxe(n−k)h(k) where ε(n) can be highly correlated with the first precursor error (i.e., ε(n-1)) and strongly correlated with the first follower error (i.e., ε(n+1)) if the precursor FFE tap and the follower FFE tap have large values.

[0079] In some embodiments, if the slicer input y(n) is close to the slicer threshold (i.e., within the range of delayed slicer decision, defined by a first x-axis value corresponding to a first NSS threshold offset and a second x-axis value corresponding to a second NSS threshold offset), the error for y(n) (i.e., ε(n)) can be corrected by subtracting an estimate of ε(n) from y(n). Since ε(n) is correlated with ε(n-1) and ε(n+1), the error for ε(n) can be estimated linearly by subtracting ε(n-1) and ε(n+1).

[0080] In some embodiments, the linear estimator for y(n) can be calculated based on ε(n-1) and ε(n+1) using: ε(n)=[ε(n−1)ε(n+1)]⋅Rxx−1⋅Ryx

[0081] Consequently, the cross-correlation of ε(n) and [ε(n-1); ε(n+1)] can be Ryx, and the autocorrelation of [ε(n-1); ε(n+1)] can be Rxx. Therefore, the cross-correlation, Ryx, can be calculated as follows: Ryx=∑k=kminkmaxh(k−1)(h(k)⋅Var(e(n))⋅[11−β2β1−β2;−β1−β211−β2] and the autocorrelation Rxx can be calculated as follows: Rxx=∑k=kminkmaxh(k)(h(k)⋅Var(e(n))⋅[11−β2−β1−β2;−β1−β211−β2].

[0082] Based on these equations for cross-correlation and autocorrelation, the NSS coefficients can be calculated as follows: α=(∑k=kminkmaxh(k−1)h(k)) / (∑k=kminkmaxh(k)h(k)) and β=(∑k=kminkmaxh(k−2)h(k)) / (∑k=kminkmaxh(k)h(k)).

[0083] Therefore, the predictor for the error, ε(n), for the slicer input y(n) can be calculated as follows: ε(n)=[ε(n−1)ε(n+1)]⋅(α1+β))⋅[1;1].

[0084] In some embodiments, the slicer error can be used to calculate NSS coefficients that can be used in noise reduction. In some examples, noise reduction can be used to reduce high-frequency noise. In some examples, noise reduction can be used to reduce low-frequency noise by employing autocorrelation, which can provide opposite-sign coefficients not calculated by autocorrelation (e.g., cross-correlation). In some examples, the number of coefficients can be chosen to affect different waveform profiles, which can have different shapes, as illustrated by the power spectral density.

[0085] Fig. Figure 8 shows the process of an exemplary method 800, which can be used for noise suppression in accordance with at least one embodiment described in the present disclosure. The method 800 can be carried out in accordance with at least one of the embodiments described in the present disclosure.

[0086] The method 800 can be performed by a processing logic that may include hardware (circuits, dedicated logic, etc.), software (such as that executed on a computer system or a dedicated computer), or a combination of both, the processing logic being located in the processing device 1202. Fig. 12, the communication system 1100 of Fig. 11 or any other device, combination of devices or systems.

[0087] Procedure 800 can begin in block 805, where the processing logic can receive the Rx symbol from the feedforward equalizer.

[0088] In block 810, the processing logic can calculate a slicer-deferred decision area (SDD area) to identify an SDD.

[0089] In block 815, the processing logic can apply the SDD to the Rx symbol if an Rx symbol value lies within the SDD range.

[0090] In block 820, the processing logic can apply a slicer-hard decision to the Rx symbol if the Rx symbol value is not within the SDD range.

[0091] Method 800 may be modified, supplemented, or omitted without exceeding the scope of this disclosure. In some embodiments, for example, Method 800 may include any number of other components not expressly shown or described.

[0092] Fig. Figure 9 shows the process flow of an exemplary method 900, which can be used for noise suppression in accordance with at least one embodiment described in the present disclosure. The method 900 can be carried out in accordance with at least one embodiment described in the present disclosure.

[0093] The method 900 can be performed by a processing logic that may comprise hardware (circuits, dedicated logic, etc.), software (such as that executed on a computer system or a dedicated computer), or a combination of both, the processing logic being located in the processing device 1202. Fig. 12, the communication system 1100 of Fig. 11 or any other device, combination of devices or systems.

[0094] Procedure 900 can begin in block 905, where the processing logic can estimate a slicer error correlation based on a slicer error from a slicer input.

[0095] In block 910, the processing logic can calculate one or more noise reduction slice coefficients (NSS coefficients) based on the slicer error correlation.

[0096] In block 915, the processing logic can apply noise reduction to the slicer input based on one or more NSS coefficients.

[0097] In block 920, the processing logic can estimate the Rx symbol after noise reduction has been applied.

[0098] Method 900 may be modified, supplemented, or omitted without exceeding the scope of this disclosure. For example, in some embodiments, Method 900 may include any number of other components that are not explicitly shown or described.

[0099] Fig. Figure 10 shows the process of an exemplary method 1000, which can be used for noise suppression in accordance with at least one embodiment described in the present disclosure. The method 1000 can be carried out in accordance with at least one of the embodiments described in the present disclosure.

[0100] The method 1000 can be performed by a processing logic that may comprise hardware (circuits, dedicated logic, etc.), software (such as that executed on a computer system or a dedicated computer), or a combination of both, wherein the processing logic is located in the processing device 1202. Fig. 12, the communication system 1100 of Fig. 11 or any other device, combination of devices or systems.

[0101] Procedure 1000 can begin in block 1005, where the processing logic can receive an output signal with a received (Rx) symbol from a feedforward equalizer.

[0102] In block 1010, the processing logic can initialize the noise reduction slicer parameters (NSS parameters), including one or more initial NSS coefficients and one or more threshold offsets of the initial slicer delayed decision (SDD).

[0103] In block 1015, the processing logic can determine one or more updated NSS coefficients.

[0104] In block 1020, the processing logic can determine one or more updated threshold offsets for slicer delayed decision (SDD).

[0105] In block 1025, the processing logic can update the NSS parameters of a processing register based on one or more updated NSS coefficients and one or more updated SDD threshold offsets.

[0106] Method 1000 may be modified, supplemented, or omitted without exceeding the scope of this disclosure. In some embodiments, for example, Method 1000 may include any number of other components not expressly shown or described.

[0107] Fig. Figure 11 shows a block diagram of an exemplary communication system 1100 configured for noise suppression, in accordance with at least one embodiment described in the present disclosure. The communication system 1100 may comprise a digital transmitter 1102, a radio frequency circuit 1104, a device 1114, a digital receiver 1106, and a processing device 1108. The digital transmitter 1102 and the processing device may be configured to receive a baseband signal via a connection 1110. A transceiver 1116 may comprise the digital transmitter 1102 and the radio frequency circuit 1104.

[0108] In some embodiments, the communication system 1100 may comprise a system of devices that can be configured to communicate with each other via a wired or connected link. For example, a wired link in the communication system 1100 may include one or more Ethernet cables, one or more fiber optic cables, and / or other similar wired communication media. Alternatively or additionally, the communication system 1100 may comprise a system of devices that can be configured to communicate via one or more wireless links. For example, the communication system 1100 may comprise one or more devices configured to transmit and / or receive radio waves, microwaves, ultrasonic waves, optical waves, electromagnetic induction, and / or similar wireless communications.Alternatively or additionally, the communication system 1100 can also include combinations of wireless and / or wired connections. In these and other embodiments, the communication system 1100 can include one or more devices that may be configured to receive a baseband signal, perform one or more operations on the baseband signal to generate a modified baseband signal, and transmit the modified baseband signal, for example, to one or more loads.

[0109] In some embodiments, the communication system 1100 may include one or more communication channels that can communicatively couple systems and / or devices included in the communication system 1100. For example, the transceiver 1116 may be communicatively coupled with the device 1114.

[0110] In some embodiments, the transceiver 1116 can be configured to receive a baseband signal. As described herein, the transceiver 1116 can, for example, be configured to generate a baseband signal and / or receive a baseband signal from another device. In some embodiments, the transceiver 1116 can be configured to transmit the baseband signal. For example, after receiving the baseband signal, the transceiver 1116 can be configured to transmit the baseband signal to a separate device, such as the device 1114. Alternatively or additionally, the transceiver 1116 can be configured to modify, condition, and / or transform the baseband signal before transmitting it. For example, the transceiver 1116 can include a quadrature boost converter and / or a digital-to-analog converter (DAC), which can be configured to modify the baseband signal.Alternatively or additionally, the 1116 transceiver can include a direct high-frequency sampling converter that can be configured to modify the baseband signal.

[0111] In some embodiments, the digital transmitter 1102 may be configured to receive a baseband signal via the connection 1110. In some embodiments, the digital transmitter 1102 may be configured to upconvert the baseband signal. For example, the digital transmitter 1102 may include a quadrature upconverter applied to the baseband signal. In some embodiments, the digital transmitter 1102 may include an integrated digital-to-analog converter (DAC). The DAC may convert the baseband signal into an analog signal or a continuous-time signal. In some embodiments, the DAC architecture may include a direct RF sampling DAC. In some embodiments, the DAC may be a separate element from the digital transmitter 1102.

[0112] In some embodiments, the transceiver 1116 may include one or more subcomponents that can be used in preparing and / or transmitting the baseband signal. For example, the transceiver 1116 may include an RF front end (e.g., in a wireless environment) comprising a power amplifier (PA), a digital transmitter (e.g., 1102), a digital front end, a device compliant with the Institute for Data and Information Recognition and Processing (IEEE 1588v2 device), an LTE physical layer (L-PHY), an S-plane device, an M-plane device, an Ethernet media access control (MAC) / personal communications service (PCS), a resource controller / scheduler, and the like. In some embodiments, a radio device (e.g.,a radio frequency circuit 1104) of the transceiver 1116 can be synchronized with the resource control via the S-level device, which can contribute to highly accurate time control with respect to a reference clock.

[0113] In some embodiments, the transceiver 1116 can be configured to receive the baseband signal for transmission. For example, the transceiver 1116 can receive the baseband signal from a separate device, such as a signal generator. The baseband signal can originate, for example, from a converter that transforms a variable into an electrical signal, such as an audio signal output by a microphone that picks up a speaker's voice. Alternatively or additionally, the transceiver 1116 can be configured to generate a baseband signal for transmission. In these and other embodiments, the transceiver 1116 can be configured to transmit the baseband signal to another device, such as the device 1114.

[0114] In some embodiments, the device 1116 can be configured to receive a transmission from the transceiver 1116. For example, the transceiver 1116 can be configured to send a baseband signal to the device 1114.

[0115] In some embodiments, the radio frequency circuit 1104 can be configured to transmit the digital signal received from the digital transmitter 1102. In some embodiments, the RF circuit 1104 can be configured to transmit the digital signal to the device 1114 and / or the digital receiver 1106. In some embodiments, the digital receiver 1106 can be configured to receive a digital signal from the RF circuit and / or send a digital signal to the processing device 1108.

[0116] In some embodiments, the processing device 1108, as shown, can be a standalone device or system. Alternatively or additionally, the processing device 1108 can be a component of another device and / or system. In some embodiments, for example, the processing device 1108 can be integrated into the transceiver 1116. In cases where the processing device 1108 is a standalone device or system, it can be configured to communicate with additional devices and / or systems located remotely from the processing device 1108, such as the transceiver 1116 and / or the device 1114. For example, the processing device 1108 can be configured to send and / or receive transmissions from the transceiver 1116 and / or the device 1114.In some embodiments, the processing device 1108 can be combined with other elements of the communication system 1100.

[0117] For the sake of simplicity, the methods and / or processes described herein are presented and described as a series of actions. However, the actions according to this disclosure can be performed in different sequences and / or simultaneously, as well as in conjunction with other actions not presented or described here. Furthermore, not all of the actions presented may be used to carry out the methods according to the disclosed subject matter. In addition, the person skilled in the art will understand and recognize that the methods can alternatively be represented as a series of interconnected states via a state diagram or events. Moreover, the methods disclosed in this description can be stored on a manufacturing item, such as a non-transient computer-readable medium, to facilitate the transport and transfer of such methods to computer equipment.The term "product" as used here refers to a computer program that can be accessed by any computer-readable device or storage medium. Although represented as individual blocks, different blocks can be split into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0118] Fig. Figure 12 shows a schematic representation of a computer in the exemplary form of a computer device 1200, in which a set of instructions can be executed to cause the computer to perform one or more of the procedures described herein. The computer device 1200 can comprise a rackmount server, a router computer, a server computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, or any computer device with at least one processor, etc., in which a set of instructions can be executed that causes the computer to perform one or more of the procedures described herein. In alternative embodiments, the computer can be connected (e.g., networked) to other computers in a LAN, an intranet, an extranet, or the Internet. The computer can operate in the function of a server in a client-server network environment.Even if only a single computer is depicted, the term "computer" can also encompass any collection of computers that, individually or collectively, execute a set (or multiple sets) of instructions to perform one or more of the methods described herein.

[0119] The exemplary computer device 1200 comprises a processing device (e.g. a processor) 1202, a main memory 1204 (e.g. read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1206 (e.g. flash memory, static random access memory (SRAM)) and a data storage device 1216, which communicate with each other via a bus 1208.

[0120] The processing device 1202 is one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. In particular, the processing device 1202 may include a CISC (Complex Instruction Set Computing) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device 1202 may also include one or more specialized processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1202 is configured to execute instructions 1226 to perform the operations and steps discussed herein.

[0121] The computer device 1200 may further include a network interface 1222 that can communicate with a network 1218. The computing device 1200 may also include a display device 1210 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1220 (e.g., a loudspeaker). In at least one embodiment, the display device 1210, the alphanumeric input device 1212, and the cursor control device 1214 may be combined into a single component or device (e.g., an LCD touchscreen).

[0122] The data storage device 1216 may contain a computer-readable storage medium 1224 on which one or more sets of instructions 1226 are stored, embodying one or more of the methods or functions described herein. The instructions 1226 may also reside wholly or at least partially in the main memory 1204 and / or the processing device 1202 while being executed by the computing device 1200, the main memory 1204 and the processing device 1202 also being computer-readable media. The instructions may furthermore be transmitted or received over a network 1218 via the network interface device 1222.

[0123] While the computer-readable storage medium 1224 is depicted as a single medium in one embodiment, the term "computer-readable storage medium" can encompass a single medium or multiple media (e.g., a central or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable storage medium" can also encompass any medium capable of storing, encoding, or carrying a set of instructions for execution by the computer, and which causes the computer to perform one or more of the methods disclosed herein. Accordingly, the term "computer-readable storage medium" can include, but is not limited to, solid-state storage media, optical media, and magnetic media. EXAMPLES

[0124] The following are examples of the performance characteristics according to the embodiments of the present disclosure. EXAMPLE 1: Comparison between FFE and FFE with noise reduction for a higher loss channel

[0125] Fig. 13A and Fig. Section 13B illustrates exemplary results using various techniques, hardware and / or processing logic described here. Fig. 13A and Fig. Figure 13B shows the Welch power spectral density and the bit error rate (BER) for a more lossy channel compared to the one in Fig. 14A and Fig. Channel shown in 14B.

[0126] As in Fig. As shown in Figure 13A, the power spectral density of the slicer error ranged from about -25 (dB / rad / sample) for a normalized frequency of about 0.01 (in units of x pi rad / sample), to about -22 (dB / rad / sample) for a normalized frequency of about 0.5 (in units of x pi rad / sample), to about -17 (dB / rad / sample) for a normalized frequency of about 0.8 (in units of x pi rad / sample) and to about -16 (dB / rad / sample) for a normalized frequency of about 0.99 (in units of x pi rad / sample). The signal's spectral power density varied between approximately 2 dB / rad / sample and approximately 2.5 dB / rad / sample at a normalized frequency of approximately 0.01 π rad / sample to approximately 0.99 π rad / sample. The signal power reached a peak value of approximately 7 dB over the normalized frequency range.

[0127] The signal with the slicer error power spectral density and the signal power spectral density, as in Fig. 13A was shown in Fig. 13B for an FFE example and for an FFE with noise reduction simulated, based on the slicer signal-to-noise ratio to calculate the bit error rate.

[0128] For the FFE example, as represented by the double dotted line, the bit error rate ranged approximately linearly from about 0.4 × 10 -5 for a slicer SNR of approximately 19.75 over approximately 0.8 × 10 -7 for a slicer SNR of approximately 21 to approximately 1 × 10 -9 for a slicer SNR of approximately 22.

[0129] For the example of the FFE with noise suppression, as shown by the solid line, the bit error rate was approximately linear between 1 × 10 -7 for a slicer SNR of approximately 19.75 and approximately 1 × 10 -9 for a slicer SNR of approximately 21.

[0130] The bit error rate performance for the FFE with noise suppression increased compared to the bit error rate performance for the FFE example. The FFE example with noise suppression achieved a bit error rate of approximately 4.9 × 10⁻⁶. -8 with a slicer SNR of approximately 19.95. In contrast, the FFE example achieved a similar bit error rate of approximately 4.3 × 10⁻⁶. -8 with a higher slicer SNR of approximately 21.2. The bit error rate of the FFE with noise reduction thus achieves a similar bit error rate to the FFE example with a slicer SNR that is approximately 1.25 dB lower.

[0131] Furthermore, the FFE example with noise reduction achieved a bit error rate of approximately 9 × 10⁻⁶. -9 with a slicer SNR of approximately 20.45. In contrast, the FFE example achieved a similar bit error rate of approximately 8 × 10⁻⁶. -9with a higher slicer SNR of approximately 21.7. The bit error rate of the FFE with noise reduction thus achieves a similar bit error rate to the FFE example with a slicer SNR that is approximately 1.25 dB lower.

[0132] The simulation results show that the bit error rate of the FFE with noise reduction was similar to that of the FFE example at reduced slicer SNRs. The example of the FFE with noise reduction was accurate across the tested slicer SNR range of approximately 19.75 dB to approximately 22 dB. EXAMPLE 2: Comparison between FFE and FFE with noise reduction for a lower-loss channel

[0133] Fig. Figures 14A to 14B show exemplary results using various techniques, hardware and / or processing logic described here.

[0134] Fig. 14A and Fig. Figure 14B shows the Welch power spectral density and bit error rate (BER) for a lower-loss channel compared to the one in Fig. 13A and Fig. Channel 13B shown.

[0135] As in Fig. As shown in Figure 14A, the power spectral density of the slicer error ranged from about -20 (dB / rad / sample) for a normalized frequency of about 0.01 (in units of x pi rad / sample), to about -19 (dB / rad / sample) for a normalized frequency of about 0.5 (in units of x pi rad / sample), to about -16 (dB / rad / sample) for a normalized frequency of about 0.8 (in units of x pi rad / sample), to about -15 (dB / rad / sample) for a normalized frequency of about 0.99 (in units of x pi rad / sample). The signal's spectral power density varied between approximately 2 dB / rad / sample and approximately 2.5 dB / rad / sample at a normalized frequency of approximately 0.01 dB / rad / sample to approximately 0.99 dB / rad / sample. The signal power reached a peak value of approximately 4 dB over the normalized frequency range.

[0136] The signal with the slicer error power spectral density and the signal power spectral density, as in Fig. 14A was shown in Fig. 14B for an FFE example and for an FFE with noise reduction simulated, based on the slicer signal-to-noise ratio to calculate the bit error rate.

[0137] For the FFE example, as represented by the double dotted line, the bit error rate ranged approximately linearly from about 0.6 × 10 -4 for a slicer SNR of approximately 18.5 over approximately 0.1 × 10 -4 for a slicer SNR of approximately 19 to approximately 1 × 10 -6 for a slicer SNR of approximately 20.

[0138] For the example of the FFE with noise suppression, as shown by the solid line, the bit error rate ranged approximately linearly from about 0.1 × 10 -4 for a slicer SNR of approximately 18.5 to approximately 1 × 10 -6 for a slicer SNR of approximately 19.7.

[0139] The bit error rate performance for the FFE with noise suppression increased compared to the bit error rate performance for the FFE example. The FFE example with noise suppression achieved a bit error rate of approximately 1 × 10⁻⁶. -5 with a slicer SNR of approximately 18.61. In contrast, the FFE example achieved a similar bit error rate of approximately 1.1 × 10⁻⁶. -5 with a higher slicer SNR of approximately 19.12. The bit error rate of the FFE with noise reduction thus achieved a similar bit error rate to the FFE example with a slicer SNR that was approximately 0.51 dB lower.

[0140] Furthermore, the FFE example with noise reduction achieved a bit error rate of approximately 1.7 × 10⁻⁶. -6 with a slicer SNR of approximately 19.37. In contrast, the FFE example achieved a similar bit error rate of approximately 1.6 × 10⁻⁶. -6with a higher slicer SNR of approximately 19.87. The bit error rate performance of the FFE with noise reduction thus achieved a similar bit error rate to the FFE example with a slicer SNR that was approximately 0.50 dB lower.

[0141] The simulation results show that the bit error rate of the FFE with noise reduction was similar to that of the FFE example at reduced slicer SNRs. The example of the FFE with noise reduction was accurate across the tested slicer SNR range of approximately 18 dB to approximately 20.5 dB. EXAMPLE 3: Comparison between FFE with noise reduction and the theoretical limit

[0142] Fig. Figure 14 shows exemplary results and a comparison with a theoretical limit using various techniques, hardware, and / or processing logic described here. As in Fig.As shown in Figure 14, the simulation results showed that the FFE with noise reduction example delivered a bit error rate based on the slicer SNR that was close to the theoretical limit. In contrast, the DFE-BER example and the FFE-only example delivered a bit error rate based on the slicer SNR that performed worse than the FFE with noise reduction example.

[0143] For the FFE example, as shown by the dashed line, the bit error rate ranged approximately linearly from about 0.1 × 10 -4 for a slicer SNR of approximately 19 to approximately 1 × 10 -7 for a slicer SNR of approximately 21.

[0144] For the DFE-BER example, as shown by the dashed line, the bit error rate ranged approximately linearly from about 0.1 × 10 -5 for a slicer SNR of approximately 19 to approximately 0.4 × 10 -8 for a slicer SNR of approximately 21.

[0145] For the example of the FFE with noise suppression, as shown by the solid line, the bit error rate ranged approximately linearly from about 1 × 10 -6 for a slicer SNR of approximately 19 to approximately 1 × 10 -9 for a slicer SNR of approximately 21.

[0146] For the theoretical limit (calculated using the Salz SNR method), as shown by the dashed and double-dotted lines, the bit error rate ranged approximately linearly from about 0.1 × 10 -7 for a slicer SNR of approximately 19 to approximately 1 × 10 -10 for a slicer SNR of approximately 21.

[0147] The bit error rate performance for the FFE with noise suppression increased compared to the bit error rate performance for the DFE-BER example and the FFE example. The FFE example with noise suppression achieved a bit error rate of approximately 5.4 × 10⁻⁶. 7 7with a slicer SNR of approximately 19.21. In contrast, the DFE-BER example achieved a similar bit error rate of approximately 6.5 × 10⁻⁶. -7 with a higher slicer SNR of approximately 19.46. In contrast, the FFE example achieved a similar bit error rate of approximately 4.9 × 10⁻⁶. -7 with a higher slicer SNR of approximately 20.46. The bit error rate performance for the FFE with noise reduction thus achieved a similar bit error rate compared to the DFE-BER example and the FFE example at a slicer SNR that was approximately 1.25 dB lower with respect to the FFE example and approximately 0.25 dB lower with respect to the DFE-BER example.

[0148] The bit error rate performance for the FFE with noise suppression increased compared to the bit error rate performance for the DFE-BER example and the FFE example at other points along the lines shown. The FFE example with noise suppression achieved a bit error rate of approximately 1.4 × 10⁻⁶. -7with a slicer SNR of approximately 19.71. In contrast, the DFE-BER example achieved a similar bit error rate of approximately 1.4 × 10⁻⁶. -7 with a higher slicer SNR of approximately 19.96. In contrast, the FFE example achieved a similar bit error rate of approximately 1.0 × 10⁻⁶. -7 with a higher slicer SNR of approximately 20.96. The bit error rate performance for the FFE with noise reduction thus achieved a similar bit error rate compared to the DFE-BER example and the FFE example at a slicer SNR that was approximately 1.25 dB lower with respect to the FFE example and approximately 0.25 dB lower with respect to the DFE-BER example.

[0149] The FFE example with noise reduction also achieved higher BER performance at a fixed SNR. The FFE example with noise reduction achieved a bit error rate of approximately 7.2 × 10⁻⁶. -9 with a slicer SNR of approximately 20.46. In contrast, the DFE-BER example achieved a bit error rate of approximately 2.51 × 10⁻⁶.-8 with the same SNR of approximately 20.46. In contrast, the FFE example achieved a bit error rate of approximately 4.87 × 10⁻⁶. -7 with an SNR of approximately 20.46. Thus, the bit error rate performance for the FFE with noise reduction is higher compared to the DFE-BER example and the FFE example at the same slicer SNR. Furthermore, the FFE with noise reduction achieved a BER that was close to the theoretical limit (7.2 × 10⁻⁶). -9 for the FFE with noise reduction compared to 1.38 × 10 -9 (for the theoretical limit) at the same slicer SNR of 20.46.

[0150] The example of the FFE with noise reduction was within approximately 0.5 dB of the theoretical limit for the BER limit. The theoretical limit for a given SNR was: (i) approximately 4.58 × 10 -7 at an SNR of approximately 18.71; (ii) approximately 1.07 x 10 -7 at an SNR of approximately 19.21; (iii) approximately 1.38 × 10 -9 with an SNR of approximately 20.46.

[0151] Similar SNR points for the FFE example with noise reduction show that the FFE example with noise reduction is approximately 0.5 dB away from the theoretical limit for a given BER. With a theoretical BER of approximately 4.58 × 10 -7 With an SNR of approximately 18.71, the FFE with noise reduction has a similar BER of approximately 5.4 × 10 -7 with an SNR of approximately 19.21. With a theoretical BER of approximately 1.07 × 10 -7 With an SNR of approximately 19.21, the FFE with noise reduction has a similar BER of approximately 1.15 × 10 -7 with an SNR of approximately 19.71. With a theoretical BER of approximately 1.38 × 10 -9 With an SNR of approximately 20.46, the FFE with noise reduction has a similar BER of approximately 1 × 10 -9 with an SNR of approximately 20.96.

[0152] Furthermore, the DFE with noise reduction outperformed the DFE example by approximately 0.3 dB in channels with about 30% precursor noise. Thus, the performance improvement of the DFE with noise reduction compared to the DFE example occurred in various situations.

[0153] In some embodiments, the various components, modules, computers, and services described here can be implemented as objects or processes that run on a computer system (e.g., as separate threads). While some of the systems and procedures described here are generally described as being implemented in software (stored on and / or executed by hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and should be considered.

[0154] The terms used here and in particular in the attached claims (e.g. in the main parts of the attached claims) are generally to be understood as “open” terms (e.g. the term “including” is to be understood as “including but not limited to”, the term “with” as “with at least”, the term “comprises” as “comprises but not limited to”, etc.).

[0155] If a specific number of introductory claims is intended, this intention is expressly stated in the claim; if such a statement is omitted, no such intention exists. For clarity, the introductory phrases "at least one" and "one or more" may be used to introduce claim mentions in the following appended claims. However, the use of such phrases should not be interpreted as limiting a claim enumeration by the indefinite articles "one" or "a" to embodiments containing only such an enumeration, even if the same claim contains the introductory phrases "one or more" or "at least one" and indefinite articles such as "one" or "a" (e.g.,, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of certain articles used to introduce claims.

[0156] Even if a specific number of introduced claims is expressly stated, this statement is to be understood as meaning at least that stated number (e.g., the mere statement "two mentions" without further modifiers means at least two mentions or two or more mentions). In cases where a convention is used analogously to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc.", this construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is to be understood in this sense.

[0157] Furthermore, any disjunctive word or clause containing two or more alternative terms, whether in the description, claims, or drawings, should be understood to include the possibility of exactly one of the terms, one of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B".

[0158] Furthermore, the terms "first," "second," "third," etc., are not necessarily used here to denote a specific order or number of elements. Generally, the terms "first," "second," "third," etc., are used as generic terms to distinguish between different elements. Unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific order, these terms should not be understood as denoting a specific order. Similarly, unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific number of elements, these terms should not be understood as denoting a specific number of elements. For example, a first widget can be described as a first page, and a second widget as a second page.The use of the term "second page" in relation to the second widget can serve to distinguish this page of the second widget from the "first page" of the first widget, and is not intended to imply that the second widget has two pages.

[0159] All examples and conditional expressions cited herein are provided for educational purposes to facilitate the reader's understanding of the invention and the concepts to which the inventor has contributed in advancing the prior art, and are to be interpreted as not constituting a limitation to these specifically cited examples and conditions. Although embodiments of the present disclosure have been described in detail, it is to be assumed that the various modifications, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 362,887

[0001]

Claims

[1] A decision feedback equalizer device comprising: a feedforward equalizer configured to output a signal having a received symbol (Rx symbol); and a processing device configured to: to receive the Rx symbol from the feedforward equalizer; to calculate a slicer deferred decision region (SDD region) to identify an SDD; Applying the SSD to the Rx symbol if an Rx symbol value is in the SDD range; and Apply a hard slicer decision to the Rx symbol if the Rx symbol value is not in the SDD range. [2] The decision feedback equalizer device according to claim 1, wherein the processing device is further configured to: Identifying the SDD range by calculating a first SDD threshold offset of a first slicer threshold and a second SDD threshold offset of the first slicer threshold, wherein the SDD range is the range between the first SDD threshold offset and the second SDD threshold offset; and Writing the first SDD threshold offset and the second SDD threshold offset to a register of the processing device. [3] The decision feedback equalizer device according to claim 1, wherein the processing device is further configured to: Calculating a signal-to-noise ratio (SNR) of the signal; and Calculate a mapping between the SNR and the SDD range. [4] The decision feedback equalizer device according to claim 1, wherein the processing device is further configured to: Calculate an outer slicer error minimum bound; Calculating an outer slicer error maximum bound; and Writing the outer slicer error minimum limit and the outer slicer error maximum limit to a register of the processing device. [5] The decision feedback equalizer device according to claim 1, wherein the processing device is further configured to: Applying noise reduction to the slicer input; and Calculate an updated SDD range to apply an updated hard decision of the slicer after noise reduction is applied. [6] The decision feedback equalizer device according to claim 5, wherein the processing device is further configured to: Apply the updated hard decision by the slicer to the Rx symbol if the value of the Rx symbol is not in the updated SDD range. [7] The decision feedback equalizer device of claim 1, wherein the processing device is further configured to: calculate a slicer error when the hard decision is applied by the slicer to the Rx symbol. [8] The decision feedback equalizer device of claim 1, wherein the processing device is further configured to interrupt processing of the Rx symbol after the hard decision is applied to the Rx symbol by the slicer. [9] The decision feedback equalizer device according to claim 1, wherein the processing device is further configured to: Calculate the SDD range in one or more of the following ways: in real time or on demand. [10] A decision feedback equalizer (DFE) device comprising: a feedforward equalizer arranged to output a signal having a received (Rx) symbol; and a processing device configured to: Estimating a slicer error correlation based on a slicer error from a slicer input; Calculating one or more noise reduction slicer coefficients (NSS coefficients) based on the slicer error correlation; applying noise reduction to the slicer input based on the one or more NSS coefficients; and Estimating the Rx symbol after noise reduction. [11] The apparatus of claim 10, wherein the processing device is further configured to: Sending the one or more NSS coefficients to one or more infinite impulse response (IIR) filters; and Updating the one or more NSS coefficients based on the IIR outputs of the IIR filters. [12] The apparatus of claim 10, wherein the processing device is further configured to: Computing a slicer error estimator based on correlated noise from neighboring symbols in a proximity selected to reduce the slicer error in the slicer input; Applying noise reduction using the slicer error estimator. [13] The apparatus of claim 10, wherein the processing device is further configured to: Calculate a slicer error estimator based on a weighted combination of one or more of the following: Slicer errors consisting of an (n-1) symbol and an (n+1) symbol; or slicer errors consisting of an (n-2) symbol and an (n+2) symbol; and Applying noise reduction using the slicer error estimator. [14] The decision feedback equalizer apparatus of claim 10, wherein the slicer error correlation is one or more of cross-correlation or autocorrelation. [15] The decision feedback equalizer device according to claim 10, wherein the processing device is further configured to: Writing the one or more NSS coefficients into a register of the processing device. [16] The decision feedback equalizer device according to claim 10, wherein the processing device is further configured to: Estimating the one or more NSS coefficients based on a channel noise of an output signal; or Calculating the one or more NSS coefficients in one or more of the following methods: periodically, in real time, or on demand. [17] A computer-readable storage medium containing computer-executable instructions that, when executed by one or more processors, cause a decision feedback equalizer (DFE) to: Receiving an output signal comprising a received (Rx) symbol from a feedforward equalizer; Initializing noise reduction slicer (NSS) parameters, including one or more initial NSS coefficients and one or more initial slicer delayed decision (SDD) threshold offsets; Determining one or more updated NSS coefficients; Determining one or more updated SDD threshold offsets; and Updating the NSS parameters of a processing register based on the one or more updated NSS coefficients and the one or more updated SDD threshold offsets. [18] The computer-readable storage medium of claim 17, wherein the instructions, when executed by the one or more processors, cause the DFE to: Calculate an outer slicer error minimum bound; Calculating an outer slicer error maximum bound; and Writing the outer slicer error minimum and outer slicer error maximum limits to the processing register. [19] The computer-readable storage medium of claim 17, wherein the instructions, when executed by the one or more processors, cause the DFE to: Receiving an Rx symbol from a feedforward equalizer; Applying a hard slicer decision if an Rx symbol value is not within an SDD range; and Apply noise reduction based on the NSS coefficients to the Rx symbol when the Rx symbol value is in the SDD range. [20] The computer-readable storage medium of claim 17, wherein the instructions, when executed by the one or more processors, cause the DFE to: Estimating the one or more NSS coefficients based on a channel noise of the output signal; or Determining the one or more NSS coefficients based on a slicer error correlation.

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