Device and method for manufacturing a switching capacitor circuit

Abstract

Disclosed embodiments may include a device comprising: a first device layer comprising first switches, a second device layer comprising second switches, and a third device layer arranged between the first device layer and the second device layer. The third device layer comprises first capacitors. The first switches and the second switches are connected with the first capacitors to form a switching capacitor circuit. The switching capacitor circuit is configured to switch between at least two states in response to the switching of the first switches and the second switches.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and benefits from U.S. Provisional Patent Application No. 63 / 364,569, filed May 12, 2022, and U.S. Provisional Patent Application No. 63 / 364,674, filed May 13, 2022, the contents of which are incorporated herein by reference in their entirety for all purposes. TECHNICAL FIELD

[0002] The present disclosure generally relates to electronic devices. More particularly, the present disclosure relates to power converters. GENERAL STATE OF THE ART

[0003] Modern central processing units (CPUs) are evolving to deliver greater computing power, such as artificial intelligence (AI) processing and cloud computing applications, leading to an escalation of power demands from a power supply. As a result, power converters can occupy significant space in the power supply to meet the increasing power requirements of the CPUs. Accordingly, designing a compact and high-density power converter to reduce the required circuit area while meeting increasing power and space requirements has become a challenge in the field. OVERVIEW

[0004] Embodiments of the present disclosure provide a device. The device comprises: a first device layer comprising first switches, a second device layer comprising second switches, and a third device layer disposed between the first device layer and the second device layer. The third device layer comprises first capacitors. The first switches and the second switches are connected together with the first capacitors to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switches and the second switches.

[0005] Embodiments of the present disclosure provide a device. The device includes cells and a phase device cell. Each of the cells includes a capacitor and a first switch. The phase device cell includes second switches. The cells are stacked vertically above the phase device cell. The capacitor and the first switch in each cell are interconnected with the second switches to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch in each cell and the plurality of second switches.

[0006] Embodiments of the present disclosure provide a method of fabricating a switched capacitor circuit. The method includes: providing a first device layer; disposing a third device layer on the first device layer; interconnecting first capacitors within the third device layer to first switches within the first device layer; disposing a second device layer on the third device layer; and interconnecting second switches within the second device layer to the first capacitors.

[0007] Embodiments of the present disclosure provide a method of fabricating a switched capacitor circuit. The method includes: providing a phase device cell comprising a plurality of phase switches of a switched capacitor circuit; and vertically stacking cells above the phase device cell, each cell comprising a capacitor and a stack switch. The capacitor and the stack switch in each of the cells are interconnected with the phase switches.

[0008] Additional features and advantages of the disclosed embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments. The features and advantages of the disclosed embodiments may be realized and attained by means of the elements and combinations pointed out in the claims. BRIEF DESCRIPTION OF THE CHARACTERS

[0009] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a diagram illustrating an exemplary power converter according to some embodiments of the present disclosure. Fig. 2A-2B are diagrams illustrating example switched capacitor circuits according to some embodiments of the present disclosure. Fig. 3A-3D are diagrams illustrating example structures according to some embodiments of the present disclosure. Fig. 4A-4C are diagrams illustrating example passive device layers according to some embodiments of the present disclosure. Fig. 4D is a diagram illustrating an example active device layer with the molded interconnect substrate according to some embodiments of the present disclosure. Fig. 5 is a diagram illustrating an example switched capacitor circuit according to some embodiments of the present disclosure. Fig. 6A is a diagram illustrating an example structure according to some embodiments of the present disclosure. Fig. 6B is a diagram illustrating an example partial structure according to some embodiments of the present disclosure. Fig. 7 is a diagram illustrating an example structure according to some embodiments of the present disclosure. Fig. 8A and Fig. 8B are diagrams each illustrating example cells according to some embodiments of the present disclosure. Fig. Figure 9 is a diagram showing an example structure of the cell of Fig. 8A according to some embodiments of the present disclosure. Fig. 10 is a diagram illustrating another example cell according to some embodiments of the present disclosure. Fig. 11A illustrates a cross-sectional view of an exemplary portion of an LC network according to some embodiments of the present disclosure. Fig. 11B illustrates a cross-sectional view of an exemplary portion of another LC network according to some embodiments of the present disclosure. Fig. 12 is a diagram illustrating an exemplary power converter according to some embodiments of the present disclosure. Fig. 13 is a diagram illustrating an exemplary power converter package according to some embodiments of the present disclosure. Fig. 14 is a flowchart of a method of fabricating a switched capacitor circuit according to some embodiments of the present disclosure. Fig. 15 is a flowchart of another method of fabricating a switched capacitor circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure provides many different exemplary embodiments or examples for implementing various features of the provided subject matter. Specific simplified examples of components and arrangements are described below to illustrate the present disclosure. These are, of course, merely examples and are not intended to be limiting. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0011] The terms used in this specification generally have their ordinary meaning in the field and in the specific context in which each term is used. The use of examples in this specification, including examples of terms discussed herein, is merely illustrative and in no way limits the scope and meaning of the disclosure or any exemplary term. Likewise, the present disclosure is not limited to the various embodiments recited in this specification.

[0012] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be called a second element, and likewise, a second element may be called a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" encompasses any and all combinations of one or more of the associated recited items.

[0013] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used for ease of description to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees and in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0014] Throughout this document, the term "coupled" may also be referred to as "electrically coupled," and the term "connected" may be referred to as "electrically connected." "Coupled" and "connected" may also be used to indicate that two or more elements cooperate or interact with each other.

[0015] Various embodiments of the present disclosure are described with reference to embodiments in a specific context, namely a charge pump circuit. As used in this disclosure, the term "charge pump" refers to a switched capacitor network configured to convert an input voltage into an output voltage. Examples of such charge pumps include cascade multiplier, Dickson, ladder, series-parallel, Fibonacci, and doubler switched capacitor networks, all of which may be configured as a multi-phase or single-phase network.

[0016] However, the concepts in the disclosure may also apply to other types of power converters. Power converters that convert a higher input voltage power source to a lower output voltage level are generally known as buck or step-down converters because the converter "steps down" the input voltage. Power converters that convert a lower input voltage power source to a higher output voltage level are generally known as boost or step-up converters because the converter "steps up" the input voltage. In addition, some power converters, commonly known as "buck-boost converters," may be configured to convert the input voltage power source to the output voltage over a wide range, in that the output voltage can be either higher than or lower than the input voltage.In various embodiments, power converters can be bidirectional, namely a boost or buck converter, depending on how a power source is connected to the converter. In some embodiments, an AC-to-DC power converter can be constructed from a DC-to-DC power converter, for example, by first converting an AC input voltage to a DC voltage and then applying the DC voltage to a DC-to-DC power converter.

[0017] High-density, integrated switched-capacitor power converters may be desirable in applications including, but not limited to, data centers or portable electronic devices such as tablets, mobile phones, handheld computers, and IoT (Internet of Things) devices. In particular, modern high-performance microprocessors may contain billions of transistors switching at multiple gigahertz and / or consuming hundreds of amperes of current at relatively low voltages (e.g., less than 1.0 V in some situations). Furthermore, the power consumption characteristics of modern microprocessors increase with increasing processing power, posing challenges for on-board point-of-load (PoL)-type converters and / or data center power delivery devices. High-efficiency, high-density, and high-bandwidth PoL-type converters may be necessary to deliver hundreds of amperes of current (e.g.,in some situations more than 50.0 A) delivered at relatively low voltages (e.g., less than 1.0 V). Such PoL-type converters operate at relatively high voltage conversion ratios (e.g., more than 10:1) to support current and / or future high-performance microprocessors. In addition, due to increasing server power consumption, the data center industry may be transitioning from a 12 V bus architecture to a 48 V bus, potentially allowing improved overall efficiency and / or lower costs. By delivering power at, for example, 48 V, existing 48 V telecom power ecosystems can also be utilized. Power converters that may provide a lower voltage output (e.g., less than 1.0 V) regulated with relatively higher bandwidths while supplying power from a relatively high wide-range input voltage (e.g.,DC-DC converters (sourced from 40.0 V to 60.0 V) can be advantageous for supporting high-performance microprocessors and / or supporting telecommunications loads. Size, cost, and / or performance advantages provided through integration make it desirable to design modular and / or miniaturized DC-DC converters whose size and / or capabilities can be easily scaled for a range of applications that have different voltage and / or current requirements.

[0018] It will be Fig. 1 referred to. Fig. 1 is a diagram illustrating an exemplary power converter 100 according to some embodiments of the present disclosure. As shown in Fig. 1, the power converter 100 may include a device 110a that provides a power module. As used herein, a power module may refer to a physical unit or device that contains power and electronic components of a power converter circuit. The device 110a includes a switched capacitor circuit 112 (also known as a charge pump circuit) and a controller circuit 114 configured to control the operation of the switched capacitor circuit 112. In particular, the controller circuit 114 may include control circuitry, timing circuitry, protection circuitry, and gate drivers, among other components, configured to operate the switches, which in turn may change the electrical configuration of the capacitors of the switched capacitor circuit 112 between a first mode / state or a second mode / state.

[0019] In the embodiments of Fig. 1, the power converter 100 is configured to receive power from an input voltage source 102 having an input voltage V1 and supply power to an output load 104 having an output voltage V2. In some embodiments, the input voltage V1 may be higher than the output voltage V2. The switched capacitor circuit 112 is configured to convert the input voltage V1 to the output voltage V2. In some embodiments, multiple power modules may be configured in parallel within the power converter 100 to achieve a higher power rating based on low-cost and low-power rated devices. Accordingly, the modular design provides the flexibility and scalability for the power conversion circuits to meet different power system needs in various applications.

[0020] In various embodiments, controller circuitry 114 in device 110a may be an internal master controller or a slave controller that communicates with a master controller in the power system. In some other embodiments, switched capacitor circuitry 112 in device 110a may also be controlled by an external master controller coupled to device 110a. The controller circuit 114 may be fabricated on a semiconductor substrate, such as silicon, gallium nitride (GaN), silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-on-glass (SOG), silicon-on-quartz (SOQ), among other substrates, using semiconductor processing techniques compatible with complementary metal oxide semiconductor (CMOS) fabrication.The controller circuit 114 may be physically integrated with the switches in the switched capacitor circuit 112 on the same substrate (e.g., an on-chip configuration) or may be present as an off-chip component to operate the switches in the switched capacitor circuit 112.

[0021] As in Fig. 1, in some embodiments, input terminals V1p, V1n are connected to the input voltage source 102 to receive the input voltage V1, and output terminals V2p, V2n are connected to the output load 104 to output the output voltage V2. Furthermore, some input terminals of the controller circuit 114, such as a PG terminal for receiving a "power good" (PG) signal or a CLK terminal for receiving a clock signal, may be connected to other external circuitry or devices to receive the PG signal and the clock signal. Similarly, the I / O pins IOin and IOout of the device 110a may also be connected to corresponding circuitry or devices to facilitate circuit operations. In the present disclosure, the terms "node" and "terminal" may be used interchangeably.

[0022] Fig. 2A is a diagram illustrating an exemplary switched capacitor circuit 200A according to some embodiments of the present disclosure. As shown in Fig. 2A, in some embodiments, the switched capacitor circuit 200a may be a multiphase switched capacitor circuit, such as a two-phase variant of a Dickson charge pump, also known as a cascade multiplier. In some embodiments, the switched capacitor circuit 200a may be Fig. 2A for the switched capacitor circuit 112 in the device 110a of Fig. 1, but the present disclosure is not limited thereto. It is understood that in various embodiments, the switched capacitor circuit may also be a single-phase or multi-phase circuit and may be designed based on a desired conversion ratio. In the embodiments of Fig. 2A, a conversion ratio of 4:1 can be achieved. Generally, within a Dickson topology, different conversion ratios V1 / V2 (e.g., a 3:1 conversion ratio, a 5:1 conversion ratio, etc.) can be achieved using a different number of capacitors and a different number of switches. As the desired conversion ratio increases, the number of capacitors and switches in a power converter can also increase.

[0023] In the embodiments of Fig. 2A, the switched capacitor circuit 200a includes stack switches 210 for a first phase, stack switches 220 for a second phase, stack switches 230 shared by both phases, a first set of capacitors 240 including first capacitors C1A, C2A, and C3A associated with the first phase and connected to the stack switches 210, and a second set of capacitors 250 including second capacitors C1B, C2B, and C3B associated with the second phase and connected to the stack switches 220. The stack switches 210 associated with the first phase include switches S1A, S2A, S3A, and S4A. The stack switches 220 associated with the second phase include switches S1B, S2B, S3B, and S4B. The phase switches 230 include switches S5, S6, S7, and S8.Accordingly, switched capacitor circuit 200a provides a switching network that causes transitions between first and second states depending on which of these switches are open and which are closed. A first switch configuration causes the switched capacitor network to transition from the first state to the second state. A second switch configuration causes the switched capacitor network to transition from the second state to the first state. As a result, the switches cause the switched capacitor network to switch between these states, the capacitors 240 and 250 are charged or discharged in a charge pump cycle to perform power conversion, and the power is transferred from the supply to the load.

[0024] In the Fig. In the design shown in Figure 2A, the switching network comprises two switch chains, i.e., switches connected in series. Specifically, stack switches S1A, S2A, S3A, and S4A form one switch chain associated with the first phase, while stack switches S1B, S2B, S3B, and S4B form another switch chain associated with the second phase. Stack switches S1A, S2A, S3A, and S4A are each coupled to positive terminals of first capacitors C1A, C2A, and C3A, respectively, associated with the first phase via corresponding DC nodes. Similarly, stack switches S1B, S2B, S3B, and S4B are each coupled to positive terminals of second capacitors C1B, C2B, and C3B, respectively, associated with the second phase via corresponding DC nodes.

[0025] The phase switches S5 and S6 are connected to negative terminals of the first and second capacitors C1B, C2A, and C3B via a first phase node P1, while the phase switches S7 and S8 are connected to negative terminals of the first and second capacitors C1A, C2B, and C3A via a second phase node P2. In other words, the phase node P1 is coupled to negative terminals of a first subset of the first capacitors (e.g., capacitor C2A) and a first subset of the second capacitors (e.g., capacitors C1B and C3B), while the second phase node P2 is coupled to negative terminals of a second subset of the first capacitors (e.g., capacitors C1A and C3A) and a second subset of the second capacitors (e.g., capacitor C2B).

[0026] During operation, switches S1A, S2B, S3A, S4B, S6 and S7, which are located in Fig. 2A are marked as group 1, and the switches S1B, S2A, S3B, S4A, S5 and S8, which are in Fig. 2A are marked as group 2, are in complementary states. For example, in a first state, in response to commands from the controller circuit, switches S1A, S2B, S3A, S4B, S6, and S7 may be open, and switches S1B, S2A, S3B, S4A, S5, and S8 may be closed. In a second state following the first state, in response to commands from the controller circuit, switches S1A, S2B, S3A, S4B, S6, and S7 may be closed, and switches S1B, S2A, S3B, S4A, S5, and S8 may be open. Furthermore, a dead-time interval may exist between the first state and the second state. During the dead-time interval, all switches are open, ensuring a clean transition between the two switch states. It will be understood that the present disclosure is not limited to such a relationship or such a type of conversion circuit.In various embodiments, a buck or boost configuration may be applied for all possible charge pump ratios.

[0027] Fig. 2B is a diagram illustrating another exemplary switched capacitor circuit 200b according to some embodiments of the present disclosure. As shown in Fig. 2B, in some embodiments, the switched capacitor circuit 200b may further include a first set of inductors 260 including first inductors L1A, L2A, and L3A associated with the first phase and each connected between corresponding capacitors C1A, C2A, and C3A and the phase switches 230, and a second set of inductors 270 including second inductors L1B, L2B, and L3B associated with the second phase and each connected between corresponding capacitors C1B, C2B, and C3B and the phase switches 230.

[0028] As in Fig. 2B, various circuit topologies can be used in the present disclosure to form different types of power converters, such as a hybrid converter, a resonant switched-capacitor converter, or a multi-level power converter comprising transistors, capacitors, and one or more inductors as energy storage elements, or a converter with an LC filter coupled to the switched-capacitor network to promote adiabatic charging or discharging. In particular, hybrid converters, such as multi-level power converters or series-capacitor buck converters, also comprise a switched-capacitor circuit combined with different topologies.

[0029] Fig. 3A is a diagram illustrating an exemplary structure 300a according to some embodiments of the present disclosure. The structure 300a may be used to Fig. 2A to implement the switched capacitor circuit 200a. As shown in Fig. As shown in Figure 3A, a plurality of layers 310-350 are stacked vertically, i.e., along a Z-direction perpendicular to a substrate, one above the other in the structure 300a. In particular, the structure 300a includes active device layers 310, 330, and 350 and passive device layers 320 and 340. A stacked configuration may include a stack of alternating active device layers 310, 330, and 350 and passive device layers 320 and 340, but the present disclosure is not limited thereto.

[0030] In some embodiments, active device layers 310, 330, and 350 may include switching elements (e.g., switches 210, 220, and 230 of Fig. 2A) fabricated on a semiconductor substrate, such as, but not limited to, bulk silicon, doped silicon, GaN, GaAs, or SOI. The stack switches 210 and 220 and the phase switches 230 may be implemented by field-effect transistors, bipolar transistors, diodes, or other electrical devices. In some embodiments, one or more of the active device layers 310, 330, and 350 may further include control circuitry (e.g., controller circuit 114 of Fig. 1) fabricated on the same semiconductor substrate as the switching elements, such that the controller circuit 114 is physically integrated with the switches. In some embodiments, the passive device layers 320 and 340 may include passive devices that include capacitors (e.g., capacitors 240 and 250 of Fig. 2A) or resistors fabricated on a substrate. The substrate may include, but is not limited to, glass, quartz, silicon, SOI, SOS, SOG, SOQ, ceramic (aluminum oxide, aluminum nitride, sapphire), or composite, among other substrate materials.

[0031] In the structure 300a, the passive device layer 320 is arranged between the active device layer 310 and the active device layer 330. In particular, the passive device layer 320 is stacked above the active device layer 310, which may be a bottom layer. The active device layer 330 is stacked above the passive device layer 320. In some embodiments, the active device layer 310 includes first switches (e.g., stacked switches 210 in Fig. 2A, which are associated with the first phase). The passive device layer 320 includes first capacitors (e.g., capacitors 240 in Fig. 2A, which are associated with the first phase). The active device layer 330 includes second switches (e.g., phase switch 230 in Fig. 2A, which are shared by the first and second phases). By providing conductive features (e.g., contacts), the stack switches 210 in the active device layer 310 and the phase switches 230 in the active device layer 330 can be interconnected with the capacitors 240 in the passive device layer 320 to form the switched capacitor circuit for the Fig. 2A. As previously described in Fig. 2A, the switched capacitor circuit changes between at least two states in response to the switching of the stack switches 210 and the phase switches 230.

[0032] Similarly, the passive device layer 340 is disposed between the active device layer 330 and the active device layer 350 to form the switched capacitor circuit for the Fig. 2A. Thus, the phase switches 230 in the active device layer 330 can be split into two phases and connected together with the two capacitors 240 and 250. In particular, the passive device layer 340 is stacked over the active device layer 330, and the active device layer 350, which may be a top layer, is stacked over the passive device layer 340. As used herein, a "bottom" layer is the layer closest to a substrate, thus providing an electrical interface, and a "top" layer is the layer farthest from the substrate.

[0033] The active layer 350 comprises three switches (e.g. stack switch 220 in Fig. 2A, which are associated with the second phase). The passive layer 340 includes second capacitors (e.g., capacitors 250 in Fig. 2A, which are associated with the second phase). By providing conductive features (e.g., contacts), the stack switches 220 in the active device layer 350 and the phase switches 230 in the active device layer 330 can be interconnected with the capacitors 250 in the passive device layer 340 to form the switched capacitor circuit for the Fig. to form the second phase shown in Figure 2A.

[0034] Accordingly, the structure 300a may include a multi-phase switched capacitor circuit (e.g., the two-phase switched capacitor circuit 200a of Fig. 2A) that switches between at least two states in response to the switching of the stack switches 210, 220 and the phase switches 230 configured in different active device layers. In the present embodiments, the first switches in a lower layer (e.g., the active device layer 310) may be stack switches 210 associated with the first phase. The third switches in an upper layer (e.g., the active device layer 350) may be stack switches 220 associated with the second phase. The second switches in an intermediate layer (e.g., the active device layer 330) are phase switches 230 for both the first phase and the second phase to switch the first capacitors in one layer (e.g., the passive device layer 320) stacked below the intermediate layer and the second capacitors in another layer (e.g.,the passive device layer 340) stacked above the intermediate layer, with split phase nodes (e.g., phase nodes P1 and P2 in . Fig. 2A) of the switched capacitor circuit.

[0035] It should also be noted that in other embodiments, structure 300a may include multiple passive device layers stacked on a single active device layer, or multiple active device layers stacked on a single passive device layer, or a stack comprising at least one of a passive device layer, an interconnect layer, and an active device layer. For example, structure 300a may additionally include an interconnect layer to provide electrical connection between active device layers and passive device layers, or to provide electrical connection between devices in active device layers via metal lines.

[0036] Fig. 3B is a diagram illustrating an example structure 300b according to some embodiments of the present disclosure. Compared to the embodiments of Fig. 3A, as in Fig. As shown in Figure 3B, a controller layer 360, which includes the switching technology of the controller circuit 114, may be arranged as a lower layer, and the device layers 310-350 are stacked above the controller layer 360. The controller circuit 114 in the controller layer 360 may be coupled to switches in the device layers 310, 330, and 350 via contacts and vias to provide control signals for controlling the stack switches and the phase switches for each phase. Accordingly, the structure 300b may be used to Fig. 1 to implement the device 110a shown.

[0037] Fig. 3C is a diagram illustrating an example structure 300c according to some embodiments of the present disclosure. Compared to the embodiments of Fig. 3A and Fig. 3B, in structure 300c, device layers 310, 330, and 350 may each include corresponding control circuitry for controlling the switching of the stack switches or the phase switches in the same device layer. In some embodiments, the control circuitry in these device layers 310, 330, and 350 may communicate with each other via contacts and vias and collectively perform operations of controller circuit 114 to provide control signals for each phase. Accordingly, structure 300c may also be used to Fig. 1 to implement the device 110a shown.

[0038] Fig. 3D is a diagram illustrating an exemplary structure 300d according to some embodiments of the present disclosure. Compared to the embodiments of Fig. 3A- Fig. 3C, the structure 300d further comprises additional passive device layers 370 and 380. The passive device layers 370 and 380 are inductor layers that respectively comprise inductors 260 and 270 of Fig. 2B. For example, the passive device layer 370 may be stacked between the passive device layer 320 and the active device layer 330 such that inductors (e.g., the first inductors L1A, L2A, and L3A in Fig. 2B) in the passive device layer 370 between corresponding capacitors (e.g., the first capacitors C1A, C2A and C3A in Fig. 2B) in the passive device layer 320 and the phase switches 230 in the active device layer 330.

[0039] Similarly, the passive device layer 380 may be stacked between the passive device layer 340 and the active device layer 330 such that inductors (e.g., the second inductors L1B, L2B, and L3B in Fig. 2B) in the passive device layer 380 between corresponding capacitors (e.g., the second capacitors C1B, C2B and C3B in Fig. 2B) in the passive device layer 340 and the phase switches 230 in the active device layer 330. Accordingly, the structure 300d can also be used to Fig. 2B. It should be noted that in other alternative embodiments, the passive device layer 370 may be stacked between the passive device layer 320 and the active device layer 310, and the passive device layer 380 may be stacked between the passive device layer 340 and the active device layer 350. The structure 300d in Fig. 3D is an example and is not intended to limit the present disclosure.

[0040] In various embodiments, the passive device layers 320 and 340 may be implemented in different ways to provide vertical capacitors connecting between the phase switches and stack switches, which may reduce the routing distance and reduce parasitic inductance in the circuit. Fig. 4A-4C are diagrams illustrating example passive device layers 400a, 400b, and 400c according to some embodiments of the present disclosure. In some embodiments, the capacitors C1, C2, C3 through Cn embedded in each passive device layer 400a, 400b, or 400c may be multi-layer ceramic capacitors (MLCCs). MLCCs may store electrical energy in multiple ceramic layers having a high dielectric constant. For example, barium titanate (BaTiO3) may be selected as the dielectric. In the structure of an MLCC, numerous metal electrodes and ceramic layers are alternately stacked within the capacitor. The internal electrodes are arranged in an interdigitated pattern with the adjacent electrodes extending to the opposite terminals, while the non-adjacent electrodes extend to the same terminal.At each terminal, the exposed electrode edges are electrically connected by a metallized coating applied to the outer surfaces, known as a termination. MLCCs offer high capacitance, small size, low cost, high reliability, and excellent high-frequency characteristics, making them widely used in a variety of applications.

[0041] As in Fig. 4A, in some embodiments, positive terminals of capacitors C1, C2, C3 through Cn are coupled to corresponding contacts located on a first surface 402 of passive device layer 400a, and negative terminals of capacitors C1, C2, C3 through Cn are coupled to corresponding contacts located on a second surface 404 of passive device layer 400a opposite first surface 402. Passive device layer 400a is stacked with the layer having stack switches over first surface 402 and with the layer having phase switches over second surface 404. Thus, the stack switches may be coupled to positive terminals of capacitors C1, C2, C3 through Cn via DC nodes, and the phase switches may be coupled to negative terminals of capacitors C1, C2, C3 through Cn via corresponding phase nodes.It will be appreciated that in different arrangements, the stack switches may be stacked below or above the passive device layer 400a, such that the first surface 402 may be either the top surface or the bottom surface. In the embodiments of FIG. Fig. 4A, the multilayer ceramic capacitors C1, C2, C3 to Cn are embedded in the substrate such that the long edge of each multilayer ceramic capacitor C1, C2, C3 to Cn is substantially perpendicular to the upper surface or the lower surface of the passive device layer 400a, but the present disclosure is not limited thereto.

[0042] As in the passive device layer 400b in Fig. 4B, the multilayer ceramic capacitors C1, C2, C3 to Cn may also be embedded in the substrate such that the long edge of each multilayer ceramic capacitor C1, C2, C3 to Cn is substantially parallel to the top surface or the bottom surface of the passive device layer 400b. Similar to the embodiments of Fig. 4A, positive terminals of the capacitors C1, C2, C3 to Cn are coupled to corresponding contacts located on the first surface 402, while negative terminals of the capacitors C1, C2, C3 to Cn are coupled to corresponding contacts located on the second surface 404 opposite the first surface 402. As in the passive device layer 400c in Fig. 4C, in some other embodiments, the multilayer ceramic capacitors C1, C2, C3 to Cn may also be vertically embedded in molded composite material 406, such as a molded plastic or other electrical insulator material, to form the passive device layer 400c. It will be understood that the passive device layer may be realized by other approaches, and the Fig. The embodiments illustrated in Figures 4A-4C are merely examples and are not intended to limit the present disclosure.

[0043] In some embodiments, the active device layers 310, 330 and 350 and / or the passive device layers 320 and 340 in the structure 300a of Fig. 3A may also be formed using a molded interconnect substrate (MIS), and one or more of the stacking switches 210, 220, the phase switches 230, and the capacitors 240, 250 may be embedded in the molded interconnect substrate (MIS). The molded interconnect substrate is a packaging technology built upon a lead frame substrate that supports single-die or multi-die configurations.

[0044] Fig. 4D is a diagram illustrating an exemplary active device layer 400d with the molded interconnect substrate according to some embodiments of the present disclosure. In the active device layer 400d, one or more IC dies 410 including active components (e.g., switches) are attached to a lead frame 420, with a thermal interface material 430 disposed between the IC dies 410 and the lead frame 420. Conductive legs (e.g., Cu legs) 440 and 450 are arranged to connect the IC die(s) 410 or the lead frame 420 to an MIS 460 with a pre-molded structure. The MIS 460 may include one or more layers preconfigured with copper plating or interconnects to provide electrical connections.

[0045] Fig. 5 is a diagram illustrating an exemplary switched capacitor circuit 500 according to some embodiments of the present disclosure. As shown in Fig. 5, in some embodiments, the switched capacitor circuit 500 includes a plurality of single-phase switched capacitor networks 510, 520, and 530 connected in parallel for three different phases. For example, as shown in Fig. 5, switched capacitor network 510 may be implemented by a 4:1 Dickson switched capacitor network including switches S1A-S8A and capacitors C1A, C2A, and C3A. Similarly, switched capacitor networks 520 and 530 may also be implemented by 4:1 Dickson switched capacitor networks including switches S1B-S8B, S1C-S8C, and capacitors C1B-C3B, C1C-C3C, respectively. Switches S1A-S8A, S1B-S8B, and S1C-S8C may be controlled in response to commands from a controller circuit 540 coupled to switched capacitor networks 510, 520, and 530.

[0046] The switched capacitor network 510 includes stack switches 512 and phase switches 514 for a first phase and capacitors 516 associated with the first phase. The stack switches 512 associated with the first phase include switches S1A, S2A, S3A, and S4A, which form a switch chain. The phase switches 514 include switches S5A, S6A, S7A, and S8A. In the Fig. In the design shown in Figure 5, stack switches S1A, S2A, S3A, and S4A are each coupled to positive terminals of capacitors C1A, C2A, and C3A via corresponding DC nodes. Phase switches S5A and S6A are connected to negative terminals of capacitors C1A and C3A via one phase node, while phase switches S7A and S8A are connected to the negative terminal of capacitor C2A via another phase node. Similarly, switched capacitor networks 520 and 530 include stack switches 522, 532 and phase switches 524, 534 for the second phase or the third phase, respectively, and capacitors 526, 536 associated with the second phase or the third phase. Arrangements of circuit components in the switched capacitor networks 520 and 530 are similar to those in the switched capacitor network 510, and therefore further details are omitted for brevity. Compared to the embodiments of Fig. 2A, in switched capacitor circuit 500, switched capacitor networks 510, 520, and 530 do not share phase nodes and phase switches. Capacitors 516, 526, and 536 are coupled to respective sets of phase switches 514, 524, and 534 for different phases.

[0047] As with the embodiments of Fig. 2A, each of the switched capacitor networks 510, 520, and 530 causes transitions between first and second states in response to commands from the controller circuit 540, depending on which of these switches are open and which are closed. Accordingly, a charge pumping operation occurs because the switches cause the switched capacitor network to transition between these states. In some embodiments, the controller circuit 540 may output appropriate control signals to cause the switched capacitor networks 510, 520, and 530 to operate 120 degrees out of phase with each other. Fig. The topologies shown in Figure 5 can be further modified to combine N phases in parallel and operate them 360 / N degrees out of phase with each other, where N is any integer greater than 1. Through such arrangements, the switched capacitor circuit 500 provides reduced output voltage ripple and increased output power handling capability.

[0048] Fig. 6A is a diagram illustrating an exemplary structure 600 according to some embodiments of the present disclosure. The structure 600 may be used to implement the Fig. 5 shown switched capacitor circuit 500. As in Fig. As shown in Figure 6A, the structure 600 includes substructures 610, 620, 630, and 640 stacked vertically along the Z-direction perpendicular to the substrate and one above the other.

[0049] Each of the substructures 610, 620 and 630 is connected to a corresponding phase of the switched capacitor circuit 500 of Fig. 5. For example, substructure 610 corresponds to switched capacitor network 510 for the first phase, substructure 620 corresponds to switched capacitor network 520 for the second phase, and substructure 630 corresponds to switched capacitor network 530 for the third phase. Substructure 640, which may be a lower layer among substructures 610, 620, and 630, includes controller circuitry 540.

[0050] As in Fig. 6A, each of the substructures 610, 620, and 630 includes the first device layer (e.g., layers 612, 622, or 632) including the stacked switches (e.g., stacked switches 512, 522, or 524), the second device layer (e.g., layers 614, 624, or 634) including the phase switches (e.g., phase switches 514, 524, or 534), and the third device layer (e.g., layers 616, 626, or 636) including the capacitors (e.g., capacitors 516, 526, or 536) stacked between the first and second device layers. By providing contacts and contact holes in each layer of the structure 600, the substructures 610, 620 and 630 can be stacked on top of each other to couple the switched capacitor networks 510, 520 and 530 in parallel, thus forming the switched capacitor circuit 500 in Fig. 5. Furthermore, the controller circuit 540 in the lower layer can be coupled to switches in the substructures 610, 620, and 630 via these contacts and vias to provide control signals for controlling the stack switches and the phase switches for each phase.

[0051] Fig. 6B is a diagram illustrating an exemplary substructure 610 according to some embodiments of the present disclosure. It will be understood that substructures 620 and 630 may also include the same or similar features of substructure 610 of Fig. 6B may include. In Fig. 6B, the passive device layer 616 is stacked over the active device layer 614, and the active device layer 612 is stacked over the passive device layer 616. The substructure 610 provides lower contacts 611 on a lower surface and upper contacts 615 on an upper surface opposite the lower surface for electrical connections to other substructures stacked above or below the substructure 610. One or more vias 613 may be formed and extend, in elevation, through the active device layer 612, the passive device layer 616, and the active device layer 614. As shown in Fig. 6B, vias 613 may be configured to connect corresponding lower contacts 611 and upper contacts 615.

[0052] With the Fig. 3A or Fig. With the stacked structures shown in Figure 6A, a switched-capacitor power converter can be formed with its stack switches, capacitors, and phase switches stacked vertically in different layers. Accordingly, the horizontal surface area required for the power converter can be reduced. Fig. 3A and Fig. The structures 300a and 600 disclosed in Figure 6A are suitable for various devices or systems, such as power converters used in modern data centers, but the present disclosure is not limited thereto. The disclosed embodiments may also be used in other power applications or scenarios where package height is less critical.

[0053] Fig. Figure 7 is a diagram illustrating an exemplary structure 700 according to some embodiments of the present disclosure. The structure 700 may be used to implement a single-phase switched capacitor network. As shown in Fig. 7, the structure 700 comprises two sets of cells 710 and 720 and a phase device cell 730. The cells 710 and 720 are stacked vertically one above the other and above the phase device cell 730 along the Z-direction perpendicular to the substrate. As shown in Fig. 7, each cell 710 or 720 includes upper contacts located on an upper surface and lower contacts located on a lower surface for connecting to contacts from another cell stacked above or below the cell.

[0054] Each of cells 710 and 720 includes at least one capacitor (e.g., one of capacitors C1-C5) and a first switch (e.g., one of switches S1-S5) coupled to the positive terminal of the corresponding capacitor. The first switches S1-S5 in the stacked cells 710 and 720 are coupled in series to the stack switches of the single-phase switched-capacitor network. The phase device cell 730 includes the second switches S6, S7, S8, and S9, which are the phase switches of the single-phase switched-capacitor network and are coupled to negative terminals of corresponding capacitors C1-C5. By stacking cells 710 and 720 onto the phase device cell 730, the capacitor C1-C5 and the first switch S1-S5 in each cell 710 or 720 are connected together with the second switches S6, S7, S8, and S9 to form the single-phase switched capacitor network. As in the previous embodiments, the Fig. 7 may be configured to switch between at least two states in response to the switching of the first switch S1-S5 in each cell 710 or 720 and the second switches S6-S9.

[0055] In structure 700, cells 710 and 720 are alternately stacked to couple capacitors C1-C5 to corresponding phase nodes 732 or 734. Specifically, in each cell 710, the capacitor (e.g., capacitors C1, C3, or C5) is coupled to a first subset of the second switches (e.g., switches S8 and S9) at a first phase node 732 of the switched capacitor circuit, and in each cell 720, the capacitor (e.g., capacitors C2 or C4) is coupled to a second subset of the second switches (e.g., switches S6 and S7) at a first phase node 734 of the switched capacitor circuit.

[0056] As with the previous embodiments, in the switch chain comprising first switches S1-S5, adjacent switches are in complementary states. In other words, during operation in a first state, in response to commands from the controller circuit, the first switch in each cell 710, e.g., switches S1, S3, and S5, may be turned on, and the first switch in each cell 720, e.g., switches S2 and S4, may be turned off. In a second state following the first state, in response to commands from the controller circuit, the first switch in each cell 710 may be turned off, and the first switch in each cell 720 may be turned on.

[0057] In some embodiments, each of the first switches S1-S5 may be a field-effect transistor having a source terminal and a drain terminal coupled to one of the upper contacts and one of the lower contacts, respectively. Each of the capacitors C1-C5 is coupled between the source terminal of the corresponding field-effect transistor and the first phase node 732 or the second phase node 734 of the switched capacitor circuit via corresponding contacts and / or vias in the cells 710 and 720.

[0058] Fig. 8A and Fig. 8B are diagrams illustrating example cells 710 and 720, respectively, according to some embodiments of the present disclosure. As in Fig. 8A and Fig. As shown in Figure 8B, each of the cells 710 and 720 includes upper contacts T1-T5 located on an upper surface and lower contacts B1-B5 located on a lower surface. The upper contacts T1, T2, T4, and T5 are coupled to contacts B1, B2, B4, and B5, respectively, to provide electrical connections among the stacked cells 710 and 720.

[0059] In cells 710 and 720, the source terminal S of transistor 712 or 722 is coupled to the lower contact B3 and the drain terminal D of transistor 712 or 722 is coupled to the upper contact T3. For cell 710 in Fig. 8A, the gate terminal G of transistor 712 is coupled to the upper contact T1 and the lower contact B1. For cell 720 in Fig. 8B, the gate terminal G of transistor 722 is coupled to the upper contact T2 and the lower contact B2. Accordingly, when cells 710 and 720 are alternately stacked, the gate terminals of transistor 712 in cell 710 are electrically coupled to receive a first control signal, while the gate terminals of transistor 722 in cell 720 are electrically coupled to receive a second control signal. Therefore, the adjacent switches in the switch chain can operate in complementary states.

[0060] For cell 710 in Fig. 8A, the capacitor 714 is coupled between the source terminal S of the transistor 712 and a node 716. The node 716 is coupled to the upper contact T5 and the lower contact B5, which are connected to a first phase node (e.g., phase node 732 in Fig. 7) of the switched capacitor circuit will be electrically coupled via the electrical connections among the stacked cells 710 and 720. However, for the cell 720 in Fig. 8B, the capacitor 724 is coupled between the source terminal S of the transistor 722 and a node 726. The node 726 is coupled to the upper contact T4 and the lower contact B4, which are connected to a second phase node (e.g., phase node 734 in Fig. 7) the switched capacitor circuit will be electrically coupled via the electrical connections among the stacked cells 710 and 720. Accordingly, when the cells 710 and 720 are alternately stacked, the capacitor 714 and the capacitor 724 in adjacent cells are coupled to different subsets of the phase switches, thereby Fig. 7 shown single-phase switched capacitor network is formed.

[0061] Fig. Fig. 9 is a diagram showing an exemplary structure of the cell 710 of Fig. 8A according to some embodiments of the present disclosure. As in Fig. 9, the upper contacts T1-T5 and the lower contacts B1-B5 can be placed at corresponding locations on opposite surfaces of the cell 710, such that the upper contacts T1-T5 can be connected to corresponding contacts of the adjacent cell 720 stacked above the cell 710, and the lower contacts B1-B5 can be connected to corresponding contacts of the adjacent cell 720 stacked below the cell 710. The transistor 712 and the capacitor 714 within the cell 710 can be configured to optimize electrical connections among the components, the upper contacts T1-T5, and the lower contacts B1-B5. A similar structure can be used for the cell 720 of Fig. 8B, which is not repeated here for the sake of brevity.

[0062] Fig. 10 is a diagram illustrating another exemplary cell 1000 according to some embodiments of the present disclosure. As in Fig. As shown in Figure 10, the transistors 712 and 722 and the capacitors 714 and 724, which operate in complementary states, can also be integrated into a single cell to form the switched capacitor network. Accordingly, the Fig. 7 can be formed by stacking one or more cells 1000, as an alternative to a pair of a cell 710 and a cell 720. In Fig. 10, cell 1000 includes transistors 712 and 722 and capacitors 714 and 724. Similar to the embodiments of Fig. 8A and Fig. 8B, capacitor 714 is coupled between the source terminal S1 of transistor 712 and node 716, which is coupled to the upper contact T5 and the lower contact B5, while capacitor 724 is coupled between the source terminal S2 of transistor 722 and node 726, which is coupled to the upper contact T4 and the lower contact B4.

[0063] Transistors 712 and 722 are coupled in series between the upper contact T3 and the lower contact B3. Specifically, the drain terminal D1 of transistor 712 is coupled to the upper contact T3, the drain terminal D2 of transistor 722 is coupled to the source terminal S1 of transistor 712, and the source terminal S2 of transistor 722 is coupled to the lower contact B3. The gate terminal G1 of transistor 712 is coupled to the upper contact T1 and the lower contact B1, while the gate terminal G2 of transistor 722 is coupled to the upper contact T2 and the lower contact B2.

[0064] It should be noted that while cell 1000 includes two stacked switches (e.g., transistors 712 and 722) and two capacitors 714 and 724 in a single cell, the present disclosure is not limited thereto. In other embodiments, a cell may include a number of stacked switches coupled in series and corresponding capacitors coupled to the stacked switches. In other words, in some embodiments, at least one of the stacked cells may include multiple capacitors and multiple stacked switches coupled together with the phase switches to form the switched capacitor circuit.

[0065] In the embodiments of Fig. 7-10, by stacking multiple stackable cells 710, 720 and / or 1000 above the phase device cell 730, a switched capacitor power converter with its electrical components stacked vertically can be formed. As in the embodiments of Fig. 2A-6D, the horizontal surface area required for the power converter can be reduced, which may be desirable for various power applications or scenarios where package height is less critical. Furthermore, the conversion ratio of the switched capacitor network can be easily modified by stacking a different number of cells, providing modularity and flexibility for the power converter design to meet different power requirements in diverse applications at low cost.

[0066] It will be appreciated that the structures 300a-300d, 600, and 700 in the present disclosure may also be modified and applied to other types of power converters with different implementations, arrangements, and / or topologies. For example, the structures disclosed herein may form a resonant switched-capacitor converter or a multi-level power converter comprising transistors, capacitors, and one or more inductors as energy storage elements, or a converter with an LC filter coupled to the switched-capacitor network to promote adiabatic charging or discharging.

[0067] In such implementations, capacitors and inductors can be placed in the same passive device layer or in separate passive device layers. Again referring to Fig. 3A, in some embodiments, the passive device layers 320 or 340 may further include one or more inductors coupled to one or more of the capacitors 240 or 250 in the same layer. Alternatively, as in Fig. 3D, the structure 300d may include one or more additional inductor layers, i.e., passive device layers 370 and 380, stacked vertically adjacent to the passive device layers 320 or 340. The passive device layers 370 and 380 include one or more inductors coupled to one or more of the capacitors 240 or 250 in the passive device layers 320 or 340.

[0068] It will be Fig. 11A and Fig. 11B, which illustrate one or more additional inductor layers stacked vertically adjacent to the passive device layer comprising the capacitors. Fig. 11A illustrates a cross-sectional view of an exemplary portion of an LC network 1100a according to some embodiments of the present disclosure. As shown in Fig. As shown in Figure 11A, the LC network 1100a may include a capacitor layer 1110 and an inductor layer 1120, with contacts and / or vias configured to enable electrical series connection of the inductor layer 1120 to the capacitor layer 1110. The LC network 1100a may be fabricated by bonding a bottom surface of the capacitor layer 1110 to a top surface of the inductor layer 1120. In some embodiments, the bonding may include a hybrid bond such that a metal-to-metal and oxide-to-oxide bond is formed between the bonding surfaces of the capacitor layer 1110 and the inductor layer 1120.

[0069] Fig. 11B illustrates a cross-sectional view of an exemplary portion of another LC network 1100b according to some embodiments of the present disclosure. In Fig. 11B, the LC network 1100b may include two inductor layers 1120 and 1130 and a capacitor layer 650 coupled between the two inductor layers 1120 and 1130, with contacts and / or vias configured to enable electrical series connection. For example, the LC network 1100b may be used in resonant switched-capacitor converters. It will be appreciated that the relative arrangement of the Fig. 11A and Fig. 11B, the inductor layers 1120 and 1130 and the capacitor layer 1110 are non-limiting examples, and other arrangements are also possible. In various embodiments, the LC network may include one or more inductor layers, one or more capacitor layers, one or more vias, and electrical contact pads, as desired.

[0070] It will be Fig. 12 referred to. Fig. 12 is a diagram illustrating an exemplary power converter 1200 according to some embodiments of the present disclosure. Compared to the embodiments of Fig. 1, the power converter 1200 may include a plurality of devices 110a, 110b, and 110c coupled together, and each device provides a power module. In a preferred embodiment, a power module may include one or more of the devices 110a, 110b, and 110c. It should be noted that the number of devices 110a, 110b, and 110c may vary in different embodiments, and Fig. 12 is a simplified example and is not intended to limit the present disclosure. In the embodiments of Fig. 12, the power converter 1200 can achieve higher power ratings based on low-cost and low-power devices by using multiple power modules (e.g., including multiple devices 110a, 110b, and 110c) with input terminals V1p and V1n of the switched capacitor circuits connected together and output terminals V2p and V2n of the switched capacitor circuits connected together in the power converter 1200. Accordingly, the modular design provides the flexibility and scalability for the power conversion circuits to meet different power system needs in various applications.

[0071] In some embodiments, devices 110a, 110b, and 110c may each include a corresponding switched capacitor circuit 112 and an individual controller circuit 114, but the present disclosure is not limited thereto. In some embodiments, the switched capacitor circuits 112 in devices 110a, 110b, and 110c may be controlled by an external master controller coupled to devices 110a, 110b, and 110c. In some other embodiments, power converter 1200 may include an internal master controller (e.g., controller circuit 114 in device 110a) and one or more slave controllers (e.g., controller circuit 114 in devices 110b and 110c) configured to communicate with the internal master controller.Furthermore, one or more of the power modules in the power converter 100 may support the Power Management Bus (PMBUS) communication protocol, while remaining power modules are “lightweight” power modules having a simpler design without PMBUS and / or telemetry circuitry.

[0072] As in Fig. As shown in Figure 12, in some embodiments, input terminals V1p, V1n and output terminals V2p, V2n of the switched capacitor circuit 112 in each device 110a, 110b, and 110c are coupled in parallel. Furthermore, some input terminals of the controller circuit 114, such as the PG terminal or the CLK terminal, may also be coupled in parallel so that the devices 110a, 110b, and 110c can receive the same PG signal and the same clock signal. Some other terminals, such as the I / O pins IOin and IOout of the devices 110a, 110b, and 110c, may be coupled in series to facilitate circuit operations.

[0073] In various embodiments of the present disclosures, for applications where circuit size is critical, devices 110a, 110b, and 110c, including charge pump circuits, may be stacked vertically in a package to provide higher power density for power converter 1200. For example, central processing units (CPUs) in laptops or in data centers may provide sufficient height margins (e.g., approximately 2-9 mm or approximately 7-22 mm) to allow low-profile charge pump power modules to be stacked vertically in a Z-direction. Therefore, as the package height increases, the area occupied by the charge pump circuitry on the horizontal surface (i.e., the XY plane) may be reduced, and accordingly, the footprint may be saved.

[0074] Compared to the charge pump power module in the present embodiments, a buck converter power module typically includes a relatively high-profile inductor, such as a wire-wound inductor. In particular, the inductor is usually the largest and tallest component in the traditional module and the bottleneck for reducing the module height in the Z direction. Traditional buck converters would not stack due to the height of the large inductor, and such vertically stacked buck converter power modules would exceed the height limitation and are therefore undesirable for power supply applications for CPUs in laptops or data centers. In contrast, with the switched-capacitor architecture in the present embodiments, low-profile charge pump power modules (e.g., approximately 1 mm) are suitable for stacking in various power supply applications.

[0075] Fig. 13 is a diagram illustrating an exemplary power converter package 1300 according to some embodiments of the present disclosure. The power converter package 1300 includes multiple integrated circuit packages (e.g., devices 110a, 110b, and 110c) stacked vertically to increase power density without increasing the overall package area. As shown in Fig. 13, the device 110a at the lower layer may be a lower package providing lower bonding contacts 1312a on one surface (e.g., a lower surface) and upper bonding contacts 1314a on another surface (e.g., an upper surface) opposite the surface having lower bonding contacts 1312a. One or more vias 1316a of the device 110a connect a corresponding lower bonding contact(s) 1312a and a corresponding upper bonding contact(s) 1314a.

[0076] Similarly, the device 110b at an intermediate layer may be an intermediate package providing lower bonding contacts 1312b on a lower surface and upper bonding contacts 1314b on an upper surface opposite the lower surface, with one or more vias 1316b connecting a corresponding lower bonding contact(s) 1312b and a corresponding upper bonding contact(s) 1314b. The device 110c at an upper layer may be an upper package providing lower bonding contacts 1312c on a lower surface. Alternatively, in the embodiments of Fig. 13, lower bonding contacts on one surface of the package provide connections to a substrate or an adjacent lower package stacked below the package, and upper bonding contacts on an opposite surface provide connections to an adjacent upper package stacked above the package.

[0077] It should be noted that, in some embodiments, the upper package may be a stackable package or a non-stackable package. In other words, while the device 110c at the upper layer may provide upper bonding contacts on the upper surface, in other embodiments, the device 110c may only provide lower bonding contacts 1312c. It should also be noted that, in various embodiments, depending on the application, the orientation of the non-stackable package and the stackable package(s) in the power converter package 1300 may be varied.

[0078] As in Fig. As shown in Figure 13, devices 110a, 110b, and 110c are stacked on top of each other via bonds 1320a, 1320b, and 1320c, which may be electrical bonds (e.g., bumps), thermocompression bonds, or hybrid bonds between two adjacent packages. In some embodiments, bonds 1320a, 1320b, and 1320c may include electrically conductive bumps that conduct both heat and electrical signals, and thermally conductive bumps that serve only for heat transfer. In particular, bonds 1320a are configured to bond bottom bonding contacts 1312a in the lower layer to a substrate, such as a motherboard (printed circuit board (PCB) 1310. The bonds 1320b and 1320c are configured to bond the upper bonding contacts placed on the upper surface of the package in one layer to corresponding lower bonding contacts placed on the lower surface of another package in an adjacent layer.Bonds 1320a, 1320b, and 1320c and vias 1316a and 1316b provide electrical connections between stacked devices 110a, 110b, and 110c. Accordingly, stacked devices 110a, 110b, and 110c may be formed in . Fig. 13 the power converter 1200 in Fig. 12, in which the switched capacitor circuits in different modules are electrically connected in parallel.

[0079] As discussed above, one or more controller circuits configured to control the operation of the switched capacitor circuits may be implemented in devices 110a, 110b, and 110c. In some embodiments, a master controller circuit may be implemented in the lower package (e.g., device 110a), and slave controller circuit(s) may be implemented in one or more intermediate packages (e.g., device 110b) or in the upper package (e.g., device 110c). The slave controller circuit(s) may be electrically connected to the master controller circuit implemented in the lower package via corresponding lower bonding contacts 1312a-1312c and upper bonding contacts 1314a and 1314b of the integrated circuit packages.

[0080] Fig. 14 is a flowchart of a method 1400 for fabricating a switched capacitor circuit according to some embodiments of the present disclosure. It should be understood that additional operations may be performed before, during, and / or after the Fig. 14, and that some other processes may only be briefly described herein. The method 1400 may be performed to form the structure 300a of Fig. 3A for manufacturing integrated circuits for power converter applications, such as the power converter 100 in Fig. 1 and the power converter 1200 from Fig. 12. Method 1400 includes operations 1410-1490.

[0081] In operation 1410, a first device layer (e.g., active device layer 310 in Fig. 3A). In operation 1420, a third device layer (e.g., passive device layer 320 in Fig. 3A) are arranged on the first device layer. In operation 1430, first capacitors (e.g., capacitors 240 in Fig. 3A) within the third device layer with first switches (e.g. stack switch 210 in Fig. 3A) are interconnected within the first device layer. Lower contacts of the third device layer can be connected to corresponding upper contacts of the first device layer to couple positive terminals of the first capacitors to corresponding first switches.

[0082] In operation 1440, a third device layer (e.g., active device layer 330 in Fig. 3A) are arranged on the third device layer. In operation 1450, second switches (e.g., phase switch 230 in Fig. 3A) are interconnected within the second device layer with the first capacitors. Lower contacts of the second device layer can be connected to corresponding upper contacts of the third device layer to couple negative terminals of the first capacitors to corresponding second switches.

[0083] In operation 1460, a fifth device layer (e.g., passive device layer 340 in Fig. 3A) are arranged on the second device layer. In operation 1470, second capacitors (e.g., capacitors 250 in Fig. 3A) are interconnected within the fifth device layer with the second switches. Lower contacts of the fifth device layer can be connected to corresponding upper contacts of the second device layer to couple negative terminals of the second capacitors to corresponding second switches.

[0084] In operation 1480, a fourth device layer (e.g., active device layer 350 in Fig. 3A) are arranged on the fifth device layer. In operation 1490, third switches (e.g., stack switch 220 in Fig. 3A) are interconnected within the fourth device layer with the second capacitors. Lower contacts of the fourth device layer can be connected to corresponding upper contacts of the fifth device layer to couple positive terminals of the second capacitors to corresponding third switches.

[0085] Optionally, in some embodiments, in operation 1420 or 1460, one or more inductor layers (e.g., inductor layers 1120 and / or 1130 in Fig. 11A and Fig. 11B) vertically to the passive device layer (e.g. capacitor layer 1110 in Fig. 11A and Fig. 11B) may be stacked adjacently, before or after stacking the third device layer. The inductor layer may include one or more inductors coupled to one or more first capacitors in the passive device layer to form an LC network.

[0086] As discussed above, in method 1400, the first and fifth device layers may be formed by embedding multilayer ceramic capacitors vertically into a substrate, with one or more contacts coupled to positive terminals of the multilayer ceramic capacitors located on a first surface and one or more contacts coupled to negative terminals of the multilayer ceramic capacitors located on a second surface opposite the first surface. In some other embodiments, the first and fifth device layers may be formed by embedding multilayer ceramic capacitors into the molded composite material. In some other embodiments, one or more of the active device layers or the passive device layers may be formed by embedding the switches and / or the capacitors in a molded interconnect substrate.

[0087] Through the operations 1410-1490 discussed above, a structure (e.g., structure 300a of Fig. 3A), which has multiple layers stacked vertically one above the other, can be obtained to implement the switched-capacitor circuit. A switched-capacitor power converter can therefore be formed with its stack switches, capacitors, and phase switches stacked vertically in different layers, and the horizontal surface area required for the power converter can be reduced.

[0088] Fig. 15 is a flowchart of another method 1500 for fabricating a switched capacitor circuit according to some embodiments of the present disclosure. It should be understood that additional operations may be performed before, during, and / or after the Fig. 15, and that some other processes may only be briefly described herein. The method 1500 may be performed to form the structure 700 of Fig. 7 for manufacturing integrated circuits for power converter applications, such as the power converter 100 in Fig. 1 and the power converter 1200 from Fig. 12. The method 1500 includes operations 1510-1520.

[0089] In operation 1510, a phase device cell (e.g., phase device cell 730 in Fig. 7), the phase switches (e.g. switches S6-S8 in Fig. 7) for a switched capacitor circuit. In operation 1520, a plurality of cells (e.g., cells 710 and 720 in Fig. 7) Stacked vertically above the phase device cell. Each cell includes a capacitor (e.g., one of the capacitors C1-C5) and a stack switch (e.g., one of the switches S1-S5). The capacitor and stack switch in each cell are interconnected with the phase switches. In each cell, the capacitor is coupled between a corresponding lower contact and upper contact, and the stack switch is coupled between a corresponding lower contact and upper contact.

[0090] The process of stacking cells at operation 1520 may involve connecting, in each cell, lower contacts (e.g., lower contacts B1-B5 in Fig. 8A and Fig. 8B) lying on a lower surface, with contacts of another cell stacked below the cell, and connecting, in each cell, upper contacts (e.g., the upper contacts T1-T5 in Fig. 8A and Fig. 8B) lying on a top surface with contacts of another cell stacked above the cell.

[0091] In some embodiments, in operation 1520, one or more cells in a set (e.g., cells 710 in Fig. 7) and one or more cells in another set (e.g. cells 720 in Fig. 7) are alternately stacked. In each cell 710, the capacitor is connected to a first subset of the phase switches (e.g., switches S8 and S9 in Fig. 7) at a first phase node (e.g. phase node 732 in Fig. 7) of the switched capacitor circuit. In each cell 720, the capacitor is coupled to a second subset of the phase switches (e.g., switches S6 and S7 in Fig. 7) at a second phase node (e.g. phase node 734 in Fig. 7) of the switched capacitor circuit.

[0092] Through the operations 1510 and 1520 discussed above, a structure (e.g., structure 700 of Fig. 7) can be obtained to implement the switched-capacitor circuit, and a switched-capacitor power converter can therefore be formed with its electrical components stacked vertically, reducing the horizontal surface area required for the power converter. As discussed above, by applying method 1500 to fabricate the switched-capacitor circuit, the conversion ratio of the switched-capacitor network can be easily modified by stacking a different number of cells, thereby providing modularity and flexibility for the power converter design to meet different power requirements in different applications at low cost.

[0093] In summary, in various embodiments of the present disclosure, switches and capacitors can be vertically stacked in different ways to construct a single-phase or multi-phase switched-capacitor network that can be applied in various power conversion circuits, such as charge pump switching, resonant switched-capacitor converter circuits, multi-level power converter circuits, etc., to provide increased power density per unit area. Accordingly, the overall area required for the power converter can be reduced, which is desirable for data center power delivery devices and other power applications.It is noted that switched capacitor circuits and / or power converters in the present disclosure may be implemented with various topologies depending on the desired voltage conversion ratio and the allowable switching voltage.

[0094] In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications of the described embodiments may be made. Other embodiments may be apparent to those skilled in the art by examining the specification and practicing the disclosure disclosed herein. It is also intended that the sequence of steps shown in the figures is for illustrative purposes only and is not limited to any particular sequence of steps. As such, those skilled in the art will understand that these steps may be performed in different orders while implementing the same method.

[0095] It will be appreciated that certain features of the specification described in the context of separate embodiments for clarity may also be provided in combination with a single embodiment. Conversely, various features of the specification described in the context of a single embodiment for brevity may also be provided separately or in any suitable subcombination or as appropriate in any other described embodiments of the specification. Certain features described in the context of various embodiments are not considered essential features of those embodiments unless the embodiment is ineffective without those elements.

[0096] The embodiments may be further described using the following clauses: 1. A device that includes: a first device layer comprising a plurality of first switches; a second device layer comprising a plurality of second switches; and a third device layer disposed between the first device layer and the second device layer, wherein the third device layer comprises a plurality of first capacitors; wherein the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; and wherein the switched capacitor circuit is configured to change between at least two states in response to the switching of the plurality of first switches and the plurality of second switches. 2. The device according to clause 1, wherein the plurality of first switches are stack switches coupled to positive terminals of the plurality of first capacitors via a plurality of DC nodes; and wherein the plurality of second switches are phase switches coupled to negative terminals of the plurality of first capacitors via a first phase node or a second phase node. 3. The device of clause 2, wherein the first phase node is coupled to negative terminals of a first subset of the plurality of first capacitors and the second phase node is coupled to negative terminals of a second subset of the plurality of first capacitors. 4. Device according to any of clauses 1-3, which further includes: a fourth device layer comprising a plurality of third switches; and a fifth device layer disposed between the second device layer and the fourth device layer, wherein the fifth device layer comprises a plurality of second capacitors, wherein the switched capacitor circuit is a multi-phase switched capacitor circuit; wherein the plurality of second switches are phase switches for a first phase and a second phase for connecting the plurality of first capacitors and the plurality of second capacitors to shared phase nodes of the switched capacitor circuit; wherein the plurality of first switches are stack switches associated with the first phase; and wherein the plurality of third switches are stack switches associated with the second phase. 5. The device of any one of clauses 1-4, wherein positive terminals of the plurality of first capacitors are coupled to corresponding contacts located on a first surface of the third device layer, and negative terminals of the plurality of first capacitors are coupled to corresponding contacts located on a second surface of the third device layer opposite the first surface. 6. The device according to any one of clauses 1-5, wherein the plurality of first capacitors are multilayer ceramic capacitors. 7. A device according to clause 6, wherein the multilayer ceramic capacitors are embedded in a substrate, with a long edge of each multilayer ceramic capacitor being substantially perpendicular to a top surface of the third device layer. 8. A device according to clause 6, wherein the multilayer ceramic capacitors are embedded in a substrate, with a long edge of each multilayer ceramic capacitor being substantially parallel to a top surface of the third device layer. 9. A device as defined in clause 6, wherein the multilayer ceramic capacitors are vertically embedded in a cast composite material. 10. The device according to any one of clauses 1-9, wherein one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded in a molded interconnection substrate. 11. The device of any one of clauses 1-10, wherein the third device layer further comprises an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter. 12. Device as defined in any of clauses 1-11, which further includes: an inductor layer stacked vertically adjacent to the third device layer, the inductor layer comprising an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter. 13. The device of any one of clauses 1-12, wherein the device includes a plurality of substructures stacked vertically one above the other, each substructure being associated with a respective phase of the switched capacitor circuit and including the first device layer, the second device layer, and the third device layer. 14. Apparatus according to clause 13, wherein the plurality of substructures form a multi-phase switched capacitor circuit, with n phases being 360 / n degrees out of phase with each other, where n is any integer greater than 1. 15. A device that contains: a plurality of cells, each cell including a capacitor and a first switch; and a phase device cell comprising a plurality of second switches, the plurality of cells being stacked vertically above the phase device cell, wherein the capacitor and the first switch in each cell are connected together with the plurality of second switches to form a switched capacitor circuit; and wherein the switched capacitor circuit is configured to switch between at least two states in response to switching of the first switch in each cell and the plurality of second switches. 16. The device of clause 15, wherein the plurality of cells includes two sets of cells alternately stacked vertically, wherein in one set of cells the capacitor is coupled to a first subset of the plurality of second switches at a first phase node of the switched capacitor circuit, and in another set of cells the capacitor is coupled to a second subset of the plurality of second switches at a second phase node of the switched capacitor circuit. 17. A device according to clause 16, wherein during a first state of the switched capacitor circuit, each first switch in one set of cells is turned on and each first switch in the other set of cells is turned off; and wherein during a second state of the switched capacitor circuit, each first switch in one set of cells is turned off and each first switch in the other set of cells is turned on. 18. Device according to any of clauses 15-17, each cell comprising: upper contacts lying on an upper surface of the cell, the upper contacts being connected to contacts of another cell stacked above the cell; lower contacts lying on a lower surface of the cell, the lower contacts being connected to contacts from another cell stacked below the cell. 19. The device of clause 18, wherein a first phase node of the switched capacitor circuit is electrically coupled to one of the upper contacts and one of the lower contacts, and a second phase node of the switched capacitor circuit is electrically coupled to another of the upper contacts and another of the lower contacts. 20. A device according to clause 18 or clause 19, wherein each first switch of each cell includes a field effect transistor having a source terminal and a drain terminal coupled to one of the upper contacts and one of the lower contacts of the cell, respectively. 21. A device according to clause 20, wherein in each cell the capacitor is coupled between the source terminal of the field effect transistor and one of a first phase node or a second phase node of the switched capacitor circuit. 22. The device according to any one of clauses 15-21, wherein at least one of the cells includes a plurality of capacitors and a plurality of first switches interconnected with the plurality of second switches to form the switched capacitor circuit. 23. A device according to any one of clauses 15-22, wherein at least one of the cells further comprises an inductor. 24. A method of fabricating a switched capacitor circuit comprising: Providing a first device layer; Arranging a third device layer on the first device layer; interconnecting a plurality of first capacitors within the third device layer with a plurality of first switches within the first device layer; Arranging a second device layer on the third device layer; and interconnecting a plurality of second switches within the second device layer with the plurality of first capacitors. 25. Procedure under Clause 24, which further includes: Arranging a fifth device layer on the second device layer; interconnecting a plurality of second capacitors within the fifth device layer with the plurality of second switches; Disposing a fourth device layer on the fifth device layer; and interconnecting a plurality of third switches within the fourth device layer with the plurality of second capacitors. 26. Procedure under Clause 24 or Clause 25, which further includes: Connecting a lower contact of the third device layer to a corresponding upper contact of the first device layer to couple a positive terminal of one of the plurality of first capacitors to one of the plurality of first switches. 27. Procedure under any of clauses 24-26, which further includes: Connecting a lower contact of the second device layer to a corresponding upper contact of the third device layer to couple a negative terminal of one of the plurality of first capacitors to one of the plurality of second switches. 28. Procedure under any of Clauses 24-27, which further includes: Embedding multilayer ceramic capacitors vertically into a substrate to form the third device layer; wherein one or more contacts are coupled to positive terminals of the multilayer ceramic capacitors located on a first surface of the third device layer; and wherein one or more contacts are coupled to negative terminals of the multilayer ceramic capacitors located on a second surface of the third device layer opposite the first surface. 29. Procedure under any of clauses 24-27, which further includes: Embedding multilayer ceramic capacitors into a molded composite material to form the third device layer. 30. Procedure under any of Clauses 24-29, which further includes: Embedding one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors in a molded interconnection substrate. 31. Procedure under any of Clauses 24-30, which further includes: Stacking an inductor layer vertically adjacent to the third device layer, the inductor layer comprising an inductor coupled to one or more of the plurality of first capacitors. 32. A method of fabricating a switched capacitor circuit comprising: Providing a phase device cell comprising a plurality of phase switches of a switched capacitor circuit; and Stacking a plurality of cells vertically above the phase device cell, each cell comprising a capacitor and a stack switch; wherein the capacitor and the stack switch in each of the plurality of cells are interconnected with the plurality of phase switches. 33. A method according to clause 32, wherein stacking the plurality of cells comprises: Stacking one or more cells in one set and one or more cells in another set vertically, wherein in each cell in one set the capacitor is coupled to a first subset of the plurality of phase switches at a first phase node of the switched capacitor circuit, and in each cell in the other set the capacitor is coupled to a second subset of the plurality of phase switches at a second phase node of the switched capacitor circuit. 34. A method according to clause 32 or clause 33, wherein stacking the plurality of cells comprises: Connecting, in each cell, lower contacts lying on a lower surface of the cell to contacts of another cell stacked beneath the cell; and Connecting, in each cell, top contacts lying on a top surface of the cell to contacts from another cell stacked above the cell. 35. A method according to clause 34, wherein in each cell the capacitor is coupled between the corresponding lower contact and upper contact. 36. A method according to clause 34 or clause 35, wherein in each cell the stacking switch is coupled between the corresponding lower contact and upper contact.

[0097] The foregoing outlines features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the same benefits of the embodiments presented herein. Those skilled in the art should also understand that such equivalent designs do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 364,569

[0001] US 63 / 364,674

[0001]

Claims

[1] A device that includes: a first device layer comprising a plurality of first switches; a second device layer comprising a plurality of second switches; and a third device layer disposed between the first device layer and the second device layer, the third device layer comprising a plurality of first capacitors; wherein the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; and wherein the switched capacitor circuit is configured to change between at least two states in response to the switching of the plurality of first switches and the plurality of second switches. [2] The device of claim 1, wherein the plurality of first switches are stack switches coupled to positive terminals of the plurality of first capacitors via a plurality of DC nodes; and wherein the plurality of second switches are phase switches coupled to negative terminals of the plurality of first capacitors via a first phase node or a second phase node. [3] The device of claim 2, wherein the first phase node is coupled to negative terminals of a first subset of the plurality of first capacitors and the second phase node is coupled to negative terminals of a second subset of the plurality of first capacitors. [4] Device according to one of claims 1 to 3, further comprising: a fourth device layer comprising a plurality of third switches; and a fifth device layer disposed between the second device layer and the fourth device layer, the fifth device layer comprising a plurality of second capacitors, wherein the switched capacitor circuit is a multi-phase switched capacitor circuit; wherein the plurality of second switches are phase switches for a first phase and a second phase for connecting the plurality of first capacitors and the plurality of second capacitors to shared phase nodes of the switched capacitor circuit; wherein the plurality of first switches are stack switches associated with the first phase; and wherein the plurality of third switches are stack switches associated with the second phase. [5] The device of any one of claims 1 to 4, wherein positive terminals of the plurality of first capacitors are coupled to corresponding contacts located on a first surface of the third device layer, and negative terminals of the plurality of first capacitors are coupled to corresponding contacts located on a second surface of the third device layer opposite the first surface. [6] The apparatus according to any one of claims 1 to 5, wherein the plurality of first capacitors are multilayer ceramic capacitors. [7] The device according to claim 6, wherein the multilayer ceramic capacitors are embedded in a substrate, with a long edge of each multilayer ceramic capacitor being substantially perpendicular to a top surface of the third device layer. [8] The device according to claim 6, wherein the multilayer ceramic capacitors are embedded in a substrate, with a long edge of each multilayer ceramic capacitor being substantially parallel to a top surface of the third device layer. [9] A device according to claim 6, wherein the multilayer ceramic capacitors are vertically embedded in a molded composite material. [10] The device of any one of claims 1 to 9, wherein one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded in a molded interconnection substrate. [11] The device of any one of claims 1 to 10, wherein the third device layer further comprises an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter. [12] Device according to one of claims 1 to 11, further comprising: an inductor layer stacked vertically adjacent to the third device layer, the inductor layer comprising an inductor connected to one or more several of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter. [13] The device of any one of claims 1 to 12, wherein the device includes a plurality of substructures stacked vertically one above the other, each substructure being associated with a respective phase of the switched capacitor circuit and including the first device layer, the second device layer, and the third device layer. [14] The apparatus of claim 13, wherein the plurality of substructures form a multi-phase switched capacitor circuit, wherein n phases are 360 / n degrees out of phase with each other, where n is any integer greater than 1. [15] A device that includes: a plurality of cells, each cell including a capacitor and a first switch; and a phase device cell comprising a plurality of second switches, the plurality of cells being stacked vertically above the phase device cell, wherein the capacitor and the first switch in each cell are connected together with the plurality of second switches to form a switched capacitor circuit; and wherein the switched capacitor circuit is configured to switch between at least two states in response to switching of the first switch in each cell and the plurality of second switches. [16] The device of claim 15, wherein the plurality of cells includes two sets of cells alternately stacked vertically, wherein in one set of cells the capacitor is coupled to a first subset of the plurality of second switches at a first phase node of the switched capacitor circuit, and in another set of cells the capacitor is coupled to a second subset of the plurality of second switches at a second phase node of the switched capacitor circuit. [17] The device of claim 16, wherein during a first state of the switched capacitor circuit, each first switch in the one set of cells is turned on and each first switch in the other set of cells is turned off; and wherein during a second state of the switched capacitor circuit, each first switch in the one set of cells is turned off and each first switch in the other set of cells is turned on. [18] Device according to one of claims 15 to 17, wherein each cell comprises: upper contacts lying on an upper surface of the cell, the upper contacts being connected to contacts of another cell stacked above the cell; lower contacts lying on a lower surface of the cell, the lower contacts being connected to contacts from another cell stacked below the cell. [19] The device of claim 18, wherein a first phase node of the switched capacitor circuit is electrically coupled to one of the upper contacts and one of the lower contacts, and a second phase node of the switched capacitor circuit is electrically coupled to another of the upper contacts and another of the lower contacts. [20] The device of claim 18 or 19, wherein each first switch of each cell includes a field effect transistor having a source terminal and a drain terminal coupled to one of the upper contacts and one of the lower contacts of the cell, respectively. [21] The device of claim 20, wherein in each cell the capacitor is coupled between the source terminal of the field effect transistor and one of a first phase node or a second phase node of the switched capacitor circuit. [22] The apparatus of any one of claims 15 to 21, wherein at least one of the cells includes a plurality of capacitors and a plurality of first switches interconnected with the plurality of second switches to form the switched capacitor circuit. [23] A device according to any one of claims 15 to 22, wherein at least one of the cells further comprises an inductor. [24] A method of manufacturing a switched capacitor circuit comprising: Providing a first device layer; Arranging a third device layer on the first device layer; interconnecting a plurality of first capacitors within the third device layer with a plurality of first switches within the first device layer; Arranging a second device layer on the third device layer; and interconnecting a plurality of second switches within the second device layer with the plurality of first capacitors. [25] A method according to claim 24, further comprising: Arranging a fifth device layer on the second device layer; interconnecting a plurality of second capacitors within the fifth device layer with the plurality of second switches; Arranging a fourth device layer on the fifth device layer; and interconnecting a plurality of third switches within the fourth device layer with the plurality of second capacitors. [26] A method according to claim 24 or 25, further comprising: Connecting a lower contact of the third device layer to a corresponding upper contact of the first device layer to couple a positive terminal of one of the plurality of first capacitors to one of the plurality of first switches. [27] A method according to any one of claims 24 to 26, further comprising: Connecting a lower contact of the second device layer to a corresponding upper contact of the third device layer to couple a negative terminal of one of the plurality of first capacitors to one of the plurality of second switches. [28] A method according to any one of claims 24 to 27, further comprising: Embedding multilayer ceramic capacitors vertically into a substrate to form the third device layer; wherein one or more contacts are coupled to positive terminals of the multilayer ceramic capacitors located on a first surface of the third device layer; and wherein one or more contacts are coupled to negative terminals of the multilayer ceramic capacitors located on a second surface of the third device layer opposite the first surface. [29] A method according to any one of claims 24 to 27, further comprising: Embedding multilayer ceramic capacitors into a molded composite material to form the third device layer. [30] A method according to any one of claims 24 to 29, further comprising: Embedding one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors in a molded interconnection substrate. [31] A method according to any one of claims 24 to 30, further comprising: Stacking an inductor layer vertically adjacent to the third device layer, the inductor layer comprising an inductor coupled to one or more of the plurality of first capacitors. [32] A method of manufacturing a switched capacitor circuit comprising: Providing a phase device cell comprising a plurality of phase switches of a switched capacitor circuit; and Stacking a plurality of cells vertically above the phase device cell, each cell comprising a capacitor and a stack switch; wherein the capacitor and the stack switch in each of the plurality of cells are interconnected with the plurality of phase switches. [33] The method of claim 32, wherein stacking the plurality of cells includes: Stacking one or more cells in one set and one or more cells in another set vertically, wherein in each cell in one set the capacitor is coupled to a first subset of the plurality of phase switches at a first phase node of the switched capacitor circuit, and in each cell in the other set the capacitor is coupled to a second subset of the plurality of phase switches at a second phase node of the switched capacitor circuit. [34] A method according to claim 32 or 33, wherein stacking the plurality of cells comprises: Connecting, in each cell, lower contacts lying on a lower surface of the cell to contacts of another cell stacked beneath the cell; and Connecting, in each cell, top contacts lying on a top surface of the cell to contacts from another cell stacked above the cell. [35] A method according to claim 34, wherein in each cell the capacitor is coupled between the corresponding lower contact and upper contact. [36] A method according to claim 34 or 35, wherein in each cell the stack switch is coupled between the corresponding lower contact and upper contact.

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