Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device comprising a field plate connected to a protective ring formed in a termination area via an interposed metal barrier layer, wherein it is possible to suppress the residue of the metal barrier layer.According to the present invention, a termination area 22 comprises the following: a semiconductor substrate 1 of a first conductivity type; several guard rings 2 of a second conductivity type, the guard rings 2 being formed on the semiconductor substrate; an insulating layer 3 being in contact with the semiconductor substrate and the guard rings while having openings at positions corresponding to the guard rings; several metal barrier layers 4 being formed at least in the openings of the insulating layer such that they are in contact with the guard rings while being separated from one another; and several field plates 5 whose outlines in plan view lie outside the outlines of the metal barrier layers while being arranged such that they are separated from one another and are in contact with the upper surfaces of the metal barrier layers and the upper surface of the insulating layer.

Description

Technical area

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. State of the art

[0002] A semiconductor device, such as a power semiconductor, includes an active region in which a semiconductor element is formed and a main current flows, and a termination region formed around the active region for holding a voltage resistance.

[0003] As a structure of the termination region, for example, Patent Literature 1 describes a structure including a guard ring (p-layer) and an electrode (also called a field electrode or field plate) coupled to the guard ring via a metal barrier layer.

[0004] In particular, describe Fig. 1 and Fig. 2 and the abstract of the patent literature that “a semiconductor device capable of achieving both high voltage withstand and miniaturization in a power semiconductor device is provided” by “a high voltage withstand power semiconductor device having a termination region formed of a guard ring in which an active region is connected to a first electrode via a first metal barrier layer, the guard ring is connected to a second electrode via a second metal barrier layer, and a channel stopper is connected to a third electrode via a third metal barrier layer.The metal barrier layers are arranged at intervals from each other, a width of each of the metal barrier layers (first to third metal barrier layers) is wider than that of each of the electrodes to be connected (first to third electrodes) in a direction crossing the termination region, and a part of each of the metal barrier layers protrudes from both sides in a crossing direction of each electrode to be connected." Citation listPatent literature

[0005] Patent Literature 1: JP 2010-251404 A Summary of the inventionTechnical problem

[0006] However, in order to realize the structure described in Patent Literature 1, in Patent Literature 1, after a thin film for forming a metal barrier layer and a metal layer for forming an electrode such as a field electrode are formed, the metal layer is over-etched by wet etching using a photoresist to pattern the metal layer and form the electrode, and the thin film is patterned by anisotropic dry etching using the same photoresist to form the metal barrier layer, as in Fig. 3 of Patent Literature 1.

[0007] Therefore, if an opening of a photomask is insufficient due to foreign matter or the like, or if wet etching is insufficient, the metal barrier layer under the electrode, such as the field electrode, is likely to be insufficiently etched and likely to remain as a residue between the electrodes. There is a problem that if the metal barrier layer remains as the residue, the field electrodes are electrically coupled to each other, the guard rings coupled to the respective field electrodes have the same potential, and sufficient voltage resistance cannot be ensured in the termination region.

[0008] An object of the present invention is to provide a semiconductor device capable of reducing a residue remaining on a metal barrier layer in a semiconductor device having a field plate coupled to a guard ring formed in a termination region via a metal barrier layer, and a method of manufacturing the same. Solution to the problem

[0009] To solve the above problem, a semiconductor device of the present invention is, for example, a semiconductor device comprising an active region in which a semiconductor element is formed, and a termination region surrounding the active region, the termination region comprising: a semiconductor substrate of a first conductivity type; a plurality of guard rings of a second conductivity type formed on the semiconductor substrate; an insulating layer in contact with the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard ring; a plurality of metal barrier layers formed at least in the opening of the insulating layer, in contact with the guard ring, and arranged to be spaced apart from each other;and a plurality of field plates having an outer shape on the outside relative to an outer shape of the metal barrier layer in plan view, in contact with an upper surface of the metal barrier layer and an upper surface of the insulating layer, and arranged to be spaced apart from each other;

[0010] Further, a method for manufacturing a semiconductor device of the present invention is, for example, a method for manufacturing a semiconductor device comprising an active region in which a semiconductor element is formed, and a termination region surrounding the active region, the termination region comprising: a semiconductor substrate of a first conductivity type, a plurality of guard rings of a second conductivity type formed on the semiconductor substrate, an insulating layer in contact with the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard ring, a plurality of metal barrier layers in contact with the guard ring and arranged to be spaced apart from each other, and a plurality of field plates in contact with the metal barrier layer and arranged to be spaced apart from each other,the method comprising: the method comprises: etching the metal barrier layer after the metal barrier layer has been formed and before the field plate is formed., Advantageous effects of the invention

[0011] According to the semiconductor device of the present invention, since the outer shape of the metal barrier layer is on the inside relative to the field plate, it is possible to remove the residue, for example, by re-etching the metal barrier layer on the outside relative to the field plate, even if the residue remains when the metal barrier layer is patterned, and to reduce the residue remaining on the metal barrier layer.

[0012] Furthermore, according to the method for manufacturing a semiconductor device of the present invention, since the metal barrier layer is etched before the field plate is formed, it is possible to reduce the residue remaining on the metal barrier layer. Furthermore, even if the residue remains when the metal barrier layer is patterned, it is possible to remove the residue, for example, by re-etching the metal barrier layer during or after etching the field plate, and reduce the residue remaining on the metal barrier layer. Short description of the drawings [ Fig. 1] Fig. 1 shows a cross-sectional view of a semiconductor device according to Embodiment 1. [ Fig. 2] Fig. 2 shows a plan view of the semiconductor device according to Embodiment 1. [ Fig. 3] Fig. 3 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to Embodiment 1. [ Fig. 4] Fig. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to Embodiment 1. [ Fig. 5] Fig. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to Embodiment 1. [ Fig. 6] Fig. 6 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to Embodiment 1. [ Fig. 7] Fig. 7 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to Embodiment 1. [ Fig. 8] Fig. 8 shows a cross-sectional view of a semiconductor device according to Embodiment 2. Description of the embodiments

[0013] Embodiments of the present invention will be described below with reference to the drawings. In each drawing and each embodiment, the same or similar components are denoted by the same reference numerals, and duplicate descriptions thereof are omitted. Embodiment 1

[0014] Fig. 1 shows a cross-sectional view of a semiconductor device according to Embodiment 1 and Fig. 2 shows a plan view of the semiconductor device according to Embodiment 1. Fig. 1 shows a cross-sectional view along the line AA in Fig. 2.

[0015] A semiconductor device 20 according to Embodiment 1 includes an active region 21 in which a semiconductor element is formed, and a termination region 22 surrounding the active region 21. The termination region 22 includes a semiconductor substrate 1 of a first conductivity type (n-type in Fig. 1), several guard rings 2 of a second conductivity type (p-type in Fig. 1) formed on the semiconductor substrate 1, an insulating layer 3, a metal barrier layer 4 and a field plate 5.

[0016] In Fig. 1, an example is described in which the semiconductor element formed in the active region 21 is an insulated gate bipolar transistor (IGBT). Accordingly, the active region 21 includes a drift layer made of the semiconductor substrate 1, a body layer 6 of a second conductivity type serving as a main junction layer, the metal barrier layer 4 formed in contact with the body layer 6, a front-surface main electrode 7 formed in contact with the metal barrier layer 4, a buffer layer 8 of a first conductivity type formed on the back surface side of the semiconductor substrate 1, a collector layer 9 of a second conductivity type, and a back surface main electrode 10. The buffer layer 8 may be omitted. Furthermore, the active region 21 includes a gate electrode, a gate, and a gate insulating layer, although these are not shown. Since in Fig. 1 an impurity concentration of the semiconductor substrate 1 is low, the impurity concentration is represented as n-. In Fig. 1, the first conductivity type is n-type and the second conductivity type is p-type, however, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0017] The semiconductor element may be a metal oxide semiconductor field effect transistor (MOSFET), in which case a drain layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.

[0018] Furthermore, the semiconductor element may be a diode element instead of a switching element such as an IGBT or MOSFET. In this case, a cathode layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.

[0019] Next, a structure of the termination portion 22 in Embodiment 1 will be described in detail.

[0020] The plurality of protective rings 2 are formed so that they are spaced apart from each other.

[0021] The insulating layer 3 is in contact with the semiconductor substrate 1 and the guard ring 2 and includes an opening at a position overlapping the guard ring 2.

[0022] A plurality of metal barrier layers 4 are formed and arranged to be spaced from each other, and are formed at least within the opening of the insulating layer 3 and in contact with the guard ring 2. In Embodiment 1, the metal barrier layer 4 is also formed on an upper surface of the insulating layer 3. The metal barrier layer 4 may be formed of, for example, any one of Ti, TiN, TiW, and MoSi2. The metal barrier layer 4 has a function of preventing a metal (for example, Al) contained in the field plate 5 from diffusing into a semiconductor layer (for example, Si) forming the guard ring 2. Therefore, it is desirable that the metal barrier layer 4 be formed in an entire region of the opening of the insulating layer 3 that overlaps the guard ring 2.

[0023] A plurality of field plates 5 are formed and arranged to be spaced apart from each other, have an outer shape on the outside relative to an outer shape of the metal barrier layer 4 in plan view, and contact with an upper surface of the metal barrier layer 4 and the upper surface of the insulating layer 3. The field plate 5 can be formed from, for example, one of Al, AlSi, AlCu, and AlSiCu. In Embodiment 1, since the metal barrier layer 4 is also formed on the upper surface of the insulating layer 3, the field plate 5 also contacts a side surface of the metal barrier layer 4 on the upper surface of the insulating layer 3.

[0024] With the configuration described above, a distance between the plurality of field plates 5 is smaller than a distance between the plurality of metal barrier layers 4. An end portion of the metal barrier layer 4 is located on the inner side compared to an end portion of the field plate 5. The metal barrier layer 4 has a structure in which the metal barrier layer 4 is completely covered with the field plate 5 and does not protrude.

[0025] According to the semiconductor device 20 of Embodiment 1, since the outer shape of the metal barrier layer 4 is on the inner side relative to the field plate 5, even if the residue remains when the metal barrier layer 4 is patterned, it is possible to remove the residue by, for example, re-etching the metal barrier layer on the outer side relative to the field plates 5 and reduce the residue remaining on the metal barrier layer 4.

[0026] When the metal barrier layer 4 remains as the residue, the metal barrier layer 4 and the field plate 5 are electrically coupled to each other, and the guard ring 2 coupled to each field plate 5 has the same potential, causing a problem that sufficient voltage resistance cannot be ensured in the termination region 22. On the other hand, according to the semiconductor device 20 of Embodiment 1, since the outer shape of the metal barrier layer 4 is located on the inner side relative to the field plate 5 and the residue remaining on the metal barrier layer 4 can be reduced, this problem can be reduced.

[0027] Next, a method for manufacturing the semiconductor device 20 of Embodiment 1 will be described. The semiconductor device 20 of Embodiment 1 can be formed by etching the metal barrier layer 4 after the metal barrier layer 4 is formed and before the field plate 5 is formed.

[0028] Fig. 3 to Fig. 7 shows cross-sectional views illustrating a method of manufacturing the semiconductor device of Embodiment 1. Only a front surface side is described here, and a back surface side is not illustrated or described.

[0029] First, as in Fig. 3, impurities of the second conductivity type are implanted into the semiconductor substrate 1 to form the guard rings 2 and the body layer 6. Then, after the insulating layer 3 is formed, the opening is formed at a necessary location.

[0030] Next, a metal layer serving as the metal barrier layer 4 is formed by sputtering or vapor deposition as shown in Fig. 4 illustrates.

[0031] Next, the metal barrier layer 4 is processed by etching using a photoresist 11, as shown in Fig. 5. If the metal barrier layer 4 is etched before the field plate 5 is formed, it is possible to reduce the residue remaining on the metal barrier layer 4 and also to process the outer shape of the metal barrier layer 4 so that the outer shape lies on the inside relative to the outer shape of the field plate 5.

[0032] Next, a metal layer serving as the field plate 5 is formed by sputtering or vapor deposition as shown in Fig. 6 illustrates.

[0033] Next, the field plate 5 is processed by etching using the photoresist 11 as shown in Fig. 7. In this case, the outer shape of the field plate 5 is processed so that the outer shape of the field plate 5 is on the outside relative to the outer shape of the metal barrier layer 4 when viewed in plan view. Accordingly, the distance between the plurality of field plates 5 becomes smaller than the distance between the plurality of metal barrier layers 4. Then, it is possible to Fig. 1 by removing the photoresist 11.

[0034] Furthermore, even if the residue remains, if the metal barrier layer 4 is formed according to the Fig. 7, it is possible to remove the residue, for example, by re-etching the metal barrier layer 4 during or after etching the field plate 5. This makes it possible to reduce the residue remaining on the metal barrier layer 4. Embodiment 2

[0035] Embodiment 2 is a variation of Embodiment 1. In Embodiment 2, differences from Embodiment 1 are mainly described, and overlapping descriptions are omitted.

[0036] Fig. 8 shows a cross-sectional view of a semiconductor device according to Embodiment 2.

[0037] A metal barrier layer 4 of the semiconductor device 20 according to Embodiment 2 differs from that according to Embodiment 1 in that the metal barrier layer 4 is not formed on an upper surface of an insulating layer 3. In other words, the metal barrier layer 4 is formed only in an opening of the insulating layer 3. A manufacturing method is substantially the same as that according to Embodiment 1 except for a form of patterning the metal barrier layer 4. In Embodiment 2, it is possible to achieve the same effects as in Embodiment 1.

[0038] Although the examples of the present invention have been described above, the present invention is not limited to the configurations described in the examples, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each example can be combined and applied. List of reference symbols 1 semiconductor substrate 2 protective ring 3 Insulating layer 4 Metal barrier layer 5 field plate 6 body layer 7 Front surface main electrode 8 Buffer layer 9 Collector layer 10 Rear surface main electrode 11 Photoresist 12 Electrode layer 20 semiconductor device 21 Active area 22 Final area QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2010-251404 A

[0005]

Claims

[1] A semiconductor device comprising an active region in which a semiconductor element is formed and a termination region surrounding the active region, the termination region comprising: a semiconductor substrate of a first conductivity type; a plurality of guard rings of a second conductivity type formed on the semiconductor substrate; an insulating layer in contact with the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard ring; a plurality of metal barrier layers formed at least in the opening of the insulating layer, in contact with the guard ring, and arranged to be spaced apart from each other; and a plurality of field plates having an outer shape on the outside relative to an outer shape of the metal barrier layer in plan view, in contact with an upper surface of the metal barrier layer and an upper surface of the insulating layer, and arranged to be spaced apart from each other. [2] A semiconductor device according to claim 1, wherein the metal barrier layer is also formed on the upper surface of the insulating layer, and the field plate is in contact with a side surface of the metal barrier layer on the upper surface of the insulating layer. [3] The semiconductor device according to claim 1, wherein the metal barrier layer is not formed on the upper surface of the insulating layer. [4] The semiconductor device according to claim 1, wherein the metal barrier layer is formed in an entire region of the opening of the insulating layer that overlaps the guard ring. [5] The semiconductor device according to claim 1, wherein the metal barrier layer is formed of one of Ti, TiN, TiW and MoSi2. [6] The semiconductor device according to claim 1, wherein a distance between the plurality of field plates is smaller than a distance between the plurality of metal barrier layers. [7] A semiconductor device according to claim 1, wherein the semiconductor element is a switching element. [8] A semiconductor device according to claim 1, wherein the semiconductor element is a diode element. [9] A method of manufacturing a semiconductor device comprising an active region in which a semiconductor element is formed and a termination region surrounding the active region, the termination region comprising: a semiconductor substrate of a first conductivity type, a plurality of guard rings of a second conductivity type formed on the semiconductor substrate, an insulating layer in contact with the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard ring, a plurality of metal barrier layers in contact with the guard ring and arranged to be spaced apart from each other, and a plurality of field plates in contact with the metal barrier layer and arranged to be spaced apart from each other, the method comprising: Etching the metal barrier layer after the metal barrier layer is formed and before the field plate is formed. [10] A method of manufacturing a semiconductor device according to claim 9, wherein a distance between the plurality of field plates is smaller than a distance between the plurality of metal barrier layers. [11] A method of manufacturing a semiconductor device according to claim 9, comprising: Re-etching the metal barrier layer during or after etching the field plate.

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