PANORAMA GENERATION USING NEURAL NETWORKS

Abstract

Devices, systems, and techniques for generating images. In at least one embodiment, one or more neural networks are used to generate a panoramic image from a segmentation mask.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Patent Application No. 18 / 195,784, filed May 10, 2022, entitled "PANORAMA GENERATION USING NEURAL NETWORKS," and U.S. Provisional Application No. 63 / 396,561, entitled "GENERATING SPHERICAL PANORAMA IMAGES USING A SEGMENTATION AND NEURAL NETWORKS," filed August 9, 2022, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] One embodiment relates to processors or computing systems used to generate a panoramic image according to various novel techniques described herein. BACKGROUND

[0003] Techniques for using neural networks to generate panoramic images produce unsatisfactory results. Techniques for generating panoramic images using neural networks can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a projection of a panorama according to at least one embodiment; Fig. 2A illustrates an example of a segmentation and a corresponding image according to at least one embodiment; Fig. 2B illustrates an example of synthesizing a normal perspective image based on a partial image and segmentation, according to at least one embodiment; Fig. 3A illustrates an example method for generating a normal perspective image from a spherical projection according to at least one embodiment; Fig. Figure 3B illustrates an example of a method described with reference to Fig. 3A is discussed; Fig. 4 illustrates a method for synthesizing a spherical panorama using a spherical segmentation mask and a neural network according to at least one embodiment; Fig. 5A-5D illustrate a partial example of generating a spherical panorama from a spherical segmentation according to at least one embodiment; Fig. 6. illustrates an example of a processor according to at least one embodiment; Fig. 7A illustrates logic according to at least one embodiment; Fig. 7B illustrates logic according to at least one embodiment; Fig. 8 illustrates training and deployment of a neural network according to at least one embodiment; Fig. 9 illustrates an exemplary data center system according to at least one embodiment; Fig. 10A illustrates an example of an autonomous vehicle according to at least one embodiment; Fig. 10B illustrates an example of camera positions and fields of view for the autonomous vehicle from Fig. 10A according to at least one embodiment; Fig. 10C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. 10D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle. Fig. 10A according to at least one embodiment; Fig. 11 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 illustrates a computer system according to at least one embodiment; Fig. 14 illustrates a computer system according to at least one embodiment; Fig. 15A illustrates a computer system according to at least one embodiment; Fig. 15B illustrates a computer system according to at least one embodiment; Fig. 15C illustrates a computer system according to at least one embodiment; Fig. 15D illustrates a computer system according to at least one embodiment; Fig. 15E and Fig. 15F illustrate a common programming model according to at least one embodiment; Fig. 16 illustrates example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 17A to Fig. 17B illustrate example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 18A to Fig. 18B illustrate additional example graphics processor logic according to at least one embodiment; Fig. 19 illustrates a computer system according to at least one embodiment; Fig. 20A illustrates a parallel processor according to at least one embodiment; Fig. 20B illustrates a partition unit according to at least one embodiment; Fig. 20C illustrates a processing cluster according to at least one embodiment; Fig. 20D illustrates a graphics multiprocessor according to at least one embodiment; Fig. 21 illustrates a system having multiple graphics processing units (GPUs) according to at least one embodiment; Fig. 22 illustrates a graphics processor according to at least one embodiment; Fig. 23 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 24 illustrates a deep learning application processor according to at least one embodiment; Fig. 25 is a block diagram illustrating an exemplary neuromorphic processor according to at least one embodiment; Fig. 26 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 27 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 28 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 29 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 30 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 31A to Fig. 31B illustrate thread execution logic including an arrangement of processing elements of a graphics processor core, according to at least one embodiment; Fig. 32 illustrates a parallel processing unit ("PPU") according to at least one embodiment; Fig. 33 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. 34 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment; Fig. 35 illustrates a streaming multiprocessor according to at least one embodiment; Fig. 36 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. 37 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Fig. 38 includes an exemplary illustration of an advanced computing pipeline 3710A for processing imaging data in accordance with at least one embodiment; Fig. 39A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 39B includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment; Fig. 40A illustrates a data flow diagram for a process for training a machine learning model according to at least one embodiment; and Fig. 40B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION

[0004] Fig. 1 illustrates an example of a projection of a panorama 102 according to at least one embodiment. In at least one embodiment, such as in Fig. 1, the panorama 102 may be a spherical panorama. In at least one embodiment, the panorama 102 may be a non-spherical or partial panorama. In at least one embodiment, the panorama 102 is mapped to the projection 104 by mapping meridians 106 to vertical straight lines and latitudes 108 to horizontal straight lines. In at least one embodiment, such as in Fig. 1, projection 104 may be an isosceles projection, with meridians 106 mapped onto equally spaced vertical straight lines and latitudes mapped onto equally spaced horizontal straight lines. In at least one embodiment, projection 104 may be a non-isosceles projection.

[0005] Fig. 2A illustrates an example of a segmentation 202a and a corresponding image 202b according to at least one embodiment. In at least one embodiment, such as in Fig. 2A, the segmentation 202a may be an isosceles projection of a segmentation of a spherical panorama. In at least one embodiment, such as in Fig. As illustrated in Figure 2A, image 202b may be an isosceles projection of a spherical panorama. In at least one embodiment, segmentation 202a is provided by the user. In at least one embodiment, segmentation 202a is generated by a neural network.

[0006] In at least one embodiment, the image 202b is generated by a neural network based on semantic labels for regions of the segmentation 202a. In at least one embodiment, such as in Fig. 2A, the segmentation 202a may include a region 204a labeled as "ground", a region 206a labeled as "trees", a region 208a labeled as "sky", and a region 210a labeled as "sun", and the image 202b may include corresponding regions 204b, 206b, 208b, and 210b, respectively.

[0007] Fig. 2B illustrates an example of synthesizing a normal perspective image 218 based on a partial image 212 and a segmentation 216 according to at least one embodiment. In at least one embodiment, such as in Fig. As illustrated in Figure 2B, a partial image 212 includes a missing region 214; a segmentation 216 is provided that semantically identifies contents of the image 212, including desired content of the missing region 214. In at least one embodiment, a neural network uses the segmentation 216 to fill the missing region 214, resulting in image 218. In at least one embodiment, a normal perspective image may include an image with a perspective corresponding to a normal camera or human view.

[0008] Fig. 3A illustrates an example method 300 for generating a normal perspective image 302 from a spherical projection 304, according to at least one embodiment. In at least one embodiment, the spherical projection 304 is an isosceles projection. In at least one embodiment, the spherical projection 304 is projected onto a sphere 306. In at least one embodiment, given a viewing direction and a field of view with respect to the sphere, a spherical panoramic portion 308 is selected from a corresponding portion of the sphere 306. In at least one embodiment, the spherical panoramic portion 308 is projected into the normal perspective image 302.

[0009] Fig. 3B illustrates an example of the method 300 described with reference to Fig. 3A. In at least one embodiment, such as in Fig. 3B, a normal perspective image 310 may be generated from a spherical panorama portion 312 corresponding to a viewing direction and a field of view of an isosceles projection 314 of a spherical panorama.

[0010] Fig. 4 illustrates a method 400 for synthesizing a spherical panorama using a spherical segmentation mask and a neural network according to at least one embodiment. In at least one embodiment, this neural network is trained to generate normal perspective images, such as in Fig. 2B illustrates.

[0011] In at least one embodiment, method 400 continues according to Algorithm 1 below.

[0012] In at least one embodiment, a spherical panorama is initialized 402. In at least one embodiment, this spherical panorama may be initialized to all zeros. In at least one embodiment, a set of view directions is initialized 404. In at least one embodiment, a view direction corresponds to an orientation of a viewer of a spherical panorama. In at least one embodiment, a view direction may be represented by an ordered triple of the shape (length, width, field of view), and view directions may be {(0, 90, 105), (0, 0, 90), (0, -90, 105), (60, 0, 90), (300, 0, 90), (120, 0, 90), (240, 0, 90), (180, 0, 90)}.

[0013] In at least one embodiment, for a given viewing direction, a corresponding spherical panoramic section is projected onto a normal perspective image 406, such as in Fig. 3A and Fig. 3B, and an input spherical segmentation is projected onto a normal perspective segmentation 408. In at least one embodiment, the generated normal perspective image includes one or more incomplete portions because the method 400 has not yet fully generated this spherical panorama.

[0014] In at least one embodiment, the generated normal perspective image and the normal perspective segmentation 410 are used by a normal image generator (e.g., a neural network) to generate a finished normal perspective image, such as in Fig. 2B. In at least one embodiment, this completed normal perspective image 412 (e.g., an inverse function of that used in step 406) is back-projected onto the corresponding spherical panoramic portion.

[0015] In at least one embodiment, method 400 includes determining whether steps 406 through 412 have been completed for all view directions. In at least one embodiment, if steps 406 through 412 have not been completed for all view directions, method 400 repeats to a next view direction 416, and steps 406 through 414 are repeated. In at least one embodiment, if steps 406 through 412 have been completed for all view directions, method 400 returns a completed spherical panorama 418 at step 414.

[0016] Fig. 5A-5D illustrate a partial example of generating a spherical panorama from a spherical segmentation according to at least one embodiment.

[0017] In at least one embodiment, a partial normal perspective image 502a is generated from a portion of a spherical panorama sampled for a given viewing direction (e.g., step 406 described in Fig. 4). In at least one embodiment, for example, as shown in Fig. 5A, this spherical image is initialized to zero, and therefore, for a first iteration, an empty sub-image is generated. In at least one embodiment, a corresponding partial normal perspective segmentation 504a is generated from a spherical segmentation (e.g., step 408 illustrated in Fig. 4). In at least one embodiment, a neural network generates an output image 506a based on the partial normal perspective image 502a and the partial normal perspective segmentation 504a (e.g., step 410 illustrated in Fig. 4). In at least one embodiment, the output image 506a is projected backward onto an updated spherical panorama 508a (e.g., step 412 shown in Fig. 4), which is considered an isosceles projection in Fig. 5A is illustrated.

[0018] In at least one embodiment, for example, as in Fig. 5B-5D illustrates a new partial normal perspective image 502b (502c or 502d for Fig. 5C and Fig. 5D) from a section of the updated spherical panorama 508a (508b or 508c for Fig. 5C and Fig. 5D). In at least one embodiment, successive viewing directions slightly overlap each other, so that, for example, as in Fig. 5B-5D, partially normal perspective images 502b, 502c, and 502d are not completely empty, but instead contain content at a boundary between a previous view direction and a current view direction; this allows continuity to be maintained in a final spherical panorama. For example, in at least one embodiment, as in Fig. 5B illustrates the output image 504b (504c or 504d for Fig. 5C and Fig. 5D) backwards to an updated spherical panorama 508b (508c or 508d for Fig. 5C and Fig. 5D) projected.

[0019] In at least one embodiment, a method such as that described in Fig. 5A-5D, until a complete spherical panorama is created.

[0020] Fig. 6 illustrates an example of a processor 600 according to at least one embodiment. In at least one embodiment, the processor 600 performs one or more methods such as those described with reference to Fig. 1-5 to use one or more neural networks to generate one or more panoramic images based at least in part on a segmentation map indicating content to be included. In at least one embodiment, generating panoramic images may comprise generating one or more normal perspective images and projecting them onto portions of panoramic images. In at least one embodiment, panoramic images may be spherical panoramic images. In at least one embodiment, normal perspective images may be generated based at least in part on a segmentation map. In at least one embodiment, normal perspective images may correspond to one or more panoramic image view directions. In at least one embodiment, view directions may overlap.In at least one embodiment, normal perspective images may be projected onto panoramic images based on viewing directions.

[0021] In at least one embodiment, the processor 600 includes one or more processors, such as those used in conjunction with the Fig. 19-34. In at least one embodiment, processor 600 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs.

[0022] In at least one embodiment, the processor 600 includes a neural network training module 602, an input module 604, an output module 606, an initialization module 608, a gaze direction module 610, an image generation module 612, a projection module 614, and a backprojection module 616. In at least one embodiment, the neural network training module 602, the input module 604, the output module 606, the initialization module 608, the gaze direction module 610, the image generation module 612, the projection module 614, and the backprojection module 616 are part of the processor 600, such as in Fig. 6, or may be part of one or more other processors. In at least one embodiment, the neural network training module 602, the input module 604, the output module 606, the initialization module 608, the gaze direction module 610, the image generation module 612, the projection module 614, and the backprojection module 616 are distributed among multiple processors that may be connected via a bus, a network, by writing to shared memory, or any suitable communication method, such as those described with reference to the Fig. 16-28.

[0023] In at least one embodiment, the neural network training module 602 includes circuitry that causes all or a portion of the neural networks to be trained to perform image generation from a segmentation map or a sub-image and a segmentation map, such as in Fig. 2B illustrates.

[0024] In at least one embodiment, the input module 604 includes circuitry that causes an input, for example, a spherical segmentation such as that shown in Fig. 2A, is received by a neural network. In at least one embodiment, the output module 608 includes circuitry that generates an output, such as a spherical panorama or an isosceles projection of a spherical panorama, such as that shown in Fig. 2A, isosceles projection 202b, from a neural network. In at least one embodiment, the output module 606 may perform operations to complete step 418 illustrated in Fig. 4 is illustrated.

[0025] In at least one embodiment, the initialization module 608 includes circuitry to initialize a new spherical panorama, for example, to all zeros. In at least one embodiment, the initialization module 608 may perform operations to complete step 404 described in Fig. 4 is illustrated.

[0026] In at least one embodiment, the gaze direction module 610 includes circuitry to initialize and select from a set of gaze directions. In at least one embodiment, the gaze direction module 610 may perform operations to implement steps 404 and 416 described in Fig. 4 are illustrated.

[0027] In at least one embodiment, the image generation module 612 includes circuitry for using a neural network to generate an image, e.g., a normal perspective image, from a segmentation map or a partial image and a segmentation map, such as in Fig. 2B. In at least one embodiment, the image generation module 612 may perform operations to complete step 410 illustrated in Fig. 4 is illustrated.

[0028] In at least one embodiment, the projection module 614 includes circuitry to project at least a portion of a spherical panorama or spherical segmentation onto a normal perspective image or segmentation, such as in Fig. 3B. In at least one embodiment, the projection module 614 may perform operations to implement steps 406 and 408 illustrated in Fig. 4 are illustrated.

[0029] In at least one embodiment, the rear projection module 616 includes circuitry to project at least a portion of a normal perspective image backward onto a corresponding portion of a spherical panorama, such as in Fig. 5A-5D. In at least one embodiment, the backprojection module 616 may perform operations to complete step 412 illustrated in Fig. 4 is illustrated. LOGIC

[0030] Fig. 7A illustrates logic 715, which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein according to at least one embodiment. In at least one embodiment, logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is reasoning and / or training logic. Details regarding logic 715 are described below in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide functionality or operations described herein, where logic, collectively or individually, may be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0031] In at least one embodiment, logic 715 may include, without limitation, code and / or data storage 701 for storing feedforward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network that are trained and / or used for reasoning in aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software for controlling timing and / or ordering, wherein weights and / or other parameter information are to be loaded for configuring logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads weighting, or other parameter information into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, code and / or data storage 701 stores weighting parameters and / or input / output data of each neural network layer trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0032] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, a choice of whether code and / or data storage 701 is, for example, internal or external to a processor or comprises DRAM, SRAM, flash, or another type of memory may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inference functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0033] In at least one embodiment, logic 715 may include, without limitation, code and / or data storage 705 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 705 stores weighting parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during backpropagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software for controlling timing and / or sequencing, wherein weight and / or other parameter information is to be loaded for configuring logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0034] In at least one embodiment, code, such as graph code, causes weight or other parameter information to be loaded into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including an L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, a choice of whether code and / or data storage 705 is, for example, internal or external to a processor or comprises DRAM, SRAM, flash, or another memory type may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inference functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0035] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate memory structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be a combined memory structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0036] In at least one embodiment, logic 715 may include, without limitation, one or more arithmetic logic units ("ALU(s)") 710, including integer and / or floating point units, to perform logical and / or mathematical operations based at least in part on or specified by training and / or reasoning code (e.g., graph code), a result of which may generate activations (e.g., output values ​​of layers or neurons within a neural network) stored in an activation store 720 that are functions of input / output and / or weighting parameter data stored in code and / or data store 701 and / or code and / or data store 705.In at least one embodiment, activations stored in activation memory 720 are generated according to linear algebraic and / or matrix-based mathematics performed by ALU(s) 710 in response to the execution of instructions or other code, wherein weight values ​​stored in code and / or data memory 705 and / or data memory 701 are used as operands along with other values, such as deviation values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 705 or code and / or data memory 701 or other on-chip or off-chip memory.

[0037] In at least one embodiment, ALU(s) 710 are included in one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 710 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALU(s) 710 may be included in the execution units of a processor or otherwise included in a bank of ALUs that are accessible by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.).In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation memory 720 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or a combination of them and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation memory 720 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.Furthermore, inference and / or training code may be stored with other code that is accessible by a processor or other hardware logic or circuitry and that is retrieved and / or processed using the fetch, decode, scheduling, execution, retirement and / or other logic circuitry of a processor.

[0038] In at least one embodiment, activation memory 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 720 may be wholly or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, a choice of whether activation memory 720 is, for example, internal or external to a processor or comprises DRAM, SRAM, flash, or another memory type may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inference functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0039] In at least one embodiment, the Fig. 7A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., “Lake Crest”) from Intel Corp. In at least one embodiment, the logic illustrated in Fig. 7A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0040] Fig. 7B illustrates logic 715 according to at least one embodiment. In at least one embodiment, logic 715 is reasoning and / or training logic. In at least one embodiment, logic 715 may be used in conjunction with application-specific integrated logic 715, including, without limitation, hardware logic in which computational resources are dedicated or otherwise used exclusively in connection with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic illustrated in Fig. 7B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., "Lake Crest") from Intel Corp. In at least one embodiment, the logic illustrated in Fig. 7B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 715 includes, without limitation, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight values, and / or other information, including deviation values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, Fig. 7B, each of code and / or data memory 701 and code and / or data memory 705 is associated with a dedicated computing resource, such as computing hardware 702 and computing hardware 706, respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data memory 701 and code and / or data memory 705, respectively, the result of which is stored in activation memory 720.

[0041] In at least one embodiment, each of code and / or data storage 701 and 705, or corresponding compute hardware 702 and 706, corresponds to different layers of a neural network, such that the resulting activation from one memory / compute pair 701 / 702 of code and / or data storage 701 and compute hardware 702 is provided as input to a next memory / compute pair 705 / 706 of code and / or data storage 705 and compute hardware 706 to mirror a conceptual organization of a neural network. In at least one embodiment, each of memory / compute pairs 701 / 702 and 705 / 706 may correspond to more than one layer of a neural network. In at least one embodiment, additional memory / compute pairs (not shown) may be included after or in parallel with memory / compute pairs 701 / 702 and 705 / 706 in logic 715. TRAINING AND DEPLOYMENT OF A NEURAL NETWORK

[0042] Fig. 8 illustrates training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is a PyTorch framework, whereas in other embodiments, the training framework 804 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or another training framework. In at least one embodiment, the training framework 804 trains an untrained neural network 806 and enables it to be trained using processing resources described herein to produce a trained neural network 808. In at least one embodiment, weights may be selected randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be performed in either a supervised, semi-supervised, or unsupervised manner.

[0043] In at least one embodiment, an untrained neural network 806 is trained using supervised learning, where the training data set 802 includes an input paired with a desired output for an input, or where the training data set 802 includes an input having a known output, and an output of the neural network 806 is manually graded. In at least one embodiment, an untrained neural network 806 is trained in a supervised manner and processes inputs from the training data set 802 and compares resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts weights that control the untrained neural network 806.In at least one embodiment, the training framework 804 includes tools to monitor how well the untrained neural network 806 converges on a model, such as the trained neural network 808, capable of generating correct answers, such as in the result 814, based on input data, such as a new data set 812. In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806 while adjusting weights to refine an output of the untrained neural network 806 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 achieves a desired accuracy.In at least one embodiment, the trained neural network 808 may then be used to implement any number of machine learning operations.

[0044] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 802 for unsupervised learning includes input data without associated output data or ground truth data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training data set 802 and can determine how individual inputs relate to the untrained data set 802. In at least one embodiment, the unsupervised training can be used to generate a self-organizing map in the trained neural network. The neural network 808 is capable of performing operations useful in reducing the dimensionality of the new data set 812.In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables identification of data points in the new data set 812 that deviate from normal patterns of the new data set 812.

[0045] In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training data set 802 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 804 may be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to the new data set 812 without forgetting knowledge embedded in the trained neural network 808 during initial training.

[0046] In at least one embodiment, the training framework 804 is a framework processed in conjunction with a software development toolkit, such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as those developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein.

[0047] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, in particular neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0048] In at least one embodiment, Open VINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image inking, style transfer, action recognition, colorization, and / or variations thereof.

[0049] In at least one embodiment, Open VINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that enables transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., changing the size of inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as an integer), and / or variations thereof.

[0050] In at least one embodiment, Open VINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or any suitable programming language library. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and produce one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.

[0051] In at least one embodiment, OpenVINO provides various capabilities for heterogeneously executing one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to execute a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA.In at least one embodiment, Open VINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0052] In at least one embodiment, OpenVINO includes various functionalities similar to functionalities associated with a CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0053] Fig. Figure 9 illustrates an example data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0054] In at least one embodiment, as in Fig. 9, the data center infrastructure layer 910 may include a resource orchestrator 912, clustered compute resources 914, and node compute resources ("Node CRs") 916(1)-916(N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, the Node CRs 916(1)-916(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more Node CRs may be selected from the Node CRs 916(1)-916(N) may be a server that has one or more of the computing resources listed above.

[0055] In at least one embodiment, the grouped computing resources 914 may include separate groupings of node CRs housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped computing resources 914 may include grouped computing, networking, storage, or memory resources that may be configured or assigned to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0056] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more node CRs 916(1)-916(N) and / or clustered computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure ("SDI") management entity for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or a combination thereof.

[0057] In at least one embodiment, as in Fig. 9, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework to support software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or application(s) 942 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be some type of free and open source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize the distributed file system 928 for large-scale data processing (e.g., "Big Data").In at least one embodiment, job scheduler 922 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring various layers, such as software layer 930 and framework layer 920, including Spark and distributed file system 928, to support large-scale computing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped compute resources allocated or assigned to support distributed file system 928 and job scheduler 922. In at least one embodiment, clustered or grouped compute resources may include grouped compute resources 914 on data center infrastructure layer 910.In at least one embodiment, the resource manager 926 may coordinate with the resource orchestrator 912 to manage these allocated or assigned computing resources.

[0058] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least portions of the node CRs 916(1)-916(N), the clustered computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet website search software, email virus scanning software, database software, and streaming video content software.

[0059] In at least one embodiment, the application(s) 942 included in the application layer 940 may include one or more types of applications used by at least portions of the node CRs 916(1)-916(N). In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomic application, a cognitive computing application, and a machine learning application, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0060] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 900 from making potentially poor configuration decisions and potentially avoiding underutilized and / or poorly performing portions of a data center.

[0061] In at least one embodiment, data center 900 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 900.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 900 by using weighting parameters calculated by one or more training techniques described herein.

[0062] In at least one embodiment, the data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using resources described above. Furthermore, one or more software and / or hardware resources described above may be configured as a service to enable users to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0063] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 may be used in data center 900 to infer or predict operations based at least in part on weighting parameters used using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0064] In at least one embodiment, logic 715 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates. AUTONOMOUS VEHICLE

[0065] Fig. 10A illustrates an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1000 may be a tractor-trailer truck used to haul cargo. In at least one embodiment, the vehicle 1000 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0066] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of that standard). In at least one embodiment, the vehicle 1000 may be capable of operating according to one or more of Levels 1 through 5 of the autonomous driving levels. For example, in at least one embodiment, the vehicle 1000 may be capable of conditionally automating (Level 3), highly automating (Level 4), and / or fully automating (Level 5), depending on the embodiment.

[0067] In at least one embodiment, vehicle 1000 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1000 may include, without limitation, a propulsion system 1050 such as an internal combustion engine, a hybrid electric power plant, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to a drivetrain of vehicle 1000, which may include, without limitation, a transmission, to facilitate propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving signals from throttle / accelerator pedal(s) 1052.

[0068] In at least one embodiment, a steering system 1054, which may include, without limitation, a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is in motion). In at least one embodiment, the steering system 1054 may receive signals from a steering actuator(s) 1056. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to apply vehicle brakes in response to receiving signals from a brake actuator(s) 1048 and / or brake sensors.

[0069] In at least one embodiment, the controller(s) 1036, which may include, without limitation, one or more system-on-chips (“SoCs”) (in Fig. 10A not shown) and / or graphics processing unit(s) ("GPU(s)"), provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, the controller(s) 1036 may send signals to actuate vehicle brakes via a brake actuator(s) 1048, to actuate the steering system 1054 via a steering actuator(s) 1056, to actuate the propulsion system 1050 via a throttle / accelerator pedal(s) 1052. In at least one embodiment, the controller(s) 1036 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1000.In at least one embodiment, the controller(s) 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0070] In at least one embodiment, the controller(s) 1036 provide signals to control one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be obtained, for example and without limitation, from Global Navigation Satellite System ("GNSS") sensor(s) 1058 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1060, ultrasonic sensor(s) 1062, LIDAR sensor(s) 1064, Inertial Measurement Unit ("IMU") sensor(s) 1066 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 1096, stereo camera(s) 1068, wide-angle camera(s) 1070 (e.g., fisheye cameras), infrared camera(s) 1072, environmental camera(s) 1074 (e.g., 360-degree cameras), remote cameras (in Fig. 10A not shown), mid-range camera(s) (in Fig. 10A not shown), speed sensor(s) 1044 (e.g., for measuring the speed of the vehicle 1000), vibration sensor(s) 1042, steering sensor(s) 1040, brake sensor(s) (e.g., as part of the brake sensor system 1046), and / or other sensor types.

[0071] In at least one embodiment, one or more of the controller(s) 1036 may receive inputs (e.g., represented by input data) from an instrument cluster 1032 of the vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface ("HMI") display 1034, an audible indicator, a speaker, and / or via other components of the vehicle 1000. In at least one embodiment, outputs may include information such as vehicle speed, velocity, time, map data (e.g., a high-resolution map (not shown in Fig. 10A), location data (e.g., location of vehicle 1000, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1036, etc. In at least one embodiment, HMI display 1034 may, for example, display information about the presence of one or more objects (e.g., a road sign, warning sign, traffic light change, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., change lanes now, take exit 34B in two miles, etc.).

[0072] In at least one embodiment, the vehicle 1000 further includes a network interface 1024 that may utilize one or more wireless antennas 1026 and / or one or more modems to communicate over one or more networks. For example, in at least one embodiment, the network interface 1024 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also facilitate communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks, such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc.and / or one or more low-power wide area networks (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0073] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in vehicle 1000 may be used to infer or predict operations based at least in part on weighting parameters obtained using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0074] In at least one embodiment, one or more controllers 1036 are used to at least partially implement panoramic imaging, as in Fig. 1-6 illustrates.

[0075] Fig. 10B illustrates an example of camera positions and fields of view for the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at various positions on vehicle 1000.

[0076] In at least one embodiment, camera types may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 1000. In at least one embodiment, camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, camera types may be capable of achieving any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof.In at least one embodiment, the color filter array may include a red-clear-clear-clear color filter array ("RCCC"), a red-clear-clear-blue color filter array ("RCCB"), a red-blue-green clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0077] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign support, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0078] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to mask stray light and reflections from within the vehicle 1000 (e.g., dashboard reflections reflected in windshield mirrors) that may interfere with camera image data collection capabilities. With reference to wing mirror mounting assemblies, in at least one embodiment, wing mirror assemblies may be custom 3D printed such that a camera mounting plate conforms to a shape of a wing mirror. In at least one embodiment, camera(s) may be integrated into wing mirrors. In at least one embodiment, camera(s) for side view cameras may also be integrated into four pillars at each corner of a cab.

[0079] In at least one embodiment, cameras with a field of view that includes portions of an environment in front of the vehicle 1000 (e.g., forward-facing cameras) may be used for surround vision to help identify forward paths and obstacles, as well as to help provide information critical to generating an occupancy grid and / or determining preferred vehicle paths using one or more controllers 1036 and / or control SoCs. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, but not limited to, lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0080] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform incorporating a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a far-view camera 1070 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 10B illustrates only one wide-view camera 1070, in other embodiments, there may be any number (including zero) of wide-view cameras on the vehicle 1000. In at least one embodiment, any number of long-range camera(s) 1098 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1098 may also be used for object detection and classification, as well as basic object tracking.

[0081] In at least one embodiment, any number of stereo cameras 1068 may also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 1068 may include an integrated control unit comprising a scalable processing unit that may provide a field-programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's surroundings, including a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo camera(s) 1068 may include, among other things, one or more compact stereo vision sensors, which may include, among other things, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance from the vehicle 1000 to the target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1068 may be used in addition to or alternatively to those described herein.

[0082] In at least one embodiment, cameras with a field of view that includes portions of the environment to the sides of the vehicle 1000 (e.g., side view cameras) may be used for surround vision, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, one or more surround cameras 1074 (e.g., four surround cameras, as in Fig. 10B) may be positioned on the vehicle 1000. In at least one embodiment, the surround view camera(s) 1074 may include, but are not limited to, any number and combination of wide view cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may utilize three surround view cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround view camera.

[0083] In at least one embodiment, cameras with a field of view that includes portions of an environment behind the vehicle 1000 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 1098 and / or medium-range cameras 1076, stereo camera(s) 1068, infrared camera(s) 1072, etc.), as described herein.

[0084] Fig. 10C is a block diagram illustrating an exemplary system architecture for the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 is Fig. 10C as connected via a bus 1002. In at least one embodiment, bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1000 used to assist in controlling various features and functionalities of vehicle 1000, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPMs"), button positions, and / or other vehicle status indicators.In at least one embodiment, bus 1002 may be a CAN bus that is ASIL B compliant.

[0085] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses that make up bus 1002, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses that use different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control.In at least one embodiment, each bus of bus 1002 may communicate with any of the components of vehicle 1000, and two or more buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) ("SoC(s)") 1004 (such as SoC 1004(A) and SoC 1004(B)), each of controller(s) 1036, and / or each computer within the vehicle may have access to the same input data (e.g., inputs from sensors of vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0086] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to Fig. 10A. In at least one embodiment, the controller(s) 1036 may be used for a variety of functions. In at least one embodiment, the controller(s) 1036 may be coupled to any of various other components and systems of the vehicle 1000 and may be used to control the vehicle 1000, artificial intelligence of the vehicle 1000, infotainment for the vehicle 1000, and / or other functions.

[0087] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, without limitation, central processing units ("CPU(s)") 1006, graphics processing units ("GPU(s)") 1008, processor(s) 1010, cache(s) 1012, accelerator(s) 1014, data storage(s) 1016, and / or other unillustrated components and features. In at least one embodiment, SoC(s) 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1004 may be combined in a system (e.g., system of vehicle 1000) with a high-definition ("HD") card.In at least one embodiment, the SoC(s) 1004 may include one or more databases 1022 that receive map updates and / or updates via the network interface 1024 from one or more servers (in . Fig. 10C not shown).

[0088] In at least one embodiment, the CPU(s) 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 1006 may include multiple cores and / or level-two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1006 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1006 (e.g., CCPLEX) may be configured to support concurrent cluster operations, allowing any combination of clusters of CPU(s) 1006 to be active at any one time.

[0089] In at least one embodiment, one or more of the CPU(s) 1006 may implement power management capabilities, including, without limitation, one or more of the following features: Individual hardware blocks may be automatically clocked when idle to conserve dynamic power; Each core clock may be clocked when such core is not actively executing due to the execution of wait for interrupt ("WFI") / wait for event ("WFE") instructions; Each core may be independently clocked; Each core cluster may be independently clocked when all cores are clocked or underclocked; and / or Each core cluster may be independently clocked when all cores are clocked.In at least one embodiment, CPU(s) 1006 may further implement an improved performance state management algorithm, specifying allowable performance states and expected wake-up times, and hardware / microcode determining which best performance state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified performance state entry sequences in software with work offloaded to microcode.

[0090] In at least one embodiment, the GPU(s) 1008 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, the GPU(s) 1008 may be programmable and may be efficient for parallel workloads. In at least one embodiment, the GPU(s) 1008 may use an enhanced tensor instruction set. In at least one embodiment, the GPU(s) 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-one ("L1") cache (e.g., an L1 cache with at least 96 KB of memory capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of memory capacity). In at least one embodiment, the GPU(s) 1008 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1008 may utilize one or more Compute Application Programming Interface(s) (API(s)). In at least one embodiment, the GPU(s) 1008 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0091] In at least one embodiment, one or more of the GPU(s) 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1008 may be fabricated on fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block could include 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g.,Warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0092] In at least one embodiment, one or more of the GPU(s) 1008 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or alternatively to the HBM memory, a synchronous graphics random access memory ("SGRAM") may be used, such as a type five double data rate synchronous graphics random access memory ("GDDR5").

[0093] In at least one embodiment, the GPU(s) 1008 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to enable the GPU(s) 1008 to directly access page tables of the CPU(s) 1006. In at least one embodiment, when a GPU of the memory management unit ("MMU") of the GPU(s) 1008 experiences a fault, an address translation request may be transmitted to the CPU(s) 1006. In response, two CPUs of the CPU(s) 1006, in at least one embodiment, may look in their page tables for a virtual-to-physical mapping for an address and transmit the translation back to the GPU(s) 1008.In at least one embodiment, the unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1006 and the GPU(s) 1008, thereby simplifying programming of the GPU(s) 1008 and porting applications to the GPU(s) 1008.

[0094] In at least one embodiment, the GPU(s) 1008 may include any number of access counters that may track the frequency of access by the GPU(s) 1008 to the memory of other processors. In at least one embodiment, the access counter(s) may help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving efficiency for memory shared between processors.

[0095] In at least one embodiment, one or more of the SoC(s) 1004 may include any number of cache(s) 1012, including those described herein. For example, in at least one embodiment, the cache(s) 1012 may include a level-three ("L3") cache available to both the CPU(s) 1006 and the GPU(s) 1008 (e.g., connected to the CPU(s) 1006 and the GPU(s) 1008). In at least one embodiment, the cache(s) 1012 may include a write-back cache that can track the states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0096] In at least one embodiment, one or more of the SoC(s) 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1008 and offload some tasks from the GPU(s) 1008 (e.g., to free up more cycles of the GPU(s) 1008 to perform other tasks). In at least one embodiment, the accelerator(s) 1014 could be configured for targeted workloads (e.g.,Perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are robust enough to be amenable to acceleration may be used. In at least one embodiment, a CNN may include a region-based or regional convolutional neural network ("RCNNs") and fast RCNNs (e.g., as used for object detection), or another type of CNN.

[0097] In at least one embodiment, the accelerator(s) 1014 (e.g., hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as inference.In at least one embodiment, the design of DLA(s) can provide more performance per millimeter than a typical general-purpose GPU and typically significantly exceeds the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, the DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety and / or security-related events.

[0098] In at least one embodiment, the DLA(s) may perform any function of GPU(s) 1008, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1008 for any function. For example, in at least one embodiment, a designer may focus the processing of CNNs and floating-point operations on DLA(s) and leave other functions to GPU(s) 1008 and / or accelerator(s) 1014.

[0099] In at least one embodiment, the accelerator(s) 1014 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system ("ADAS") applications 1038, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computing ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0100] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application-specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, RISC cores may include an instruction cache and / or tightly coupled RAM.

[0101] In at least one embodiment, DMA may enable components of the PVA to access system memory independently of the CPU(s) 1006. In at least one embodiment, DMA may support any number of features used to provide optimization for a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, a block width, a block height, a block depth, a horizontal block stride, a vertical block stride, and / or a depth stride.

[0102] In at least one embodiment, vector processors may be programmable processors that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

[0103] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image.In at least one embodiment, vector processors included in a particular PVA may concurrently execute different computer vision algorithms on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance overall system security.

[0104] In at least one embodiment, the accelerator(s) 1014 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example, and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may include an on-chip computer line of sight network that connects a PVA and a DLA to memory (e.g., using APB).

[0105] In at least one embodiment, an on-chip computer line of sight network may include an interface that determines that both a PVA and a DLA are ready and providing valid signals prior to transmitting any control signal / address / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0106] In at least one embodiment, one or more of the SoC(s) 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may include a real-time ray tracing hardware accelerator. An accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model) to generate real-time visualization simulations for radar signal interpretation, sound propagation synthesis and / or analysis, simulation of sonar systems, general wave propagation simulation, comparison with lidar data for localization and / or other functions, and / or for other uses.

[0107] In at least one embodiment, the accelerator(s) 1014 may have a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are a good match for algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA performs well on semi-dense or dense regular computation, even on small datasets, which might require predictable, low-latency, and low-power runtimes. In at least one embodiment, such as in vehicle 1000, PVAs could be designed to execute classical computer vision algorithms because they can be efficient at object detection and operating on integer mathematics.

[0108] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications use on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0109] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA may process raw radar data (e.g., using a 4D fast Fourier transform) to provide processed radar data. In at least one embodiment, a PVA is used for runtime depth processing, for example, by processing raw runtime data to provide processed runtime data.

[0110] In at least one embodiment, a DLA may be used to execute any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure allows a system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, a system may set a confidence threshold and consider only detections that exceed the threshold to be true positives.In an embodiment where an automatic emergency braking ("AEB") system is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may execute a neural network to reduce the confidence score. In at least one embodiment, the neural network may take as its input at least a subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), an output from one or more IMU sensors 1066 that correlates with the orientation of the vehicle 1000, a range, 3D position estimates of an object obtained from the neural network, and / or other sensors (e.g.,LIDAR sensor(s) 1064 or RADAR sensor(s) 1060), among others.

[0111] In at least one embodiment, one or more of the SoC(s) 1004 may include one or more data stores 1016 (e.g., memory). In at least one embodiment, the data stores 1016 may be on-chip memory of SoC(s) 1004 that may store neural networks to be executed on one or more GPU(s) 1008 and / or a DLA. In at least one embodiment, the data stores 1016 may be large enough in capacity to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data stores 1016 may include one or more L2 or L3 caches.

[0112] In at least one embodiment, one or more of the SoC(s) 1004 may include any number of processor(s) 1010 (e.g., embedded processors). In at least one embodiment, the processor(s) 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1004 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance with system low power state transitions, management of thermal and temperature sensors of SoC(s) 1004, and / or management of power states of SoC(s) 1004.In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1004 may use ring oscillators to sense temperatures of CPU(s) 1006, GPU(s) 1008, and / or accelerator(s) 1014. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1004 may use ring oscillators to sense temperatures of CPU(s) 1006, GPU(s) 1008, and / or accelerator(s) 1014. In at least one embodiment, if temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place SoC(s) 1004 into a lower power state.In at least one embodiment, the boot and power management processor may include one or more processors configured to control one or more processors to place the vehicle 1000 into a power saving mode and / or the vehicle 1000 into a chauffeur-driven mode.

[0113] In at least one embodiment, processor(s) 1010 may further include a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0114] In at least one embodiment, the processor(s) 1010 may further include an always-on processor engine that may provide necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0115] In at least one embodiment, the processor(s) 1010 may further include a security cluster engine, including, without limitation, a dedicated processor subsystem to handle security management for automotive applications. In at least one embodiment, a security cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a security mode, two or more cores, in at least one embodiment, may operate in a lockstep mode, functioning as a single core with comparison logic to detect differences between their operations.In at least one embodiment, the processor(s) 1010 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1010 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0116] In at least one embodiment, the processor(s) 1010 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on one or more wide-view cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensor(s) is / are preferably monitored by a neural network running on another instance of the SoC to identify in-cabin events and respond accordingly.In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain features are available to a driver when a vehicle is operating in an autonomous mode and are otherwise disabled.

[0117] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in a video, noise reduction appropriately weights spatial information, thereby reducing weights of information provided by neighboring frames. In at least one embodiment, when an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from a previous frame to reduce noise in a current frame.

[0118] In at least one embodiment, a video image compositor may also be configured to perform stereo dewarping on input stereo lens images. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is used, and one or more GPUs 1008 are not required to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are turned on and actively performing 3D rendering, a video image compositor may be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0119] In at least one embodiment, one or more of SoC(s) 1004 may further include a Mobile Industrial Processor Interface ("MIPI") serial camera interface for receiving video and inputs from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1004 may further include one or more input / output controllers that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0120] In at least one embodiment, one or more of SoC(s) 1004 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1004 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1064, RADAR sensor(s) 1060, etc., which may be connected via Ethernet channels), and data from the bus. In at least one embodiment, SoC(s) 1004 may further include one or more GNSS sensors 1058 (e.g.,connected via an Ethernet bus or a CAN bus), one or more cameras 1090, one or more cameras 1092, one or more cameras 1094, one or more cameras 1096, one or more cameras 1098, one or more cameras 10110, one or more cameras 10120, one or more cameras 10122, one or more In at least one embodiment, one or more of SoC(s) 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free the CPU(s) 1006 from routine data management tasks.

[0121] In at least one embodiment, SoC(s) 1004 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, SoC(s) 1004 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, accelerators 1014, when combined with CPU(s) 1006, GPU(s) 1008, and data storage(s) 1016, may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0122] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to perform a wide variety of processing algorithms over a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet performance requirements of many computer vision applications, such as those related to, for example, execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0123] Embodiments described herein enable multiple neural networks to be executed concurrently and / or sequentially and for results to be combined to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU(s) 1020) may include text and word recognition, enabling the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and providing a semantic understanding of a sign and passing that semantic understanding to path planning modules running on a CPU complex.

[0124] In at least one embodiment, multiple neural networks may be executed simultaneously, such as during Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Warning: Flashing lights indicate icy conditions" along with an electrical light may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably executing on a CPU complex) that if flashing lights are detected, icy conditions exist.In at least one embodiment, a flashing light may be identified by running a third deployed neural network over multiple images, informing a vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be executed concurrently, such as within a DLA and / or on one or more GPU(s) 1008.

[0125] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turn on lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, SoC(s) 1004 provide security against theft and / or carjacking.

[0126] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1004 use a CNN to classify ambient and urban noise, as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 1058.In at least one embodiment, if a CNN is operating in Europe, it will attempt to detect European sirens, and if it is operating in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow a vehicle, pull to one side of a road, park a vehicle, and / or idle a vehicle using ultrasonic sensor(s) 1062 until emergency vehicles pass by.

[0127] In at least one embodiment, the vehicle 1000 may include CPU(s) 1018 (e.g., discrete CPU(s) or dCPU(s)) that may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1018 may include, for example, an X86 processor. The CPU(s) 1018 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1004 and / or monitoring the status and health of controller(s) 1036 and / or an infotainment system on a chip (“Infotainment SoC”) 1030. In at least one embodiment, the SoC(s) 1004 include one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0128] In at least one embodiment, the vehicle 1000 may include GPU(s) 1020 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the GPU(s) 1020 may provide additional artificial intelligence functionality, such as by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of a vehicle 1000.

[0129] In at least one embodiment, the vehicle 1000 may further include a network interface 1024, which may include, without limitation, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1024 may be used to enable wireless connection to Internet cloud services (e.g., to server(s) and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct connection may be established between the vehicle 1000 and another vehicle and / or an indirect connection may be established (e.g., via networks and over the Internet).In at least one embodiment, direct connections may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide information to the vehicle 1000 about vehicles in the vicinity of the vehicle 1000 (e.g., vehicles in front of, to one side of, and / or behind the vehicle 1000). In at least one embodiment, such above-mentioned functionality may be part of a cooperative adaptive cruise control functionality of the vehicle 1000.

[0130] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality and enables the controller(s) 1036 to communicate over wireless networks. In at least one embodiment, the network interface 1024 may include a radio frequency front end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible manner. For example, frequency conversions could be performed by well-known processes and / or using superheterodyne processes. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip.In at least one embodiment, network interfaces may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0131] In at least one embodiment, the vehicle 1000 may further include one or more data stores 1028, which may include, but are not limited to, off-chip (e.g., off-SoC(s) 1004) memory. In at least one embodiment, the data stores 1028 may include, but are not limited to, one or more memory elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0132] In at least one embodiment, the vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, sensing, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, and without limitation, a GPS using a USB connector with an Ethernet-to-serial (e.g., RS-232) bridge.

[0133] In at least one embodiment, the vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, the RADAR sensor(s) 1060 may be used by the vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR sensor(s) 1060 may utilize a CAN bus and / or bus 1002 (e.g., to transmit data generated by the RADAR sensor(s) 1060 for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples). In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and among other things, the RADAR sensor(s) 1060 may be suitable for front, rear, and side RADAR use.In at least one embodiment, one or more sensors of RADAR sensor(s) 1060 is / are a pulse Doppler RADAR sensor.

[0134] In at least one embodiment, the RADAR sensor(s) 1060 may include different configurations, such as long range with narrow field of view, short range with wide field of view, ...B. within a range of 250 m (meters). In at least one embodiment, the RADAR sensor(s) 1060 may help distinguish between static and moving objects and may be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, the sensor(s) 1060 included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment, a central four-antenna array with six antennas may produce a focused beam pattern configured to record the surroundings of the vehicle 1000 at higher speeds with minimal interference from traffic in adjacent lanes.In at least one embodiment, two additional antennas may expand the field of view, making it possible to quickly detect vehicles entering or leaving a lane of the vehicle 1000.

[0135] In at least one embodiment, medium-range RADAR systems may include, for example, a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensors 1060 configured to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may generate two beams that continuously monitor blind spots in a rearward direction and alongside a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1038 for blind spot detection and / or lane change assistance.

[0136] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, the ultrasonic sensor(s) 1062, which may be positioned at a front, rear, and / or side location of the vehicle 1000, may be used for parking and / or for creating and updating an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different sensing ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1062 may operate at functional safety levels of ASIL B.

[0137] In at least one embodiment, the vehicle 1000 may include one or more LIDAR sensors 1064. In at least one embodiment, the LIDAR sensor(s) 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1064 may operate at ASIL B functional safety level. In at least one embodiment, the vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0138] In at least one embodiment, the LIDAR sensor(s) 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1064 may have an advertised range of approximately 100 m with an accuracy of 2 cm to 3 cm and with support for a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-prominent LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1064 may include a small device that may be embedded in a front, rear, side, and / or corner location of the vehicle 1000.In at least one embodiment, the LIDAR sensor(s) 1064 in such an embodiment may provide up to a 120-degree horizontal field of view and a 35-degree vertical field of view with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor(s) 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0139] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1000 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receiver that records the laser pulse time of flight and reflected light at each pixel, which in turn corresponds to a range from the vehicle 1000 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1000.In at least one embodiment, 3D flash lidar systems include, without limitation, a solid-state 3D staring array lidar camera with no moving parts other than a fan (e.g., a non-scanning lidar device). In at least one embodiment, the flash lidar device may use a 5-nanosecond Class I (eye-safe) laser pulse per image and may collect reflected laser light as a 3D range point cloud and simultaneously registered intensity data. In at least one embodiment, the flash lidar device may use a 5-nanosecond Class I (eye-safe) laser pulse per image and may collect reflected laser light as a 3D range point cloud and.

[0140] In at least one embodiment, the vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, the IMU sensor(s) 1066 may be located at a center of a rear axle of the vehicle 1000. In at least one embodiment, the IMU sensor(s) 1066 may include, for example, and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1066 may include, without limitation, accelerometer(s) and gyroscope(s). In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1066 may include, without limitation, accelerometer(s), gyroscope(s), and magnetometer(s).

[0141] In at least one embodiment, the IMU sensor(s) 1066 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1066 may enable the vehicle 1000 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to the IMU sensor(s) 1066. In at least one embodiment, the IMU sensor(s) 1066 and the GNSS sensor(s) 1058 may be combined into a single integrated unit.

[0142] In at least one embodiment, the vehicle 1000 may include one or more microphones 1096 placed in and / or around the vehicle 1000. In at least one embodiment, the microphone(s) 1096 may be used for, among other things, emergency vehicle detection and identification.

[0143] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including stereo camera(s) 1068, wide-view camera(s) 1070, infrared camera(s) 1072, surround camera(s) 1074, long-range camera(s) 1098, medium-range camera(s) 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of the vehicle 1000. In at least one embodiment, the type of cameras used depends on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1000. In at least one embodiment, a number of cameras employed may vary depending on the embodiment.For example, in at least one embodiment, vehicle 1000 could include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera could be configured as previously described with respect to . Fig. 10A and Fig. 10B will be described in more detail.

[0144] In at least one embodiment, the vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, the vibration sensor(s) 1042 may measure vibrations of components of the vehicle 1000, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a driven axle and a free-spinning axle).

[0145] In at least one embodiment, vehicle 1000 may include ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, among other things, an SoC in some examples. In at least one embodiment, ADAS system 1038 may include, among other things, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward collision warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keeping assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic alert (“RCTW”) system, a forward collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0146] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicles ahead. In at least one embodiment, a lateral ACC system performs follow-through and advises the vehicle 1000 to change lanes if necessary. In at least one embodiment, lateral ACC relates to other ADAS applications, such as LC and CW.

[0147] In at least one embodiment, a CACC system utilizes information from other vehicles that may be received via network interface 1024 and / or one or more wireless antennas 1026 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided through a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided through an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information from vehicles ahead of vehicle 1000 and has the potential to improve traffic flow smoothness and reduce congestion on the road.

[0148] In at least one embodiment, an FCW system is designed to warn a driver of a hazard so that such a driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is / are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, an FCW system can provide a warning, such as in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0149] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and may automatically apply braking if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may utilize one or more forward-facing cameras and / or one or more radar sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, that AEB system may automatically apply braking to prevent or at least mitigate the impact of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake assist and / or imminent collision braking.

[0150] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle crosses 1000 lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intended lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, an LKA system is a variation of an LDW system.In at least one embodiment, an LKA system provides steering inputs or braking to correct the vehicle 1000 when the vehicle 1000 begins to depart from its lane.

[0151] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile's blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may include rear-facing camera(s) and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0152] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside of a rear camera range when the vehicle 1000 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component.

[0153] In at least one embodiment, conventional ADAS systems may be prone to false positives, which may be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems warn a driver and allow that driver to decide whether a safety condition actually exists and act accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1000 itself decides whether to consider the result from a primary computer or a secondary computer (e.g., a first controller or a second controller of the controllers 1036). For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module.In at least one embodiment, a backup computer rationality monitor may execute redundant, diverse software on hardware components to detect errors in perceptual and dynamic driving tasks. In at least one embodiment, outputs from the ADAS system 1038 may be provided to a monitoring MCU. In at least one embodiment, when outputs from a primary computer and outputs from a secondary computer conflict, a monitoring MCU determines how to reconcile the conflict to ensure safe operation.

[0154] In at least one embodiment, a primary computer may be configured to provide a monitoring MCU with a confidence value indicating the confidence of that primary computer in a selected result. In at least one embodiment, if that confidence value exceeds a threshold, that monitoring MCU may follow the instruction of that primary computer regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, if a confidence value does not meet a threshold and if primary and secondary computers indicate different results (e.g., a conflict), a monitoring MCU may arbitrate between computers to determine an appropriate result.

[0155] In at least one embodiment, a monitoring MCU may be configured to execute neural network(s) trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural networks in a monitoring MCU may learn when the output of a secondary computer can be trusted and when it cannot. For example, in at least one embodiment, if that secondary computer is a radar-based FCW system, neural network(s) in that monitoring MCU may learn when an FCW system identifies metallic objects that are not actually hazards, such as a drainage grate or manhole cover, that trigger an alarm.In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU may learn to override LDW when cyclists or pedestrians are present and lane departure is actually a safest maneuver. In at least one embodiment, a monitoring MCU may include at least one of a DLA or a GPU capable of executing neural network(s) with associated memory. In at least one embodiment, a monitoring MCU may include and / or be included as a component of the SoC(s) 1004.

[0156] In at least one embodiment, ADAS system 1038 may include a secondary computer that performs ADAS functionality using conventional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision rules (if-then), and the presence of a neural network(s) in a supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementation and intended non-identity makes an overall system more fault-tolerant, particularly against errors caused by software (or software-hardware interface) functionality.For example, in at least one embodiment, if there is a software bug or error in the software executing on a primary computer and non-identical software code executing on a secondary computer provides a consistent overall result, a monitoring MCU may have greater confidence that an overall result is correct and a bug in the software or hardware on that primary computer does not cause a significant error.

[0157] In at least one embodiment, an output of the ADAS system 1038 may be fed into the perception block of a primary computer and / or the dynamic driving task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1038 displays a forward collision warning due to an immediately ahead object, a perception block may use this information in identifying objects. In at least one embodiment, a secondary computer may have its own neural network trained, thus reducing the risk of false positives, as described herein.

[0158] In at least one embodiment, the vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, among other things, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, among other things, a combination of hardware and software that may be used to provide the vehicle 1000 with audio (e.g., music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g.,Navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door opening / closing, air filter information, etc.). For example, the infotainment SoC 1030 could include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car putters, in-vehicle entertainment, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1030 may be further used to provide information (e.g.,visual and / or audible), such as information from the ADAS system 1038, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0159] In at least one embodiment, the infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via the bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a supervisory MCU so that a GPU of an infotainment system can perform some self-driving functions in the event that the primary controller(s) 1036 (e.g., primary and / or backup computers of the vehicle 1000) fail. In at least one embodiment, the infotainment SoC 1030 may place the vehicle 1000 into a chauffeur-in-safety stop mode, as described herein.

[0160] In at least one embodiment, the vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital instrument panel, an electronic instrument cluster, a digital dashboard, etc.). In at least one embodiment, the instrument cluster 1032 may include, among other things, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 1032 may include, among other things, any number and combination of a set of instruments such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, gear shift position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between the infotainment SoC 1030 and the instrument cluster 1032. In at least one embodiment, the instrument cluster 1032 may be included as part of the infotainment SoC 1030, or vice versa.

[0161] Fig. 10D is a diagram of a system for communication between cloud-based server(s) and the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, the system may include, among other things, server(s) 1078, network(s) 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, server(s) 1078 may include, among other things, a plurality of GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be connected to high-speed interconnects, such as, but not limited to, NVLink interfaces 1088 developed by NVIDIA and / or PCIe interconnects 1086.In at least one embodiment, GPUs 1084 are connected via an NVLink and / or NVSwitch SoC, and GPUs 1084 and PCIe switches 1082 are connected via PCIe connections. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1078 may include, among other things, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, the server(s) 1078 could each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0162] In at least one embodiment, the server(s) 1078 may receive, via the network(s) 1090 and from vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced roadwork. In at least one embodiment, the server(s) 1078 may transmit, via the network(s) 1090 and to vehicles, neural networks 1092, updated or otherwise, and / or map information 1094, including, but not limited to, information related to traffic and road conditions. In at least one embodiment, updates to the map information 1094 may include, but are not limited to, updates to the HD map 1022, such as information related to construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 1092 and / or map information 1094 may result from new training and / or experience represented in data received from any number of vehicles in an environment and / or may be based at least in part on training performed in a data center (e.g., using server(s) 1078 and / or other servers).

[0163] In at least one embodiment, the server(s) 1078 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles and / or may be generated in a simulation (e.g., using a gaming machine). In at least one embodiment, any amount of training data is labeled (e.g., if an associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if an associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g.,transmitted to vehicles via the network(s) 1090) and / or machine learning models may be used by the server(s) 1078 to remotely monitor vehicles.

[0164] In at least one embodiment, the server(s) 1078 may receive data from vehicles and apply data to real-time neural networks for intelligent real-time inference. In at least one embodiment, the server(s) 1078 may include deep learning supercomputers and / or dedicated AI computers powered by one or more GPU(s) 1084, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1078 may include a deep learning infrastructure using CPU-powered data centers.

[0165] In at least one embodiment, the deep learning infrastructure of server(s) 1078 may be capable of fast, real-time inference and may use this capability to assess and verify the health of processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a sequence of images and / or objects that vehicle 1000 has been located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by the vehicle 1000, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1000 is malfunctioning, the server(s) 1078 may send a signal to the vehicle 1000 instructing a fail-safe computer of the vehicle 1000 to take control, notify passengers, and complete a safe parking maneuver.

[0166] In at least one embodiment, the server(s) 1078 may include one or more GPU(s) 1084 and one or more programmable inference accelerators (e.g., TensorRT 3 devices from NVIDIA). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, such as when performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, one or more hardware structures 715 are used to perform one or more embodiments. Details regarding hardware structures 715 are described herein in connection with Fig. 7A and / or Fig. 7B provided. COMPUTER SYSTEMS

[0167] Fig. 11 is a block diagram illustrating an example computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1100 may include, but is not limited to, a component, such as a processor 1102, for employing execution units that include logic for performing algorithms on process data, according to the present disclosure, such as in the embodiment described herein.In at least one embodiment, computer system 1100 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1100 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0168] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of performing one or more instructions according to at least one embodiment.

[0169] In at least one embodiment, computer system 1100 may include, without limitation, a processor 1102, which may include, without limitation, one or more execution units 1108 to perform machine learning model training and / or reasoning according to techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computing ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor.In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0170] In at least one embodiment, processor 1102 may include, without limitation, a Level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may be external to processor 1102. Other embodiments may also include a combination of both internal and external caches depending on a particular implementation and requirements. In at least one embodiment, a register file 1106 may store various types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0171] In at least one embodiment, execution unit 1108, including without limitation logic for performing integer and floating-point operations, is also located in processor 1102. In at least one embodiment, processor 1102 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for handling a packed instruction set 1109. In at least one embodiment, by incorporating packed instruction set 1109 into an instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1102.In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across that processor's data bus to perform one or more operations one data item at a time.

[0172] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0173] In at least one embodiment, a system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, a system logic chip may include, without limitation, a memory control node ("MCH") 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage and for storing graphics commands, data, and textures. In at least one embodiment, MCH 1116 may route data signals between processor 1102, memory 1120, and other components in computer system 1100, and may bridge data signals between processor bus 1110, memory 1120, and a system I / O interface 1122.In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 may be coupled to memory 1120 via high-bandwidth memory path 1118, and a graphics / video card 1112 may be coupled to MCH 1116 via an accelerated graphics port ("AGP") connection 1114.

[0174] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary node interface bus to couple MCH 1116 to an I / O control node ("ICH") 1130. In at least one embodiment, ICH 1130 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102.Examples may include, without limitation, an audio controller 1129, a firmware node ("Flash BIOS") 1128, a wireless transceiver 1126, a data storage 1124, an alt I / O controller 1123 containing user input and keyboard interfaces 1125, a serial expansion port 1127, such as a Universal Serial Bus ("USB") port, and a network controller 1134. In at least one embodiment, the data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0175] In at least one embodiment, Fig. 11 a system that includes interconnected hardware devices or ‘chips’, whereas Fig. 11 may illustrate an exemplary SoC in other embodiments. In at least one embodiment, Fig. 11 may be connected using proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using Compute Express Link (CXL) interconnects.

[0176] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in computer system 1100 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0177] In at least one embodiment, computer system 1100 is used to at least partially implement panoramic imaging as in Fig. 1-6 illustrates.

[0178] Fig. 12 is a block diagram illustrating an electronic device 1200 for using a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0179] In at least one embodiment, electronic device 1200 may include, without limitation, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SM bus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-resolution audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 12 a system that includes interconnected hardware devices or ‘chips’, whereas Fig. 12 may illustrate an exemplary SoC in other embodiments. In at least one embodiment, Fig. 12 may be connected to proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 12 connected using Compute Express Link (CXL) connections.

[0180] In at least one embodiment, Fig. 12 a display 1224, a touchscreen 1225, a touchpad 1230, a near-field communication unit (“NFC”) 1245, a sensor node 1240, a thermal sensor 1246, an Express Chipset (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220, such as a solid-state disk (“SSD”) or a hard disk drive (“HDD”), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254, such as a USB 3.0 camera, and / or a low double data rate ("LPDDR") ("LPDDR3") memory device 1215, implemented, for example, in an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0181] In at least one embodiment, other components may be communicatively coupled to processor 1210 through components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor ("ALS") 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to sensor node 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and the touchpad 1230 may be communicatively coupled to the EC 1235. In at least one embodiment, speakers 1263, headphones 1264, and a microphone ("mic") 1265 may be communicatively coupled to an audio unit ("audio codec and class-D amplifier") 1262, which in turn may be communicatively coupled to the DSP 1260. In at least one embodiment, the audio unit 1262 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252, as well as the WWAN unit 1256, may be implemented in a next-generation form factor ("NGFF").

[0182] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in electronic device 1200 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0183] In at least one embodiment, the electronic device 1200 is used to implement at least partially panoramic imaging, as in Fig. 1-6 illustrates.

[0184] Fig. Figure 13 illustrates a computer system 1300 according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described in this disclosure.

[0185] In at least one embodiment, computer system 1300 includes, without limitation, at least one central processing unit ("CPU") 1302 connected to a communications bus 1310 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communications protocol(s). In at least one embodiment, computer system 1300 includes, without limitation, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem (“Network Interface”) 1322 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1300.

[0186] In at least one embodiment, computer system 1300 includes, without limitation, input devices 1308, a parallel processing system 1312, and display devices 1306, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is received from input devices 1308, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be arranged on a single semiconductor platform to form a processing system.

[0187] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in computer system 1300 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0188] In at least one embodiment, computer system 1300 is used to at least partially implement panoramic imaging as in Fig. 1-6 illustrates.

[0189] Fig. 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 includes, among other things, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, among other things, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, among other things, a server, a cloud instance, a laptop, and a desktop computer.

[0190] In at least one embodiment, the USB flash drive 1420 includes, among other things, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 may include, among other things, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 comprises an application-specific integrated circuit ("ASIC") optimized to perform any set and type of operations associated with machine learning.For example, in at least one embodiment, processing unit 1430 is a tensor processing unit ("TPC") optimized to perform inference operations for machine learning. In at least one embodiment, processing unit 1430 is a vision processing unit ("VPU") optimized to perform inference operations for machine vision and machine learning.

[0191] In at least one embodiment, the USB interface 1440 may be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic that enables the processing unit 1430 to connect to devices (e.g., the computer 1410) via the USB connector 1440.

[0192] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in computer system 1400 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0193] In at least one embodiment, computer system 1400 is used to at least partially implement panoramic imaging as in Fig. 1-6 illustrates.

[0194] Fig. 15A illustrates an example architecture in which a plurality of GPUs 1510(1)-1510(N) are communicatively coupled to a plurality of multi-core processors 1505(1)-1505(M) via high-speed interconnects 1540(1)-1540(N) (e.g., buses, point-to-point connections, etc.). In at least one embodiment, high-speed interconnects 1540(1)-1540(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.In at least one embodiment, one or more GPUs in a plurality of GPUs 1510(1) to 1510(N) include one or more graphics cores (also referred to simply as “cores”) 1800, as shown in FIGS. Fig. 18A and Fig. 18B. In at least one embodiment, one or more graphics cores 1800 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0195] In at least one embodiment, two or more of the GPUs 1510 are interconnected via high-speed interconnects 1529(1) through 1529(2), which may be implemented using similar or different protocols / connections than those used for high-speed interconnects 1540(1) through 1540(N). Likewise, two or more of the multi-core processors 1505 may be interconnected via a high-speed interconnect 1528, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between different Fig. 15A using similar protocols / connections (e.g., via a common interconnect structure).

[0196] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to a processor memory 1501(1) through 1501(M) via memory interconnects 1526(1) through 1526(M), respectively, and each GPU 1510(1) through 1510(N) is communicatively coupled to GPU memory 1520(1) through 1520(N) via GPU memory interconnects 1550(1) through 1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may use similar or different memory access technologies. For example, and not by way of limitation, the processor memories 1501(1) through 1501(M) and the GPU memories 1520 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memories (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of processor memory 1501 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0197] As described herein, various multi-core processors 1505 and GPUs 1510 may each be physically coupled to a particular memory 1501, 1520, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed across various physical memories. For example, processor memories 1501(1) through 1501(M) may each comprise 64 GB of system memory address space, and GPU memories 1520(1) through 1520(N) may each comprise 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0198] Fig. 15B illustrates additional details for a connection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an example embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed interconnect 1540 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1546 may be integrated on a package or die with the processor 1507.

[0199] In at least one embodiment, processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as "execution units"), each having a translation buffer ("TLB") 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components for executing instructions and processing data, not illustrated. In at least one embodiment, caches 1562A-1562D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included within caches 1562A-1562D and shared by sets of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are coupled to system memory 1514, which includes processor memories 1501(1) through 1501(M) of FIG. Fig. 15A may include.

[0200] In at least one embodiment, coherency for data and instructions stored in various caches 1562A through 1562D, 1556, and system memory 1514 is maintained via intercore communication over a coherency bus 1564. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry associated with it to communicate over the coherency bus 1564 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over the coherency bus 1564 to snoop cache accesses.

[0201] In at least one embodiment, a proxy circuit 1525 communicatively couples the graphics acceleration module 1546 to the coherence bus 1564, enabling the graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of the cores 1560A through 1560D. Specifically, in at least one embodiment, an interface 1535 provides a connection to the proxy circuit 1525 via the high-speed interconnect 1540, and an interface 1537 connects the graphics acceleration module 1546 to the high-speed interconnect 1540.

[0202] In at least one embodiment, an accelerator integration circuit 1536 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1531(1) to 1531(N) of the graphics acceleration module 1546. In at least one embodiment, the graphics processing engines 1531(1) to 1531(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1531(1) to 1531(N) of the graphics acceleration module 1546 includes one or more graphics cores 1800, as described in connection with the Fig. 18A and Fig. 18B. In at least one embodiment, graphics processing engines 1531(1) to 1531(N) may alternatively comprise various types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1546 may be a GPU with a plurality of graphics processing engines 1531(1) to 1531(N), or graphics processing engines 1531(1) to 1531(N) may be individual GPUs integrated on a common package, line card, or die.

[0203] In at least one embodiment, accelerator integration circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation buffer (TLB) (not shown) for caching virtual / effective to physical / real translations. In at least one embodiment, a cache 1538 may store instructions and data for efficient access by graphics processing engines 1531(1) through 1531(N).In at least one embodiment, data stored in cache 1538 and graphics memories 1533(1) to 1533(M) is maintained coherently with core caches 1562A to 1562D, 1556, and system memory 1514, possibly using a fetch unit 1544. As noted, this may be accomplished via proxy circuitry 1525 for cache 1538 and memories 1533(1) to 1533(M) (e.g., sending updates to cache 1538, updating cache 1538 with respect to modifications / accesses to cache lines on processor caches 1562A to 1562D, 1556, and receiving updates from cache 1538).

[0204] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1) through 1531(N), and a context management circuit 1548 manages thread contexts. For example, context management circuit 1548 may perform save and restore operations to save and restore contexts of different threads during context switches (e.g., when a first thread is saved and a second thread is saved so that a second thread can be executed by a graphics processing engine). For example, upon a context switch, context management circuit 1548 may save current register values ​​to a particular region in memory (e.g., identified by a context pointer). It may then restore register values ​​when returning to a context.In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0205] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1531 are translated by the MMU 1539 into real / physical addresses in system memory 1514. In at least one embodiment, accelerator integration circuitry 1536 supports multiple (e.g., 4, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is depicted in which resources of graphics processing engines 1531(1) through 1531(N) are shared among multiple applications or virtual machines (VMs).In at least one embodiment, resources may be divided into "slices" that are assigned to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0206] In at least one embodiment, accelerator integration circuitry 1536 operates as a bridge to a system for graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, accelerator integration circuitry 1536 may provide virtualization facilities for a host processor to manage the virtualization of graphics processing engines 1531(1) through 1531(N), interrupts, and memory management.

[0207] In at least one embodiment, each host processor can address these resources directly using an effective address value because hardware resources of graphics processing engines 1531(1) through 1531(N) are explicitly mapped to a real address space seen by host processor 1507. In at least one embodiment, a function of accelerator integration circuit 1536 is to physically separate graphics processing engines 1531(1) through 1531(N) so that they appear to a system as independent entities.

[0208] In at least one embodiment, one or more graphics memories 1533(1) through 1533(M) are each coupled to each of the graphics processing engines 1531(1) through 1531(N), and N = M. In at least one embodiment, the graphics memories 1533(1) through 1533(M) store instructions and data processed by each of the graphics processing engines 1531(1) through 1531(N). In at least one embodiment, the graphics memories 1533(1) through 1533(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0209] In at least one embodiment, biasing techniques may be used to reduce data traffic over high-speed interconnect 1540 to ensure that data stored in graphics memories 1533(1) through 1533(M) is data most frequently used by graphics processing engines 1531(1) through 1531(N) and preferably not used by cores 1560A through 1560D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 1531(1) through 1531(N)) within caches 1562A through 1562D, 1556, and system memory 1514.

[0210] Fig. 15C illustrates another exemplary embodiment in which accelerator integration circuitry 1536 is integrated within processor 1507. In this embodiment, graphics processing engines 1531(1) through 1531(N) communicate directly over high-speed interconnect 1540 with accelerator integration circuitry 1536 via interface 1537 and interface 1535 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1536 may perform similar operations to those described with respect to Fig. 15B, but possibly with higher throughput given their close proximity to the coherence bus 1564 and the caches 1562A to 1562D, 1556. In at least one embodiment, an accelerator integration circuit supports various programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1536 and programming models controlled by the graphics acceleration module 1546.

[0211] In at least one embodiment, graphics processing engines 1531(1) through 1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to graphics processing engines 1531(1) through 1531(N), thereby providing virtualization within a VM / partition.

[0212] In at least one embodiment, graphics processing engines 1531(1) through 1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1531(1) through 1531(N) to provide access by any operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 1531(1) through 1531(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize graphics processing engines 1531(1) through 1531(N) to provide access to any process or application.

[0213] In at least one embodiment, the graphics acceleration module 1546 or an individual graphics processing engine 1531(1)-1531(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1514 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when its context is registered with the graphics processing engine 1531(1)-1531(N) (that is, system software is invoked to add a process element to a linked list of process elements). In at least one embodiment, a lower 16-bit of a process handle may be an offset of a process element within a linked list of process elements.

[0214] Fig. 15D illustrates an example accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a specified portion of processing resources of accelerator integration circuitry 1536. In at least one embodiment, an application stores process elements 1583 in an effective address space 1582 within system memory 1514. In at least one embodiment, process elements 1583 are stored in response to GPU calls 1581 from applications 1580 executing on processor 1507. In at least one embodiment, a process element 1583 contains process state for the corresponding application 1580. In at least one embodiment, a work descriptor (WD) 1584 contained within process element 1583 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of an application.

[0215] In at least one embodiment, the graphics acceleration module 1546 and / or individual graphics processing engines 1531(1) through 1531(N) may be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing process states and sending a WD 1584 to a graphics acceleration module 1546 to start a job in a virtualized environment may be included.

[0216] In at least one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or a single graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1536 for an ownership partition, and an operating system initializes the accelerator integration circuit 1536 for an ownership process when the graphics acceleration module 1546 is assigned.

[0217] In operation, in at least one embodiment, a WD fetch unit 1591 in the accelerator integration slice 1590 fetches the next WD 1584, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in registers 1545 and used by the MMU 1539, the interrupt management circuit 1547, and / or the context management circuit 1548, as illustrated. For example, one embodiment of the MMU 1539 includes segment / page walkup circuitry for accessing segment / page tables 1586 within an OS virtual address space 1585. In at least one embodiment, the interrupt management circuit 1547 may process interrupt events 1592 received from the graphics acceleration module 1546.In at least one embodiment, when performing graphics operations, an effective address 1593 generated by a graphics processing engine 1531(1) to 1531(N) is translated into a real address by the MMU 1539.

[0218] In at least one embodiment, registers 1545 are duplicated for each graphics processing engine 1531(1) through 1531(N) and / or graphics acceleration module 1546 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1590. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialized Registers Register # Beschreibung 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0219] Registers that can be initialized by an operating system are shown in Table 2. Table 2 - Operating System Initialized Registers Register # Description 1 Procedure and thread identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[0220] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engines 1531(1) through 1531(N). In at least one embodiment, it contains all the information needed by a graphics processing engine 1531(1) through 1531(N) to perform work, or it may be a pointer to a memory location where an application has established a command queue for work to be performed.

[0221] Fig.15E illustrates additional details for an exemplary embodiment of a joint model. This embodiment includes a real hypervisor address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the real hypervisor address space 1598 is accessible via a hypervisor 1596 that virtualizes graphics acceleration engine engines for the operating system 1595.

[0222] In at least one embodiment, shared programming models enable all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1546. In at least one embodiment, there are two programming models where the graphics acceleration module 1546 is shared among multiple processes and partitions: shared time slices and shared graphics-driven partitions.

[0223] In at least one embodiment, in this model, the system hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, a graphics acceleration module 1546 supports virtualization through the system hypervisor 1596, where the graphics acceleration module 1546 may adhere to certain requirements, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, (2) an application's job request is guaranteed by the graphics acceleration module 1546 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1546 provides an ability to prevent a job from being processed, and (3) the graphics acceleration module 1546 must be guaranteed fairness between processes when operating in a controlled shared programming model.

[0224] In at least one embodiment, the application 1580 is required to make a system call to the operating system 1595 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value.In at least one embodiment, the WD is specifically formatted for the graphics acceleration module 1546 and may be in the form of an instruction of the graphics acceleration module 1546, an effective address pointer to a user-defined structure, an effective address pointer to a queue of instructions, or any other data structure to describe the work to be performed by the graphics acceleration module 1546.

[0225] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuitry 1536 (not shown) and graphics acceleration module 1546 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1596 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1583.In at least one embodiment, CSRP is one of the registers 1545 that contains an effective address of a region in the effective address space 1582 of an application for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or if a job is inhibited. In at least one embodiment, the context save / restore region may be pinned system memory.

[0226] Upon receiving a system call, the operating system 1595 may verify that the application 1580 has been registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the operating system 1595 then calls the hypervisor 1596 with information shown in Table 3. Table 3 - OS-to-Hypervisor call parameters parameter Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 A Logical Interrupt Service Number (LISN)

[0227] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 has been registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 in a linked list of process elements for a corresponding graphics acceleration module type 1546. In at least one embodiment, a process element may include information shown in Table 4.

[0304] Table 4 - Process element information Item # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 Ein Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Eine Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table, abgeleitet von Hypervisor-Aufrufparametern 9 Ein State Register (SR)-Wert 10 Eine Logical Partition ID (LPID) 11 Ein Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0228] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slices 1590 registers 1545.

[0229] As in Fig. 15F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1501(1) through 1501(N) and GPU memories 1520(1) through 1520(N). In this implementation, operations performed on GPUs 1510(1) through 1510(N) use a same virtual / effective memory address space to access processor memories 1501(1) through 1501(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1501(1), a second portion to second processor memory 1501(N), a third portion to GPU memory 1520(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1501 and GPU memories 1520, allowing each processor or GPU to access each physical memory with a virtual address associated with that memory.

[0230] In at least one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more of the MMUs 1539A-1539E ensures cache coherence between caches of one or more host processors (e.g., 1505) and GPUs 1510 and implements biasing techniques that indicate physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of the bias / coherence management circuitry 1594A-1594E in Fig. 15F, the bias / coherence circuit may be implemented within an MMU of one or more host processors 1505 and / or within the accelerator integration circuit 1536.

[0231] In one embodiment, GPU memories 1520 may be allocated as part of system memory and accessed using shared virtual memory (SVM) technology, but without incurring performance penalties associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 1520 to be accessed as system memory without expensive cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement enables host processor 1505 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies.In at least one embodiment, such conventional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overheads may be critical to the execution time of an offloaded computation. In at least one embodiment, in cases with significant streaming write memory traffic, for example, the cache coherence overhead may significantly reduce an effective write bandwidth seen by a GPU 1510. In at least one embodiment, operand facility efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of GPU offloading.

[0232] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at a memory page granularity) including 1 or 2 bits per GPU-bound memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1520 with or without a bias cache in a GPU 1510 (e.g., to cache frequently / recently used bias table entries). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0233] In at least one embodiment, a bias table entry associated with each access to GPU-bound memory 1520 is accessed prior to the actual GPU memory access, causing the following operations. In at least one embodiment, local requests from a GPU 1510 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1520. In at least one embodiment, local requests from a GPU that find their page in the host bias are forwarded to the processor 1505 (e.g., over a high-speed interconnect, as described herein). In at least one embodiment, requests from the processor 1505 that find a requested page in the host processor bias complete a request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1510. In at least one embodiment, a GPU may then transition a page to host processor bias if it is not currently using a page. In at least one embodiment, a page's bias state may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0234] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn invokes a GPU's device driver, which in turn sends a message (or a command descriptor to a queue) to a GPU instructing it to change a bias state and, for some transitions, performs a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from host processor 1505 bias to GPU bias, but is not used for an opposite transition.

[0235] In at least one embodiment, cache coherence is maintained by temporarily uncacheable GPU-biased pages by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by host processor 1505, and vice versa.

[0236] In at least one embodiment, one or more hardware structures 715 are used to perform one or more embodiments. Details regarding one or more hardware structures 715 may be described herein in connection with Fig. 7A and / or Fig. 7B are provided.

[0237] Fig. Figure 16 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0238] Fig. 16 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1600 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I22S / I22C controller 1640.In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, memory may be provided by a flash memory subsystem 1660 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0239] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in integrated circuit 1600 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0240] In at least one embodiment, system-on-chip integrated circuit 1600 is used to at least partially implement panoramic imaging, as described in Fig. 1-6 illustrates.

[0241] Fig. 17A to Fig. 17B illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0242] Fig. 17A to Fig. 17B are block diagrams illustrating example graphics processors for use within an SoC according to embodiments described herein. Fig. 17A illustrates an exemplary graphics processor 1710 of a system-on-chip integrated circuit that may be manufactured using one or more IP cores in accordance with at least one embodiment. Fig. Figure 17B illustrates an additional example graphics processor.

[0243] Example graphics processor 1740 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, graphics processor 1710 is Fig. 17A, a low-power graphics processor core. In at least one embodiment, the graphics processor 1740 is Fig. 17B, ​​a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1710, 1740 may be variants of the graphics processor 1610 of Fig. be 16.

[0244] In at least one embodiment, graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 may execute different shader programs via separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1715A-1715N use primitive and vertex data generated by the vertex processor 1705 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1715A-1715N are optimized to execute fragment shader programs, as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program, as provided in a Direct 3D API.

[0245] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In at least one embodiment, one or more MMU(s) 1720A-1720B provide a virtual-to-physical mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more cache(s) 1725A-1725B. In at least one embodiment, one or more MMU(s) 1720A-1720B may be synchronized with other MMUs within a system, including one or more MMUs that are synchronized with one or more application processor(s) 1605, image processors 1615, and / or video processors 1620 of Fig. 16, so that each processor 1605-1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect to other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection. In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F through 1755N-1, and 1755N), as shown in Fig. 17B, ​​which provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores may vary. In at least one embodiment, the graphics processor 1740 includes an intercore task manager 1745 acting as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are partitioned into image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0246] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in graphics processor 1710 and / or 1740 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0247] In at least one embodiment, graphics processor 1710 is used to at least partially implement panoramic imaging, as in Fig. 1-6 illustrates.

[0248] Fig. 18A to Fig. 18B illustrate additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, components described in Fig. 18A to Fig. 18B and described in connection therewith, are integrated into a single system, such as a graphics processing unit (GPU), an SoC, or other type of processor. Fig. 18A illustrates a graphics core 1800 included in at least one embodiment in the graphics processor 1610 of Fig. 16 and in at least one embodiment, a unified shader core 1755A -1755N as in Fig. 17B can be. Fig. 18B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1830, which in at least one embodiment is suitable for deployment on a multi-chip module. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes a graphics core 1800, e.g., to form an integrated circuit and / or to form an SoC, such integrated circuit and / or SoC performing operations described herein.

[0249] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820 (e.g., including L1, L2, L3, last-level cache, or other caches) that are common execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to the graphics core 1800. In at least one embodiment, the slices 1801A-1801N have sub-slices that are part of a slice 1801A-1801N. In at least one embodiment, slices 1801A-1801N are independent of other slices or dependent on other slices.In at least one embodiment, slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler (sequencer) 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFUs 1812A-1812N), floating-point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address calculation units (ACUs 1813A-1813N), double-precision floating-point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N). In at least one embodiment, MPUs 1817A-1817N are referred to as matrix engines.

[0250] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice includes a specified portion of processing resources of a processing unit, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0251] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1801A-1801N). In at least one embodiment, a ray tracing unit computes ray tracing, triangle crossing, bounding box crossing, or other ray tracing operations.

[0252] In at least one embodiment, one or more slices 1801A-1801N include a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0253] In at least one embodiment, one or more slices 1801A-1801N are connected to L2 cache and memory fabric, interconnects, high-bandwidth memory (HBM) stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1801A-1801N include one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector machines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g.according to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in vector graphic format (e.g., shape) and converting it to a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 1801A-1801N includes a memory structure, e.g., an L2 cache.

[0254] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations.In at least one embodiment, the MPUs 1817-1817N may perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general purpose matrix-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1812A-1812N may perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0255] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in graphics core 1800 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0256] In at least one embodiment, the graphics core 1800 includes an interconnect and an interconnect fabric sublayer tied to a switch and a GPU-GPU bridge that enables multiple graphics processors 1800 (e.g., 8) to be interconnected without gluing together, with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0257] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected with an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes a compute tile, a memory tile (e.g., where a memory tile may be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, an interconnect tile, and an EMIB tile, all of which tiles are packaged together as part of a GPU in the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 1800, an L1 cache; and a base tile may include a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, an 8-connect, 8-port interconnect tile with an embedded switch. In at least one embodiment, tiles are connected by face-to-face (F2F) chip-on-chip bonding through finely spaced 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1800 includes a memory structure that includes memory and is a tile accessible by multiple tiles. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process continues, and where a hardware context represents a state of the hardware (e.g.,the state of a GPU).

[0258] In at least one embodiment, the graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream or converts a parallel data stream to a serial data stream.

[0259] In at least one embodiment, the graphics core 1800 includes a coherent unified high-speed fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and connected GPUs through an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0260] In at least one embodiment, the graphics core 1800 implements an API, where the API abstracts hardware of the graphics core 1800 and accesses libraries of instructions for performing mathematical operations (e.g., mathematical core library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis library, and / or ray tracing operations.

[0261] In at least one embodiment, graphics core 1800 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0262] Fig. 18B illustrates a GPGPU 1830 that can be configured to enable highly parallel computational operations performed by an array of graphics processing units in at least one embodiment. In at least one embodiment, the GPGPU 1830 can be directly linked with other instances of the GPGPU 1830 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communication interface or communication fabric.In at least one embodiment, GPGPU 1830 receives instructions from a host processor and uses a global scheduler 1834 (which may be referred to as a thread sequencer and / or an asynchronous computing engine) to dispatch execution threads associated with those instructions to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H utilize a cache 1838. In at least one embodiment, cache 1838 may serve as a higher-level cache for caches within compute clusters 1836A-1836H. In at least one embodiment, GPGPU 1830 is part of an SoC, such as part of integrated circuit 1600 (. Fig. 16).

[0263] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR).

[0264] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as the graphics core 1800 of Fig. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0265] In at least one embodiment, multiple instances of GPGPU 1830 may be configured to operate as a compute cluster. In at least one embodiment, the communication used by compute clusters 1836A-1836H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU interconnect 1840 that enables direct connection to other instances of GPGPU 1830. In at least one embodiment, GPU interconnect 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830.In at least one embodiment, GPU interconnect 1840 couples to a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 reside in separate computing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU interconnect 1840 may be configured to enable connection to a host processor in addition to, or alternatively to, host interface 1832.

[0266] In at least one embodiment, the GPGPU 1830 may be configured to train neural networks. In at least one embodiment, the GPGPU 1830 may be used within an inference platform. In at least one embodiment where the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H than when the GPGPU 1830 is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1844A-1844B may differ between inference and training configurations, with higher bandwidth memory technologies dedicated to training configurations. In at least one embodiment, an inference configuration of the GPGPU 1830 may support inference determinations.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.

[0267] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in GPGPU 1830 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0268] In at least one embodiment, the GPGPU 1830 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0269] Fig. 19 is a block diagram illustrating a computer system 1900 according to at least one embodiment. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory node 1905. In at least one embodiment, the memory node 1905 may be a separate component within a chipset component or may be integrated with one or more processors 1902. In at least one embodiment, the memory node 1905 couples to an I / O subsystem 1911 via a communications link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O node 1907 that may enable the computer system 1900 to receive input from one or more input devices 1908.In at least one embodiment, I / O node 1907 may enable a display controller, which may be included in one or more processors 1902, to provide outputs to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled to I / O node 1907 may include a local, internal, or embedded display device.

[0270] In at least one embodiment, processing subsystem 1901 includes one or more parallel processors 1912 coupled to storage node 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1912 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as an integrated multiple core (MIC) processor.In at least one embodiment, some or all of the parallel processor(s) 1912 may form a graphics processing subsystem that may output pixels to one or more display devices 1910A coupled via the I / O node 1907. In at least one embodiment, the parallel processor(s) 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor(s) 1912 include one or more cores, such as the graphics cores 1800 discussed herein.

[0271] In at least one embodiment, a system storage unit 1914 may connect to the I / O node 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface mechanism to enable connections between the I / O node 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919 that may be integrated into the platform, and various other devices that may be added via one or more add-on devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 1919 may include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0272] In at least one embodiment, the computing system 1900 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I / O node 1907. In at least one embodiment, communication paths connecting various components in Fig. 19 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect or interconnect protocols.

[0273] In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and represent a graphics processing unit (GPU), e.g., the parallel processor(s) 1912 include the graphics core 1800. In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 1912, the memory node 1905, the processor(s) 1902, and the I / O node 1907 may be integrated into a system-on-chip (SoC) integrated circuit.In at least one embodiment, components of computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0274] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in computing system 1900 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0275] In at least one embodiment, computing system 1900 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates. PROCESSORS

[0276] Fig. 20A illustrates a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is a variant of one or more parallel processors 1912 described in Fig. 19, according to an exemplary embodiment. In at least one embodiment, a parallel processor 2000 includes one or more graphics cores 1800.

[0277] In at least one embodiment, parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 may be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects to other devices using a node or switch interface, such as a storage node 2005. In at least one embodiment, connections between storage node 2005 and I / O unit 2004 form a communication link 2013.In at least one embodiment, the I / O device 2004 connects to a host interface 2006 and a memory crossbar 2016, where the host interface 2006 receives commands directed to performing processing operations and the memory crossbar 2016 receives commands directed to performing memory operations.

[0278] In at least one embodiment, when the host interface 2006 receives a command buffer via the I / O unit 2004, the host interface 2006 may forward work operations to a front end 2008 to perform those commands. In at least one embodiment, the front end 2008 couples to a scheduler 2010 (which may be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster assembly 2012. In at least one embodiment, the scheduler 2010 ensures that the processing cluster assembly 2012 is properly configured and in a valid state before dispatching tasks to a cluster of the processing cluster assembly 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 2012. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2012 via one of several graphics processing paths. In at least one embodiment, workloads may then be automatically distributed across the processing cluster array 2012 by the logic of the scheduler 2010 within a microcontroller that includes the scheduler 2010.

[0279] In at least one embodiment, the processing cluster arrangement 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2014A-2014N of the processing cluster arrangement 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may assign work to the clusters 2014A-2014N of the processing cluster arrangement 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each type of program or computation.In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010 or may be partially assisted by compiler logic during compilation of program logic configured for execution by the processing cluster arrangement 2012. In at least one embodiment, different clusters 2014A-2014N of the processing cluster arrangement 2012 may be assigned to process different types of programs or to perform different types of computations.

[0280] In at least one embodiment, processing cluster assembly 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster assembly 2012 is configured to perform parallel, general-purpose computing operations. For example, in at least one embodiment, processing cluster assembly 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0281] In at least one embodiment, the processing cluster assembly 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster assembly 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tiling logic and other vertex processing logic. In at least one embodiment, the processing cluster assembly 2012 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tile shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing.In at least one embodiment, data transferred during processing may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0282] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide a processing workload into approximately equal-sized tasks to better facilitate the distribution of graphics processing operations across multiple clusters 2014A-2014N of the processing cluster assembly 2012. In at least one embodiment, portions of the processing cluster assembly 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tiling and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in buffers to enable intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0283] In at least one embodiment, processing cluster assembly 2012 may receive processing tasks to be executed via scheduler 2010, which receives commands defining processing tasks from frontend 2008. In at least one embodiment, processing tasks may include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 2010 may be configured to retrieve indices corresponding to tasks or may receive indices from frontend 2008.In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster arrangement 2012 is configured to a valid state before initiating a workload specified by incoming command buffers (e.g., stack buffers, push buffers, etc.).

[0284] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may couple to a parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via memory crossbar 2016, which may receive memory requests from processing cluster assembly 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, memory interface 2018 may include multiple partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), each of which may couple to a portion (e.g., a memory unit) of parallel processor memory 2022.In at least one embodiment, a number of partition units 2020A-2020N is configured to be equal to a number of storage units, such that a first partition unit 2020A has a corresponding first storage unit 2024A, a second partition unit 2020B has a corresponding storage unit 2024B, and an Nth partition unit 2020N has a corresponding Nth storage unit 2024N. In at least one embodiment, a number of partition units 2020A-2020N may not be equal to a number of storage units.

[0285] In at least one embodiment, the memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR). In at least one embodiment, the memory units 2024A-2024N may also include stacked 3D memory, including, but not limited to, high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored via the memory units 2024A-2024N, allowing the partition units 2020A-2020N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022.In at least one embodiment, a local instance of parallel processor memory 2022 may be eliminated in favor of a unified memory design that uses system memory in conjunction with local cache memory.

[0286] In at least one embodiment, each of the clusters 2014A-2014N of the processing cluster arrangement 2012 may process data written to each of the memory units 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 may be configured to transfer an output of each cluster 2014A-2014N to each partition unit 2020A-2020N or to another cluster 2014A-2014N that may perform additional processing operations on an output. In at least one embodiment, each cluster 2014A-2014N may communicate with the memory interface 2018 via the memory crossbar 2016 to read from or write to various external storage devices.In at least one embodiment, the memory crossbar 2016 has a connection to the memory interface 2018 to communicate with the I / O device 2004, as well as a connection to a local instance of the parallel processor memory 2022, which allows processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to the parallel processing unit 2002. In at least one embodiment, the memory crossbar 2016 may use virtual channels to separate traffic flows between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0287] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld PCs, servers, workstations, game consoles, and / or embedded systems.

[0288] Fig. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of Fig. 20A. In at least one embodiment, partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, L2 cache 2021 is a read / write cache configured to perform load and store operations received from memory crossbar 2016 and ROP 2026. In at least one embodiment, read misses and urgent writeback requests are issued by L2 cache 2021 to frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 2025 for processing. In at least one embodiment, frame buffer interface 2025 interfaces with one of the memory units in parallel processor memory, such as memory units 2024A-2024N of Fig. 20A (e.g. within the parallel processor memory 2022).

[0289] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, a type of compression performed by ROP 2026 may vary based on statistical properties of data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0290] In at least one embodiment, the ROP 2026 is within each processing cluster (e.g., clusters 2014A-2014N of Fig. 20A) rather than within the partition unit 2020. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted via the memory crossbar 2016. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1910 of Fig. 19, indicated, passed for further processing by the processor(s) 1902 or for further processing by one of the processing entities within the parallel processor 2000 of Fig. 20A.

[0291] Fig. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2014A-2014N of Fig. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issuing techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters.

[0292] In at least one embodiment, the operation of the processing cluster 2014 may be controlled by a pipeline manager 2032 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of Fig. 20A and manages the execution of these instructions via a graphics multiprocessor 2034 and / or a texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may comprise one or more instances of the graphics multiprocessor 2034. The graphics multiprocessor 2034 may be included within a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed via the data crossbar 2040.

[0293] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, in which new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0294] In at least one embodiment, instructions transferred to processing cluster 2014 represent a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within a graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2034.In at least one embodiment, when a thread group contains fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is processing. In at least one embodiment, a thread group may also contain more threads than a number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when a thread group contains more threads than a number of processing engines within the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2034.

[0295] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache. The multiprocessor 2034 may forgo an internal cache and use a cache (e.g., L1 cache 2048) within the processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 also has access to L2 caches within partition units (e.g., partition units 2020A-2020N of Fig. 20A) that are shared by all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034 and can share common instructions and data that can be stored in L1 cache 2048.

[0296] In at least one embodiment, each processing cluster 2014 may include a memory management unit (MMU) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside within the memory interface 2018 of Fig. 20A. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, the MMU 2045 may include address translation buffers (TLBs) or caches that may be located within the graphics multiprocessor 2034 or the L1 2048 cache or the processing cluster 2014. In at least one embodiment, a physical address is processed to distribute surface data access locally to enable efficient request interleaving between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0297] In at least one embodiment, a processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2034 issues processed tasks to the data crossbar 2040 to provide a processed task to another processing cluster 2014 for further processing or to store a processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2016.In at least one embodiment, a pre-ROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and route data to ROP units that may be located with partition units as described herein (e.g., partition units 2020A-2020N of FIG. Fig. 20A). In at least one embodiment, the pre-ROP 2042 unit may perform optimizations for color mixing, organizing pixel color data, and performing address translations.

[0298] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in graphics processing cluster 2014 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0299] In at least one embodiment, parallel processor 2000 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0300] Fig. 20D illustrates a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, where one or more load / store units 2066 may perform load / store operations to load / store instructions according to the performance of an operation.In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to the cache memory 2072 and the shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU cores 2062 are part of an SoC, such as part of the integrated circuit 1600 in FIG. Fig. 16.

[0301] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched for execution by an instruction unit 2054. In at least one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread of the thread group is assigned to a different execution unit within GPGPU cores 2062. In at least one embodiment, an instruction may access any of a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2056 may be used to translate addresses in a unified address space into a unique memory address that may be accessed by load / store units 2066.

[0302] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2062, load / store units 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is partitioned between each of the functional units such that each functional unit is assigned a dedicated portion of register file 2058. In at least one embodiment, register file 2058 is partitioned between different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2034.

[0303] In at least one embodiment, the GPGPU cores 2062 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of the GPGPU cores 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs may implement floating-point arithmetic according to the IEEE 754-2008 standard or enable variable-precision floating-point arithmetic.In at least one embodiment, graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2062 may also include fixed-function or special-function logic.

[0304] In at least one embodiment, GPGPU cores 2062 include SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 2062 may physically execute instructions from SIMD4, SIMD8, and SIMD16, and logically execute instructions from SIMD1, SIMD2, and SIMD32. In at least one embodiment, SIMD instructions for GPGPU cores may be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single-program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may execute via a single SIMD instruction.For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0305] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to the register file 2058 and to the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that enables the load / store unit 2066 to implement load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 may operate at the same frequency as the GPGPU cores 2062, so that data transfer between the GPGPU cores 2062 and the register file 2058 may have very low latency.In at least one embodiment, shared memory 2070 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2034. For example, in at least one embodiment, cache 2072 may be used as a data cache to cache texture data communicated between the functional units and texture unit 2036. In at least one embodiment, shared memory 2070 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2062 may programmatically store data within shared memory in addition to automatically cached data stored in cache 2072.

[0306] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC includes a parallel processor or GPGPU, as described herein, with the parallel processor or GPGPU executing on the SoC. In at least one embodiment, a GPU may be integrated as cores on a package or chip and communicatively coupled to cores via an internal processor bus / interconnect within a package or chip.In at least one embodiment, processor cores may, regardless of how a GPU is connected, allocate work to such a GPU in the form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, that GPU then uses dedicated circuitry / logic to efficiently process those commands / instructions.

[0307] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in graphics multiprocessor 2034 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0308] In at least one embodiment, graphics multiprocessor 2034 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0309] Fig. 21 illustrates a multi-GPU computing system 2100 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2100 may include a processor 2102 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, GPGPUs 2106A-D may be interconnected via a set of high-speed, point-to-point GPU-to-GPU interconnects 2116. In at least one embodiment, GPU-to-GPU interconnects 2116 connect to each of the GPGPUs 2106A-D via a dedicated GPU interconnect. In at least one embodiment, P2P GPU connections 2116 enable direct communication between each of the GPGPUs 2106A-D without requiring communication over the host interface bus 2104 to which the processor 2102 is connected.In at least one embodiment, host interface bus 2104 remains available with GPU-to-GPU traffic directed to P2P GPU connections 2116 for system memory access or to communicate with other instances of multi-GPU computing system 2100, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2106A-D are connected to processor 2102 via host interface switch 2104, in at least one embodiment, processor 2102 includes direct support for P2P GPU connections 2116 and can connect directly to GPGPUs 2106A-D. In at least one embodiment, GPGPUs 2106A-D are part of an SoC, such as part of integrated circuit 1600 in FIG. Fig. 16, wherein GPGPUs 2106A-D perform operations described herein.

[0310] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 may be used in multi-GPU computing system 2100 to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0311] In at least one embodiment, the multi-GPU computer system 2100 includes one or more graphics cores 1800.

[0312] In at least one embodiment, computer system 2100 is used to at least partially implement panoramic imaging as in Fig. 1-6 illustrates.

[0313] Fig. 22 is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipelined front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors integrated into a multi-core processing system. In at least one embodiment, graphics processor 2200 includes graphics core 1800.

[0314] In at least one embodiment, graphics processor 2200 receives batches of commands via ring interconnect 2202. In at least one embodiment, incoming commands are interpreted by a command streamer 2203 in pipeline front end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2280A-2280N. In at least one embodiment, command streamer 2203 provides commands to geometry pipeline 2236 for 3D geometry processing commands. In at least one embodiment, command streamer 2203 provides commands to a video front end 2234 coupled to media engine 2237 for at least some media processing commands.In at least one embodiment, media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing and a multi-format encoder / decoder (MFX) 2233 engine to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 2236 and media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280.

[0315] In at least one embodiment, graphics processor 2200 includes scalable threaded execution resources with graphics cores 2280A-2280N (which may be modular and are sometimes referred to as core slices), each having a plurality of subcores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 may include any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A with at least a first subcore 2250A and a second subcore 2260A. In at least one embodiment, graphics processor 2200 is a low-performance processor with a single subcore (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes a plurality of graphics cores 2280A-2280N, each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N.In at least one embodiment, each subcore in the first subcores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each subcore in the second subcores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each subcore 2250A-2250N, 2260A-2260N utilizes a set of shared resources 2270A-2270N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic. In at least one embodiment, graphics processor 2200 includes load / store units in the pipeline front end 2204.

[0316] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, logic 715 in graphics processor 2200 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0317] In at least one embodiment, graphics processor 2200 is used to at least partially implement panoramic imaging, as in Fig. 1-6 illustrates.

[0318] Fig. 23 is a block diagram illustrating a microarchitecture for a processor 2300 that may include logic circuitry to perform instructions according to at least one embodiment. In at least one embodiment, processor 2300 may execute instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2300 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point form, may operate on packed data elements accompanying single-instruction, multiple-data ("SIMD"), and streaming SIMD extension ("SSE") instructions.In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, processor 2300 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0319] In at least one embodiment, processor 2300 includes an in-order front end ("front end") 2301 to fetch instructions to be executed and prepare instructions to be used later in a processor pipeline. In at least one embodiment, front end 2301 may include multiple units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and issues instructions from memory. Instructions are provided to an instruction decoder 2328, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2328 decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also referred to as "micro-ops" or "uops" or "µ-ops"), that a machine may execute.In at least one embodiment, instruction decoder 2328 parses an instruction into an opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2330 can assemble decoded uops into program-ordered sequences or traces in a uop queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, a microcode ROM 2332 provides uops needed to complete an operation.

[0320] In at least one embodiment, some instructions may be converted into a single microop, while others may require multiple microops to complete the entire operation. In at least one embodiment, if more than four microops are required to complete an instruction, instruction decoder 2328 may access microcode ROM 2332 to perform that instruction. In at least one embodiment, an instruction may be decoded into a small number of microops for processing at instruction decoder 2328. In at least one embodiment, an instruction may be stored within microcode ROM 2332 if a number of microops are required to perform such an operation.In at least one embodiment, trace cache 2330 refers to a programmable entry point logic array ("PLA") for determining a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2332 according to at least one embodiment. In at least one embodiment, after microcode ROM 2332 finishes sequencing microops for an instruction, a machine's front end 2301 may continue retrieving microops from trace cache 2330.

[0321] In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 2303 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic includes a number of buffers to smooth and reorder the flow of instructions to optimize performance as they proceed down a pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2303 includes, without limitation, an arbiter / register renamer 2340, a memory uop queue 2342, an integer / floating point uop queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general floating point scheduler (“slow / general FP scheduler”) 2304, and a simple floating point scheduler (“simple FP scheduler”) 2306.In at least one embodiment, the fast scheduler 2302, the slow / general floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to herein as "uop schedulers 2302, 2304, 2306." In at least one embodiment, the arbiter / register renamer 2340 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, the arbiter / register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, the arbiter / register renamer 2340 also allocates an entry for each uop in one of two uop queues, the memory uop queue 2342 for memory operations and the integer / floating point uop queue 2344 for non-memory operations, prior to the memory scheduler 2346 and the uop schedulers 2302, 2304, 2306.In at least one embodiment, the uop schedulers 2302, 2304, 2306 determine when a uop is ready for execution based on the readiness of their dependent input register operand sources and the availability of execution resources that uops require to complete their operation. In at least one embodiment, the fast scheduler 2302 can schedule on each half of a main clock cycle, while the slow / general floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2302, 2304, 2306 arbitrate dispatch ports to schedule uops for execution.

[0322] In at least one embodiment, execution block 2311 includes, without limitation, an integer register file / bypass network 2308, a floating point register file / bypass network ("FP register file / bypass network") 2310, address generation units ("AGUs") 2312 and 2314, fast arithmetic logic units (ALUs) ("Fast ALUs") 2316 and 2318, a slow arithmetic logic unit ("Slow ALU") 2320, a floating point ALU ("FP") 2322, and a floating point move unit ("FP move") 2324. In at least one embodiment, integer register file / bypass network 2308 and floating point register file / bypass network 2310 are also referred to herein as "register files 2308, 2310." In at least one embodiment, the AGUs 2312 and 2314, the fast ALUs 2316 and 2318, the slow ALU 2320, the floating point ALU 2322, and the floating point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324."

[0323] In at least one embodiment, register networks 2308, 2310 may be disposed between uop schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2310 performs floating-point operations. In at least one embodiment, each of register networks 2308, 2310 may include, without limitation, a bypass network that may bypass currently executing bypass operations or forward completed results that have not yet been written to a register file to new dependent uops. In at least one embodiment, register networks 2308, 2310 may communicate data with each other.In at least one embodiment, the integer register file / bypass network 2308 may include, without limitation, two separate register files, one register file for 32 low-order data bits and a second register file for 32 high-order data bits. In at least one embodiment, the floating-point register file / bypass network 2310 may include, without limitation, 128-bit wide entries, as floating-point instructions typically have operands 64 to 128 bits wide.

[0324] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register networks 2308, 2310 store integer and floating-point data operand values ​​that microinstructions must execute. In at least one embodiment, processor 2300 may include, among other things, any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2322 may include, among other things, a 64-bit by 64-bit floating point divider to perform division, square root, and remainder micro-ops.In at least one embodiment, instructions involving a floating-point value may be handled with floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2316, 2318. In at least one embodiment, the fast ALUs 2316, 2318 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations are passed to the slow ALU 2320, as the slow ALU 2320 may include, among other things, integer execution hardware for long-latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2312, 2314.In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 may be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2322 and the floating-point move unit 2324 may be implemented to support a range of operands with bits of different widths, such as 128-bit packed data operands in conjunction with SIMD and multimedia instructions.

[0325] In at least one embodiment, uop schedulers 2302, 2304, 2306 dispatch dependent operations before a parent load has completed execution. In at least one embodiment, if uops can be speculatively scheduled and executed in processor 2300, processor 2300 may also include logic to handle memory misses. In at least one embodiment, if a data load fails in a data cache, there may be dependent operations in flight in a pipeline that have exited a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks instructions that use incorrect data and reexecutes them. In at least one embodiment, dependent operations may need to be replayed, and independent ones may be allowed to complete.In at least one embodiment, the scheduler and a replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations. In at least one embodiment, the scheduler and a replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0326] In at least one embodiment, "registers" may refer to on-board processor memory locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside a processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, a register may store data, provide data, and perform functions described herein.In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0327] In at least one embodiment, processor 2300 or each core of processor 2300 includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., corresponding to operations or API calls), one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing instructions, one or more micro-operation (µOP) caches for storing

[0328] In at least one embodiment, processor 2300 or each core of ... Core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core ofProcessor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 or each core of processor 2300 In at least one embodiment, processor 2300 may access, use, perform, or execute instructions corresponding to invoking an API. In at least one embodiment, processor 2300 includes one or moreUltrapath interconnects (UPIs), e.g., this is a point-to-point processor interconnect; one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, processor 2300 includes a shared last-level cache (LLC) coupled to one or more memory controllers that can enable shared memory access across processor cores.

[0329] In at least one embodiment, processor 2300 or a core of processor 2300 comprises a mesh architecture in which processor cores, on-chip caches, memory controllers, and I / O controllers are organized into rows and columns, with wires and switches connecting them at each intersection to enable rotations. In at least one embodiment, processor 2300 comprises one or more higher bandwidth memory blocks (HMBs, e.g., HMBe) for storing data or cache data, e.g., in double data rate 5 synchronous dynamic random access memory (DDR5 SDRAM). In at least one embodiment, one or more components of processor 2300 are interconnected using Compute Express Link (CXL) interconnects. In at least one embodiment, a memory controller uses a least recently used (LRU) approach to determine what is stored in a cache.In at least one embodiment, processor 2300 includes one or more PCIe (e.g., PCIe 5.0).

[0330] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, portions or all of logic 715 may be incorporated in execution block 2311 and other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs illustrated in execution block 2311. Furthermore, weighting parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of execution block 2311 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0331] In at least one embodiment, processor 2300 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0332] Fig. 24 illustrates a deep learning application processor 2400 according to at least one embodiment. In at least one embodiment, deep learning application processor 2400 uses instructions that, when executed by deep learning application processor 2400, cause deep learning application processor 2400 to perform some or all of the processes and techniques described in this disclosure. In at least one embodiment, deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, application processor 2400 performs matrix multiplication operations either as a result of performing one or more instructions or both "hard-wired" in hardware.In at least one embodiment, deep learning application processor 2400 includes, without limitation, processing clusters 2410(1)-2410(12), inter-chip links (“ICLs”) 2420(1)-2420(12), inter-chip controllers (“ICCs”) 2430(1)-2430(2), high-bandwidth memory second generation (“HBM2”) 2440(1)-2440(4), memory controllers (“Mem Ctrlrs”) 2442(1)-2442(4), high-bandwidth memory physical layer (“HBM PHY”) 2444(1)-2444(4), a management controller central processing unit (“Management Controller CPU”) 2450, a serial peripheral interface, an inter-integrated circuit, and a General-purpose input / output block (“SPI, I2C, GPIO”) 2460, a Peripheral Component Interconnect Express controller and direct memory access block (“PCIe controller and DMA”) 2470, and a sixteen-lane Peripheral Component Interconnect Express port (“PCI Express x 16”) 2480.

[0333] In at least one embodiment, processing clusters 2410 may perform deep learning operations, including inference or prediction operations based on weighting parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 may include, among other things, any number and type of processors. In at least one embodiment, deep learning application processor 2400 may include any number and type of processing clusters 2400. In at least one embodiment, inter-chip interconnects 2420 are bidirectional.In at least one embodiment, inter-chip interconnects 2420 and inter-chip controllers 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information resulting from the execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2400 may include any number (including zero) and type of ICLs 2420 and ICCs 2430.

[0334] In at least one embodiment, HBM2s 2440 provide a total of 32 gigabytes (GB) of memory. In at least one embodiment, HBM2 2440(i) is associated with both memory controller 2442(i) and HBM PHY 2444(i), where "i" is any integer. In at least one embodiment, any number of HBM2s 2440 may provide any type and total amount of high-bandwidth memory and may be associated with any number (including zero) and type of memory controller 2442 and HBM PHY 2444. In at least one embodiment, SPI, I2C, GPIO 2460, PCIe controller, and DMA 2470 and / or PCIe 2480 may be replaced with any number and type of blocks that enable any number and type of communication standards in any technically feasible manner.

[0335] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, a deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information that is provided to the deep learning application processor 2400. In at least one embodiment, the deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., neural network) trained by another processor or system or by the deep learning application processor 2400. In at least one embodiment, the processor 2400 may be used to perform one or more neural network use cases described herein.

[0336] In at least one embodiment, processor 2400 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0337] Fig. 25 is a block diagram of a neuromorphic processor 2500 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2500 may receive one or more inputs from sources external to the neuromorphic processor 2500. In at least one embodiment, these inputs may be communicated to one or more neurons 2502 within the neuromorphic processor 2500. In at least one embodiment, the neurons 2502 and components thereof may be implemented using circuitry or logic that includes one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2500 may include, among other things, thousands or millions of instances of neurons 2502, but any suitable number of neurons 2502 may be used.In at least one embodiment, each instance of neuron 2502 may include a neuron input 2504 and a neuron output 2506. In at least one embodiment, neurons 2502 may generate outputs that may be transmitted to inputs of other instances of neurons 2502. For example, in at least one embodiment, neuron inputs 2504 and neuron outputs 2506 may be connected to each other via synapses 2508.

[0338] In at least one embodiment, neurons 2502 and synapses 2508 may be interconnected such that neuromorphic processor 2500 operates to process or analyze information received from neuromorphic processor 2500. In at least one embodiment, neurons 2502 may transmit an output pulse (or "fire" or "spike") when inputs received through neuron input 2504 exceed a threshold. In at least one embodiment, neurons 2502 may sum or integrate signals received at neuron inputs 2504. For example, in at least one embodiment, neurons 2502 may be implemented as leak-integrate-and-fire neurons, where when a sum (referred to as a "membrane potential") exceeds a threshold, neuron 2502 may generate an output (or "fire") using a transfer function such as a sigmoid or threshold function.In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs 2504 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire when multiple input signals are received at neuron inputs 2504 quickly enough to exceed a threshold (i.e., before a membrane potential decays too low to fire). In at least one embodiment, neurons 2502 may be implemented using circuitry or logic that receives inputs, integrates inputs into a membrane potential, and decays a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used.Furthermore, in at least one embodiment, neurons 2502 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron output 2506 when the result of applying a transfer function to neuron input 2504 exceeds a threshold. In at least one embodiment, once neuron 2502 fires, it may take previously received input information into account, for example, by resetting a membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2502 may resume normal operation after a suitable period of time (or refractory period).

[0339] In at least one embodiment, neurons 2502 may be interconnected by synapses 2508. In at least one embodiment, synapses 2508 may operate to transmit signals from an output of a first neuron 2502 to an input of a second neuron 2502. In at least one embodiment, neurons 2502 may transmit information via more than one instance of synapse 2508. In at least one embodiment, one or more instances of neuron output 2506 may be connected via an instance of synapse 2508 to an instance of neuron input 2504 in the same neuron 2502. In at least one embodiment, an instance of neuron 2502 that generates an output to be transmitted via an instance of synapse 2508 may be referred to as a "presynaptic neuron" with respect to that instance of synapse 2508.In at least one embodiment, an instance of neuron 2502 that receives input transmitted across an instance of synapse 2508 may be referred to as a "postsynaptic neuron" with respect to that instance of synapse 2508. Because an instance of neuron 2502 may receive input from one or more instances of synapse 2508 and may also transmit outputs across one or more instances of synapse 2508, in at least one embodiment, a single instance of neuron 2502 may therefore be both a "presynaptic neuron" and a "postsynaptic neuron" with respect to different instances of synapses 2508.

[0340] In at least one embodiment, neurons 2502 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2502 may have a neuron output 2506 that may fan out through one or more synapses 2508 to one or more neuron inputs 2504. In at least one embodiment, neuron outputs 2506 from neurons 2502 in a first layer 2510 may be connected to neuron inputs 2504 from neurons 2502 in a second layer 2512. In at least one embodiment, each instance of neuron 2502 in an instance of the first layer 2510 may fan out to each instance of neuron 2502 in the second layer 2512. In at least one embodiment, each instance of neuron 2502 in an instance of second layer 2512 may fan out to fewer than all instances of neuron 2502 in a third layer 2514.In at least one embodiment, neurons 2502 in the second layer 2512 may fan out to neurons 2502 in multiple other layers, including neurons 2502 also in the second layer 2512. In at least one embodiment, the neuromorphic processor 2500 may include, among other things, any suitable combination of recurrent layers and feedforward layers, including, among other things, both sparsely connected feedforward layers and fully connected feedforward layers.

[0341] In at least one embodiment, neuromorphic processor 2500 may include, among other things, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapses 2508 to neurons 2502. In at least one embodiment, neuromorphic processor 2500 may include, among other things, circuitry or logic that enables synapses to be assigned to different neurons 2502 as needed based on neural network topology and neuron input / output. For example, in at least one embodiment, synapses 2508 may be connected to neurons 2502 using an interconnect fabric, such as network-on-chip, or with dedicated interconnects. In at least one embodiment, synapse interconnects and components thereof may be implemented using circuitry or logic.

[0342] In at least one embodiment, the neuromorphic processor 2500 is used to at least partially implement panoramic imaging, as in Fig. 1-6 illustrates.

[0343] Fig. 26 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor desktop system, a multi-processor desktop system, a multi-processor desktop system, a multi-processor desktop system, a multi-processor desktop system, a multi-processor desktop system, or a server system with a large number of processors 2602 or processor cores 2607. In at least one embodiment, system 2600 is a processing platform integrated into a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, one or more graphics processors 2608 include one or more graphics cores 1800.

[0344] In at least one embodiment, system 2600 may include a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console, or may be integrated with a server-based gaming platform. In at least one embodiment, system 2600 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 2600 may also include, be coupled to, or integrated with a wearable device, such as a wearable smartwatch device, a smartglasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0345] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2607 is configured to process a particular instruction sequence 2609. In at least one embodiment, the instruction sequence 2609 may enable complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW) computing. In at least one embodiment, the processor cores 2607 may each process a different instruction sequence 2609, which may include instructions to facilitate emulation of other instruction sequences. In at least one embodiment, the processor core 2607 may also include other processing devices, such as a digital signal processor (DSP).

[0346] In at least one embodiment, processor 2602 includes a cache memory 2604. In at least one embodiment, processor 2602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared by various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a Level 3 (L3) cache or Last Level Cache (LLC)) (not shown) that may be shared by processor cores 2607 using known cache coherence techniques. In at least one embodiment, a register file 2606 is additionally included in processor 2602 that includes various types of registers for storing various types of data (e.g., integer registers, floating-point registers, status registers, and an instruction pointer register).In at least one embodiment, register file 2606 may include general purpose registers or other registers.

[0347] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to communicate communication signals, such as address, data, or control signals, between processor 2602 and other components in system 2600. In at least one embodiment, interface bus 2610 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface bus 2610 is not limited to a DMI bus and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, processor(s) 2602 include an integrated memory controller 2616 and a platform control node 2630.In at least one embodiment, the memory controller 2616 facilitates communication between a memory device and other components of the system 2600, while the platform control node (PCH) 2630 provides connections to I / O devices via a local I / O bus.

[0348] In at least one embodiment, a memory device 2620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other memory device with suitable performance to serve as process memory. In at least one embodiment, the memory device 2620 may operate as system memory for the system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 are executing an application or process. In at least one embodiment, the memory controller 2616 is also coupled to an optional external graphics processor 2612 that can communicate with one or more graphics processors 2608 in the processors 2602 to perform graphics and media operations.In at least one embodiment, a display device 2611 may connect to the processor(s) 2602. In at least one embodiment, the display device 2611 may include one or more of an internal display device, such as in a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2611 may include a head-mounted display (HMD), such as a stereoscopic display device, for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0349] In at least one embodiment, the platform control node 2630 enables peripherals to connect to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, touch sensors 2625, a network controller 2634, an audio controller 2646, a network controller 2634, a network controller 2634, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, touch sensors 2625, and a data storage device 2624 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2624 may be connected to the host computer via a memory interface (e.g.,SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensors 2625 may include touchscreen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a cellular network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 may enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 2610.In at least one embodiment, the audio controller 2646 is a multi-channel high-resolution audio controller. In at least one embodiment, the system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2600. In at least one embodiment, the platform control node 2630 may also be connected to one or more Universal Serial Bus (USB) controllers 2642 that connect input devices, such as keyboard and mouse 2643 combinations, a camera 2644, or other USB input devices.

[0350] In at least one embodiment, an instance of the memory controller 2616 and the platform control node 2630 may be integrated into a discrete external graphics processor, such as the external graphics processor 2612. In at least one embodiment, the platform control node 2630 and / or the memory controller 2616 may be external to one or more processors 2602. For example, in at least one embodiment, the system 2600 may include an external memory controller 2616 and a platform control node 2630, which may be configured as a memory control node and a peripheral control node within a system chipset in communication with the processor(s) 2602.

[0351] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, portions or all of logic 715 may be integrated into graphics processor 2608. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs embodied in a 3D pipeline. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that described in Fig. 7A or Fig. 7B. In at least one embodiment, weighting parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of graphics processor 2608 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0352] In at least one embodiment, graphics processor 2608 is used to at least partially implement panoramic imaging, as in Fig. 1-6 illustrates.

[0353] Fig. 27 is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714, and an integrated graphics processor 2708, according to at least one embodiment. In at least one embodiment, processor 2700 may include additional cores up to and including additional core 2702N, represented by dashed-line boxes. In at least one embodiment, each of the processor cores 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core also has access to one or more shared cache units 2706. In at least one embodiment, graphics processor 2708 includes one or more graphics cores 1800.

[0354] In at least one embodiment, internal cache units 2704A-2704N and shared cache units 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, cache memory units 2704A-2704N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other cache levels, with a highest cache level prior to external memory being classified as an LLC. In at least one embodiment, cache coherence logic maintains coherence between various cache units 2706 and 2704A-2704N.

[0355] In at least one embodiment, processor 2700 may also include a set of one or more bus control units 2716 and a system agent core 2710. In at least one embodiment, bus control units 2716 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2710 provides management functionality for various processor components. In at least one embodiment, system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

[0356] In at least one embodiment, one or more of the processor cores 2702A-2702N include support for concurrent multi-threading. In at least one embodiment, the system agent core 2710 includes components for coordinating and operating the cores 2702A-2702N during multi-threaded processing. In at least one embodiment, the system agent core 2710 may additionally include: a power control unit (PCU) including logic and components for regulating one or more power states of the processor cores 2702A-2702N and the graphics processor 2708.

[0357] In at least one embodiment, processor 2700 additionally includes graphics processor 2708 to perform graphics processing operations. In at least one embodiment, graphics processor 2708 couples to shared cache units 2706 and system agent core 2710, including one or more integrated memory controllers 2714. In at least one embodiment, system agent core 2710 also includes a display controller 2711 to drive the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2711 may also be a separate module coupled to graphics processor 2708 via at least one connection, or may be integrated into graphics processor 2708.

[0358] In at least one embodiment, a ring-based interconnect 2712 is used to couple internal components of processor 2700. In at least one embodiment, an alternative interconnect may be used, such as a point-to-point connection, a switched connection, or other techniques. In at least one embodiment, graphics processor 2708 couples to ring interconnect 2712 via an I / O connection 2713.

[0359] In at least one embodiment, I / O interconnect 2713 represents at least one of several variations of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2718, such as an eDRAM module. In at least one embodiment, each of the processor cores 2702A-2702N and the graphics processor 2708 utilize the embedded memory module 2718 as a shared last-level cache.

[0360] In at least one embodiment, processor cores 2702A-2702N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2702A-2702N are instruction set architecture (ISA) heterogeneous, where one or more of processor cores 2702A-2702N execute a common instruction set, while one or more other cores of processor cores 2702A-2702N execute a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores 2702A-2702N are microarchitecturally heterogeneous, where one or more relatively higher power cores couple with one or more lower power cores. In at least one embodiment, processor 2700 can be implemented on one or more chips or as an integrated circuit (SoC).

[0361] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are described herein in connection with Fig. 7A and / or Fig. 7B. In at least one embodiment, portions or all of the logic 715 may be integrated into graphics processor 2708. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs embodied in a 3D pipeline, graphics core(s) 2702, shared functional logic, or other logic in Fig. 27. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that described in Fig. 7A or Fig. 7B. In at least one embodiment, weighting parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of processor 2700 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0362] In at least one embodiment, processor 2700 is used to at least partially implement panoramic image generation, as in Fig. 1-6 illustrates.

[0363] Fig. 28 is a block diagram of a graphics processor 2800, which may be a discrete graphics processing unit or may be a graphics processor integrated with a plurality of processing cores. In at least one embodiment, the graphics processor 2800 communicates with registers on the graphics processor 2800 and with instructions located in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2800 includes a memory interface 2814 to access memory. In at least one embodiment, the memory interface 2814 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory. In at least one embodiment, the graphics processor 2800 includes the graphics core 1800.

[0364] In at least one embodiment, graphics processor 2800 also includes a display controller 2802 for driving display output data to a display device 2820. In at least one embodiment, display controller 2802 includes hardware for one or more overlay layers for display device 2820 and the composition of multiple layers of video or user interface elements. In at least one embodiment, display device 2820 may be an internal or external display device. In at least one embodiment, display device 2820 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device.In at least one embodiment, the graphics processor 2800 includes a video codec engine 2806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and So...

Claims

[1] Processor comprising: one or more circuits for using one or more neural networks to generate one or more panoramic images based at least in part on a segmentation map indicating content to be included in the one or more panoramic images. [2] The processor of claim 1, wherein generating the one or more panoramic images comprises generating one or more normal perspective images and projecting the one or more normal perspective images onto one or more portions of the one or more panoramic images. [3] The processor of claim 2, wherein the one or more normal perspective images are generated based at least in part on the segmentation map. [4] The processor of claim 2, wherein the one or more normal perspective images correspond to a plurality of viewing directions of the one or more panoramic images. [5] The processor of claim 4, wherein two or more of the plurality of view directions correspond to two or more portions of the panoramic image that at least partially overlap. [6] The processor of claim 4, wherein the one or more normal perspective images are projected onto the one or more portions of the one or more panoramic images based at least in part on the plurality of view directions. [7] The processor of claim 1, wherein the panoramic image comprises a spherical panoramic image. [8] Method comprising: Using one or more neural networks to generate one or more panoramic images based at least in part on a segmentation map indicating content to be included in the one or more panoramic images. [9] The method of claim 8, wherein generating the one or more panoramic images comprises generating one or more normal perspective images and projecting the one or more normal perspective images onto one or more portions of the one or more panoramic images. [10] The method of claim 9, wherein the one or more normal perspective images are generated based at least in part on the segmentation map. [11] The method of claim 9, wherein the one or more normal perspective images correspond to a plurality of viewing directions of the one or more panoramic images. [12] The method of claim 11, wherein two or more of the plurality of viewing directions correspond to two or more portions of the panoramic image that at least partially overlap. [13] The method of claim 11, wherein the one or more normal perspective images are projected onto the one or more portions of the one or more panoramic images based at least in part on the plurality of view directions. [14] The method of claim 8, wherein the panoramic image comprises a spherical panoramic image. [15] System comprising: one or more processors to use one or more neural networks to generate one or more panoramic images based at least in part on a segmentation map indicating content to be included in the one or more panoramic images. [16] The system of claim 15, wherein generating the one or more panoramic images comprises generating one or more normal perspective images and projecting the one or more normal perspective images onto one or more portions of the one or more panoramic images. [17] The system of claim 16, wherein the one or more normal perspective images are generated based at least in part on the segmentation map. [18] The system of claim 16, wherein the one or more normal perspective images correspond to a plurality of viewing directions of the one or more panoramic images. [19] The system of claim 18, wherein two or more of the plurality of viewing directions correspond to two or more portions of the panoramic image that at least partially overlap. [20] The system of claim 18, wherein the one or more normal perspective images are projected onto the one or more portions of the one or more panoramic images based at least in part on the plurality of view directions.

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