APPARATUS, SYSTEM, AND METHOD FOR COMPILING CODE FOR A PROCESSOR

Abstract

For example, a compiler may be configured to identify a loop nest based on source code to be compiled into target code to be executed by a target processor, the loop nest including a plurality of loops including at least a first loop and a second loop nested within the first loop, the first loop including at least one instruction of the first loop outside the second loop;and to generate address generation unit (AGU) configuration code to configure an AGU of the target processor based on the instruction of the first loop, wherein the AGU configuration code is to configure a first dimension of the AGU based on the first loop and a second dimension of the AGU based on the second loop, to configure a memory access operation based on the instruction of the first loop to be executed at the beginning of the second loop or at the end of the second loop;

Description

CROSS-REFERENCE

[0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 415,308, entitled "APPARATUS, SYSTEM, AND METHOD OF VECTOR PROCESSING," filed October 12, 2022, the entire disclosure of which is incorporated herein by reference. BACKGROUND

[0002] A compiler can be configured to compile source code into target code that is configured for execution by a processor.

[0003] It is necessary to provide a technical solution to support efficient processing functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For simplicity and clarity, the elements depicted in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others to clarify the illustration. Furthermore, reference numbers may be repeated in the figures to indicate corresponding or analogous elements. The figures are listed below. Fig. 1 is a schematic block diagram representation of a system according to some example aspects. Fig. 2 is a schematic representation of a compiler according to some exemplary aspects. Fig. 3 is a schematic diagram of a vector processor according to some example aspects. Fig. 4 is a schematic diagram of an execution scheme for performing a latch operation in a loop nest according to some example aspects. Fig. 5 is a schematic representation of an execution scheme for performing a pre-header load or store operation in a loop nest according to some example aspects. Fig. 6 is a schematic flowchart representation of a method of compiling code for a processor according to some example aspects. Fig. 7 is a schematic representation of a product according to some exemplary aspects. DETAILED DESCRIPTION

[0005] In the following detailed description, numerous specific details are included to provide a thorough understanding of some aspects. However, those skilled in the art will understand that some aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, units, and / or circuits have not been described in detail to avoid obscuring the discussion.

[0006] Some sections of the following detailed description are presented in the form of algorithms and symbolic representations of operations on data bits or binary digital signals in a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing field to communicate the content of their work to others skilled in the art.

[0007] An algorithm is considered here and generally to be a self-consistent sequence of actions or operations that lead to a desired result. This includes physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has sometimes been found convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be understood, however, that all these and similar expressions are to be associated with the corresponding physical quantities and are merely convenient labels for these quantities.

[0008] Terms such as "processing", "calculating", "determining", "setting", "analyzing", "testing" or the like may refer to the operation(s) and / or process(es) of a computer, computer platform, computer system, or other electronic computing device that manipulates and / or converts data represented as physical (e.g., electronic) quantities in the registers and / or memory of the computer into other data similarly represented as physical quantities in the registers and / or memory of the computer or other information storage medium that can store instructions for performing operations and / or processes.

[0009] The terms "plurality" and "a plurality," as used herein, include, for example, "several" or "two or more." For example, "a plurality of elements" includes two or more elements.

[0010] References to "an aspect," "an aspect," "an exemplary aspect," "various aspects," etc., indicate that the aspect(s) so described may include a particular feature, structure, or property, but not every aspect necessarily includes that particular feature, structure, or property. Furthermore, the repeated use of the phrase "in an aspect" does not necessarily refer to the same aspect, although it may.

[0011] As used herein, the use of the ordinal adjectives "first," "second," "third," etc., to describe a common object, unless otherwise noted, merely indicates that reference is made to different instances of like objects and is not intended to imply that the objects so described must be in any particular sequence, whether temporally, spatially, in order of precedence, or in any other way.

[0012] For example, some aspects may take the form of a completely hardware-related aspect, a completely software-related aspect, or a aspect that includes both hardware and software elements. Some aspects may be implemented in software, including, but not limited to, firmware, resident software, microcode, or the like.

[0013] Furthermore, some aspects may take the form of a computer program product accessible from a computer-usable or computer-readable medium that provides program code for use by or in connection with a computer or any instruction execution system. For example, a computer-usable or computer-readable medium may be or include a device that can contain, store, communicate, transmit, or transport the program for use by or in connection with the instruction execution system, device, or apparatus.

[0014] In some example aspects, the medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or apparatus) or transmission medium.

[0015] In some example aspects, a data processing system capable of storing and / or executing program code may include at least one processor coupled directly or indirectly to storage elements, for example, via a system bus. The storage elements may include, for example, local memory used during actual execution of the program code, mass storage, and cache memories that may provide temporary storage of at least a portion of the program code to reduce the number of times code is retrieved from mass storage during execution.

[0016] In some example aspects, input / output or I / O devices (including, but not limited to, keyboards, displays, pointing devices, etc.) may be coupled to the system either directly or through intermediate I / O control devices. In some example aspects, network adapters may be coupled to the system to couple the computing system to other computing systems or remote printers or storage devices, for example, through intermediate private or public networks. In some example aspects, modems, cable modems, and Ethernet cards are exemplary examples of types of network adapters. Other suitable components may also be used.

[0017] Some aspects may be used in connection with various devices and systems, such as a computing unit, a computer, a mobile computer, a non-mobile computer, a server computer, or the like.

[0018] As used herein, the term "circuitry" may refer to, be a part of, or include an application-specific integrated circuit (ASIC), an integrated circuit, an electronic circuit, a processor (shared, dedicated, or in a group), and / or memory (shared, dedicated, or in a group) executing one or more software or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the described functionality. In certain aspects, some functions associated with the circuitry may be implemented by one or more software or firmware modules. In some aspects, the circuitry may include logic operable at least partially in hardware.

[0019] The term "logic" may, for example, refer to computational logic embedded in the circuitry of a computing device and / or computational logic stored in a memory of a computing device. For example, a processor of the computing device may access the logic to execute the computational logic to perform computational functions and / or operations. For example, the logic may be embedded in various types of memory and / or firmware, e.g., in silicon blocks of various chips and / or processors. Logic may be included in and / or implemented as part of various circuits, e.g., in processor circuitry, control circuitry, and / or the like. In one example, the logic may be embedded in volatile memory and / or non-volatile memory, including random access memory, read-only memory, programmable memory, magnetic memory, flash memory, persistent memory, and the like.Logic may be executed by one or more processors using memory, such as registers, read-only memory, buffers, and / or the like, coupled to the one or more processors, such as as required to execute the logic.

[0020] Referring to Fig. 1, which schematically illustrates a block diagram of a system 100 according to some example aspects.

[0021] As in Fig. 1, the system 100 may include a computing unit 102 according to some example aspects.

[0022] In certain example aspects, the device 102 may be implemented using suitable hardware components and / or software components, such as processors, controllers, memory devices, storage devices, input devices, output devices, communication devices, operating systems, applications, or the like.

[0023] In some example aspects, device 102 may include, for example, a computer, a mobile computing device, a non-mobile computing device, a laptop, a notebook, a tablet computer, a handheld computer, a personal computer (PC), or the like.

[0024] For example, in some example aspects, device 102 may include one or more processors 191, an input unit 192, an output unit 193, a memory unit 194, and / or a storage unit 195. Device 102 may optionally include other suitable hardware and / or software components. In some example aspects, some or all components of one or more devices 102 may be enclosed in a common housing or package and connected to one another or connected in one operation via one or more wired or wireless connections. In other aspects, components of one or more devices 102 may be distributed across multiple or separate devices.

[0025] In certain aspects, processor 191 may include, for example, a central processing unit (CPU), a digital signal processor (DSP), one or more processor cores, a single-core processor, a dual-core processor, a multi-core processor, a microprocessor, a host processor, a controller, a plurality of processors or controllers, a chip, a microchip, one or more circuits, a circuit assembly, a logic unit, an integrated circuit (IC), an application-specific integrated circuit (ASIC), or other suitable general-purpose or special-purpose processor or controller. Processor 191 may execute instructions, for example, from an operating system (OS) of a device 102 and / or from one or more suitable applications.

[0026] In some example aspects, input device 192 may include, for example, a keyboard, keypad, mouse, touchscreen, touchpad, trackball, stylus, microphone, or other suitable pointing or input device. Output device 193 may include, for example, a monitor, screen, touchscreen, flat panel display, light-emitting diode (LED) display, liquid crystal display (LCD) display, plasma display, one or more speakers or headphones, or other suitable output devices.

[0027] In some example aspects, memory 194 includes, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), flash memory, volatile memory, non-volatile memory, cache memory, a buffer, short-term storage, long-term storage, or other suitable storage devices. Storage device 195 may include, for example, a hard drive, a solid-state drive (SSD), or other suitable removable or non-removable storage devices. Memory device 194 and / or storage device 195 may, for example, store data processed by device 102.

[0028] In some example aspects, device 102 may be configured to communicate with one or more other devices over at least one network 103, e.g., a wireless and / or wired network.

[0029] In some example aspects, the network 103 may include a wired network, a local area network (LAN), a wireless network, a wireless LAN (WLAN), a radio network, a cellular network, a WiFi network, an IR network, a Bluetooth (BT) network, and the like.

[0030] In some example aspects, device 102 may be configured to perform one or more operations, modules, processes, methods, and / or the like, e.g., as described herein.

[0031] In some example aspects, the device 102 may include a compiler 160 that may be configured to generate target code 115, for example, based on source code 112, as described below.

[0032] In some example aspects, the compiler 160 may be configured to translate the source code 112 into the target code 115, as described below.

[0033] In some example aspects, compiler 160 may include or be implemented as software, a software module, an application, a program, a subroutine, instructions, an instruction set, computational code, words, values, symbols, and / or the like.

[0034] In some example aspects, the source code 112 may include computer code written in a source language.

[0035] In some example aspects, the source language may include a programming language. For example, the source language may include a high-level programming language, such as the C programming language, the C++ programming language, and / or the like.

[0036] In some example aspects, the target code 115 may include computer code written in a target language.

[0037] In some exemplary respects, the target language may include a low-level language such as assembly language, object code, machine code, or the like.

[0038] In some example aspects, the target code 115 may include one or more object files that may, for example, create and / or form an executable program.

[0039] In some example aspects, the executable program may be configured to run on a target computer. For example, the target computer may include particular computer hardware, a particular machine, and / or a particular operating system.

[0040] In some example aspects, the executable program may be configured to execute on a processor 180, as described below.

[0041] In some example aspects, processor 180 may include a vector processor 180, e.g., as described below. In other aspects, processor 180 may include any other type of processor.

[0042] Some example aspects are described herein with respect to a compiler, e.g., compiler 160, configured to compile source code 112 into target code 115 configured to be executed by a vector processor 180, as described below. In other aspects, a compiler, e.g., compiler 160, is configured to compile source code 112 into target code 115 configured to be executed by any other type of processor 180.

[0043] In some example aspects, processor 180 may be implemented as part of device 102.

[0044] In other respects, processor 180 may be implemented as part of any other device, e.g., separate from device 102.

[0045] In some example aspects, the vector processor 180 (also referred to as an "array processor") may include a processor that may be configured to process an entire vector into one instruction, e.g., as described below.

[0046] From other perspectives, the executable program may be configured to run on any other additional or alternative processor type.

[0047] In some example aspects, vector processor 180 may be designed to support high-performance image and / or vector processing. For example, vector processor 180 may be configured to process 1 / 2 / 3 / 4D arrays of fixed-point data and / or floating-point arrays very quickly and / or efficiently.

[0048] In some example aspects, vector processor 180 may be configured to process arbitrary data, e.g., structures with pointers to structures. For example, vector processor 180 may include a scalar processor to compute the non-vector data, e.g., assuming the non-vector data is minimal.

[0049] In some example aspects, compiler 160 may be implemented as a local application executed by device 102. For example, memory unit 194 and / or storage unit 195 may store instructions leading to compiler 160, and / or processor 191 may be configured to execute the instructions leading to compiler 160 and / or perform one or more computations and / or processes of compiler 160, e.g., as described below.

[0050] In other aspects, the compiler 160 may include a remote application executed by any suitable computer system, e.g., a server 170.

[0051] In some example aspects, server 170 may include at least one of a remote server, a web-based server, a cloud server, and / or any other server.

[0052] In some example aspects, server 170 may include a suitable memory and / or storage device 174 on which instructions leading to compiler 160 are stored and a suitable processor 171 to execute the instructions, e.g., as described below.

[0053] In some example aspects, the compiler 160 may include a combination of a remote application and a local application.

[0054] In one example, compiler 160 may be downloaded and / or received by the user of device 102 from another computer system, e.g., a server 170, so that compiler 160 may be executed locally by users of device 102. For example, the instructions may be received and stored, e.g., temporarily in memory or a suitable short-term storage or buffer of device 102, e.g., before being executed by processor 191 of device 102.

[0055] In another example, compiler 160 may include a client module executed locally by device 102 and a server module executed by server 170. For example, the client module may include and / or be implemented as a local application, a web application, a website, a web client, e.g., a Hypertext Markup Language (HTML) web application, or the like.

[0056] For example, one or more first operations of compiler 160 may be performed locally, such as by device 102, and / or one or more second operations of compiler 160 may be performed remotely, such as by server 170.

[0057] In other aspects, compiler 160 may include or be implemented by any other suitable arrangement and / or scheme of computing units.

[0058] In some example aspects, the system 100 may include an interface 110, e.g., a user interface, to interface between a user of the device 102 and one or more elements of the system 100, e.g., the compiler 160.

[0059] In some example aspects, the interface 110 may be implemented using any suitable hardware and / or software components, such as processors, controllers, memory devices, storage devices, input devices, output devices, communication devices, operating systems, and / or applications.

[0060] In some aspects, the interface 110 may be implemented as part of a suitable module, system, device, or component of the system 100.

[0061] From other perspectives, the interface 110 may be implemented as a separate element of the system 100.

[0062] In some example aspects, interface 110 may be implemented as part of device 102. For example, interface 110 may be connected to and / or included as part of device 102.

[0063] For example, interface 110 may be implemented as middleware and / or as part of any suitable application of device 102. For example, interface 110 may be implemented as part of compiler 160 and / or as part of an operating system of device 102.

[0064] In some example aspects, interface 110 may be implemented as part of server 170. For example, interface 110 may be connected to and / or included as part of server 170.

[0065] In one example, interface 110 may include or be a part of a web-based application, a website, a web page, a plug-in, an ActiveX control, a rich content component, such as a Flash or Shockwave component, or the like.

[0066] In some example aspects, the interface 110 may, for example, be connected to and / or include a gateway (GW) 113 and / or an application programming interface (API) 114, for example, to communicate information and / or communications between elements of the system 100 and / or to one or more other, e.g., internal or external, parties, users, applications, and / or systems.

[0067] In some aspects, the interface 110 may include any suitable graphical user interface (GUI) 116 and / or any other suitable interface.

[0068] In some example aspects, the interface 110 may be configured to receive the source code 112, for example, from a user of the device 102, e.g., via the GUI 116 and / or the API 114.

[0069] In some example aspects, the interface 110 may be configured to transfer the source code 112 to, for example, the compiler 160 to generate the target code 115, for example, as described below.

[0070] It will now Fig. 2, which schematically illustrates a compiler 200 according to some exemplary aspects. For example, the compiler 160 ( Fig. 1) implement one or more elements of the compiler 200 and / or perform one or more operations and / or functionalities of the compiler 200.

[0071] In some exemplary aspects, as in Fig. 2, the compiler 200 may be configured to generate a target code 233, for example, by compiling a source code 212 in a source language.

[0072] In some exemplary aspects, as in Fig. 2, the compiler 200 may include a front end 210 configured to receive and parse the source code 212 in the source language.

[0073] In some example aspects, the front end 210 may be configured to generate intermediate code 213, for example, based on the source code 212.

[0074] In some example aspects, intermediate code 213 may include a degraded representation of source code 212.

[0075] In some example aspects, front-end 210 may be configured to perform, for example, lexical analysis, syntax analysis, semantic analysis, and / or other additional or alternative type of analysis of source code 212.

[0076] In some example aspects, the front-end 210 may be configured to identify errors and / or problems with a result of analyzing the source code 212. For example, the front-end 210 may be configured to generate error information, e.g., including error and / or warning messages that may, for example, identify a location in the source code 212 where an error or problem is detected.

[0077] In some exemplary aspects, as in Fig. 2, compiler 200 may include a middle end 220 configured to receive and process intermediate code 213 and generate customized, e.g., optimized, intermediate code 223.

[0078] In some example aspects, the middle end 220 may be configured to perform one or more adjustments, e.g., optimizations, to the intermediate code 213 to generate, for example, the adjusted intermediate code 223.

[0079] In some example aspects, the middle end 220 may be configured to perform one or more optimizations to the intermediate code 213, for example, regardless of the type of target computer, to execute the target code 233.

[0080] In some exemplary aspects, the middle end 220 may be implemented to support the use of the optimized intermediate code 223, for example, for different machine types.

[0081] In some example aspects, the middle end 220 may be configured to optimize the intermediate representation of the intermediate code 223, for example, to improve the performance and / or quality of the generated target code 233.

[0082] In some example aspects, the one or more optimizations of the intermediate code 213 may include, for example, inline expansion, dead code elimination, constant transfer, loop conversion, parallelization, and / or the like.

[0083] In some exemplary aspects, as in Fig. 2, the compiler 200 may include a backend 230 configured to receive and process the customized intermediate code 213 and generate the target code 233 based on the customized intermediate code 213.

[0084] In some example aspects, the backend 230 may be configured to perform one or more operations and / or processes that may be specific to the target computer to execute the target code 233. For example, the backend 230 may be configured to process the optimized intermediate code 213 by applying analysis, transformation, and / or optimization operations to the customized intermediate code 213, which may be configured, for example, based on the target computer to execute the target code 233.

[0085] In some example aspects, the one or more analysis, conversion, and / or optimization operations applied to the adapted intermediate code 213 may include, for example, resource and storage decisions, e.g., register allocation, instruction scheduling, and / or the like.

[0086] In some example aspects, the target code 233 may include target-dependent assembly code that may be specific to the target computer and / or a target operating system of the target computer that is to execute the target code 233.

[0087] In some example aspects, the target code 233 may include target-dependent assembly code for a processor, e.g., vector processor 180 ( Fig. 1).

[0088] In some example aspects, compiler 200 may include a Vector Micro-Code Processor (VMP) compiler for Open Computing Language (OpenCL), e.g., as described below. In other aspects, compiler 200 may include or be implemented as part of any other vector processor compiler.

[0089] In some example aspects, the VMP OpenCL compiler may include a Low Level Virtual Machine (LLVM)-based (LLVM-based) compiler that may be configured according to an LLVM-based compilation scheme, for example, to lower OpenCL C code to VMP accelerator assembly code suitable for execution by vector processor 180, for example ( Fig. 1).

[0090] In some example aspects, compiler 200 may include one or more technologies that may be required to compile code into a format suitable for a VMP architecture, e.g., in addition to open source LLVM compiler passes.

[0091] In some exemplary aspects, FE 210 may be configured to parse and translate the OpenCL C code, e.g., through an Abstract Syntax Tree (AST), into, for example, an LLVM Intermediate Representation (IR).

[0092] In some example aspects, compiler 200 may include a dedicated API, for example, to identify a correct pattern for compiler pattern matching suitable for, for example, the VMP. For example, the VMP may be configured as a complex instruction set computer (CISC) implementing a very complex instruction set architecture (ISA) that may be difficult to address from standard C code. According to this case, compiler pattern matching may not easily identify the correct pattern, and in this case, the compiler may require a dedicated API.

[0093] In some exemplary aspects, FE 210 may implement one or more built-in vendor extensions that may, for example, target VMP-specific ISAs, in addition to standard OpenCL integrations that may be optimized for a VMP machine.

[0094] In some exemplary aspects, FE 210 may be configured to implement OpenCL structures and / or work item functions.

[0095] In some example aspects, ME 220 may be configured to process LLVM IR code, which may, for example, be general and target-independent, although it may include one or more hooks for specific target architectures.

[0096] In some example aspects, ME 220 may perform one or more custom passes, for example, to support the VMP architecture as described below.

[0097] In some example aspects, ME 220 may be configured to perform one or more CFG (Control Flow Graph) linearization operations, as described below.

[0098] In some example aspects, CFG linearization may be configured to linearize the code, for example, by converting if statements to selection patterns, if the VMP vector code does not support standard control flow.

[0099] In an example, ME 220 can receive a specific code, e.g. as follows: If (x > 0) { A = A + 5;} else { B = B * 2;}

[0100] According to this example, ME 220 can be configured to apply CFG linearization analysis to the given code, for example, as follows: tmpA = A + 5; tmpB = B * 2; mask = x > 0; A = Select mask, tmpA, A B = Select not mask, tmpB, B Example (1)

[0101] In some example aspects, ME 220 may be configured to perform one or more auto-vectorization analysis operations, e.g., as described below.

[0102] In some example aspects, the auto-vectorization analysis may be configured to vectorize a given code, e.g., automatically vectorize it to utilize the vector capabilities of the VMP.

[0103] In some example aspects, ME 220 may be configured to perform auto-vectorization analysis, e.g., to vectorize code in scalar form. For example, some or all of the auto-vectorization analysis operations may not be performed, e.g., if the code is already provided in vectorized form.

[0104] In some exemplary aspects, e.g., in some use cases and / or scenarios, a compiler may not always be able to automatically vectorize code, e.g., due to data dependencies between loop iterations.

[0105] In one example, ME 220 can receive a specific code, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i++) { a[i]=b[i]+c[i];}

[0106] According to this example, ME 220 can be configured to perform CFG auto-vectorization analysis by applying a first conversion, e.g., as follows: char* a,b,c; for (int i=0; i < 2048; i+=32) { a[i.i+31]=b[i...i+31]+c[i...i+31];} Example (2a)

[0107] For example, ME 220 may be configured to perform CFG auto-vectorization analysis by applying a second transformation, e.g., after the first transformation, e.g., as follows: char32* a,b,c; for (int i=0; i < 64; i++) { a[i]=b[i]+c[i];} Example (2b)

[0108] In some example aspects, ME 220 may be configured to perform one or more Scratch Pad Memory Loop Access Analysis (SPMLAA) operations, such as described below.

[0109] In some exemplary respects, the SPMLAA may define processing blocks (PBs), such as those that should later be outlined and compiled for VMP.

[0110] In some example aspects, the processing blocks may include accelerated loops that may be executed by the vector unit of the VMP.

[0111] In some example aspects, a PB, e.g., each PB, may include memory references. For example, some or all memory accesses may reference local memory banks.

[0112] In some example aspects, the VMP may enable access to memory banks via AGUs, e.g., AGUs 320 as described below with reference to Fig. 3, and scatter-gather units (SG).

[0113] In some exemplary aspects, the AGUs may be preconfigured, e.g., before the execution of a loop. For example, the number of loop iterations may be calculated, e.g., before executing a processing block.

[0114] In some exemplary aspects, image references, e.g., some or all of the image references, may be created in this phase, and steps and offsets may be calculated, e.g., per dimension for each reference.

[0115] In some example aspects, ME 220 may be configured to perform one or more AGU planner analysis operations, e.g., as described below.

[0116] In some example aspects, the AGU scheduler analysis may include an iterator assignment that may cover image references, e.g., all image references, from the entire processing block.

[0117] In some example aspects, an iterator may cover a single reference or a group of references.

[0118] In some example aspects, one or more references to memory may be merged and / or the same access may be reused through shuffle instructions and / or values ​​read from previous iterations may be stored.

[0119] In some example aspects, other references to memory, such as those without a linear access pattern, may be processed using a scatter-gather (SG) unit, but this may result in a performance penalty because indexes and / or masks may need to be maintained.

[0120] In some example aspects, a plan may be configured as an array of iterators within a processing block. For example, a processing block may theoretically have multiple plans.

[0121] In some exemplary aspects, the AGU planner analysis may be configured to create all possible plans for all PBs and select a combination, e.g., a best combination, from all valid combinations.

[0122] In some exemplary aspects, the total number of iterators in a valid combination may be restricted, e.g., to not exceed the number of available AGUs on a VMP.

[0123] In some example aspects, one or more parameters, e.g., including step size, width, and / or base, may be defined for an iterator, e.g., for each iterator as part of the AGU planner analysis. For example, min-max ranges may be defined for the iterators in a dimension, e.g., in each dimension, e.g., as part of the AGU planner analysis.

[0124] In some example aspects, the AGU scheduler analysis may be configured to track and evaluate a reference to memory, e.g., any reference to memory to an image, e.g., to understand its access pattern.

[0125] In an example according to Examples 2a / 2b, the image “a”, which is the base address, can be accessed with steps of 32 bytes for 64 iterations.

[0126] In some example aspects, the LLVM may include a scalar evaluation analysis (SCEV) that may compute an access pattern, e.g., to understand each reference to images.

[0127] In some exemplary aspects, ME 220 may utilize masking capabilities of the AGUs, e.g., to avoid maintaining an induction variable that may degrade performance.

[0128] In some example aspects, ME 220 may be configured to perform one or more rewrite analysis operations, e.g., as described below.

[0129] In some example aspects, the rewrite analysis may be configured to transform the code of a processing block, e.g., while setting iterators and / or changing memory access instructions.

[0130] In some exemplary aspects, setting the iterators, e.g., all iterators, in IR can be implemented in target-specific intrinsic functions. For example, setting the iterators can be in a pre-header of an outermost loop.

[0131] In some example aspects, the rewrite analysis may include loop perfection analysis, as described below.

[0132] In some exemplary aspects, the code can be compiled with the goal that essentially all calculations should be performed within the innermost loop.

[0133] For example, loop perfection analysis can lift instructions, such as moving an operation that is performed after a final iteration of the loop into a loop.

[0134] For example, loop perfection analysis can lower instructions, such as moving an operation that is performed before a first iteration of the loop into a loop.

[0135] For example, loop perfection analysis can raise and / or lower instructions, e.g., such that essentially all instructions are moved from outer loops to the innermost loops.

[0136] For example, the loop perfection analysis can be configured to provide a technical solution to support VMP iterators, e.g., to work only with perfectly nested loops.

[0137] For example, loop perfection analysis may lead to a situation where there are no instructions between the "for" statements that make up the loop, e.g., to support VMP iterators, which cannot emulate such cases.

[0138] In some example aspects, the loop perfection analysis may be configured to summarize a nested loop into a single summarized loop.

[0139] In one example, ME 220 can receive a specific code, e.g., as follows: for (int i = 0; i < N; i++) { int sum = 0; for (int j = 0; j < M; j++) { sum += a[j + stride * i];} res[i] = sum;}

[0140] According to this example, ME 220 can be configured to perform loop perfection analysis to combine the nested loop in the code into a single combined loop, for example, as follows: for (int k = 0; k < N * M; k++) { sum = (k % M == 0 ? 0 : sum); sum += a[k % M + stride * (k / M)]; res[k / M] = sum;} Example (3)

[0141] In some example aspects, ME 220 may be configured to perform one or more vector loop contour analysis operations, as described below.

[0142] In some example aspects, the vector loop outline analysis may be configured to split code between a scalar subsystem and a vector subsystem, e.g., vector processing block 310 ( Fig. 3) and scalar processor 330 ( Fig. 3), as described below with reference to Fig. 3 described.

[0143] In some example aspects, the VMP accelerator may include the scalar and / or vector subsystems, e.g., as described below. For example, each of the subsystems may have different compute units / processors. Accordingly, scalar code may be compiled on a scalar compiler, e.g., an SSC compiler, and / or accelerated vector code may be executed on the VMP vector processor.

[0144] In some exemplary aspects, the vector loop outline analysis may be configured to create a separate function for a loop body of the accelerated vector code. These functions may, for example, be marked for VMP and / or continue to the VMP backend, while the rest of the code can be compiled by the SSC compiler.

[0145] In some example aspects, one or more parts of a vector loop, such as vector unit configuration and / or vector register initialization, may be performed by a scalar unit. However, these parts may be performed at a later stage, such as by backpatching into the scalar code, since the scalar code may still be in LLVM IR prior to processing by the SSC compiler.

[0146] In some exemplary aspects, BE 230 may be configured to translate the LLVM IR into machine instructions. For example, BE 230 may not be target-agnostic and may be familiar with target-specific architecture and optimizations, e.g., compared to ME 220, which may be target-specific architecture agnostic.

[0147] In some example aspects, BE 230 may be configured to perform one or more analyses that may be specific to a target computer, such as a VMP computer, to which the code is lowered, although BE 230 may use the common LLVM.

[0148] In some example aspects, BE 230 may be configured to perform one or more instruction descent analysis operations, e.g., as described below.

[0149] In some example aspects, the instruction descent analysis may be configured to translate LLVM IR into directed instructions (Machine IR, MIR), for example, by translating the LLVM IR into a directed acyclic graph (DAG).

[0150] In some example aspects, the DAG may undergo a legalization process of instructions, for example, based on the data types and / or VMP instructions that can be supported by a VMP HW.

[0151] In some example aspects, the instruction depression analysis may be configured to perform a pattern matching process, e.g., after the instruction legalization process, to, for example, depression of a node, e.g., each node, in the DAG, e.g., into a VMP-specific machine instruction.

[0152] In some example aspects, the instruction descent analysis may be configured to generate the MIR, e.g., after the pattern matching process.

[0153] In some example aspects, the instruction descent analysis may be configured to descent the instruction according to the machine application binary interface (ABI) and / or calling conventions.

[0154] In some example aspects, BE 230 may be configured to perform one or more unit balancing analysis operations, e.g., as described below.

[0155] In some example aspects, the unit balancing analysis may be configured to balance instructions between VMP compute units, e.g., compute units 316 ( Fig. 3), as described below with reference to Fig. 3, be balanced.

[0156] In some exemplary aspects, the unit balancing analysis may be familiar with some or all of the available arithmetic conversions and / or perform conversions according to an optimal algorithm.

[0157] In some example aspects, BE 230 may be configured to perform one or more modulo scheduler (pipelined) analysis operations, e.g., as described below.

[0158] In some example aspects, the pipeliner may be configured to schedule the instructions according to one or more constraints, such as data dependency, resource constraints, and / or other constraints, for example, using Swing Modulo Scheduling (SMS) heuristics and / or other additional and / or alternative heuristics.

[0159] In some example aspects, the pipeliner may be configured to create a schedule for a group of Very Long Instruction Word (VLIW) instructions, such as an initiation interval (II), that the program traverses, for example, during a steady state.

[0160] In some example aspects, a performance metric, which may be based on a number of cycles that a typical loop can execute, may be measured, for example, as follows: (Size of input data in bytes) * II / (bytes consumed / generated per iteration)

[0161] In some exemplary aspects, the pipeliner may attempt to minimize II, e.g., as much as possible, to improve performance.

[0162] In some example aspects, the pipeliner may be configured to calculate a minimum II and create a schedule accordingly. For example, if the pipeliner fails to meet the schedule, it may attempt to increase the II and recreate the schedule, e.g., until a predefined II threshold is exceeded.

[0163] In some example aspects, BE 230 may be configured to perform one or more register mapping analysis operations, e.g., as described below.

[0164] In some example aspects, the register allocation analysis may be configured to attempt to allocate a register in an efficient, e.g., optimal, manner.

[0165] In some example aspects, the register mapping analysis may assign values ​​to bypass vector registers, general purpose vector registers, and / or scalar registers.

[0166] In some example aspects, the values ​​may include private variables, constants, and / or values ​​that are rotated across iterations.

[0167] In some exemplary aspects, the register mapping analysis may implement an optimal heuristic that matches one or more VMP register file (regfile) constraints. For example, in some use cases, the register mapping analysis may not use a standard LLVM register mapping.

[0168] In some exemplary aspects, the register mapping analysis may fail in some cases, which may mean that the loop cannot be compiled. Accordingly, the register mapping analysis may implement a retry mechanism that returns to the modulo scheduler and attempts to reschedule the loop, e.g., with an increased initiation interval. For example, increasing the initiation interval may reduce register pressure and / or aid compilation of the vector loop, e.g., in many cases.

[0169] In some example aspects, BE 230 may be configured to perform one or more SSC configuration analysis operations, e.g., as described below.

[0170] In some example aspects, the SSC configuration analysis may be configured to determine a configuration for running the kernel, such as the AGU configuration.

[0171] In some exemplary aspects, the SSC configuration analysis may be performed at a late stage, for example, due to configurations calculated after legalization, register mapping analysis, and / or modulo scheduling analysis.

[0172] In some example aspects, the SSC configuration analysis may include a zero-overhead loop (ZOL) mechanism in the vector loop. For example, the ZOL mechanism may configure a loop execution count based on an access pattern of memory references in the loop, for example, to avoid executing instructions that check the loop exit condition on each iteration.

[0173] In some example aspects, a VMP compilation flow may include one or more steps, e.g., some steps that may be called during the compilation flow in a test library (testlib), such as a wrapper script for compilation, execution, and / or program testing. These steps may, for example, be executed outside of the LLVM compiler.

[0174] In some example aspects, a PCB Hardware Description Language (PHDL) simulator may be implemented to perform one or more roles of an assembler, encoder, and / or linker.

[0175] In some exemplary aspects, compiler 200 may be configured to provide a technical solution to support robustness, allowing the compilation of a wide range of loops with hardware constraints. For example, compiler 200 may be configured to support a technical solution that does not generate verification errors.

[0176] In some exemplary aspects, compiler 200 may be configured to provide a technical solution that supports programmability, allowing a user to express code in various ways that can be correctly compiled for the VMP architecture.

[0177] In some example aspects, compiler 200 may be configured to provide a technical solution to support an enhanced user experience, which may enable the user to debug and / or profile code. For example, the enhanced user experience may provide informative error messages, reporting tools, and / or a profiler.

[0178] In some example aspects, compiler 200 may be configured to provide a technical solution to support improved performance, e.g., to optimize VMP assembly code and / or iterator accesses, which may result in faster execution. For example, improved performance may be achieved by high utilization of the compute units and leveraging their complex CISC.

[0179] It will now Fig. 3, which schematically illustrates a vector processor 300 according to some example aspects. For example, the vector processor 180 ( Fig. 1) implement one or more elements of the vector processor 300 and / or perform one or more operations and / or functionalities of the vector processor 300.

[0180] In some example aspects, the vector processor 300 may include a vector microprocessor (VMP).

[0181] In some example aspects, the vector processor 300 may include a WVM (Wide Vector Machine) that supports, for example, Very Long Instruction Word (VLIW) and / or Single Instruction / Multiple Data (SIMD) architectures.

[0182] In some example aspects, the vector processor 300 may be configured to provide a technical solution to support high performance for short integer types, which may be common in, for example, computer vision and / or deep learning algorithms.

[0183] In other aspects, the vector processor 300 may include any other type of vector processor and / or be configured to support other additional or alternative functionality.

[0184] In some exemplary aspects, as in Fig. 3, the vector processor 300 may include a vector processing block (vector processor) 310, a scalar processor 330, and a direct memory access (DMA) 340, as described below.

[0185] In some exemplary aspects, as in Fig. 3, the vector processing block 310 may be configured to efficiently process, for example, image data and / or vector data. For example, the vector processing block 310 may be configured to use vector calculation units, for example, to accelerate calculations.

[0186] In some example aspects, scalar processor 330 may be configured to perform scalar calculations. For example, scalar processor 330 may be used as "glue logic" for programs that include vector calculations. For example, some, e.g., even most, calculations of the programs may be performed by vector processing block 310. However, several tasks, for example, some essential tasks, e.g., scalar calculations, may be performed by scalar processor 330.

[0187] In some example aspects, the DMA 340 may be configured to interface with one or more memories in a chip that includes the vector processor 300.

[0188] In some example aspects, the DMA 340 may be configured to read inputs from main memory and / or write outputs to main memory.

[0189] In some example aspects, the scalar processor 330 and the vector processing block 310 may use respective local memories to process data.

[0190] In some exemplary aspects, as in Fig. 3, the vector processor 300 may include a fetch and decode unit 350 that may be configured to control the scalar processor 330 and / or the vector processing block 310.

[0191] In some example aspects, operations of the scalar processor 330 and / or the vector processing block 310 may be triggered by instructions stored in a program memory 352.

[0192] In some example aspects, the DMA 340 may be configured to transfer data in parallel with the execution of the program instructions in the memory 352, for example.

[0193] In some example aspects, the DMA 340 may be controlled by software, e.g., via configuration registers, rather than instructions, and accordingly may be considered a second "thread of execution" in the vector processor 300.

[0194] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may include one or more data processing units, such as a set of data processing units as described below.

[0195] In some example aspects, the computing units may include hardware configured to perform calculations, such as an arithmetic logic unit (ALU).

[0196] In one example, a computing device may be configured to add numbers and / or store the numbers in a memory.

[0197] In some example aspects, the data processing units may be controlled by instructions encoded, for example, in program memory 352 and / or configuration registers. For example, the configuration registers may be mapped as memory and written by the memory store instructions of scalar processor 330.

[0198] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may include a state configuration that includes a set of registers and memories, as described below.

[0199] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a set of vector memories 312, which may be configured, for example, to store data to be processed by the vector processor block 310.

[0200] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a set of vector registers 314, which may be configured, for example, for use in data processing by the vector processor block 310.

[0201] In some example aspects, the scalar processor 330, the vector processing block 310, and / or the DMA 340 may be coupled to a set of memory maps.

[0202] In some example aspects, a memory map may include a set of addresses accessible by a computing device that can load and / or store data from registers and memories.

[0203] In some exemplary aspects, as in Fig. 3, the vector processing block 310 may include a plurality of address generation units (AGUs) 320, which may include addresses accessible to them, e.g., in one or more memories 312.

[0204] In some exemplary aspects, as in Fig. 3, the vector processor block 310 may include a plurality of data processing units 316, for example, as described below.

[0205] In some example aspects, computing units 316 may be configured to process instructions, e.g., including multiple numbers at a time. In one example, an instruction may include 8 numbers. In another example, an instruction may include 4 numbers, 16 numbers, or any other number of numbers.

[0206] In some example aspects, two or more computing units 316 may be used simultaneously. In one example, computing units 316 may process and execute a plurality of different instructions, e.g., three different instructions including, for example, eight numbers, during a single cycle.

[0207] In some example aspects, computing units 316 may be asymmetric. For example, first and second computing units 316 may support different instructions. For example, a first computing unit 316 may perform an addition and / or a second computing unit 316 may perform a multiplication. For example, both operations may be performed by one or more additional computing units 316.

[0208] In some example aspects, data processing units 316 may be configured to support arithmetic operations on many combinations of input and output data types.

[0209] In some example aspects, data processing units 316 may be configured to support one or more operations that may be less common. For example, processing units 316 may support operations that operate on a look-up table (LUT) of a vector processor 300 and / or any other operations.

[0210] In some example aspects, data processing units 316 may be configured to support efficient computation of nonlinear functions, histograms, and / or random data access, which may be useful, for example, for implementing algorithms such as image scaling, Hough transforms, and / or other algorithms.

[0211] For example, in some example aspects, vector memories 312 may include memory banks of 16K or other sizes that may be accessed in the same cycle.

[0212] In one example, a maximum memory access size may be 64 bits. According to this example, a peak throughput may be 256 bits, e.g., 64x4 = 256. For example, a high memory bandwidth may be implemented to utilize the computing capabilities of the data processing units 316.

[0213] In one example, two data processing units 316 can support 16 8-bit multiply-and-accumulate (MAC) operations per cycle. According to this example, the two data processing units 316 may not be useful, for example, if the input numbers are not fetched at this speed and / or there are not exactly 256 bits of input, e.g., 16 x 8 x 2 = 256.

[0214] In some example aspects, AGUs 320 may be configured to perform memory-related operations, such as loading and storing data from / to vector memory 314.

[0215] In some example aspects, AGUs 320 may be configured to calculate addresses of input and output data elements, for example, to process I / O and utilize data processing units 316, e.g., when raw bandwidth is insufficient.

[0216] In some example aspects, AGUs 320 may be configured to calculate the addresses of the input and / or output data elements, for example, based on configuration registers written by scalar processor 330, for example, before a block of vector instructions, e.g., a loop, is entered.

[0217] For example, AGUs 320 may be configured to write an image base pointer, width, height, and / or step to the configuration registers to, for example, iterate over an image.

[0218] In some example aspects, AGUs 320 may be configured to handle addressing, e.g., all addressing, to provide a technical solution where compute units 316 do not have the burden of incrementing pointers or counters in a loop and / or the burden of checking for end-of-line conditions, e.g., to set a counter in the loop to zero.

[0219] In some exemplary aspects, as in Fig. As shown in Figure 3, AGUs 320 may include four AGUs, and accordingly, four memories 312 may be accessed in one cycle. From other perspectives, any other number of AGUs 32 may be implemented.

[0220] In some example aspects, AGUs 320 may not be "tied" to memory banks 312. For example, an AGU 320, e.g., any AGU 320, may access a memory bank 312, e.g., any memory bank 312, as long as two or more AGUs 320 do not attempt to access the same memory bank 312 in the same cycle.

[0221] In some example aspects, vector registers 314 may be configured to support communication between the data processing units 316 and the AGUs 320.

[0222] In one example, the total number of vector registers 314 may be 28, which may be divided into multiple subsets, e.g., based on their function. For example, a first subset of the vector registers 314 may be used for input / output of, e.g., all compute units 316 and / or AGUs 320; and / or a second subset of the vector registers 314 may not be used for output of some operations, e.g., most operations, and may be used for one or more other operations, e.g., storing loop-invariant inputs.

[0223] In some example aspects, a compute unit 316, e.g., each compute unit 316, may include one or more registers to host an output of a most recently executed operation, which may, for example, be fed as inputs to other compute units 316. For example, these registers may "bypass" the vector registers 314 and operate faster than if these outputs were written to the first set of vector registers 314.

[0224] In some example aspects, fetch and decode unit 350 may be configured to support low-overhead vector loops, such as very low-overhead vector loops (also referred to as "zero-overhead vector loops"). In such cases, for example, it may not be necessary to check an exit condition during the execution of the vector loop.

[0225] For example, an exit condition may be signaled by an AGU 320, for example, when the AGU 320 has completed iterating over a configured memory range.

[0226] For example, the fetch and decode unit 350 may exit the loop, for example, when the AGU 320 signals the termination condition.

[0227] For example, the scalar processor 330 may be used to configure the loop parameters, such as first and last instructions and / or the exit condition.

[0228] In one example, vector loops may be used, for example, in conjunction with high memory bandwidth and / or low-cost addressing to solve a control and data flow problem, for example, to provide a technical solution that enables the data processing units 316 to process data, e.g., without significant additional overhead.

[0229] In some example aspects, scalar processor 330 may be configured to provide one or more functionalities that may be complementary to those of vector processing block 310. For example, a large portion, e.g., most, of the work in a vector program may be performed by data processing units 316. For example, scalar processor 330 may be used to "stitch together" the various blocks of vector code of the vector program.

[0230] In some example aspects, the scalar processor 330 may be implemented separately from the vector processing block 310. In other aspects, the scalar processor 330 may be configured to share one or more components and / or functionality with the vector processing block 310.

[0231] In some example aspects, the scalar processor 330 may be configured to perform operations that are not suitable for execution in the vector processing block 310.

[0232] For example, scalar processor 330 may be used to execute 32-bit C programs. Scalar processor 330 may, for example, be configured to support 1-, 2-, and / or 4-byte C code data types and / or some or all of C code's arithmetic operators.

[0233] For example, the scalar processor 330 may be configured to provide a technical solution to perform operations that cannot be performed in the vector processing block 310, for example, without using a full CPU.

[0234] In some example aspects, the scalar processor 330 may include a scalar memory 332, which may be, for example, 16K or other size, and may be configured to store data, such as variables used by the scalar portions of a program.

[0235] For example, the scalar processor 330 may store local and / or global variables declared by portable C code that may be assigned to the scalar data store by a compiler, e.g., compiler 200 ( Fig. 2).

[0236] In some exemplary aspects, as in Fig. 3, the scalar processor 330 may include or be coupled to a set of vector registers 334 that may be used in a data processing process executed by the scalar processor 330.

[0237] In some example aspects, the scalar processor 330 may be coupled to a scalar memory map that may assist the scalar processor 330 in accessing substantially all states of the vector processor 300. For example, the scalar processor 330 may configure the vector units and / or the DMA channels via the scalar memory map.

[0238] In some example aspects, the scalar processor 330 may not be permitted to access one or more control registers for blocks that may be used by external processors to execute and debug vector programs.

[0239] In some example aspects, DMA 340 may be configured to communicate with one or more other components of a chip implementing vector processor 300, for example, via main memory. For example, DMA 340 may be configured to transfer blocks of data, such as large, contiguous blocks of data, to support, for example, the scalar processor 330 and / or the vector processing block that may manipulate data stored in the local memories. For example, a vector program may read data from the chip's main memory using DMA 340.

[0240] In some example aspects, DMA 340 may be configured to communicate with other elements of the chip, for example, via a plurality of DMA channels, e.g., 8 DMA channels or any other number of DMA channels. For example, a DMA channel, e.g., any DMA channel, may be capable of transferring a rectangular patch from the local memories to the chip's main memory, or vice versa. In other aspects, the DMA channel may transfer any other type of data block between the local memories and the chip's main memory.

[0241] In some example aspects, a rectangular patch may be defined by a base pointer, a width, a height, and a step size.

[0242] For example, at maximum throughput, 8 bytes can be transferred per cycle, but overhead may be incurred for each patch and / or for each row in a patch.

[0243] In some example aspects, DMA 340 may be configured to transfer data in parallel with computations, e.g., across multiple DMA channels, as long as executing instructions do not access any local memory involved in the transfer.

[0244] For example, because all channels access the same memory bus, using multiple channels to perform a transfer may not save I / O cycles compared to, for example, using a single channel. However, the multiple DMA channels can be used to schedule multiple transfers and execute them in parallel with computations. This can be advantageous compared to, for example, a single channel, where a second transfer may not be scheduled before the first is complete.

[0245] In some exemplary aspects, DMA 340 may be associated with a memory mapper that can assist the DMA channels in accessing vector memory and / or the scalar data. For example, access to the vector memory may be performed in parallel with computations. For example, parallel access to the scalar data is generally not permitted because the scalar processor 330 may be involved in almost any meaningful program and is likely to access its local variables while the transfer is being performed, which may result in a memory conflict with the active DMA channel.

[0246] In some exemplary aspects, DMA 340 may be configured to provide a technical solution to support the parallelization of I / O and computations. For example, a program performing computations may not need to wait for I / O, e.g., if those computations can be performed quickly by vector processing block 310.

[0247] In some example aspects, an external processor, e.g., a CPU, may be configured to initiate execution of a program on vector processor 300. For example, vector processor 300 may remain idle until program execution is initiated.

[0248] In some example aspects, the external processor may be configured to debug the program, i.e., execute a single step at a time, stop when the program reaches breakpoints, and / or check the contents of registers and memory in which the program variables are stored.

[0249] In some example aspects, external memory mapping may be implemented to assist the external processor in controlling the vector processor 300 and / or debugging the program, for example, by writing to control registers of the vector processor 300.

[0250] In some example aspects, external memory mapping may be implemented by a superset of scalar memory mapping. This implementation may, for example, make all registers and memory defined by the architecture of vector processor 300 accessible to a debugger backend running on the external processor.

[0251] In some example aspects, the vector processor 300 may trigger an interrupt signal, for example, when the vector processor 300 terminates a program.

[0252] In some example aspects, the interrupt signal may be used, for example, to implement a driver that manages a queue of programs scheduled for execution by the vector processor 300 and / or to start a new program, e.g., by the external processor, for example, upon completion of a previously executed program.

[0253] Referring to Fig. 1, in some example aspects, compiler 160 may be configured to generate target code 115 based on one or more loops, which may be based on source code 112, for example, as described below.

[0254] In some example aspects, the compiler 160 may be configured to generate the target code 115 based on one or more loops, which may be configured according to a loop execution scheme, as described below.

[0255] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support one or more vector processing architectures, such as VLIW architectures and / or any other architectures, as described below.

[0256] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support the improvement of one or more types of loop nests, for example, incomplete loop nests, as described below.

[0257] In some example aspects, a loop nest may include at least one outer and one inner loop, as described below.

[0258] In some example aspects, the loop nest may include an outer loop, e.g., an outermost loop, an inner loop, e.g., an innermost loop, and one or more nested loops (also referred to as "intermediate nesting loops" or "intermediate loops") that may be nested between the outer loop and the inner loop, e.g., as described below.

[0259] In some example aspects, the loop nest may include a plurality of loops nested in a plurality of nest levels, as described below.

[0260] In one example, the plurality of loops may include a first loop, e.g., an outer loop, for example, in a first nesting level, and a second loop, e.g., an inner loop, for example, in a second nesting level.

[0261] In one example, the plurality of loops may include one or more intermediate loops, for example, in one or more intermediate nesting levels, for example, between the first nesting level and the second nesting level.

[0262] In one example, the plurality of loops may include three loops at three nesting levels. For example, the three loops may include a first loop, e.g., an outermost loop, at a first nesting level, a second loop, e.g., an intermediate loop, at a second nesting level, and a third loop, e.g., an innermost loop, at a third nesting level. For example, the second loop may be nested within the first loop, and the third loop may be nested within the second loop.

[0263] In some example aspects, it may be necessary to provide a technical solution to efficiently convert incomplete loop nests into perfect loop nests, for example, to improve the performance of an executable program, for example, when executed by a processor, such as a vector processor or other target processor, as described below.

[0264] In some exemplary aspects, a perfect loop nest may be configured to include a loop nest in which all operations of the loop nest lie in an innermost loop of the perfect loop nest.

[0265] For example, outer loops of the perfect loop nest must not contain any calculation instructions.

[0266] For example, all calculation instructions of the perfect loop nest can be located in the innermost loop of the perfect loop nest.

[0267] In one example, one or more processor architectures may require and / or benefit from the use of perfect loop nests in a program.

[0268] In another example, the perfect loop nests may be suitable for one or more, e.g., many more, loop optimizations.

[0269] In another example, one or more schedulers, such as modulo scheduling, which may be a crucial optimization for VLIW goals, may not be able to optimize code across loop levels / basic blocks, e.g., when perfect loop nests are not used.

[0270] In another example, one or more processor architectures may support only perfect loop nests. These architectures may, for example, rely on perfecting loop nests into perfect loops.

[0271] In some example aspects, the compiler 160 may be configured to generate the target code 115 based on one or more loops, which may be configured, for example, according to a loop execution scheme that may be configured to provide a technical solution to improve the performance of a program executed by a target processor, such as a vector processor, for example, by converting incomplete loop nests to complete loop nests, as described below.

[0272] In some example aspects, the loop execution scheme may be configured to provide a technical solution to improve the performance of a program executed by a target processor, e.g., a vector processor, for example, by efficiently converting incomplete loop nests into merged loops, as described below.

[0273] In some example aspects, a collapsed loop of a perfect loop nest may be configured to enclose a single basic block loop including all nested loops of the perfect loop, as described below.

[0274] In some example aspects, the execution of the individual basic block loop may be pre-configured, for example, along various dimensions that may correspond to the original loops in the original loop nest.

[0275] For example, the execution of the combined loop may be configured in advance, e.g., by controlling the hardware (“HW-controlled”), as described below.

[0276] In one example, one or more processor architectures may support only aggregated loops. These processor architectures may, for example, be based on the ability to aggregate and / or perfect nests of loops into individual basic block and / or perfect loops.

[0277] In some example aspects, compiler 160 may be configured to generate target code 115 based on one or more loops, which may be configured, for example, according to a loop execution scheme that may be configured to provide a technical solution to support the conversion of incomplete loop nests to complete loop nests, for example, to improve the performance of an executable program, as described below.

[0278] In some example aspects, the loop execution scheme may be configured to provide a technical solution to efficiently convert incomplete loop nests into summarized loops, for example, by converting perfect loop nests into summarized loops, as described below.

[0279] In some example aspects, the compiler 160 may be configured to generate the target code 115 based on a compilation scheme that may, for example, be configured to provide a technical solution to support the computation of one or more predicates that may be used for converting incomplete loop branches to complete loop nests and / or for converting incomplete loop branches to summarized loops, as described below.

[0280] In some example aspects, a predicate may be configured to indicate, identify, confirm, predict, and / or assert the beginning of a loop and / or the end of a loop, e.g., a first iteration or a last iteration of the loop.

[0281] In some example aspects, the predicate may be configured to identify the beginning of a loop and / or the end of a loop, for example, even without handling and / or maintaining an induction variable, as described below.

[0282] In one example, one or more predicates may be used to indicate the start and / or end of execution of one or more inner loops nested within an original loop nest, for example, as described below.

[0283] In one example, it may be important to compute the predicates efficiently, e.g., in cases where loop perfection and / or loop collapse rely on predication, e.g., as described below.

[0284] In another example, it may be important to compute the predicates efficiently, e.g., to support processor architectures that may not be able to compute induction variables efficiently, as described below.

[0285] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support processor architectures that may not support predicated instructions for non-memory access operations.

[0286] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support computational predicates, for example, to support the conversion of loop nests to perfect loop nests and / or summarized loops, as described below.

[0287] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support the execution of programs more efficiently, e.g., by avoiding the need to compute a predicate based on an induction variable, as described below.

[0288] In some example aspects, the loop execution scheme may be configured to provide a technical solution to support one or more architectures that do not have predicated operations in hardware and / or hardware-controlled loop nesting, as described below.

[0289] In some example aspects, compiler 160 may be configured to identify one or more loop nests based on the source code, e.g., as described below.

[0290] In some example aspects, the compiler 160 may be configured to identify one or more of the loop nests in the source code 112, e.g., in the event that the loop nests are included in the source code 112.

[0291] In some example aspects, the compiler 160 may be configured to identify one or more of the loop nests in the code, e.g., middle-end code that may be compiled from the source code 112.

[0292] In some example aspects, compiler 160 may be configured to convert one or more identified loop nests into one or more perfect loop nests, as described below.

[0293] In some example aspects, the compiler 160 may be configured to compile the source code into the target code 115, for example, such that the target code 115 may be based on one or more perfect loop nests, such as described below.

[0294] In some example aspects, the compiler 160 may be configured to convert the one or more identified loop nests into the one or more perfect loop nests, for example, according to a loop perfection scheme as described below.

[0295] In some example aspects, compiler 160 may be configured to move one or more outer instructions from outer loop levels of a loop nest into an inner loop, e.g., an innermost loop, of the loop nest, using, for example, one or more predicates to monitor the execution of the outer instructions moved into the inner loop, as described below.

[0296] In some example aspects, the predicates may be configured to check and / or represent a state of an induction variable that counts a number of iterations of the inner loop, as described below.

[0297] In some example aspects, a predicate (also referred to as a "loop start predicate") may be configured to indicate when the induction variable may correspond to the beginning of a respective inner loop, e.g., for an instruction (also referred to as a "sunk instruction") that has been moved from before the inner loop into the inner loop, as described below.

[0298] In some example aspects, a predicate (also referred to as a "loop end predicate") may be configured to indicate when the induction variable may correspond to the end of a respective inner loop, e.g., for an instruction (also referred to as a "hoist instruction") that is moved from after the inner loop into the inner loop, as described below.

[0299] In some example aspects, compiler 160 may be configured to move all instructions from outer loop levels (nesting levels) of the loop nest into the innermost loop of the loop nest, for example, to convert the loop nest into a perfect loop nest, as described below.

[0300] In some example aspects, compiler 160 may be configured to identify one or more instructions of an outer loop of an outer loop of a loop nest that is outside an inner loop of the loop nest, as described below.

[0301] In some example aspects, the compiler 160 may be configured to move the outer loop instruction into the inner loop of the loop nest, for example, based on a location-based criterion related to a location of the outer loop instruction with respect to the inner loop, as described below.

[0302] In some example aspects, the location-based criterion may be used to determine whether the outer loop instruction is before the inner loop ("a pre-header instruction") or after the inner loop ("a latch instruction"), as described below.

[0303] In some example aspects, compiler 160 may be configured to convert an outer loop instruction into a conditional instruction in the inner loop, which may be located within the inner loop of the loop nest, as described below.

[0304] For example, the conditional command may be configured based on the location-based criterion, e.g., as described below.

[0305] For example, in some example aspects, the conditional instruction may be configured based on a predicate to indicate, identify, confirm, predict, and / or assert a number of iterations of the inner loop, e.g., as described below.

[0306] In some example aspects, the predicate may be used to indicate, identify, confirm, predict, and / or assert whether the inner loop is in a first inner loop iteration or a last inner loop iteration, as described below.

[0307] In some example aspects, the conditional instruction may be configured as a memory access operation, which may be based, for example, on the predicate about the number of iterations of the inner loop, as described below.

[0308] In some example aspects, the outer loop instruction may include a load operation, and the memory access operation may be configured to perform the load operation, for example, based on the predicate about the number of iterations of the inner loop, as described below.

[0309] In some example aspects, the outer loop instruction may include a store operation, and the memory access operation may be configured to perform the store operation, for example, based on the predicate of the number of iterations of the inner loop, as described below.

[0310] In some example aspects, compiler 160 may be configured to lower an instruction, for example, by moving an instruction to be executed before a first iteration of the inner loop into an inner loop, as described below.

[0311] In some example aspects, a pre-header instruction may be lowered, for example, by moving the pre-header instruction into the inner loop and converting the pre-header instruction to a conditional pre-header instruction, as described below.

[0312] In some example aspects, the conditional pre-header instruction may include a condition to configure a result of the conditional pre-header instruction based on a predicate, for example, in the inner loop as described below.

[0313] In some example aspects, the compiler 160 may generate the target code 115 based on compiled code that may be configured to configure a particular result of the conditional pre-header instruction, for example, when the predicate indicates that execution of the inner loop occurs before the first iteration of the inner loop, as described below.

[0314] In some example aspects, compiler 160 may be configured to elevate an instruction, for example, by moving an instruction to be executed after a final iteration of the inner loop into an inner loop, as described below.

[0315] In some example aspects, a latch instruction may be lifted, for example, by moving the latch instruction into the inner loop and converting the latch instruction to a latch conditional instruction (also referred to as a "lifted conditional instruction"), as described below.

[0316] In some example aspects, the latch-conditional instruction may include a condition to configure a result of the latch-conditional instruction based on a predicate, for example, in the inner loop as described below.

[0317] In some example aspects, the compiler 160 may generate the target code 115 based on the compiled code, which may be configured to configure a particular result of the latch-conditional instruction, e.g., if the predicate specifies that execution of the inner loop occurs after the last iteration of the inner loop.

[0318] In some example aspects, compiler 160 may be configured to perform the raising and / or lowering operations repeatedly and / or iteratively, for example, to traverse all instructions in the loop nest until substantially all instructions are moved from outer loops to the innermost loops, as described below.

[0319] For example, the loop execution scheme may be configured to provide a technical solution to support VMP iterators that only work with perfectly nested loops. For example, the loop execution scheme may result in a situation where there are no instructions between two consecutive "for" statements that comprise the loop, as described below.

[0320] In some example aspects, compiler 160 may be configured to compile source code 112 into target code 115, for example, by converting one or more loop nests into merged loops, as described below.

[0321] In some example aspects, the one or more loop nests may be converted into merged loops, for example, to provide a technical solution to improve the performance of execution of a program by a target processor, for example, a vector processor and / or another processor, as described below.

[0322] In some example aspects, compiler 160 may be configured to convert one or more identified loop nests into collapsed loops, for example, according to a loop collapse scheme as described below.

[0323] In some example aspects, the compiler 160 may be configured to apply the loop collapse scheme, for example, based on a result of the loop perfection scheme, as described below.

[0324] From some demonstrative points of view, compiler 160 may be configured to apply the loop collapsing scheme, for example, even without performing the loop perfection scheme, for example, when the loop perfection scheme is unnecessary, e.g., when an input loop nest encloses a perfect loop nest.

[0325] In one example, compiler 160 may be configured to apply the loop collapse scheme to provide, for example, target code 115 configured for execution by one or more processor architectures that support only single basic block loops.

[0326] In some example aspects, compiler 160 may be configured to combine a plurality of individual loops of a loop nest into a single loop, which may be configured to execute substantially all iterations of the original loop nest, as described below.

[0327] In some example aspects, the execution of the merged loop may be configured in advance, for example, to configure evolution along the dimensions of the original loop.

[0328] In some example aspects, the loop collapse scheme may be configured to provide a technical solution to support execution of target code 115 by one or more processor architectures, including processor architectures where the calculation of induction variables may be computationally intensive.

[0329] In some example aspects, the compiler 160 may be configured to identify a perfect loop nest that includes a plurality of nested loops, for example, based on the source code 112, as described below.

[0330] In some example aspects, the plurality of nested loops may correspond to a respective plurality of dimensions, as described below.

[0331] In some example aspects, a dimension of a nested loop may be executed during a number of iterations of the nested loops, as described below.

[0332] In some example aspects, the compiler 160 may be configured to configure a combined loop based on the loop nest, for example, by combining the plurality of loop nests into a single loop, for example, based on the plurality of dimensions, as described below.

[0333] In some example aspects, compiler 160 may compile source code 112 of a program to be executed by a target processor, e.g., processor 180, as described below.

[0334] For example, the compiler 160, based on the source code 112, for example, may identify a loop nest that includes an outer loop (y-loop) along a dimension based on a variable height, a nested loop (x-loop) along a dimension based on a variable width, and an inner loop (z-loop) along a dimension based on a variable area, for example, as follows: Example (4)

[0335] For example, as shown in Example 4, the nested loop may include a pre-header instruction, such as out1[y * width + x] = inp1[y * width + x] + 7, which may be located before the header of the inner loop (z-loop).

[0336] Example 4 shows that the pre-header instruction (out1[y * width + x] = inp1[y * width + x] + 7) can be executed before the execution of the inner loop begins.

[0337] Example 4 shows that the pre-header instruction (out1[y * width + x] = inp1[y * width + x] + 7) can include an outer load operation, e.g., inp1[y * width + x], and an outer store operation, e.g., "out1[y * width + x]=", which can be executed each time, for example, before the execution of the inner loop begins.

[0338] In some example aspects, compiler 160 may be configured to insert the pre-header instruction into the inner loop, for example, to create a perfect loop nest, as described below.

[0339] For example, compiler 160 may be configured to move the pre-header instruction (out1[y * width + x] = inp1[y * width + x] + 7) into the inner loop and convert the pre-header instruction (out1[y * width + x] = inp1[y * width + x] + 7) into a conditional pre-header instruction (also called a "sunk conditional instruction"), as described below.

[0340] For example, as shown in Example 4, the outer loop may include a latch instruction, such as out2[y] = a, which may be located after the nested loop and the inner loop.

[0341] For example, as shown in Example 4, the latch instruction may include an outer storage operation, e.g., out2[y] = a.

[0342] Example 4 shows that the latch instruction (out2[y] = a) can be executed every time after the last iteration of the inner loop and the nested loop.

[0343] In some example aspects, compiler 160 may be configured to move the latch instruction (out2[y] = a) into the inner loop, for example, to create a perfect loop nest, as described below.

[0344] For example, the compiler 160 may be configured to move the latch instruction (out2[y] = a) into the inner loop and convert the latch instruction (out2[y] = a) into a conditional latch instruction (also called a "hoisted conditional instruction"), which may be based on the latch instruction, as described below.

[0345] For example, as shown in Example 4, the inner loop may include an inner load instruction, e.g., a = inp2[y * width * area + x * area + z], which may be located inside the inner loop.

[0346] In some example aspects, the compiler 160 may be configured to convert the perfect loop nest into a summarized loop along a dimension, which may be based, for example, on the height value, the width value, and the area value, e.g., as follows: for(int ind = 0; ind < height * width * area; ind++) { char val = inp1[inp1_ind]; char result = val + 7; if (first_iteration_of_z_loop) out1[out1_ind] = result; char a = inp2[inp2_ind]; if(last_iteration_of_x_and_z_loops) out2[out2_ind] = a;} Example (5)

[0347] In some example aspects, as illustrated in Example 5, the combined loop may include a single block that contains instructions based on all of the instructions of Example 4.

[0348] In some exemplary aspects, as shown in Example 5, load and store operations in the pre-header instruction “out1[y * width + x] = inp1[y * width + x] + 7” can be converted into a conditional pre-header instruction: “if (first_iteration_of_z_loop) out1[out1_ind] = result”.

[0349] In some example aspects, as illustrated in Example 5, the conditional pre-header instruction may include a predicate-based condition that may indicate, identify, assert, predict, and / or assert a start of the inner loop.

[0350] For example, in some exemplary aspects, as shown in Example 5, the conditional pre-header instruction can be executed only if the predicate (first_iteration_of_z_loop) is true, that is, only when the inner loop starts executing.

[0351] In some exemplary aspects, as shown in Example 5, the latch instruction out2[y] = a can be converted into a conditional latch instruction “if(last_iteration_of_x_and_z_loops) out2[out2_ind] = a”.

[0352] In some example aspects, as illustrated in Example 5, the conditional latch instruction may include a predicate-based condition that may indicate, identify, confirm, predict, and / or assert the last iteration of the inner loop and the last iteration of the nested loop.

[0353] For example, in some exemplary aspects, as shown in Example 5, the conditional latch instruction can only be executed if the predicate (last_iteration_of_x_and_z_loops) is true, that is, only if the inner loop and the nested loop are after the last iteration.

[0354] In some exemplary aspects, as illustrated in Example 5, the inner load instruction, e.g., a = inp2[y * width * area + x * area + z], can be converted to a load instruction, e.g., char a = inp2[inp2_ind]. Example 5 shows that the inner load instruction (a = inp2[y * width * area + x * area + z]) cannot be converted to a conditional instruction.

[0355] In some exemplary aspects, as illustrated in Example 5, indices of the load and store instructions can be calculated as AGU parameters, for example.

[0356] In some example aspects, as illustrated in Example 5, indices of the conditional latch instruction and / or the conditional pre-header instruction may be calculated, for example, as AGU parameters, e.g., as described below.

[0357] In some example aspects, compiler 160 may be configured to provide a technical solution to support computational predicates, such as conditional instructions, that may be used to convert outer loop instructions to summarized loop instructions, as described below.

[0358] In some exemplary aspects, e.g., in some use cases, implementations, and / or scenarios, converting the outer loop instructions using conditional store / load instructions may be inefficient.

[0359] In one example, the conditional save / load instruction may require an additional conditional instruction.

[0360] In another example, the conditional save / load instructions may require maintaining one or more induction variables in the loop.

[0361] In some example aspects, compiler 160 may be configured to configure a summarized loop, e.g., the summarized loop of Example 5, e.g., according to a predicate-based memory access mechanism, which may be configured to support the configuration of memory access operations, e.g., based on one or more predicates, e.g., as described below.

[0362] In some example aspects, the predicate-based memory access mechanism may be configured to provide a technical solution to support the configuration of memory access operations, e.g., load instructions and / or store instructions, based on a loop start predicate and / or a loop end predicate, as described below.

[0363] In some example aspects, the predicate-based memory access mechanism may be configured to provide a technical solution to support memory access operations based on the loop start predicate and / or the loop end predicate, for example, even without computing induction variables of one or more of the loops in the loop nest, as described below.

[0364] In some example aspects, the predicate-based memory access mechanism may be configured to provide a technical solution to support memory access operations based on the loop start predicate and / or the loop end predicate, for example, in processor architectures that may not support the computation of induction variables.

[0365] In some example aspects, the predicate-based memory access mechanism may be configured to provide a technical solution to support memory access operations based on the loop start predicate and / or the loop end predicate, for example, in processor architectures where the calculation of induction variables may be computationally intensive, e.g., when loops are fully configured in advance.

[0366] In some example aspects, compiler 160 may be configured to implement the hoisted conditional instruction and / or the sunk conditional instruction of Example 5, for example, by setting one or more AGU parameters corresponding to the hoisted conditional instruction and / or the sunk conditional instruction, as described below.

[0367] In some example aspects, the complier 160 may be configured to configure an AGU to perform a memory access operation, which may be performed, for example, at the beginning of an inner loop or at the end of an inner loop, based on an outer loop instruction, as described below.

[0368] In some example aspects, compiler 160 may be configured to identify a loop nest based on source code 112 to be compiled into target code 150 to be executed by a target processor 180, e.g., as described below.

[0369] In some example aspects, compiler 160 may be configured to generate target code 115 configured, for example, for execution by a target vector processor, such as vector processor 180, as described below.

[0370] In some example aspects, compiler 160 may be configured to generate target code 115 configured, for example, for execution by a Very Long Instruction Word (VLIW) Single Instruction / Multiple Data (SIMD) target processor, e.g., processor 180.

[0371] In other respects, the compiler 160 may be configured to generate the target code 115 configured, for example, for execution by another suitable processor type.

[0372] In some example aspects, the compiler 160 may be configured to generate the target code 115, for example, based on the source code 112 that includes Open Computing Language (OpenCL) code.

[0373] In other aspects, the compiler 160 may be configured to generate the target code 115 based on, for example, the source code 112 including another suitable type of code.

[0374] In some example aspects, the compiler 160 may be configured to compile the source code 112 into the target code 115, for example, according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme.

[0375] In other aspects, the compiler 160 may be configured to compile the source code 112 into the target code 115 according to any other suitable compilation scheme.

[0376] In some example aspects, the compiler 160 may be configured to identify the loop nest in the source code 112, e.g., in the event that the loop nest is included in the source code 112.

[0377] In some example aspects, the compiler 160 may be configured to identify the loop nest in code, such as middle-end code or other code that can be compiled from the source code 112.

[0378] In some example aspects, the loop nest may include a plurality of loops, for example, at least one outer loop and an inner loop within the outer loop, as described below.

[0379] In some example aspects, the plurality of loops may include at least a first loop, e.g., an outer loop, and a second loop, e.g., an inner loop, nested within the first loop, e.g., as described below.

[0380] In some example aspects, the first loop may include at least one instruction for the first loop (outer loop instruction), which may be outside the second loop, e.g., as described below.

[0381] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to configure an AGU of target processor 180, for example, based on the first loop instruction, as described below.

[0382] In some example aspects, the AGU configuration code may be configured to configure a first dimension of the AGU, for example, based on the first loop, as described below.

[0383] In some example aspects, the AGU configuration code may be configured to configure a second dimension of the AGU, for example, based on the second loop, as described below.

[0384] In some example aspects, the AGU configuration code may be configured to configure the second dimension of the AGU, for example, to configure a memory access operation to be performed at the beginning of the second loop or at the end of the second loop, as described below.

[0385] For example, in some example aspects, the memory access operation may be based on the first loop instruction, as described below.

[0386] In some example aspects, the memory access operation may include a load operation or a store operation, e.g., as described below.

[0387] In some example aspects, compiler 160 may be configured to generate target code 115, for example, based on compiling source code 112, as described below.

[0388] In some example aspects, the target code 115 may be based on the AGU configuration code, for example, as described below.

[0389] In some example aspects, the plurality of loops may include a third loop, which may be nested within the first loop, for example, as described below.

[0390] In some example aspects, the second loop may be nested within the third loop, as described below.

[0391] In some example aspects, the instruction of the first loop may be outside the third loop, as described below.

[0392] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to configure a third dimension of the AGU, for example, based on the third loop as described below.

[0393] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to configure the third dimension, for example, to configure the memory access operation to be performed at the beginning of the second loop or at the end of the second loop, as described below.

[0394] In some example aspects, the third loop may include an instruction for the third loop, which may be located outside of the second loop, for example, as described below.

[0395] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to configure a different AGU of the target processor, for example, based on the third loop instruction, as described below.

[0396] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to configure a first dimension of the other AGU, for example, based on the third loop, as described below.

[0397] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to configure a second dimension of the other AGU, for example, based on the second loop, as described below.

[0398] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to configure the second dimension of the other AGU, for example, to configure a different memory access operation to be performed at the beginning of the second loop or at the end of the second loop, as described below.

[0399] For example, in some example aspects, the other memory access operation may be based on the third loop instruction, as described below.

[0400] In some example aspects, Complier 160 may be configured to convert the loop nest into a converted loop that includes the memory access operation, as described below.

[0401] For example, in some example aspects, the target code 115 may be based on the converted loop as described below.

[0402] In some example aspects, the converted loop may include the memory access operation and the other memory access operation, as described below.

[0403] In some example aspects, the converted loop may include a perfect flat loop in which, for example, all operations of the loop nest are implemented in the converted loop, as described below.

[0404] In some example aspects, the converted loop may include a fully aggregated loop, e.g., including only a single basic block loop, e.g., based on the plurality of loops, e.g., as described below.

[0405] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set a base parameter of the AGU, for example, based on a memory pointer of the first loop instruction, as described below.

[0406] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set a maximum (Max) parameter of the second dimension of the AGU, for example, based on an input corresponding to the first loop instruction, as described below.

[0407] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set the max parameter of the second dimension of the AGU and to set a max parameter of the third dimension of the AGU, for example, based on the input size corresponding to the instruction of the first loop, for example, in the case where the second loop is nested within the third loop, as described below.

[0408] In some example aspects, the at least one instruction of the first loop may include a pre-header instruction to be executed before a first iteration of the inner loop, e.g., as described below.

[0409] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to configure the second dimension of the AGU, for example, to configure the memory access operation to be executed only at the beginning of the second loop, for example, when the first loop instruction includes the pre-header instruction, as described below.

[0410] In some example aspects, compiler 160 may be configured to generate AGU configuration code to, for example, set the AGU's base parameter to the pre-header instruction's memory pointer, such as when the first loop instruction includes the pre-header instruction, as described below.

[0411] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to set a minimum (Min) parameter of the second dimension of the AGU to zero, for example, when the first loop instruction includes the pre-header instruction, as described below.

[0412] In some example aspects, the pre-header instruction may include a loading operation as described below.

[0413] In some example aspects, complier 160 may be configured to, for example, configure the AGU configuration code to set a step parameter of the second dimension of the AGU to zero, based on a determination that the pre-header instruction includes a load operation, e.g., as described below.

[0414] In some example aspects, the pre-header instruction may include a save operation, as described below.

[0415] In some example aspects, the complier 160 may be configured, for example, based on a determination that the pre-header instruction includes a store operation, to configure the AGU configuration code to set the step parameter of the second dimension of the AGU, for example, based on an input corresponding to the pre-header instruction, as described below.

[0416] In some example aspects, the at least one instruction of the first loop may include a latch instruction that executes after a final iteration of the second loop, e.g., as described below.

[0417] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to configure the second dimension of the AGU, for example, to configure the memory access operation to be executed only at the end of the second loop, for example, when the first loop instruction includes the latch instruction, as described below.

[0418] In some example aspects, the latch instruction may include a load operation, as described below.

[0419] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the base parameter of the second dimension of the AGU, for example, to the memory pointer of the latch instruction, for example, when the latch instruction includes the load operation, as described below.

[0420] In some example aspects, the compiler 160 may be configured to generate AGU configuration code, for example, to set a min parameter of the second dimension of the AGU to zero, for example, when the latch instruction includes the load operation, as described below.

[0421] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to set the Max parameter of the second dimension of the AGU to an input size corresponding to the latch instruction, for example, when the latch instruction includes the load operation, as described below.

[0422] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to set the step parameter of the second dimension of the AGU to zero, for example, when the latch instruction includes the load operation, as described below.

[0423] In some example aspects, the latch instruction may include a storage operation as described below.

[0424] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the base parameter of the AGU, for example, based on a first parameter value, a second parameter value, and a third parameter value, for example, when the latch instruction includes the storage operation, as described below.

[0425] In some example aspects, the first parameter value may include the input corresponding to the latch instruction, e.g., as described below.

[0426] In some example aspects, the second parameter value may include a total number of iterations over one or more loops located within the first loop and including the second loop, as described below.

[0427] In some example aspects, the third parameter value may include a number of dimensions of the AGU corresponding to one or more loops, as described below.

[0428] In some exemplary aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the AGU's base parameter Base as follows: Base = OrigBase + EntrySize * ([Σ TripCount(L)] - #InnerDims), where OrigBase denotes a memory pointer of the latch instruction, where EntrySize is the input size corresponding to the latch instruction, where [Σ TripCount(L)] denotes the total number of iterations over the one or more loops that are in the first loop and enclose the second loop, and where #InnerDims denotes the number of dimensions of the AGU corresponding to the one or more loops, e.g., as described below.

[0429] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set the step parameter of the second dimension of the AGU, for example, based on the input corresponding to the latch instruction, for example, when the latch instruction includes the store operation, for example, as described below.

[0430] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the min parameter of the second dimension of the AGU, for example, based on the input size corresponding to the latch instruction and a number of iterations in the second loop, for example, when the latch instruction includes the store operation, as described below.

[0431] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the max parameter of the second dimension of the AGU, for example, based on the min parameter of the second dimension of the AGU and the input size corresponding to the latch instruction, for example, when the latch instruction includes the store operation, as described below.

[0432] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the step parameter of the second dimension of the AGU, for example, based on an additive inverse of the input size corresponding to the latch instruction, for example, when the latch instruction includes the store operation, as described below.

[0433] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set the min parameter of the second dimension of the AGU, for example, based on the input size corresponding to the latch instruction and the number of iterations in the second loop, for example, when the latch instruction includes the store operation, as described below.

[0434] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set the min parameter of the second dimension of the AGU, for example, based on a product of the additive inverse of the input corresponding to the latch instruction and a subtraction result where one is subtracted from the number of iterations in the second loop, for example, when the latch instruction includes the store operation, as described below.

[0435] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set the max parameter of the second dimension of the AGU, for example, based on the min parameter of the second dimension of the AGU and the input size corresponding to the latch instruction, for example, when the latch instruction includes the store operation, as described below.

[0436] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set the max parameter of the second dimension of the AGU, for example, based on a sum of the min parameter of the second dimension of the AGU and the input size corresponding to the latch instruction, for example, when the latch instruction includes the store operation, as described below.

[0437] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, based on determining that the plurality of loops includes a third loop nested within the first loop, that the second loop is nested within the third loop, and that the latch instruction including the storage operation is outside of the third loop, for example, as described below.

[0438] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to configure the third dimension of the AGU, for example, based on the third loop, for example, when the latch instruction enclosing the storage operation is outside the third loop, for example, as described below.

[0439] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set a step parameter of the third dimension of the AGU, for example, based on the input size corresponding to the latch instruction, for example, when the latch instruction including the store operation is outside the third loop, as described below.

[0440] In some example aspects, compiler 160 may be configured to generate the AGU configuration code, for example, to set a min parameter of the third dimension of the AGU, for example, based on the input size corresponding to the latch instruction and a number of iterations in the third loop, for example, when the latch instruction including the storage operation is outside the third loop, as described below.

[0441] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to set a max parameter of the third dimension of the AGU, for example, based on the min parameter of the third dimension of the AGU, and the input size corresponding to the latch instruction, for example, when the latch instruction including the store operation is outside the third loop, as described below.

[0442] In some example aspects, compiler 160 may be configured to perform one or more operations, for example, according to a loop compilation scheme, which may be configured to compile instructions for a loop, as described below.

[0443] In some example aspects, compiler 160 may be configured to identify load and / or store operations and analyze one or more attributes of a load / store operation, e.g., for each load and / or store operation, as described below.

[0444] In some example aspects, compiler 160 may be configured to analyze a load / store operation, e.g., for each load and / or store operation, its innermost enclosing loop, its base parameter, its step parameter, e.g., step size, its offset, its bounds, e.g., min / max parameters, and / or its pass value.

[0445] In some example aspects, compiler 160 may be configured to divide the identified loads and / or stores into one or more groups, for example, according to their attributes, e.g., according to their stride, limit, and / or traversal values.

[0446] In some example aspects, compiler 160 may be configured to assign an AGU to a group of identified load / store operations, e.g., each group of identified load / store operations.

[0447] In one example, each group of identified load / store operations can be implemented with a single AGU.

[0448] In some example aspects, compiler 160 may be configured to configure AGU configuration code for AGUs that implement load and / or store operations that may be outside of an innermost loop.

[0449] For example, the AGU configuration code may specify one or more special parameters, e.g., including a special base parameter, a special step parameter, and / or special min / max parameters, for a load and / or store operation in an outer loop, e.g., as described below.

[0450] In some example aspects, the compiler 160 may be configured to lower or raise an outer load that may be outside of an inner loop.

[0451] In some example aspects, the compiler 160 may be configured to generate AGU configuration code, for example, to configure an AGU based on the outer load.

[0452] In some example aspects, the AGU configuration code may configure a load operation based on the outer load operation, which may be executed at the beginning or end of the inner loop.

[0453] In some example aspects, the compiler 160 may be configured to generate the AGU configuration code, for example, to configure the AGU to perform the loading operation in the first iteration of the inner loop or in the last operation of the inner loop.

[0454] In some example aspects, compiler 160 may be configured to set a base parameter of the AGU, for example, to a memory pointer of the outer loader, e.g., similar to a usual setting of the base parameter.

[0455] In some example aspects, compiler 160 may be configured to set the AGU's step parameter for a dimension corresponding to an inner loop, denoted, for example, by L, to zero for each inner loop as follows:

[0456] For example, the setting of Step L = 0 with regard to charging operations.

[0457] In some example aspects, the compiler 160 may be configured to set the minimum parameter of the AGU for a dimension corresponding to the inner loop L to zero and set the maximum parameter of the AGU for the dimension corresponding to the inner loop L, for example, based on an input of the outer loader, as follows:

[0458] For example, in some exemplary aspects, compiler 160 may be configured to lower the inp1[y * width + x] loading of the pre-header instruction of Example 4 into the inner loop of Example 4.

[0459] In some exemplary aspects, compiler 160 may be configured to identify an innermost enclosing loop of the outer loader of Example 4.

[0460] For example, compiler 160 may identify the loop over x (X-loop) as the innermost enclosing loop for the load operation inp1[y * width + x], while the loop over z (Z-loop) may be more inner than the loop of the load operation inp1[y * width + x].

[0461] In some example aspects, compiler 160 may be configured to identify an input size of the memory pointer inp1. For example, the input size of the memory pointer inp1 may be 1 because the memory pointer inp1 may be configured to enclose a character (char).

[0462] In some exemplary aspects, compiler 160 may be configured to convert the outer load inp1[y * width + x] into a load instruction, e.g., char val = inp1[inp1_ind], by configuring the AGU configuration code for a dimension corresponding to the inner loop, e.g., the dimension corresponding to the Z-loop, of an AGU that implements the memory pointer inp1, e.g., as follows: Base = inp1 Step(Z-Loop) = 0 Min(Z-Loop) = 0 Max(Z loop) = sizeof(char) = 1

[0463] In some example aspects, compiler 160 may be configured to lower an outer store operation that may be outside of an inner loop, e.g., as described below.

[0464] In some example aspects, the compiler 160 may be configured to generate AGU configuration code, for example, to configure an AGU based on the lowering of the outer store operation.

[0465] In some example aspects, the AGU configuration code may configure a store operation based on the descent of the outer store operation, which may be executed at the beginning of the inner loop. For example, the store operation may be executed on the first iteration of the inner loop.

[0466] In some example aspects, the compiler 160 may be configured to set the base parameter of the AGU to, for example, a memory pointer of the outer store operation, e.g., similar to a typical setting of the base parameter.

[0467] In some example aspects, the compiler 160 may be configured to set the step parameter of the AGU for a dimension corresponding to an inner loop, denoted L, for example, for each inner loop, for example, based on an input of the outer store operation, as follows:

[0468] In some example aspects, compiler 160 may be configured to set the minimum parameter of the AGU for the dimension corresponding to the inner loop L, e.g., to zero, and to set the maximum parameter of the AGU for the dimension corresponding to the inner loop L, e.g., based on an input of the outer store operation, e.g., as follows:

[0469] In some exemplary aspects, compiler 160 may be configured to lower the outer store operation "out1[y * width + x]=.." of the pre-header instruction of Example 4, for example, into the inner loop of Example 4.

[0470] In some exemplary aspects, compiler 160 may be configured to identify an innermost enclosing loop of the outer store operation of Example 4.

[0471] For example, compiler 160 may identify the X-loop as the innermost enclosing loop for the store operation "out1[y * width + x]=..", while the Z-loop may be more inner than the loop of the store operation "out1[y * width + x]= - -".

[0472] In some example aspects, compiler 160 may be configured to identify an input size of the memory pointer out1.

[0473] For example, the input size of the memory pointer out1 may be 1 because the memory pointer out1 may be configured to enclose a character (Char).

[0474] In some exemplary aspects, compiler 160 may be configured to convert the outer store operation "out1[y * width + x]=.." into a store instruction, e.g., "if (first_iteration_of_z_loop) out1[out1_ind] = result," for example, by configuring the AGU configuration code for a dimension corresponding to the inner loop, e.g., the dimension corresponding to the Z loop, from an AGU that implements the memory pointer out1, e.g., as follows:

[0475] In some example aspects, compiler 160 may be configured to lift an outer store operation that may be outside of an inner loop, e.g., as described below.

[0476] In some example aspects, the compiler 160 may be configured to generate AGU configuration code, for example, to configure an AGU based on the lifting of the outer store operation.

[0477] For example, in some example aspects, the AGU configuration code may configure a store operation based on the lifting of the outer store operation, which may be executed at the end of the inner loop. For example, the store operation may be executed on the last iteration of the inner loop.

[0478] In some example aspects, compiler 160 may be configured to determine a base parameter of the AGU, for example, based on an input corresponding to the outer storage operation, for example, as follows: Base=OrigBase+EntrySize*([∑TripCount(L)]−#InnerDims) where OrigBase denotes the base of the outer storage process, where TripCount(L) is the number of iterations for the loop L, and where #InnerDims denotes the number (total number) of AGU dimensions corresponding to loops that are inner than the loop of the outer storage operation. For example, the summation over loop L can be performed over all loops L that are inner than the loop of the outer storage operation that is lifted.

[0479] In some example aspects, compiler 160 may be configured to set the step parameter of the AGU, e.g., for dimensions corresponding to the inner loops, based, for example, on the input size of the outer store operation, e.g., as follows:

[0480] In some example aspects, compiler 160 may be configured to set the minimum parameter of the AGU, e.g., for a dimension corresponding to an inner loop L, e.g., for each inner loop, and set the maximum parameter of the AGU for the dimension corresponding to the inner loop L, e.g., based on the input size of the outer store operation, e.g., as follows:

[0481] In some example aspects, compiler 160 may be configured to, for example, elevate the storage operation “outf2[y] = a” of the latch instruction of Example 4 into the inner loop of Example 4.

[0482] In some exemplary aspects, compiler 160 may be configured to identify an innermost enclosing loop of the outer store operation of Example 4.

[0483] For example, compiler 160 may identify the loop over y (Y-loop) as the innermost enclosing loop for the store operation "ouf2[y] = a", while the X-loop and the Z-loop may be more inner than the loop of the store operation "out2[y] = a".

[0484] In some exemplary aspects, compiler 160 may be configured to identify an input size of the memory pointer out2.

[0485] For example, the input size of the memory pointer out2 may be 1 because the memory pointer out2 may be configured to enclose a character (char).

[0486] In some exemplary aspects, the compiler 160 may be configured to determine the number of iterations (trip count) of the inner X-loop and the number of iterations (trip count) of the inner Z-loop, for example, as follows:

[0487] In some example aspects, compiler 160 may be configured to convert the outer store operation "outf2[y] = a", for example, into a conditional store instruction, e.g., "if( / ast_iteration_of_x_and_z_loops) out2[out2_ind] = a", for example, by configuring AGU configuration code for dimensions of the inner loops, e.g., the dimension corresponding to the X loop and the dimension corresponding to the Z loop, from an AGU that implements the memory pointer out2, e.g., as follows:

[0488] In some exemplary aspects, the compiler 160 may configure AGU configuration code to, for example, configure a plurality of AGUs based on the code of Example 4, for example, as follows: Example (6a)

[0489] In some exemplary aspects, compiler 160 may configure loop code to execute the loop of Example 4, for example, based on the AGU configuration code of Example 6a, for example, as follows: Example (6b)

[0490] In some example aspects, as illustrated in Example 6a, compiler 160 may allocate a first AGU, e.g., agu1, to perform the load operation “val = agu1.load(),” for example, based on the outer load operation “inp1[y * width + x]” of Example 4.

[0491] In some example aspects, as illustrated in Example 6a, compiler 160 may allocate a second AGU, e.g., agu2, to perform the load operation "a = agu2.load()", for example, based on the inner load operation "a = inp2[y * width * area + x * area + z]" of Example 4.

[0492] In some example aspects, as illustrated in Example 6a, compiler 160 may allocate a third AGU, e.g., agu3, to perform the store operation "agu3.store(val);", for example, based on the outer store operation "out1[y*width + x] = ...;" from Example 4.

[0493] In some example aspects, as illustrated in Example 6a, compiler 160 may allocate a fourth AGU, e.g., agu4, to perform a store operation "agu4.store(a)", e.g., based on the outer store operation "out2[y] = a" of Example 4.

[0494] In some exemplary aspects, as shown in Example 6a, Compiler 160 may configure AGU configuration code to configure agu1.

[0495] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu1 may be configured to set a base parameter of the first AGU to the memory pointer agu1.

[0496] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu1 may be configured to set a min parameter for the dimension z of the first AGU to zero and to set the max parameter for the dimension z of the first AGU to 1.

[0497] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu1 may be configured to set a number of iterations for the dimension z of the first AGU to the value area and to set the step (step size) for the dimension z of the first AGU to zero.

[0498] For example, these settings for the dimension z of the first AGU can configure the load operation val = agu1.load() to be executed, for example, at the beginning of the inner loop z.

[0499] In some exemplary aspects, as shown in Example 6a, Compiler 160 can configure AGU configuration code to configure agu3.

[0500] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu3 may be configured to set a base parameter of the third AGU to the memory pointer out1.

[0501] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu3 may be configured to set a min parameter for the dimension z of the third AGU to zero and to set the max parameter for the dimension z of the third AGU to 1.

[0502] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu1 may be configured to set a number of iterations for the dimension z of the third AGU to the value area and to set the step (step size) for the dimension z of the third AGU to 1.

[0503] For example, these settings for the dimension z of the first AGU can configure the loading operation agu3.store(val) to be executed, for example, at the beginning of the inner loop z.

[0504] In some exemplary aspects, as shown in Example 6a, Compiler 160 can configure AGU configuration code to configure agu4.

[0505] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to set a base parameter of the fourth AGU based, for example, on the memory pointer out2 and a number of iterations of the inner loops, e.g., the values ​​area and width, such as the following:

[0506] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a min parameter for the dimension x of the fourth AGU, for example, as follows:

[0507] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a max parameter for the dimension x of the fourth AGU, for example, as follows:

[0508] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a stride parameter for dimension x of the fourth AGU, for example, as follows:

[0509] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to set a count parameter for the dimension x of the fourth AGU to width, e.g., according to the number of iterations of the X-Loop.

[0510] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a min parameter for the dimension z of the fourth AGU, e.g., as follows:

[0511] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a max parameter for the dimension z of the fourth AGU, e.g., as follows:

[0512] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to specify a stride parameter for the dimension z of the fourth AGU, for example, as follows:

[0513] In some exemplary aspects, as illustrated in Example 6a, the AGU configuration code for configuring agu4 may be configured to set a Count parameter for the z dimension of the fourth AGU to area, e.g., according to the number of iterations of the Z-loop.

[0514] In one example, the compiler 160 may process the source code 112, which may be based on Example 4, for example, with a setting of width=3, and a setting of area=5, as follows: Example (7)

[0515] In some exemplary aspects, as illustrated in Example 7, an outermost loop (Y-loop) may include an outer store instruction, e.g., [y] = c, which may be located after a nested loop (X-loop) and an inner loop (Z-loop).

[0516] In some example aspects, the outer store instruction may be executed after 3 iterations of the X-loop, where each iteration of the X-loop includes 5 iterations of the Z-loop. For example, the outer store instruction may be executed after a total of 15 iterations, e.g., 3*5=15.

[0517] In some example aspects, compiler 160 may be configured to generate AGU configuration code, for example, to configure an AGU based on the outer store instruction of Example 7.

[0518] In some example aspects, the AGU configuration code may specify parameters, for example, for the x-dimension and the z-dimension of the AGU, e.g., including the base parameter, the total number of iterations, the step parameter, the min parameter, and the max parameter, e.g., based on the outer storage instruction out[y] = c, e.g., as described above.

[0519] Referring to Fig. 4, which schematically illustrates an execution scheme 400 for performing a latch operation in a loop nest according to some example aspects.

[0520] In some example aspects, execution scheme 400 may demonstrate setting the AGU to configure execution of the outer store operation out[y] = c of Example 7.

[0521] In some exemplary aspects, as in Fig. 4, the execution scheme 400 may include three execution steps, for example, corresponding to the three iterations of the X-loop of Example 7.

[0522] In some exemplary aspects, as in Fig. 4, the execution scheme 400 may include a first execution step 410 corresponding to a first iteration of the X-loop, e.g., x=0.

[0523] In some exemplary aspects, as in Fig. 4, the execution scheme 400 may include a second execution step 420 corresponding to a second iteration of the X-loop, e.g., x=1.

[0524] In some exemplary aspects, as in Fig. 4, the execution scheme 400 may include a third execution step 430 corresponding to a third iteration of the X-loop, e.g., x=2.

[0525] In some exemplary aspects, as in Fig. 4, the Z-loop may perform 5 iterations, for example, in each execution step of the execution scheme 400.

[0526] In some exemplary aspects, as in Fig. 4, the AGU configuration code may be configured based on Example 7, for example, to set the Min parameter to zero and the Max parameter to one, e.g., for each of the x-dimension and the z-dimension of the AGU.

[0527] In some exemplary aspects, as in Fig. 4, the AGU configuration code may be configured based on Example 7, for example, to set the AGU base parameter to a memory pointer 6.

[0528] In some exemplary aspects, as in Fig. 4, during the first execution step 410, a first iteration of the Z-loop may begin at a memory pointer 7 and a final iteration of the Z-loop may be at a memory pointer 2. Accordingly, the store operation, which may be limited by the min parameter zero and the max parameter one, may not be executed.

[0529] In some exemplary aspects, as in Fig. 4, during the second execution step 420, a first iteration of the Z-loop may begin at memory pointer 6, and the last iteration of the Z-loop may be at memory pointer 1. Accordingly, the store operation, which may be limited by the min parameter zero and the max parameter one, may not be executed.

[0530] In some exemplary aspects, as in Fig. 4, during the third execution step 430, a first iteration of the Z-loop may begin at memory pointer 5, and the last iteration of the Z-loop may be at memory pointer 0. Accordingly, the store operation, which may be limited by the min parameter zero and the max parameter one, may, for example, only be performed on the last iteration of the Z-loop in the last iteration of the X-loop.

[0531] Referring to Fig. 5, which schematically illustrates an execution scheme 500 for performing a pre-header load or store operation in a loop nest according to some example aspects.

[0532] In some example aspects, execution scheme 500 may illustrate execution of the pre-header load or store instruction, for example, according to the loop execution scheme.

[0533] In some example aspects, the pre-header load or store instruction may be within an outer loop, which may be outside an inner loop.

[0534] In some exemplary aspects, as in Fig. 5, the AGU configuration code corresponding to an AGU for executing the pre-header load or store operation may, for example, set the Min parameter to zero and the Max parameter to one, for example, for a dimension of the AGU corresponding to the pre-header load or store instruction.

[0535] In some exemplary aspects, as in Fig. 5, the AGU configuration code corresponding to the AGU that performs the pre-header load or store operation may set the base parameter of the AGU, for example, to the memory pointer of the outer pre-header load or store instruction.

[0536] In some exemplary aspects, as in Fig. 5, the AGU configuration code can be configured to provide a technical solution to ensure that the pre-header load or store operation is executed only once at the beginning of the inner loop.

[0537] For example, by setting the min parameter and the max parameter, which can restrict the execution of the load or store operation only to the first iteration of the inner loop, it can be ensured that the pre-header load or store operation is executed only once at the beginning of the inner loop, as described above.

[0538] It will now Fig. 6, which schematically illustrates a method of compiling code for a processor. For example, one or more acts of the method of Fig. 6 from a system, e.g. System 100 ( Fig. 1); a device, e.g. device 102 ( Fig. 1); a server, e.g. Server 170 ( Fig. 1); and / or a compiler, e.g. Compiler 160 ( Fig. 1) and / or Compiler 200 ( Fig. 2) are carried out.

[0539] In some example aspects, as indicated in block 602, the method may include identifying a loop nest based on source code to be compiled into target code to be executed by a target processor. For example, the loop nest may include a plurality of loops, the plurality of loops including at least a first loop and a second loop nested within the first loop. For example, the first loop may include at least one instruction of the first loop that is outside the second loop. For example, compiler 160 ( Fig. 1) be configured to identify the loop nest, for example based on the source code 112 ( Fig. 1), e.g. as described above.

[0540] In some example aspects, as indicated in block 604, the method may include generating AGU configuration code to configure an AGU of the target processor based on the instruction of the first loop. For example, the AGU configuration code may configure a first dimension of the AGU based on the first loop and a second dimension of the AGU based on the second loop. For example, the AGU configuration code may configure the second dimension of the AGU to configure a memory access operation to be performed at the beginning of the second loop or at the end of the second loop. For example, the memory access operation may be based on the instruction of the first loop. For example, the compiler 160 ( Fig. 1) be configured to generate the AGU configuration code to configure the AGU of the target processor 180 ( Fig. 1) based on the first loop command as described above.

[0541] In some example aspects, as indicated in block 606, the method may include generating the target code based on compiling the source code. The target code may be based, for example, on the AGU configuration code. For example, compiler 160 ( Fig. 1) be configured to receive destination code 115 ( Fig. 1) is generated based on the AGU configuration code, for example based on compiling the source code 112 ( Fig. 1), as described above.

[0542] It will now Fig. 7, which schematically illustrates a product of manufacture 700 according to some example aspects. Product 700 may include one or more tangible computer-readable ("machine-readable") non-transitory storage media 702 that may contain computer-executable instructions, e.g., implemented by logic 704, that, when executed by at least one computer processor, enables the at least one computer processor to perform one or more operations on device 102 ( Fig. 1), the server 170 ( Fig. 1) and / or the compiler 160 ( Fig. 1) to implement the device 102 ( Fig. 1), the server 170 ( Fig. 1) and / or the compiler 160 ( Fig. 1) to cause one or more operations and / or functionalities to be carried out, triggered and / or implemented, and / or to carry out one or more operations and / or functionalities that are intended to be carried out with reference to the Fig.1 to 6, and / or to execute, initiate, and / or implement one or more of the operations described herein. The terms "non-transitory machine-readable medium" and "computer-readable non-transitory storage medium" may be construed to include all computer-readable media, with the sole exception of a transient transmitted signal.

[0543] In some example aspects, the product 700 and / or the machine-readable storage medium 702 may include one or more types of computer-readable storage media capable of storing data, including volatile memory, non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. For example, machine-readable storage media 702 may include RAM, DRAM, double data rate DRAM (DDR-DRAM), SDRAM, static RAM (SRAM), ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content-addressable memory (CAM), polymer memory, phase-change memory, ferroelectric memory, silicon oxide-nitride-oxide-silicon (SONOS) memory, a disk, a hard disk, and the like.The computer-readable storage medium may include any suitable medium related to the downloading or transmission of a computer program from a remote computer to a requesting computer, carried by data signals embodied in a carrier wave or other propagation medium over a communications link, such as a modem, radio, or network connection.

[0544] In some example aspects, logic 704 may include instructions, data, and / or code that, when executed by a machine, may cause the machine to perform a method, process, and / or operations as described herein. For example, the machine may include any suitable processing platform, computing platform, computing unit, processing unit, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware, software, firmware, and the like.

[0545] In some example aspects, logic 704 may include or be implemented as software, a software module, an application, a program, a subroutine, instructions, an instruction set, arithmetic code, words, values, symbols, and the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, style, or syntax to instruct a processor to perform a particular function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language, machine code, and the like. EXAMPLES

[0546] The following examples refer to further aspects. Example 1 includes a product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions that, when executed by at least one processor, enable the at least one processor to cause a compiler to identify a loop nesting based on source code to be compiled into target code to be executed by a target processor, the loop nesting comprising a plurality of loops, the plurality of loops comprising at least a first loop and a second loop nested within the first loop, the first loop comprising at least one instruction of the first loop that is outside the second loop;Generate address generation unit (AGU) configuration code for configuring an AGU of the target processor based on the first loop instruction, the AGU configuration code for configuring a first dimension of the AGU based on the first loop and for configuring a second dimension of the AGU based on the second loop, the AGU configuration code for configuring the second dimension of the AGU to configure a memory access operation to be performed at the beginning of the second loop or at an end of the second loop, the memory access operation being based on the first loop instruction; and generate the target code based on compiling the source code, the target code being based on the AGU configuration code. Example 2 includes the subject matter of Example 1, and optionally, wherein the plurality of loops comprises a third loop nested within the first loop, the second loop nested within the third loop, the instruction of the first loop is outside the third loop, wherein the AGU configuration code is to configure a third dimension of the AGU based on the third loop, wherein the AGU configuration code is to configure the third dimension to configure the memory access operation to be performed at the beginning of the second loop or at the end of the second loop. Example 3 includes the subject matter of Example 2 and optionally, wherein the third loop comprises a third loop instruction located outside the second loop, wherein the AGU configuration code is to configure a different AGU of the target processor based on the third loop instruction, wherein the AGU configuration code is to configure a first dimension of the different AGU based on the third loop and a second dimension of the different AGU based on the second loop, wherein the AGU configuration code is to configure the second dimension of the different AGU to configure a different memory access operation to be performed at the beginning of the second loop or at the end of the second loop, wherein the different memory access operation is based on the third loop instruction. Example 4 includes the subject matter of Example 3, and optionally, wherein the instructions, when executed, cause the compiler to convert the loop nest into a converted loop comprising the memory access operation and the other memory access operation, the target code being based on the converted loop. Example 5 includes the subject matter of any of Examples 2 to 4, and optionally, wherein the AGU configuration code is to set a maximum (Max) parameter of the second dimension of the AGU and a Max parameter of the third dimension of the AGU based on an input corresponding to the instruction of the first loop. Example 6 includes the subject matter of any of Examples 1 to 5, and optionally, wherein the AGU configuration code is to set a base parameter of the AGU based on a memory pointer of the first loop instruction, and to set a maximum (Max) parameter of the second dimension of the AGU based on an input size corresponding to the first loop instruction. Example 7 includes the subject matter of any of Examples 1 to 6, and optionally, wherein the at least one instruction of the first loop comprises a pre-header instruction to be executed before a first iteration of the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure the memory access operation to be executed only at the beginning of the second loop. Example 8 includes the subject matter of Example 7, and optionally, wherein the AGU configuration code shall set a minimum (Min) parameter of the second dimension of the AGU to zero. Example 9 includes the subject matter of Example 7 or 8, and optionally, wherein the instructions, when executed, cause the compiler, based on a determination that the pre-header instruction includes a load operation, to configure the AGU configuration code to set a step parameter of the second dimension of the AGU to zero. Example 10 includes the subject matter of any of Examples 7 to 9, and optionally, wherein the instructions, when executed, cause the compiler, based on a determination that the pre-header instruction includes a store operation, to configure the AGU configuration code to set a step parameter of the second dimension of the AGU based on an input corresponding to the pre-header instruction. Example 11 includes the subject matter of any of Examples 7 through 10, and optionally, wherein the AGU configuration code sets a base parameter of the AGU to a memory pointer of the pre-header instruction. Example 12 includes the subject matter of any of Examples 1 to 11, and optionally, wherein the at least one instruction of the first loop comprises a latch instruction to be executed after a final iteration of the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure the memory access operation to be executed only at the end of the second loop. Example 13 includes the subject matter of Example 12, and optionally, wherein the latch instruction comprises a load operation. Example 14 includes the subject matter of Example 13 and optionally, wherein the AGU configuration code sets a base parameter of the AGU to a memory pointer of the latch instruction, sets a minimum (Min) parameter of the second dimension of the AGU to zero, sets a maximum (Max) parameter of the second dimension of the AGU to an input size corresponding to the latch instruction, and sets a step parameter of the second dimension of the AGU to zero. Example 15 includes the subject matter of Example 12, and optionally, wherein the latch instruction comprises a storage operation. Example 16 includes the subject matter of Example 15, and optionally, wherein the AGU configuration code sets a base parameter of the AGU based on a first parameter value, a second parameter value, and a third parameter value, wherein the first parameter value comprises an input corresponding to the latch instruction, the second parameter value comprises a total number of iterations over one or more loops located within the first loop and enclosing the second loop, the third parameter value comprises a number of dimensions of the AGU corresponding to the one or more loops. Example 17 includes the subject matter of Example 16, and optionally, wherein the AGU configuration code sets the base parameter, denoted as Base, of the AGU as follows: where OrigBase denotes a memory pointer of the latch instruction, EntrySize denotes the input size, [Σ TripCount(L)] denotes the total number of iterations over the one or more loops, and #InnerDims denotes the number of dimensions of the AGU corresponding to the one or more loops. Example 18 includes the subject matter of any of Examples 15 to 17, and optionally, wherein the AGU configuration code sets a step parameter of the second dimension of the AGU based on an input corresponding to the latch instruction; sets a minimum (Min) parameter of the second dimension of the AGU based on the input and a number of iterations in the second loop; and sets a maximum (Max) parameter of the second dimension of the AGU based on the Min parameter of the second dimension of the AGU and the input. Example 19 includes the subject matter of Example 18, and optionally, wherein the AGU configuration code sets the step parameter of the second dimension of the AGU based on an additive inverse of the input size. Example 20 includes the subject matter of Example 18 or 19, and optionally, wherein the AGU configuration code is to set the min parameter of the second dimension of the AGU based on a product of an additive inverse of the input size and a subtraction result of subtracting one from the number of iterations in the second loop. Example 21 includes the subject matter of any of Examples 18 to 20, and optionally, wherein the AGU configuration code is to set the max parameter of the second dimension of the AGU based on a sum of the min parameter of the second dimension of the AGU and the input size. Example 22 includes the subject matter of any of Examples 16 to 21, and optionally, wherein the plurality of loops comprises a third loop nested within the first loop, the second loop nested within the third loop, the latch instruction is outside the third loop, wherein the AGU configuration code is to configure a third dimension of the AGU based on the third loop. Example 23 includes the subject matter of Example 22, and optionally, wherein the AGU configuration code is to set a step parameter of the third dimension of the AGU based on the input size, set a minimum (Min) parameter of the third dimension of the AGU based on the input size and a number of iterations in the third loop, and set a maximum (Max) parameter of the third dimension of the AGU based on the Min parameter of the third dimension of the AGU and the input size. Example 24 includes the subject matter of any of Examples 1 to 23, and optionally, wherein the instructions, when executed, cause the compiler to convert the loop nest into a converted loop comprising the memory access operation, wherein the target code is based on the converted loop. Example 25 includes the subject matter of Example 24, and optionally, wherein the converted loop comprises a perfect flat loop in which all computational operations of the loop nest are implemented in the converted loop. Example 26 includes the subject matter of Example 24 or 25, and optionally, wherein the converted loop comprises a fully aggregated loop comprising only a single basic block loop based on the plurality of loops. Example 27 includes the subject matter of any of Examples 1 to 26, and optionally, wherein the memory access operation comprises a load operation or a store operation. Example 28 includes the subject matter of any of Examples 1 to 27, wherein the source code optionally includes Open Computing Language (OpenCL) code. Example 29 includes the subject matter of any of Examples 1 to 28, and optionally, wherein the computer-executable instructions, when executed, cause the compiler to compile the source code into the target code according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme. Example 30 includes the subject matter of any of Examples 1 to 29, and optionally, wherein the target code is configured for execution by a Very Long Instruction Word (VLIW) Single Instruction / Multiple Data (SIMD) target processor. Example 31 includes the subject matter of any of Examples 1 to 30, and optionally, wherein the target code is configured for execution by a target vector processor. Example 32 includes a compiler configured to perform any of the described operations of any of Examples 1 through 31. Example 33 includes a computing device configured to perform any of the described operations of any of Examples 1 to 31. Example 34 includes a computer system comprising at least one memory for storing instructions and at least one processor for retrieving instructions from the memory and executing the instructions to cause the computer system to perform any of the described operations of any of Examples 1 to 31. Example 35 includes a computer system comprising a compiler for generating target code according to any of the described operations of any of Examples 1 to 31 and a processor for executing the target code. Example 36 includes an apparatus comprising means for performing any of the described operations of any of Examples 1 to 31. Example 37 includes a device comprising: a memory interface; and processing circuitry configured to perform any of the described operations of any of Examples 1 to 31. Example 38 includes a method comprising any of the described operations of any of Examples 1 to 31.

[0547] Functions, operations, components, and / or features described herein with reference to one or more aspects may be combined with or used in combination with one or more other functions, operations, components, and / or features described herein with reference to one or more other aspects, or vice versa.

[0548] While certain features have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes that remain within the true spirit of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 415,308

[0001] Cited non-patent literature

[0000] APPARATUS, SYSTEM, AND METHOD OF VECTOR PROCESSING”, which was published on October 12, 2022

[0001]

Claims

[1] A product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions that, when executed by at least one processor, enable the at least one processor to cause a compiler to: Identifying a loop nest based on source code to be compiled into target code to be executed by a target processor, the loop nest comprising a plurality of loops, the plurality of loops comprising at least a first loop and a second loop nested within the first loop, the first loop comprising at least one instruction of the first loop that is outside the second loop; Generating address generation unit (AGU) configuration code to configure an AGU of the target processor based on the first loop instruction, wherein the AGU configuration code is to configure a first dimension of the AGU based on the first loop and a second dimension of the AGU based on the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure a memory access operation to be performed at the beginning of the second loop or at the end of the second loop, the memory access operation being based on the first loop instruction; and Generating the target code based on compiling the source code, where the target code is based on the AGU configuration code. [2] The product of claim 1, wherein the plurality of loops includes a third loop nested within the first loop, the second loop nested within the third loop, the instruction of the first loop is outside the third loop, wherein the AGU configuration code is to configure a third dimension of the AGU based on the third loop, wherein the AGU configuration code is to configure the third dimension to configure the memory access operation to be performed at the beginning of the second loop or at the end of the second loop. [3] The product of claim 2, wherein the third loop comprises a third loop instruction located outside the second loop, wherein the AGU configuration code is to configure another AGU of the target processor based on the third loop instruction, wherein the AGU configuration code is to configure a first dimension of the another AGU based on the third loop and a second dimension of the another AGU based on the second loop, wherein the AGU configuration code is to configure the second dimension of the another AGU to configure another memory access operation to be performed at the beginning of the second loop or at the end of the second loop, wherein the another memory access operation is based on the third loop instruction. [4] The product of claim 3, wherein the instructions, when executed, cause the compiler to convert the loop nest into a converted loop comprising the memory access operation and the other memory access operation, the target code being based on the converted loop. [5] The product of claim 2, wherein the AGU configuration code is to set a maximum (Max) parameter of the second dimension of the AGU and a Max parameter of the third dimension of the AGU based on an input corresponding to the first loop instruction. [6] The product of claim 1, wherein the AGU configuration code is to set a base parameter of the AGU based on a memory pointer of the first loop instruction and a maximum (Max) parameter of the second dimension of the AGU based on an input corresponding to the first loop instruction. [7] The product of claim 1, wherein the at least one instruction of the first loop comprises a pre-header instruction to be executed before a first iteration of the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure the memory access operation to be executed only at the beginning of the second loop. [8] The product of claim 7, wherein the AGU configuration code sets a minimum (Min) parameter of the second dimension of the AGU to zero. [9] The product of claim 7, wherein the instructions, when executed, cause the compiler to configure the AGU configuration code to set a step parameter of the second dimension of the AGU to zero based on a determination that the pre-header instruction includes a load operation. [10] The product of claim 7, wherein the instructions, when executed, cause the compiler, based on a determination that the pre-header instruction includes a store operation, to configure the AGU configuration code to set a step parameter of the second dimension of the AGU based on an input corresponding to the pre-header instruction. [11] The product of claim 7, wherein the AGU configuration code sets a base parameter of the AGU to a memory pointer of the pre-header instruction. [12] The product of any one of claims 1 to 11, wherein the at least one instruction of the first loop comprises a latch instruction to be executed after a final iteration of the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure the memory access operation to be executed only at the end of the second loop. [13] The product of claim 12, wherein the latch instruction comprises a load operation. [14] The product of claim 13, wherein the AGU configuration code sets a base parameter of the AGU to a memory pointer of the latch instruction, sets a minimum (Min) parameter of the second dimension of the AGU to zero, sets a maximum (Max) parameter of the second dimension of the AGU to an input corresponding to the latch instruction, and sets a step parameter of the second dimension of the AGU to zero. [15] The product of claim 12, wherein the latch instruction comprises a storage operation. [16] The product of claim 15, wherein the AGU configuration code sets a base parameter of the AGU based on a first parameter value, a second parameter value, and a third parameter value, wherein the first parameter value comprises an input corresponding to the latch instruction, the second parameter value comprises a total number of iterations over one or more loops located within the first loop and enclosing the second loop, the third parameter value comprises a number of dimensions of the AGU corresponding to the one or more loops. [17] The product of claim 16, wherein the AGU configuration code sets the base parameter, referred to as Base, of the AGU as follows: Base=OrigBase+EntrySize*([∑TripCount(L)]−#InnerDims), where OrigBase denotes a memory pointer of the latch instruction, EntrySize denotes the input size, [Σ TripCount(L)] denotes the total number of iterations over the one or more loops, and #InnerDims denotes the number of dimensions of the AGU corresponding to the one or more loops. [18] The product of claim 15, wherein the AGU configuration code sets a step parameter of the second dimension of the AGU based on an input corresponding to the latch instruction; sets a minimum (Min) parameter of the second dimension of the AGU based on the input and a number of iterations in the second loop; and sets a maximum (Max) parameter of the second dimension of the AGU based on the Min parameter of the second dimension of the AGU and the input. [19] The product of claim 18, wherein the AGU configuration code is to determine the step parameter of the second dimension of the AGU based on an additive inverse of the input variable. [20] The product of claim 18, wherein the AGU configuration code is to set the min parameter of the second dimension of the AGU based on a product of an additive inverse of the input size and a subtraction result of subtracting one from the number of iterations in the second loop. [21] The product of claim 18, wherein the AGU configuration code is to set the max parameter of the second dimension of the AGU based on a sum of the min parameter of the second dimension of the AGU and the input size. [22] The product of any one of claims 1 to 11, wherein the instructions, when executed, cause the compiler to convert the loop nest into a converted loop comprising the memory access operation, the target code being based on the converted loop. [23] The product of claim 22, wherein the converted loop comprises a perfect flat loop in which all computational operations of the loop nest are implemented in the converted loop. [24] The product of claim 22, wherein the converted loop comprises a fully aggregated loop comprising only a single basic block loop based on the plurality of loops. [25] A product according to any one of claims 1 to 11, wherein the memory access operation comprises a load operation or a store operation. [26] The product of any of claims 1 to 11, wherein the source code comprises Open Computing Language (OpenCL) code. [27] The product of any of claims 1 to 11, wherein the computer-executable instructions, when executed, cause the compiler to compile the source code into the target code according to a Low Level Virtual Machine (LLVM)-based (LLVM-based) compilation scheme. [28] The product of any one of claims 1 to 11, wherein the target code is configured for execution by a Very Long Instruction Word Single Instruction / Multiple Data (VLIW) SIMD target processor. [29] The product of any of claims 1 to 11, wherein the target code is configured for execution by a target vector processor. [30] Computer system comprising: at least one memory for storing instructions; and at least one processor for retrieving the instructions from memory and executing the instructions to cause the computer system to: Identifying a loop nest based on source code to be compiled into target code to be executed by a target processor, the loop nest comprising a plurality of loops, the plurality of loops comprising at least a first loop and a second loop nested within the first loop, the first loop comprising at least one instruction of the first loop that is outside the second loop; Generating address generation unit (AGU) configuration code to configure an AGU of the target processor based on the first loop instruction, wherein the AGU configuration code is to configure a first dimension of the AGU based on the first loop and a second dimension of the AGU based on the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure a memory access operation to be performed at the beginning of the second loop or at the end of the second loop, the memory access operation being based on the first loop instruction; and Generating the target code based on compiling the source code, where the target code is based on the AGU configuration code. [31] A computer system according to claim 30, comprising the target processor for executing the target code. [32] Method comprising: Identifying a loop nest based on source code to be compiled into target code to be executed by a target processor, the loop nest comprising a plurality of loops, the plurality of loops comprising at least a first loop and a second loop nested within the first loop, the first loop comprising at least one first loop instruction located outside the second loop; Generating an address generation unit (AGU) configuration code for configuring an AGU of the target processor based on the instruction of the first loop, wherein the AGU configuration code is to configure a first dimension of the AGU based on the first loop and to configure a second dimension of the AGU based on the second loop, wherein the AGU configuration code is to configure the second dimension of the AGU to configure a memory access operation to be performed at the beginning of the second loop or at the end of the second loop, wherein the memory access operation is based on the instruction of the first loop; and Generating the target code based on the compilation of the source code, where the target code is based on the AGU configuration code. [33] The method of claim 32, wherein the plurality of loops comprises a third loop nested within the first loop, the second loop nested within the third loop, the instruction of the first loop is outside the third loop, wherein the AGU configuration code is to configure a third dimension of the AGU based on the third loop, wherein the AGU configuration code is to configure the third dimension to configure the memory access operation to be performed at the beginning of the second loop or at the end of the second loop.

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