SEMICONDUCTOR COMPONENT

Abstract

A semiconductor device having an IGBT region and a diode region includes a semiconductor substrate of a first conductivity type, a back main electrode, a first semiconductor layer of a second conductivity type extending from the IGBT region into the interior of the diode region and in contact with the back main electrode, a second semiconductor layer of the first conductivity type formed in the diode region and in contact with the back main electrode, and a short-lifetime region formed on the first semiconductor layer in the diode region in the semiconductor substrate. This can prevent recovery destruction and reduce recovery loss while suppressing an increase in the forward voltage of the IGBT.

Description

Technical area

[0001] The present invention relates to a semiconductor device. State of the art

[0002] In reverse conducting IGBTs (RC-IGBTs), in which an IGBT (insulated gate bipolar transistor) and a diode are formed in the same semiconductor device, it is necessary to optimize the device characteristics of each of them in order to achieve high efficiency and high breakdown strength.

[0003] For the RC-IGBT, the following method is known: The lifetime of the semiconductor substrate is controlled by electron beam irradiation or the injection of light ions such as hydrogen and helium into the diode region, and the charge carriers remaining in the drift layer during the recovery process are reduced, thereby reducing the recovery current and the recovery loss.

[0004] For example, Patent Literature 1 discloses a semiconductor device including a semiconductor substrate having one surface and the other surface, wherein, in a surface direction of the one surface of the semiconductor substrate, a region functioning as an IGBT element is an IGBT region, and a region functioning as a diode element is a diode region, and the IGBT region and the diode region are alternately and repeatedly arranged, the semiconductor substrate including at least one low-life region on a boundary side between the IGBT region and the diode region in the IGBT region. Cited literaturePatent literature

[0005] Patent Literature 1: JP 2012-43891A Summary of the inventionTechnical problem

[0006] In the prior art described above, a low-lifetime region is formed in a region on the base layer side (front side) in the drift layer of the diode region, a boundary region with an n-type buffer layer in the drift layer of the IGBT region (back side p-type collector layer: back side), and a region on the front side of a boundary region with the diode region. This suppresses hole injection from the back side p-type collector layer in the IGBT region into the diode region, causing carriers that contribute to the recovery current to recombine and disappear, thus suppressing recovery loss.

[0007] However, since the low-lifetime region is formed on the back side of the IGBT region, the carrier accumulation in the drift layer becomes insufficient when the IGBT is conductive, so the IE (injection enhancement) effect becomes weak and the on-state loss increases, resulting in an increase in the on-state voltage.

[0008] The present invention has been made in view of the foregoing, and an object of the present invention is to provide a semiconductor device capable of preventing recovery destruction and reducing recovery loss while suppressing an increase in the forward voltage of an IGBT. Solution to the problem

[0009] The present application includes a variety of means for solving the problem described above, and an example thereof includes a semiconductor device having an IGBT region and a diode region, the semiconductor device comprising a semiconductor substrate of a first conductivity type, a back main electrode, a first semiconductor layer of a second conductivity type formed from the IGBT region into the diode region and in contact with the back main electrode, a second semiconductor layer of the first conductivity type formed in the diode region and in contact with the back main electrode, and a short lifetime region formed on the first semiconductor layer in the diode region in the semiconductor substrate. Advantageous effects of the invention

[0010] According to the present invention, recovery destruction can be prevented and recovery loss can be reduced while suppressing an increase in the forward voltage of the IGBT. Short description of the drawings [ Fig. 1] Fig. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to Embodiment 1. [ Fig. 2] Fig. 2 is a cross-sectional view illustrating a structure of a semiconductor device according to Embodiment 2. [ Fig. 3] Fig. 3 is a cross-sectional view illustrating a structure of a semiconductor device according to Embodiment 3. [ Fig. 4] Fig. 4 is a cross-sectional view illustrating a structure of a semiconductor device according to Embodiment 4. Description of the embodiments

[0011] Embodiments of the present invention will be described below with reference to the accompanying drawings. <Ausführungsbeispiel 1>

[0012] Embodiment 1 of the present invention will be described with reference to Fig. 1 described.

[0013] Fig. Figure 1 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to the present embodiment. In the following description, the upper part of the drawings is referred to as the front side of the semiconductor device, and the lower part thereof is referred to as the back side.

[0014] In Fig. 1, a reverse conducting IGBT (RC-IGBT: Reverse Conducting-Insulated Gate Bipolar Transistor), shown as an example of a semiconductor device, integrally comprises an IGBT region 100 that fulfills the function of an IGBT and a diode region 200 that fulfills the function of a freewheeling diode, and comprises a semiconductor substrate 1 of a first conductivity type, a body layer 2 of a second conductivity type formed on the front side of the semiconductor substrate 1, an emitter layer 3 of the first conductivity type formed on the front side in the IGBT region 100 of the body layer 2, an emitter electrode 4 formed on the front side of the body layer 2 to connect the body layer 2 and the emitter layer 3, a plurality of trenches 5 formed to extend from the front side of the body layer 2 to the semiconductor substrate 1, a Insulating layer 7, which is designedthat it covers the interior of the plurality of trenches 5, a gate electrode 6 formed inside each trench formed in the IGBT region 100 of the plurality of trenches 5 via the insulating layer 7, an emitter electrode 8 formed inside each trench formed in the diode region 200 under the plurality of trenches 5 via the insulating layer 7, a buffer layer 10 of the first conductivity type formed on the back side of the semiconductor substrate 1, a collector layer 11 (first semiconductor layer) of a second conductivity type formed on the back side of the buffer layer 10 so as to extend from the IGBT region 100 to a part of the diode region 200, a cathode layer 12 (second semiconductor layer) of the first conductivity type formed in a region where the collector layer 11 is not on the back side of the buffer layer 10 of the diode region 200 is formed,a collector electrode 13 (back main electrode) formed on the back side of the collector layer 11 and the cathode layer 12 to connect the collector layer 11 and the cathode layer 12; and a short-lifetime region 20a formed within the semiconductor substrate 1 of the diode region 200 and along the buffer layer 10 in a region where the collector layer 11 extends on the back side from the IGBT region 100 side. Here, the short-lifetime region 20a is a region formed by electron beam irradiation or implantation of light ions such as hydrogen and helium.

[0015] The operation and advantageous effect of the semiconductor device configured as described above in the present embodiment will be described.

[0016] In the semiconductor device of the present embodiment, carriers for recombination with carriers accumulated in the diode region 200 are mainly injected from the collector layer 11 under the diode region 200 at the time of diode recovery. At this time, a portion of the carriers injected from the collector layer 11 also flows into the IGBT region 100. Since carriers injected from the collector layer 11 are suppressed by the short-lifetime region 20a, the carriers can be prevented from flowing into the IGBT region 100, and latch-up of the IGBT can be prevented. In addition, since the amount of carriers injected into the diode region 200 is also reduced, the recovery loss can also be reduced. Further, since it is configured such that the low-life region 20a is not formed in the IGBT region 100, an increase in the forward voltage of the IGBT can be suppressed.That is, recovery destruction can be prevented and recovery loss can be reduced while suppressing an increase in the forward voltage of the IGBT. <Ausführungsbeispiel 2>

[0017] Embodiment 2 of the present invention will be described with reference to Fig. 2 described.

[0018] The present embodiment shows the case where a low-life region is formed over the entire back side of the interior of the semiconductor substrate 1 in the diode region 200.

[0019] In the present embodiment, only the differences from Embodiment 1 will be described, and in the drawings of the present embodiment, elements similar to those in Embodiment 1 are given the same reference numerals and symbols, and their description will be omitted if necessary.

[0020] Fig. 2 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to the present embodiment.

[0021] In Fig. 2, the semiconductor component in the present embodiment comprises, as in embodiment 1, a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating layer 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12 and a collector electrode 13.

[0022] A low lifetime region 20b is formed along the buffer layer 10 on the backside within the semiconductor substrate 1 in the diode region 200.

[0023] Other configurations are the same as those of Example 1.

[0024] Also in the present embodiment described up to this point, the same effects as those of Embodiment 1 can be achieved.

[0025] Furthermore, charge carriers on the back of the diode region 200 are eliminated more quickly, and the tail current at the time of recovery is reduced, so that the recovery loss can be reduced. <Ausführungsbeispiel 3>

[0026] Embodiment 3 of the present invention will be described with reference to Fig. 3 described.

[0027] The present embodiment shows the case where a charge injection layer is formed in the diode region 200 and a short lifetime region is formed in a region on the back side of the semiconductor substrate 1 where the charge injection layer is not formed.

[0028] In the present embodiment, only the differences from Embodiment 2 will be described, and in the drawings of the present embodiment, elements similar to those in Embodiment 2 are given the same reference numerals and symbols, and their description will be omitted if necessary.

[0029] Fig. 3 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to the present embodiment.

[0030] In Fig. 3, the semiconductor component according to the present embodiment comprises, as in Embodiment 2, a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating layer 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12, and a collector electrode 13.

[0031] Furthermore, a carrier injection layer 14 (third semiconductor layer) of a second conductivity type, which is adjacent to the cathode layer 12 and connected to the collector electrode 13, is formed at a position separated from the collector layer 11 of the cathode layer 12 in the diode region 200 (in other words, at the position farthest from the IGBT region 100).

[0032] A low lifetime region 20c is formed along the buffer layer 10 on the back side inside the semiconductor substrate 1 of the diode region 200, in a region where the collector layer 11 extends from the IGBT region 100 side and a region where the cathode layer 12 is formed (in other words, a region where the carrier injection layer 14 is not formed).

[0033] Other configurations are the same as those of Example 2.

[0034] Also in the present embodiment described up to this point, the same effects as those of Embodiment 2 can be achieved.

[0035] Furthermore, since carriers are injected from the carrier injection layer 14 at the time of recovery, the carrier count on the back surface is increased, and depletion of carriers is suppressed, so that soft recovery can be realized. At this time, since the carrier injection layer 14 is formed at a position away from the IGBT region 100, no carrier injection from the carrier injection layer 14 into the IGBT region 100 occurs at the time of recovery, and no destruction occurs due to carrier influence from the carrier injection layer 14 into the IGBT region 100. <Ausführungsbeispiel 4>

[0036] Embodiment 4 of the present invention will be described with reference to Fig. 4 described.

[0037] The present embodiment shows the case where a short lifetime region is formed on a part of the back side and the front side of the interior of the semiconductor substrate 1 in the diode region 200.

[0038] In the present embodiment, only the differences from Embodiment 1 will be described, and in the drawings of the present embodiment, elements similar to those in Embodiment 1 are given the same reference numerals and symbols, and their description will be omitted if necessary.

[0039] Fig. 4 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to the present embodiment.

[0040] In Fig.4, the semiconductor component in the present embodiment comprises, as in embodiment 1, a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating layer 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12 and a collector electrode 13.

[0041] Further, a low lifetime region 20a is formed along the buffer layer 10 in a region where the collector layer 11 extends on the back side from the IGBT region 100 side within the semiconductor substrate 1 in the diode region 200.

[0042] Furthermore, a low lifetime region 21 is formed along the body layer 2 on the front side of the diode region 200 within the semiconductor substrate 1.

[0043] Other configurations are the same as those of Example 1.

[0044] Also in the present embodiment described up to this point, the same effects as those of Embodiment 1 can be achieved.

[0045] Furthermore, charge carriers on the front side of the diode region 200 can be reduced, and switching loss can be reduced. Since the short-life layer is not formed in the IGBT region 100 at this time, the present embodiment can be applied without considering the influence on the characteristics of the IGBT. <Zusätzliche Anmerkung>

[0046] Incidentally, the present invention is not limited to the above-described embodiments, and various modified examples and combinations thereof within the scope that does not deviate from the gist of the invention are included therein. Also, the present invention is not limited to those provided with all the configurations described in the above embodiments, but also includes those in which part of the configuration is omitted. List of reference symbols 1 semiconductor substrate 2 body layers 3 Emitter layer 4 Emitter electrode 5 ditch 6 Gate electrode 7 Insulating layer 8 Emitter electrode 10 Buffer layer 11 Collector layer 12 Cathode layer 13 Collector electrode 14 Charge carrier injection layer 20a, 20b, 20c, 21 Low lifetime area 100 IGBT range 200 diode range QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2012-43891A

[0005]

Claims

[1] Semiconductor device with an IGBT region and a diode region, comprising: a semiconductor substrate of a first conductivity type; a rear main electrode; a first semiconductor layer of a second conductivity type extending from the IGBT region to the diode region and in contact with the rear main electrode, a second semiconductor layer of the first conductivity type formed in the diode region and in contact with the rear main electrode, and a short lifetime region formed on the first semiconductor layer in the diode region in the semiconductor substrate. [2] The semiconductor device according to claim 1, wherein the short lifetime region is formed on the first semiconductor layer and the second semiconductor layer in the diode region in the semiconductor substrate. [3] A semiconductor device according to claim 2, further comprising: a third semiconductor layer of the second conductivity type formed in the diode region so as not to be in contact with the first semiconductor layer and so as to be in contact with the second semiconductor layer and the rear main electrode, wherein the short lifetime region is formed on the first semiconductor layer and the second semiconductor layer in the diode region in the semiconductor substrate. [4] The semiconductor device according to claim 1, wherein the short lifetime region is formed on the first semiconductor layer and the second semiconductor layer in the diode region in the semiconductor substrate and additionally on a front surface in the diode region in the semiconductor substrate.

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