Photonic integrated circuit packages containing substrates with glass cores

Abstract

Microelectronic assemblies, associated devices, and methods are disclosed herein. In some embodiments, a photonic assembly may include: an interposer having a surface, wherein a material of the interposer includes glass, and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical path through the interposer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to packaging photonic integrated circuits (PICs) including substrates with glass cores. More particularly, it relates to techniques, methods, and devices directed to PIC architectures including substrates with glass cores and an optical path through the glass cores. BACKGROUND

[0002] Electronic circuits, when fabricated on a wafer of semiconductor material such as silicon, are commonly referred to as integrated circuits (ICs). The wafer containing such ICs is typically cut into numerous individual dies. The dies containing a PIC can be encapsulated in an IC package, which contains one or more dies along with other electronic components such as resistors, capacitors, and inductors. The photonic IC package can be integrated onto an electronic system, such as a consumer electronics system. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Embodiments will be readily understood from the following detailed description when taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals indicate like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings. Fig. 1A is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. Fig. 1B is a schematic illustration of an exemplary detail of an active surface of a photonic integrated circuit according to some embodiments of the present disclosure. Fig. 1C is a schematic cross-sectional view of an exemplary detail of a conductive interconnect bond interface of the exemplary microelectronic assembly of Fig. 1A according to some embodiments of the present disclosure. Fig. 1D is a schematic top view of the exemplary microelectronic assembly of Fig. 1A. Fig. 2A is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. Fig. 2B is a schematic illustration of an exemplary detail of an optical bonding interface of a photonic integrated circuit according to some embodiments of the present disclosure. Fig. 2C is a schematic top view of the exemplary microelectronic assembly of Fig. 2A. Fig. 3A-3E are schematic cross-sectional views of various stages of an exemplary process for manufacturing the microelectronic assembly from Fig. 2A according to some embodiments of the present disclosure. Fig. 4 is a schematic flow diagram listing example operations that may be associated with fabricating a microelectronic assembly, according to some embodiments of the present disclosure. Fig. 5 is a cross-sectional view of a device package including one or more microelectronic assemblies, according to any of the embodiments disclosed herein. Fig. 6 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies, according to any of the embodiments disclosed herein. Fig. 7 is a block diagram of an exemplary computing device including one or more microelectronic assemblies, in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0004] For purposes of illustrating the PIC packages described herein, it is important to understand phenomena that may arise during assembly and packaging of PICs. The following basic information may be considered a basis from which the present disclosure may be adequately explained. Such information is provided for explanatory purposes only and should accordingly not be construed in any way to limit the broad scope of the present disclosure and its applications.

[0005] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic circuitry that can be included in processors and other IC devices. As a result, many processors now have multiple cores monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar because they take the form of a flat surface and are typically built on a single silicon wafer made from a monocrystalline silicon boule. The typical manufacturing process for such monolithic ICs is referred to as a planar process, which allows photolithography, etching, thermal diffusion, oxidation, and other such processes to take place on the surface of the wafer, allowing active circuit elements (e.g., transistors and diodes) to be formed on the planar surface of the silicon wafer.

[0006] Current technologies allow hundreds and thousands of such active circuit elements to be formed on a single die, allowing for numerous logic circuits to be implemented on it. With such monolithic dies, the manufacturing process must be optimized equally for all circuits, leading to trade-offs between different circuits. Furthermore, due to the limitation of circuits being placed on a planar surface, some circuits are farther apart from others, resulting in reduced performance, such as longer delays. Manufacturing yield can also be severely impacted because the entire die may have to be discarded if just one circuit fails.

[0007] One solution to address such negative effects of monolithic dies is to disaggregate the circuits into smaller dies (e.g., chiplets, tiles) that are electrically coupled by interconnect bridges. The smaller dies are part of an assembly of interconnected dies that together form a complete IC with respect to an application and / or functionality, such as a memory chip, a microprocessor, a microcontroller, a commodity IC (e.g., a chip used for repetitive processing routines, simple tasks, an application-specific IC, etc.), and a system-on-a-chip (SoC). In other words, the individual dies are connected to create the functionalities of a monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a specific functionality.For example, a processor core containing logic circuitry might target performance and thus require a highly speed-optimized layout. This has different manufacturing requirements compared to a Universal Serial Bus (USB) controller, which is built to meet certain USB standards rather than for processing speed. Accordingly, by separating different parts of the overall design into different dies, each optimized for design and manufacturing, the overall yield and cost of the combined die solution can be improved.

[0008] Connectivity between these dies can be achieved in many ways. For example, in 2.5D packaging solutions, a silicon interposer and through-silicon vias (TSVs) connect dies at a silicon interconnect speed with a minimal footprint. In another example, a silicon bridge embedded under the edges of two interconnected dies enables electrical coupling between them. In a three-dimensional (3D) architecture, the dies are stacked on top of each other, creating a smaller overall footprint. Typically, electrical connectivity and mechanical coupling in such a 3D architecture are achieved using TSVs and high-pitch solder-based bumps (e.g., C2 interconnects).The bridge and the stacked 3D architecture can also be combined to allow top-encapsulated chips to communicate with other chips horizontally using the bridge and vertically using through-mold vias (TMVs), which are typically larger than TSVs. However, these current interconnect technologies use solder or its equivalent for connectivity, resulting in low vertical and horizontal interconnect density.

[0009] One way to mitigate low vertical interconnect density is to use an interposer, which improves vertical interconnect density but suffers from low lateral interconnect density if the interposer's base wafer is passive. In general, an "interposer" is commonly used to refer to a base piece of silicon that interconnects two dies. Incorporating active circuit elements into the interposer can improve lateral speeds, but requires more expensive manufacturing processes, especially when a large base die is used to interconnect smaller dies. Furthermore, not all interfaces require fine-pitch interconnects, which can result in additional manufacturing and processing overhead without the benefits of the fine pitch.

[0010] Integrating optical communications into IC packages further increases complexity. Modern optical communications and other systems frequently employ PICs. Smaller, faster, and lower-cost optical elements can enable universal, low-cost, high-volume optical communications needed for fast and efficient communications technologies driven by high-volume internet traffic. In optical communications, information is transmitted over an optical carrier whose frequency is typically in the visible or near-infrared range of the electromagnetic spectrum. A carrier with such a high frequency is sometimes referred to as an optical signal, optical carrier, lightwave signal, or simply light. A typical optical communications network includes multiple optical fibers, each of which may contain several channels.A channel is a specified frequency band of an electromagnetic signal and is sometimes referred to as a wavelength. Technological advances now make it possible to implement parts of optical communication systems at the IC (or chip or die) level in PICs. Encapsulating such PICs presents many challenges.

[0011] In a general sense, a PIC integrates photonic functions for information signals imposed on electromagnetic waves, e.g., electromagnetic waves of optical wavelengths. PICs find application in fiber-optic communications, medical, security, sensing, and photonic computing systems. The PIC can implement one or more optical and electro-optical devices, such as lasers, photodetectors, waveguides, and modulators, on a single semiconductor chip. Additionally, the PIC can also include electrical circuitry for processing electrical signals corresponding to these optical signals. Such integrated PICs feature both photonic processing and electrical signal processing in the same process node, which can limit optimization.In other embodiments, the PIC may be located in a separate process node that optimizes PIC performance, and electrical signal processing may be located in a different process node that optimizes high-speed electrical performance.

[0012] Encapsulating the PIC is not trivial. Challenges include a need for parallel, close-pitch interconnects that enable high-density, high-bandwidth electrical communication between the PIC and other electrical devices, with concurrent optical access to the PIC for the optical signals. Indeed, transferring optical signals into and out of PICs is a driver of manufacturing cost and complexity. Furthermore, coupling a fiber-optic cable, sometimes called an "optical fiber" or simply a "fiber," to a PIC in such a way that electromagnetic signals, such as optical signals, can pass between the two is challenging.One way to couple a PIC to a fiber is to implement edge coupling by using an intermediate optical coupling structure (OCS) (sometimes called a "fiber connector," "fiber coupler," "fiber assembly unit" (FAU), or "fiber array block") that has one end optically coupled to a fiber and an opposite end positioned near and optically coupled to a PIC so that electromagnetic signals can be exchanged between the PIC and the fiber via the OCS.

[0013] However, because the signals require a transparent medium for propagation, the PIC must typically be exposed within the package to allow the fiber to be coupled to the PIC with sufficient stability, even in such edge-coupled assemblies. For example, in some packaging architectures, the PIC has an overhang for coupling to the fiber located at the edge of the package. In another example, the PIC is located within a cavity so that it is exposed, and the fiber located at the package edge is coupled to the exposed area. These two architectures cannot support small-footprint PICs because a significant area of ​​the PIC is consumed by functional structures and circuitry when coupling to the fiber. They are also limited in the density of their electrical interconnections with other ICs in the package.

[0014] Another approach is to embed a thin glass core into a package substrate or to couple a glass core to a package substrate or circuit board (e.g., integrating a glass interposer as a patch). As used here, the core and interposer can be used interchangeably. A glass core compared to a conventional epoxy core offers several advantages, including, among others, a higher density of plated through holes (PTH), lower signal losses, and lower total thickness variation (TTV). Additional functionality can be achieved by inserting a waveguide into a glass core for optical transmission through the core. A PIC requires both electrical and optical connections to the package substrate, which typically have different heights (e.g.,different z-height offsets from a top surface of the glass core, with the electrical connections having a larger z-height offset compared to the optical connections, which have a shorter z-height offset). One approach to addressing the height variation between electrical and optical connections is to form a dielectric material with conductive paths therein on an interior portion of a top surface of the glass core and leave an exterior portion (e.g., a perimeter) of the glass core exposed, so that a PIC can have electrical connections to the conductive paths through the dielectric material at a larger z-height offset and optical connections to the exposed top surface of the glass core, including the waveguide, at a lower z-height offset. A dielectric material including conductive paths may also be referred to herein as a redistribution layer (RDL).However, adding an RDL increases the overall z-height of an IC package.

[0015] In one aspect of the present disclosure, an example photonic IC packaging architecture includes coupling PICs using high-density interconnects such that z-height offset between electrical and optical PIC interconnects is minimal. As used herein, “high-density interconnects” includes interconnects with a pitch of less than 10 micrometers. As used herein, a pitch is measured from center to center (e.g., from a center of one interconnect to a center of an adjacent interconnect). In some embodiments, interconnects, such as interconnects 106, described below with reference to Fig. 1A have a pitch between 2 micrometers and 70 micrometers.

[0016] Accordingly, microelectronic assemblies, associated devices, and methods are disclosed herein. In some embodiments, a photonic assembly may include: an interposer having a surface, wherein a material of the interposer includes glass, and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by interconnects having a pitch between 2 micrometers and 70 micrometers between adjacent interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical path through the interposer.

[0017] Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may include some innovative aspects, but no single one is solely responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

[0018] In the following detailed description, various aspects of the illustrative implementations are described using terms that would be employed by one skilled in the art to convey the substance of one's work to another skilled in the art.

[0019] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components configured to cooperate with each other to provide a desired function. The terms also refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical electrical and / or electronic hardware component.

[0020] The term “integrated circuit” (IC) means a circuit that is integrated into a monolithic semiconductor or analogous material.

[0021] In some embodiments, the IC dies disclosed herein may comprise substantially monocrystalline semiconductors, such as silicon or germanium, as a base material (e.g., substrate, body) on which integrated circuits are fabricated using conventional semiconductor processing techniques. The semiconductor base material may include, for example, n-type or p-type materials. This may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure.In some embodiments, the base material of one or more of the IC dies may comprise alternative materials that may or may not be combined with silicon and include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, Group III-V, Group II-VI, or Group IV materials. In yet further embodiments, the base material may comprise compound semiconductors, for example, having a first sub-lattice of at least one element from Group III of the Periodic Table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the Periodic Table (e.g., P, As, Sb).In still further embodiments, the base material may comprise an intrinsic IV- or III-V-type semiconductor material or alloy that is not intentionally doped with any electrically active impurity; in alternative embodiments, nominal impurity dopant levels may be present. In still further embodiments, these may comprise a non-crystalline material, such as polymers; for example, the base material may comprise silicon dioxide-filled epoxy. In other embodiments, the base material may comprise a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, n- or p-type amorphous silicon or n- or p-type polysilicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be possibly doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of the material for this are described here, any material or structure that can be used as a foundation (e.g.a base material) on which IC circuits and structures as described herein can be formed, within the spirit and scope of the present disclosure.

[0022] Unless otherwise described, IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) some functionality. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement memory devices and / or memory arrays and / or control logic configured to control the memory devices and arrays, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., ICs that implement I / O functions and / or arithmetic operations and / or pipelining of data, etc.).

[0023] As another example, the terms "package" and "IC package" are synonymous, as are the terms "die," "IC," and "IC die." Note that the terms "chip," "chiplet," "die," "IC," and "IC die" are used interchangeably here. The terms "bridge die," "interconnect bridge," and "interconnect die" are used interchangeably here.

[0024] The term "insulating" means "electrically insulating," and the term "conductive" means "electrically conductive," unless otherwise specified. When referring to optical signals and / or devices, components, and elements that operate on or utilize optical signals, the term "conductive" can also mean "optically conductive."

[0025] The terms “oxide,” “carbide,” “nitride,” etc., refer to compounds containing oxygen, carbon, nitrogen, etc.

[0026] The term “high-k dielectric” refers to a material with a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material with a lower dielectric constant than silicon oxide.

[0027] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially electrically non-conductive. They may include, by way of example and not limitation, organic polymers and plastics and inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or a combination thereof. They may include dielectric materials, materials with high polarizability, and / or piezoelectric materials. A dielectric material may include any suitable dielectric material commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g.,in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); a polyimide material; or a low-k or ultra-low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and potting or pot-like materials used in encapsulation applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0028] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those that are monolithically integrated within an IC, mounted on an IC, or connected to an IC. The ICs described herein may be either analog or digital and, depending on the components associated with the IC, may be used in a variety of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc. The ICs described herein may be implemented in a single IC die or as part of a chipset to perform one or more associated functions in a computer.

[0029] In various embodiments of the present disclosure, transistors described herein may be field-effect transistors (FETs), e.g., MOSFETs. In many embodiments, a FET is a four-terminal device. For a silicon-on-insulator, nanoribbon, or gate-all-around (GAA) FET, the FET is a three-terminal device that includes a source, drain, and gate terminal and uses an electric field to control a current flowing through the device.A FET typically includes a channel material, a source region and a drain region provided in and / or above the channel material, and a gate stack including a gate electrode material, alternatively referred to as a "work function" material, provided over a portion of the channel material (the "channel portion") between the source and drain regions, and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0030] In general, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, enabling communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, enabling communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included within the term "interconnect." The nature of the interconnect being described is to be understood herein with reference to the signal medium associated with it.Thus, the term "interconnect," when used with reference to an electronic device, such as an IC that operates using electrical signals, describes any element formed from an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC and / or between various such elements. In such cases, the term "interconnect" may refer to both conductive traces (sometimes referred to as "lines," "wires," "metal lines," or "trenches") and conductive vias (sometimes referred to as "vias" or "metal vias"). Sometimes, electrically conductive traces and vias may be referred to as "conducting traces" and "conductive vias," respectively, to emphasize the fact that these elements include electrically conductive materials, such as metals.Similarly, when used with reference to a device that also operates on optical signals, such as a PIC, "interconnect" can also describe any element formed from a material that is optically conductive to provide optical connectivity to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides, including an optical fiber, optical splitters, optical combiners, optical couplers, optical couplers, and optical vias.

[0031] As used herein, the term "optical element" includes arrays of shapes fabricated in integrated circuits to receive, transform, and / or transmit optical signals as described herein. It may include optical guides such as waveguides, grating couplers, electromagnetic radiation sources such as lasers, and electro-optical devices such as photodetectors.

[0032] The term "waveguide" refers to any structure that acts to confine and guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glasses such as silicon oxide (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and so on. Waveguides can be formed using various techniques, including, but not limited to, forming waveguides in situ. For example, in some embodiments, waveguides can be formed in situ in glass using low-temperature glass-to-glass bonding or by direct laser writing (e.g., a laser-written waveguide). In situ formed waveguides can exhibit lower loss characteristics.

[0033] The term "conducting trace" can be used to describe an electrically conductive element insulated by an insulating material. Within IC dies, such an insulating material comprises an interlayer low-k dielectric provided within the IC die. Within package substrates and printed circuit boards (PCBs), such an insulating material comprises organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy resin. Such conductive traces are typically arranged in several levels or several layers of metallization stacks.

[0034] The term "conductive via" can be used to describe an electrically conductive element that connects two or more conductive lines of different levels of a metallization stack. For this purpose, a via can be provided substantially perpendicular to the plane of an IC die / chip or support structure over which an IC structure is provided, and can connect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0035] The term "packaging substrate" may be used to describe any substrate material that enables the co-encapsulation of any collection of semiconductor die and / or other electrical components, such as passive electrical components. As used herein, a packaging substrate may be formed from any material, including, but not limited to, insulating materials such as resin-impregnated glass fibers (e.g., PCB or Printed Wiring Boards (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a packaging substrate may refer to a substrate that includes build-up layers (e.g., ABF layers).

[0036] The term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC die / chip and / or a package substrate.

[0037] As used here, the term “pitch” of interconnects refers to a center-to-center distance between adjacent interconnects.

[0038] The terms "substantially," "closely," "approximately," "near," and "about" generally refer to being within + / -20% of a target value (e.g., within + / -5% or 10% of a target value) based on the context of a particular value as described herein or known in the art.

[0039] Terms indicating an orientation of different elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within + / - 5% - 20% of a target value based on the context of a particular value as described herein or known in the art.

[0040] The term "connected" means a direct connection (which includes a mechanical, electrical and / or thermal connection) between the things that are connected, without any intervening devices, while the term "coupled" means either a direct connection between the things that are connected or an indirect connection through one or more passive or active intervening devices.

[0041] The description uses the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments.

[0042] Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with reference to embodiments of the present disclosure, are synonymous.

[0043] The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side." Such descriptions are used to facilitate discussion and are not intended to limit the application of disclosed embodiments.

[0044] As used herein, the terms "over," "under," "between," and "on" refer to a relative position of a material layer or component with respect to other layers or components. For example, a layer disposed over or under another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed "between" two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to a layer that is in direct contact with that second layer.Similarly, unless otherwise specified, a feature located between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0045] The term “arranging,” as used herein, refers to a position, location, placement, and / or arrangement rather than to any particular method of formation.

[0046] The term “between”, when used with reference to measuring ranges, includes the ends of the measuring ranges.

[0047] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the phrase "A / B / C" means (A), (B), and / or (C).

[0048] Although specific elements may be referred to in the singular herein, such elements may include multiple subelements. For example, "an electrically conductive material" may include one or more electrically conductive materials. In another example, "a dielectric material" may include one or more dielectric materials.

[0049] Unless otherwise specified, the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object merely indicates that reference is made to different instances of like objects, and is not intended to imply that the objects so described must be in a given sequence, whether temporally, spatially, in order of precedence, or in any other way.

[0050] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments that may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0051] The accompanying drawings are not necessarily to scale.

[0052] In the drawings, like reference numerals refer to the same or analogous elements / materials shown, so that, unless otherwise indicated, explanations of an element / material with a given reference numeral given in the context of one of the drawings apply to other drawings in which an element / material with the same reference numeral may be illustrated. Furthermore, the singular and plural forms of the reference numeral designations may be used to refer to a single or multiple individual elements of the same or analogous kind, species, or class of elements.

[0053] Furthermore, in the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it should be understood that such schematic illustrations may not reflect actual process limitations, which may cause the features to appear less than "ideal" when any of the structures described herein are examined using, for example, images from suitable characterization tools, such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or a non-contact profilometer. Such images of actual structures may also reveal possible processing and / or surface defects, such as:Surface roughness, curvature or profile deviation, pits or scratches, imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, occasional screw, step, or combination dislocations within the crystalline region(s), and / or occasional dislocation defects of individual atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing and / or packaging.

[0054] It should be noted that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at respective interfaces) for ease of illustration only; in reality, some or all of them may be misaligned. In addition, there may be other components, such as bond pads, contact pads, metallization, etc., present in the assembly that are not shown in the figures to avoid overcrowding. Furthermore, the figures are intended to show relative arrangements of the components within their assemblies, and such assemblies may generally include other components that are not illustrated (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation).For example, in some further embodiments, the assembly, as shown in the figures, may include multiple dies along with other electrical components. Furthermore, although some components of the assemblies are illustrated in the figures as planar rectangles or as formed from rectangular solids, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes necessary due to, the manufacturing process used to fabricate various components.

[0055] In the drawings, a specific number and arrangement of structures and components are presented for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0056] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable shape or form according to material properties, manufacturing processes and operating conditions.

[0057] If there is a collection of drawings marked with different letters (e.g. Fig. 1A-1D), this collection can be presented here without the letters for the sake of simplicity (e.g. as “ Fig. 1"). If a collection of reference numbers designated by different numbers or letters (e.g., 104-1, 104-2, etc.) exists, such a collection may equally be referred to herein without the numbers or letters (e.g., as "104").

[0058] Various operations may be described as multiple discrete acts or operations performed in sequence in a manner that is extremely helpful for understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. Described operations may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted from additional embodiments.

[0059] Fig. 1A is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes a PIC 104, an interposer 103 with glass vias (TGVs) 110, and a fiber connector 187. The PIC 104 is electrically coupled to the TGVs 110 by interconnects 106 having a pitch between 2 micrometers and 70 micrometers between adjacent interconnects 106 and is optically coupled to the fiber connector 187 by an optical path 160 through the interposer 103. An example of the interconnect 106, in some embodiments, is a hybrid bond that includes metal-to-metal and dielectric-to-dielectric bonds. As used herein, the terms “microelectronic assembly,” “photonic package,” “photonic microelectronic assembly,” and similar variations may be used interchangeably.As used herein, the term "optical path" refers to a path or trajectory through which light propagates from one location to another through an optical medium. In some embodiments, an optical path 160 may include one or more waveguides or other structures that guide the light path.

[0060] The interposer 103 may include a first surface 170-1 (e.g., a bottom surface), an opposing second surface 170-2 (e.g., a top surface), and a lateral surface 170-3 substantially perpendicular to the first and second surfaces 170-1, 170-2. In some embodiments, a material of the interposer 103 may include glass. For example, an interposer 103 may include any suitable type of glass known in the art, including, but not limited to, photographic glass, borosilicate glass, soda-lime glass, quartz, or other glass material. In some embodiments, the glass interposer 103 may include a photoimageable glass or other borosilicate-based glasses with oxide additions. In some embodiments, a total thickness (e.g., a z-height) of the interposer 103 may be between 20 micrometers and 2 micrometers.The TGVs 110 in the interposer 103 may be formed from any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The TGVs 110 may be formed using any suitable process, including, for example, a direct laser drilling or laser-induced deep etching process. In some embodiments, the TGVs 110 disclosed herein may have a pitch between about 50 micrometers and 500 micrometers. As used herein, a pitch is measured from center to center (e.g., from a center of one TGV to a center of an adjacent TGV). The TGVs 110 may have any suitable size and shape. In some embodiments, the TGVs 110 may have a circular, rectangular, or other shaped cross-section.

[0061] The PIC 104 may include an active surface 105. A first portion of the active surface 105 of the PIC 104 may be optically coupled to the interposer 103, and a second portion of the active surface 105 may be electrically coupled to the TGVs 110 in the interposer 103 through interconnects 106 (e.g., hybrid bonding). The first portion of the PIC 104 may be physically coupled to the second surface 170-2 of the interposer 103 using any suitable attachment means, for example, fusion bonding (such as in Fig. 1A) or by optical adhesive (e.g. optical adhesive 117 as shown in Fig. 2A). Fusion bonding (i.e., dielectric-to-dielectric bonding without metal-to-metal bonding at the interface) may involve a layer of bonding material (e.g., dielectric material 108, as shown in Fig. 1C) on a bonding surface. In some embodiments, a bonding material may include inorganic dielectric materials, for example, silicon and one or more of oxygen, nitrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), aluminum and oxygen (e.g., in the form of aluminum oxide), and / or other forms of inorganic dielectric material typically used as an interlayer dielectric (ILD) in semiconductor devices. In some embodiments, the bonding material may cover optical elements on the active surface 105 and may act as a protective layer that maintains the integrity of the optical elements during manufacturing processes to which the PIC 104 may be subjected, for example, attaching (e.g., by fusion bonding or optical adhesive), solder reflow, grinding, polishing, underfilling, and potting.For example, the bonding material layer can ensure that the optical transmission properties of the optical elements are not compromised by contamination with potting or underfill material during manufacturing processes, or that the optical functionality is not compromised by cracking, breaking, or other destructive events during manufacturing processes. The bonding material layer can also serve to prevent leakage of optical signals from the optical elements, including the waveguide 164, during operation of the PIC 104. For example, the bonding material can further serve to provide an oxide-to-oxide bond between the optical elements of the PIC 104 and the interposer 103 when a silicon oxide material is used.In another example, the bonding material may serve to provide a nitride-to-nitride bond between the optical elements of the PIC 104 and the interposer 103 when a silicon nitride material is used. The silicon oxide layers in an oxide-to-oxide bond or the silicon nitride layers in a nitride-nitride bond may be initially bonded by van der Waals forces and subsequently by high-temperature fusion bonding. The oxide-to-oxide bond and the nitride-to-nitride bond may reduce optical signal loss. Optical adhesive may include any suitable material that allows optical signals to pass through while serving to adhere the PIC 104 and the interposer 103. The materials may include, for example, and not as limitations, ultraviolet-curing optical adhesives, epoxies, silicone, modified silane, and acrylates.The PIC 104 may be optically aligned with the interposer 103 at the bond interface to minimize optical loss across the optical path 160. In some embodiments, the bond surface of the interposer 103 (e.g., top surface 170-2) may be ground and polished to a suitable surface quality, enabling optical connection without significant loss of optical signal integrity across bond interfaces. In some embodiments, an index-matching epoxy may be used to further reduce optical loss. In some embodiments, optical alignment may not be required because the optical path 160 can be formed subsequent to the attachment (e.g., in-situ laser-scribed waveguide).

[0062] A first portion of the active surface 105 of the PIC 104 may include optical elements. Exemplary optical elements over the first portion of the active surface 105 are shown in Fig. 1B shown in more detail. Fig. 1B is a schematic representation of an area of ​​the active surface 105 (e.g., looking toward the active surface 105 of the PIC 104). Example optical elements include an electromagnetic radiation source 166, an electro-optic device 168, and a waveguide 164. In many embodiments, the optical elements may be fabricated on the active surface 105 using any known method in the art, including photolithographic methods and semiconductor deposition methods. In some embodiments, the optical elements may extend across substantially an entire area of ​​the active surface 105 (not shown). In some embodiments, the optical elements may be confined within a portion of the active surface 105, as shown.In some embodiments, a PIC 104 may be configured to transmit and / or receive an optical signal at an active surface 105, as shown. For example, the PIC 104 may include optical elements, such as a grating coupler, on an active surface 105 that enable the PIC 104 to transmit and / or receive light through the active surface 105 (e.g., vertical transmission and reception of light). In some embodiments, a PIC 104 may be configured to transmit and / or receive an optical signal at a lateral surface (not shown).In such examples, the PIC 104 may include optical elements, such as an edge coupler, a V-notch array, or an angled reflector with a grating coupler, on an active surface 105 that enable the PIC 104 to transmit and / or receive light through a lateral surface that is substantially perpendicular to the active surface 105 (e.g., lateral transmission and reception of light).

[0063] The electromagnetic radiation source 166 may enable the generation of optical signals and may include lasers, for example, if the PIC 104 supports wavelengths between approximately 0.8 and 1.7 micrometers. The electro-optic device 168 may enable the reception, transformation, and transmission of optical signals. In some embodiments, the electro-optic device 168 may be any device or component configured to encode information into / onto the electromagnetic signals, such as a modulator, polarizer, phase shifter, and photodetector.

[0064] The waveguide in the PIC 164 can guide optical signals and also perform optical coupling, switching, splitting, multiplexing, and demultiplexing of optical signals. In some embodiments, the waveguide 164 can include any component configured to inject or launch the electromagnetic signal into the propagation medium, such as an optical fiber. In some embodiments, the waveguide 164 can be further configured as an optical multiplexer and / or demultiplexer, for example, to perform wavelength division multiplexing (WDM). In some embodiments, the waveguide 164 can include a demultiplexer, such as an arrayed waveguide grating (AWG) demultiplexer, an echelle grating, a single-mode waveguide, or a thin-film filter (TFF) demultiplexer. The waveguide 164 can include any type of planar or non-planar waveguide.In one example, waveguide 164 may comprise a silicon photonic waveguide based on a silicon-on-insulator (SOI) platform and configured to guide electromagnetic radiation of any wavelength band from about 0.8 micrometers to about 5.0 centimeters. In another example, waveguide 164 may support wavelengths from about 1.2 micrometers to about 1.7 micrometers in the near-infrared and infrared bands for use in data communications and telecommunications.

[0065] Although only three such exemplary optical elements in Fig. 1B, it can be understood that the PIC 104 may include more optical elements of the same or different types that enable it to function appropriately as a photonic device that receives, transforms, and transmits optical and electrical signals.

[0066] In general, the light provided to the PIC 104 may include any electromagnetic signals with information encoded therein (or, in other words, any electromagnetic signals modulated to include information). Often, the electromagnetic signals are signals associated with optical amplitudes, phases, and wavelengths, and therefore, descriptions provided herein refer to "optical" signals (or light) and "optical" components.However, the photonic microelectronic assembly 100 with the PIC 104 as described herein is not limited to operating with electromagnetic signals of the optical spectrum, and descriptions provided herein with reference to optical signals and / or optical elements are equally applicable to electromagnetic signals of any suitable wavelength, such as electromagnetic signals in near-infrared (NIR) and / or infrared (IR) bands, as well as electromagnetic signals in the RF and / or microwave bands.

[0067] The PIC 104 may comprise a semiconductor material, including, for example, n-type or p-type materials. The PIC 104 may, for example, include a crystalline substrate formed using silicon (or another bulk semiconductor material) or an SOI structure (or generally a semiconductor-on-insulator structure). In some embodiments, the PIC 104 may be formed using alternative materials that may or may not be combined with silicon and include, but are not limited to, lithium niobite, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-N or Group IV materials.In some embodiments, the PIC 104 may comprise a non-crystalline material, such as polymers. In some embodiments, the PIC 104 may be formed on a printed circuit board (PCB). In some embodiments, the PIC 104 may be inhomogeneous, including a carrier material (such as glass or silicon carbide) as a substrate with a thin semiconductor layer over which the active surface 105 is located. Although a few examples of the material for the PIC 104 are described here, any material or structure that can serve as a foundation upon which the PIC 104 can be built falls within the spirit and scope of the present disclosure.

[0068] The microelectronic assembly 100 may further include an IC 128. The IC 128 may be electrically coupled to TGVs 110 in the interposer 103 through interconnects 106. The interconnects 106 may enable electrical coupling between the PIC 104 and the IC 128. The IC 128 may include any suitable IC functionality. In some embodiments, the IC 128 may comprise an electrically integrated circuit (EIC) configured to be electrically integrated with the PIC 104 to achieve an intended functionality of the photonic package 100. The EIC may, for example, be an application-specific integrated circuit (ASIC), including one or more switch or driver / receiver circuits used in optical communication systems.In some embodiments, the EIC may include circuitry for communicating between two or more IC dies. For example, the EIC may function as an interconnect bridge with suitable circuitry on / in a semiconductor substrate for connecting at silicon interconnect speeds with a small footprint. In some embodiments, the EIC may include active components, including one or more transistors, voltage converters, transimpedance amplifiers (TIAs), serializers and deserializers (SERDES), clock and data recovery (CDR) components, microcontrollers, etc. In some embodiments, the EIC may include passive circuitry sufficient to enable interconnection with the PIC 104 and other components in the photonic package 100 without any active components.In some embodiments, IC 128 may include an integrated processor circuit (XPU) with processing functionality, such as a central processing unit (CPU), graphics processing unit (GPU), a field-programmable gate array (FPGA), an ASIC, and an accelerator. In various embodiments, the XPU may be or include one or more voltage converters, transimpedance amplifiers (TIAs), clock and data recovery (CDR) components, microcontrollers, etc. Although . Fig. 1A shows IC 128 as a single IC that may include XPU and / or EIC functionality, in some embodiments, a microelectronic assembly 100 may include multiple ICs 128 with XPU or EIC functionality coupled by interconnects 106.

[0069] The microelectronic assembly 100 may further include a fiber connector 187 optically coupled to an interposer 103. A fiber connector 187 may also be referred to herein as "an optical component." As in Fig. 1A, a fiber connector 187 may be physically coupled to a lateral surface 170-3 (e.g., a side surface) of the interposer 103 and optically coupled to the optical path 160 in the interposer 103. In some embodiments, the fiber connector 187 may include an overhang portion that physically contacts the second surface 170-2 of the interposer 103, as shown, to increase adhesion of the fiber connector 187 to the interposer 103. A fiber connector 187 may be physically coupled to the interposer 103 using any suitable attachment means, for example, optical adhesive or fusion bonding, as previously described with reference to the PIC 104.

[0070] The microelectronic assembly 100 may further include an RDL 148 on the first surface 170-1 of the interposer 103. The RDL 148 may include conductive paths 196 (e.g., including traces, pads / contacts, and / or conductive vias, as shown) through a dielectric material. The RDL 148 may have a set of first conductive contacts 172 on the bottom surface of the RDL 148 and a set of second conductive contacts 174 on the top surface of the RDL 148, with the conductive paths 196 electrically coupling individual ones of the first and second conductive contacts 172, 174. The RDL 148 may be fabricated using any suitable technique, such as a PCB technique or a redistribution layer technique. In some embodiments, a dielectric material of the RDL 148 may be an oxide material such as silicon and oxygen (e.g., in the form of silicon oxide), a nitride material such as silicon and nitrogen (e.g.,in the form of silicon nitride), or an organic material. The RDL 148 may be electrically coupled to the PIC 104 and the IC 128 through the TGVs 110 in the interposer 103. In some embodiments, an RDL 148 may be omitted (e.g., as shown in FIG. Fig. 2A). In some embodiments, an RDL 148 may be included on both the first and second surfaces 170-1, 170-2 of the interposer 103 (not shown).

[0071] The microelectronic assembly 100 from Fig. 1A may also include a circuit board 131. In some embodiments, the circuit board 131 may be a package substrate. In particular, conductive contacts 172 on a lower surface of the RDL 148 may be electrically coupled to conductive contacts 146 on a top surface of the circuit board 131 through interconnects 190. The interconnects 190 disclosed herein may take any suitable form. The interconnects 190 may be any suitable interconnects, including solder balls for a ball grid array, pins in a pin grid array, or contact pads in a contact pad array. In some embodiments, a set of interconnects 190 may include solder 136 (e.g., solder bumps or balls that undergo thermal reflow to form the interconnects 190).The interconnects 190 that include a solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 190 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material may include microscopic conductive particles embedded in a binder or thermosetting adhesive film (e.g., a biphenyl-type thermosetting epoxy resin or an acrylic-based material).In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is uncompressed, there need not be a conductive path from one side of the material to the other. However, when the anisotropic conductive material is appropriately compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), the conductive materials near the compression region may contact each other such that a conductive path from one side of the film to the other is formed in the compression region.In some embodiments, the interconnects 190 disclosed herein may have a pitch between about 50 micrometers and 300 micrometers.

[0072] The microelectronic assembly 100 from Fig. 1A may also include an underfill material 127. In some embodiments, an underfill material 127 may extend between the RDL 148 and the circuit board 131 around the associated interconnects 190. The circuit board 131 may be, for example, a motherboard and may have other components attached to it. The circuit board may include conductive paths and other conductive contacts for conducting power, ground, and signals through the circuit board, as is known in the art. In some embodiments, the interconnects 190 may not be coupled to a circuit board 131, but may instead be coupled to another IC package, an interposer, or any other suitable component. The underfill material 127 may be an insulating material, such as a suitable epoxy material.In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a potted underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in forming the interconnects 190 during soldering and then polymerizes and encapsulates the interconnects 190. The underfill process may include dispensing underfill material in liquid form, allowing the material to flow into and fill the space between the RDL 148 and the interposer 103 and the interstitial gaps around the interconnects 190, and subjecting the assembly to a curing process, such as firing, to solidify the material. In some embodiments, an underfill material 127 may be omitted.The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between the RDL 148 and the circuit board 131 resulting from uneven thermal expansion of the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value that is between the CTE of the RDL 148 (e.g., the CTE of the dielectric material of the RDL 148) and a CTE of the insulating material of the circuit board 131.

[0073] In some embodiments, a microelectronic assembly 100 may include one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymers, photoimageable dry film polymers, acrylics, solvents), which may be provided in an IC package described herein and may not be labeled or shown to avoid cluttering the drawings. A solder resist may be a liquid or dry film material, including photoimageable polymers. In some embodiments, the solder resist may not be photoimageable.

[0074] Fig. 1C is a schematic cross-sectional view of a detail of a particular one of the interconnects 106 in the microelectronic assembly 100. It should be noted that although only the interconnect 106 is shown, the same structure and description may apply to any other such interconnects including hybrid bonds in the microelectronic assembly 100, where applicable, for example, a photoimageable dielectric (PID) with copper-copper bonding or a liquid metal ink (LMI) interconnect. In general, the interconnect 106 at an interface 130 between layers 102-1 and 102-2 may include metal-to-metal bonds between a bond pad 132 of layer 102-1 and a bond pad 134 of layer 102-2 and dielectric-to-dielectric bonds (e.g., oxide-to-oxide bonds) in a dielectric material 108 of layers 102-1 and 102-2.In some embodiments, layer 102-2 may be included in the PIC 104 or the IC 128, and layer 102-1 may be included in the interposer 103. The bond pad 132 of layer 102-1 may be bonded to the bond pad 134 of layer 102-2. The dielectric material 108 in layers 102-1 and 102-2 may be bonded to each other. Dielectric material 108 may include inorganic dielectric materials, for example, silicon and one or more of oxygen, nitrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), and / or other forms of inorganic dielectric material typically used as interlayer dielectrics (ILDs) in semiconductor devices. The bonded metal and dielectric materials form an interconnect 106 that includes hybrid bonds that provide electrical and mechanical coupling between layers 102-1 and 102-2.In various embodiments, interconnects 106 may have a linear dimension of less than 5 micrometers and a pitch of less than 10 micrometers between adjacent interconnects. In some embodiments, interconnects 106 may have a pitch between 2 micrometers and 70 micrometers (e.g., between 2 micrometers and 10 micrometers, between 10 micrometers and 45 micrometers, or between 45 micrometers and 70 micrometers).

[0075] Fig. 1D is a top view of the microelectronic assembly of Fig. 1A. As in Fig. 1D, the microelectronic assembly 100 may include a plurality of ICs 128 and a plurality of PICs 104 electrically coupled to the interposer 103 by interconnects 106 (such as in Fig. 1A), and a plurality of fiber connectors 187, wherein the plurality of fiber connectors 187 are optically coupled to the plurality of PICs 104 through optical paths 160 in the interposer 103. As shown in Fig. 1D, individual PICs 104 may be optically coupled to individual fiber connectors 187 through optical paths 160 in interposer 103; one or more fiber connectors 187 may be optically coupled to individual PICs 104 through optical paths 160 in interposer 103; and one or more PICs may be optically coupled to other PICs 104 through optical paths 160 in interposer 103. Although Fig. 1D shows the microelectronic assembly 100 with three ICs 128, three PICs 104, and four fiber connectors 187, a microelectronic assembly 100 may include any suitable number and arrangement of ICs 128, PICs 104, and fiber connectors 187, and any suitable number and arrangement of electrical and optical connections therebetween.

[0076] Fig. Figure 2A is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is similar to that of Fig. 1A, except for differences as further described. The configuration of the microelectronic assembly 100 as described herein includes first and second PICs 104-1, 104-2 and first and second fiber connectors 187-1, 187-2, wherein the first PIC 104-1 is optically coupled to the first fiber connector 187-1 by a first optical path 160-1 through the interposer 103, the second PIC 104-2 is optically coupled to the second fiber connector 187-2 by a second optical path 160-2 through the interposer 103, and the first PIC 104-1 is optically coupled to the second PIC 104-2 by a third optical path 160-3 through the interposer 103. As in Fig. 2B, the bonding interface between the first and second PIC 104-1, 104-2 and the interposer 103 may include optical adhesive 117, as previously described with reference to Fig. 1A. The first and second PICs 104-1, 104-2 may be electrically coupled to the IC 128 through interconnects 106, TGVs 110 (not shown), and conductive paths 196 through the RDL 148. The first and second PICs 104-1, 104-2 may also be electrically coupled to each other through interconnects 106, TGVs 110 (not shown), and conductive paths 196 through the RDL 148.

[0077] Fig. 2B is an enlarged cross-sectional view of a portion of the microelectronic assembly of Fig. 2A. As in Fig. 2B, a bonding interface between the PIC 104 and an interposer 103 may include an optical adhesive 117 on an active surface 105 of the PIC 104, as previously described with reference to Fig. 1A. The bonding interface may further include an anti-reflective coating 119 on a top surface of the interposer 103 to increase light efficiency and reduce light reflection or leakage. In some embodiments, an opening 113 may be formed through the optical adhesive 117 to reduce light reflection or loss at the bonding interface. Although Fig. 2B illustrates a bonding interface including an optical adhesive 117, a bonding interface between a PIC 140 and an interposer 103 may include a bonding material (e.g., a dielectric material 108 as shown in Fig. 1A) with an opening 113 and / or a reflective material 119.

[0078] Fig. 2C is a top view of the microelectronic assembly of Fig. 2A. As in Fig. 2C, the microelectronic assembly 100 may include a plurality of ICs 128 and a plurality of PICs 104 electrically coupled to an interposer 103 (not shown) through interconnects 106, and a plurality of fiber connectors 187, wherein the plurality of fiber connectors 187 are optically coupled to the plurality of PICs 104 through optical paths 160 in the interposer 103. As shown in Fig. 2C, individual PICs 104 may be optically coupled to individual fiber connectors 187 through optical paths 160 in interposer 103; one or more fiber connectors 187 may be optically coupled to individual PICs 104 through optical paths 160 in interposer 103; and one or more PICs may be optically coupled to other PICs 104 through optical paths 160 in interposer 103. Although Fig. 2C shows the microelectronic assembly 100 with two ICs 128, eight PICs 104, and eleven fiber connectors 187, a microelectronic assembly 100 may include any suitable number and arrangement of ICs 128, PICs 104, and fiber connectors 187, and any suitable number of electrical and optical connections therebetween.

[0079] Any suitable techniques may be used to fabricate the microelectronic assemblies 100 disclosed herein. For example, Fig. 3A-3E are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic assembly 100 from Fig. 2A according to various embodiments. Although the embodiments described below with reference to Fig. 3A-3E (and other accompanying drawings representing manufacturing processes) are illustrated in a particular order, these operations may be performed in any suitable order. Furthermore, additional operations not illustrated may also be performed without departing from the scope of the present disclosure. In addition, various of the operations discussed herein with reference to Fig. 3A-3E may be modified according to the present disclosure to fabricate another microelectronic assembly 100 disclosed herein.

[0080] Fig. 3A illustrates an assembly following the formation of a bonding layer 124 on a top surface 170-2 of the interposer 103. The interposer 103 may include a first surface 170-1, a second surface 170-2, and a lateral surface 170-3. The bonding layer 124 may include bond pads 132 in a dielectric material 108, as previously described with reference to Fig. 1C. The bonding layer 124 may include regions 197 of dielectric material without bond pads 132, in which dielectric material may subsequently be removed, as described below with reference to Fig. 3B. In some embodiments, the assembly may include an interposer 103 having a prefabricated waveguide therein forming the optical path 160. In some embodiments, the interposer 103 may include one or more optical paths or one or more portions of optical paths. In some embodiments, the interposer 103 may not include optical paths or portions of optical paths, and instead, the optical paths may be formed in situ. The interposer 103 may further include TGVs (e.g., TGVs 110 in Fig. 2A) (not shown), which may be prefabricated or formed by creating via openings by the interposer 103 and depositing a conductive material in the via openings.

[0081] Fig. 3B illustrates an assembly following removal of the dielectric material regions 197 to expose the second surface 170-2 of the interposer 103 and formation of optical paths 160-1, 160-2, 160-3 through the interposer 103. The dielectric material may be removed using any suitable technique, including etching, mechanical milling, or laser ablation. The second surface 170-2 of the interposer 103 may further be ground and polished to form an optically smooth surface. The optical paths 160-1, 160-2, 160-3 may be formed using any suitable technique, for example, forming waveguides in situ by laser direct writing.

[0082] Fig. 3C illustrates an assembly following electrically coupling the IC 128 and the PICs 104-1, 104-2 by forming interconnects 106 and physically and optically coupling the PICs 104-1, 104-2 (e.g., the first and second PICs 104-1, 104-2) to the interposer 103. The IC 128 and the PICs 104 may include a bonding layer on a lower surface with bond pads 134 in the dielectric material 108 (e.g., as shown in Fig. 1C). The bond pads 132 of the interposer 103 may correspond to the bond pads 134 of the IC 128 and PICs 104 to form hybrid direct bonds (e.g., interconnects 106). The active surfaces 105 of the PICs 104-1, 104-2 may be physically attached to the active surfaces 105 of the PICs 104 using any suitable technique, including optical adhesive 117, as shown, or fusion bonding. Any suitable method may be used to place the IC 128 and PICs 104, for example, automated pick-and-place. The assembly of Fig. 3C may be subjected to suitable bonding processing to form interconnects 106. For example, the bonding process may include applying a suitable pressure and heating to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 200 degrees Celsius) for a period of time.

[0083] Fig. 3D illustrates an assembly following the formation of an RDL 148 on the top surface 170-1 of the interposer 103. The RDL 148 may include conductive paths 196 between first conductive contacts 172 and second conductive contacts 174. The RDL 148 may be fabricated using any suitable technique, such as a PCB technique or a redistribution layer technique.

[0084] Fig. 3E illustrates an assembly following the physical attachment of the fiber connectors 187-1, 187-2 to the second surface 170-2 of the interposer 103 and the optical alignment with the respective optical paths 160-1, 160-2 and the performance of finishing operations. The fiber connectors 187-1, 187-2 may be optically aligned, if necessary, and optically coupled using any suitable technique, such as optical adhesive or fusion bonding. Example finishing operations include depositing solder resist (not shown) and depositing solder 136 on a lower surface of conductive contacts 172 of the RDL 148. If multiple assemblies are manufactured together, the assemblies may be singulated. The assembly of Fig. 3E may itself be a microelectronic assembly 100, as shown. Further manufacturing operations may be performed on the microelectronic assembly 100 of Fig. 3E to form another microelectronic assembly 100. For example, the solder 136 of the microelectronic assembly 100 may be Fig. 3E can be electrically coupled to a circuit board 131 to form interconnections 190, similar to the microelectronic assembly 100 of Fig. 2A.

[0085] Fig. 4 is a flowchart of an example method for manufacturing an example microelectronic assembly according to various embodiments. At 402, a bonding layer 124 including bond pads 132 in a dielectric material 108 may be formed on a surface 170-2 of an interposer 103. In some embodiments, the interposer 103 may include glass. In some embodiments, the interposer 103 may include TGVs 110 and at least a portion of an optical path 160. The bonding layer 124 may include a portion 197 of the dielectric material 108 without bond pads 132. At 404, the portion 197 of the dielectric material 108 may be removed to expose the surface 170-2 of the interposer 103, and the optical path 160 may be formed. The dielectric material 108 may be removed using any suitable process, including grinding.The optical path 160 may be formed by any suitable technique, including direct laser writing. At 406, the IC 128 and the PIC 104 may be electrically coupled to the TGVs 110 in the interposer 103. The IC 128 and the PIC 104 may include a bonding layer on a lower surface with bond pads 134 in the dielectric material 108 (e.g., as shown in FIG. Fig. 1C). The bond pads 132 of the interposer 103 may correspond to the bond pads 134 of the IC 128 and PICs 104 to form hybrid direct bonds (e.g., interconnects 106). The PIC 104 may be optically aligned with the optical path 160 as needed and attached to the surface 170-2 of the interposer 103 using any suitable technique, including optical adhesive or fusion bonding. At 408, a fiber connector 187 (also referred to herein, e.g., as an optical component) may be optically coupled to the interposer 103 such that the fiber connector 187 is optically coupled to the PIC 104 through the optical path 160 through the interposer 103. The fiber connector 187 can be optically aligned as needed and can be physically attached using any suitable technique, including optical adhesive or fusion bonding.At 410, surface finishing operations can be performed and assemblies can be separated as needed. Surface finishing operations can include, for example, dispensing solder mask and attaching solder balls.

[0086] The packages disclosed herein, e.g., any of the microelectronic assemblies 100 or other embodiments described herein, may be incorporated into any suitable electronic component. Fig. 5-7 illustrate various examples of packages, assemblies, and devices that may be used with or include any of the IC packages as disclosed herein.

[0087] Fig. Figure 5 is a side cross-sectional view of an exemplary IC package 2200, which may include IC packages according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0088] As shown in the figure, the package substrate 2252 may be formed from an insulator (e.g., a ceramic, a build-up film, an epoxy film with filler particles therein, etc.) and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between different locations on the first surface 2272 and / or between different locations on the second surface 2274. These conductive paths may take the form of any of the interconnect structures, including leads and / or vias.

[0089] The package substrate 2252 may include conductive contacts 2263 coupled to a conductive path 2262 through the package substrate 2252, thereby enabling circuitry within the die 2256 and / or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0090] The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2265 may be used, such as solder bumps, solder posts, or bond wires.

[0091] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of dies 2256, first-level interconnects 2258, and conductive contacts 2260 of an interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, thereby enabling circuitry within the dies 2256 to be electrically coupled to various ones of the conductive contacts 2261 (or to other devices not shown included in the interposer 2257). The first-level interconnects 2258 illustrated in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder posts, or bond wires. As used herein, a “conductive contact” may refer to a portion of an electrically conductive material (e.g.metal) that serves as an interface between different components; conductive contacts may be recessed into, flush with, or extend from a surface of a component and may take any suitable form (e.g., a conductive pad or a socket).

[0092] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a molding compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding compound 2268. Example materials that may be used for the underfill material 2266 and the molding compound 2268 are suitable epoxies. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in the figure are solder balls (e.g., for a ball grid array (BGA) device), but any suitable second-level interconnects 2270 may be used (e.g.,Pins in a pin grid array arrangement or contact pads in a contact pad grid array arrangement). The second-level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a printed circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and described below with reference to FIG. Fig. 6 is discussed.

[0093] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 as described herein. In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry for performing any desired functionality. In addition to one or more of the dies 2256 being the microelectronic assembly 100 as described herein, for example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., HBM), etc. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the preceding figures.In some embodiments, at least some of the dies 2256 may not include implementations as described herein.

[0094] Although the IC package 2200 illustrated in the figure is a flip-chip package, other package architectures may be used. For example, the IC package 2200 may be a BGA package, such as an eWLB (Embedded Wafer-Level Ball Grid Array) package. In another example, the IC package 2200 may be a WLCSP (Wafer-Level Chip Scale Package) or a Panel Fanout (FO) package. Although two dies 2256 are illustrated in the IC package 2200, an IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed over the first surface 2272 or the second surface 2274 of the package substrate 2252 or on both surfaces of the interposer 2257.More generally, the IC package 2200 may include any other active or passive components known in the art.

[0095] In some embodiments, an interposer 2257 may not be included in the IC package 2200; instead, the dies 2256 may be directly coupled to the conductive contacts 2263 on the first surface 2272 through second-level interconnects 2265.

[0096] Fig. 6 is a cross-sectional side view of an IC device assembly 2300 that may include components with one or more microelectronic assemblies 100, according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed over a first surface 2340 of the circuit board 2302 and on an opposite second surface 2342 of the circuit board 2302; generally, components may be disposed over one or both surfaces 2340 and 2342. In particular, any suitable components of the IC device assembly 2300 may include any of the one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; e.g.,Any of the IC packages discussed below with reference to IC device assembly 2300 may take the form of any of the IC packages discussed above with reference to . Fig. 5 discussed embodiments of the IC package 2200.

[0097] In some embodiments, circuit board 2302 may be a PCB that includes multiple metal layers separated by layers of insulator and connected by electrically conductive vias. Any one or more of the metal layers may be formed into a desired circuit pattern to carry electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In some embodiments, circuit board 2302 may be a non-PCB package substrate.

[0098] As illustrated in the figure, in some embodiments, the IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to the first surface 2340 of the circuit board 2302 by coupling components 2316. The coupling components 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0099] The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form depending on desired functionalities, such as the forms discussed above with reference to the coupling components 2316. In some embodiments, the IC package 2320 may be or include the IC package 2200, such as previously discussed with reference to Fig. 5. In some embodiments, IC package 2320 may include at least one microelectronic assembly 100 as described herein. Microelectronic assembly 100 is not specifically shown in the figure to avoid cluttering the drawing.

[0100] Although a single IC package 2320 is shown in the figure, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intermediate package substrate used to form a bridge between the circuit board 2302 and the IC package 2320. In general, the interposer 2304 may redistribute an interconnect to a larger pitch or reroute an interconnect to a different interconnect. For example, the interposer 2304 may couple the IC package 2320 to a BGA of the coupling components 2316 for coupling to the circuit board 2302.

[0101] In the embodiment illustrated in the figure, the IC package 2320 and the circuit board 2302 are mounted on opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be mounted on the same side of the interposer 2304. In some embodiments, three or more components may be interconnected via the interposer 2304.

[0102] The interposer 2304 may be formed from an epoxy resin, a glass-fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including, but not limited to, TSVs 2306. The interposer 2304 may further include embedded devices 2314, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices.More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.

[0103] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to the first surface 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0104] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to the second surface 2342 of the circuit board 2302 by the coupling components 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by coupling components 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and / or 2332 may take the form of any embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structures known in the art.

[0105] Fig. 7 is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more integrated circuit packages, in accordance with any of the embodiments disclosed herein. For example, any suitable components of computing device 2400 may include a microelectronic assembly (e.g., 100) in accordance with any of the embodiments disclosed herein. In another example, any one or more components of computing device 2400 may include any embodiments of integrated circuit package 2200 (e.g., as described in Fig. 5). In yet another example, any one or more of the components of the computing device 2400 may include an IC device package 2300 (e.g., as shown in Fig. 6 shown).

[0106] A number of components are illustrated in the figure as being included in computing device 2400, however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components may be fabricated on a single SoC die.

[0107] Additionally, in various embodiments, computing device 2400 may not include one or more of the components illustrated in the figure, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g.,connector and support circuitry) to which an audio input device 2418 or the audio output device 2408 can be coupled.

[0108] Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptoprocessors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. Computing device 2400 may include a memory 2404, which may itself include one or more storage devices, such as volatile memory (e.g.,dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0109] In some embodiments, computing device 2400 may include a communications chip 2412 (e.g., one or more communications chips). For example, communications chip 2412 may be configured to manage wireless communications for transferring data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although in some embodiments, they may not include them.

[0110] The communication chip 2412 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), LTE Project along with all modifications, updates, and / or revisions (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) Project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and interoperability tests for the IEEE 802.16 standards.The communications chip 2412 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 2412 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and variations thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2412 may operate according to other wireless protocols.Computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0111] In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., Ethernet). As mentioned above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.

[0112] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to a power source separate from computing device 2400 (e.g., the AC mains supply).

[0113] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any suitable visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0114] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, speakers, headphones, or earbuds.

[0115] Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry, as discussed above). Audio input device 2418 may include any device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI) output).

[0116] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may be in communication with a satellite-based system and receive a location of computing device 2400, as is known in the art.

[0117] Computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as discussed above). Examples of another output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for delivering information to other devices, or an additional storage device.

[0118] Computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of another input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0119] Computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.

[0120] The above description of illustrated implementations of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of the disclosure and examples thereof are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as one skilled in the art will recognize.

[0121] Example 1 is a photonic assembly including: an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical path through the interposer.

[0122] Example 2 may include the subject matter of Example 1, and may further specify that the optical component is a fiber connector.

[0123] Example 3 may include the subject matter of Examples 1 or 2, and may further specify that the hybrid bond interconnects have a pitch of 2 micrometers and 70 micrometers between adjacent interconnects.

[0124] Example 4A may include the subject matter of any of Examples 1-3 and may further specify that the optical path includes a waveguide through the interposer.

[0125] Example 4B may include the subject matter of Example 4A, and may further specify that the waveguide through the interposer is a laser-scribed waveguide.

[0126] Example 5 may include the subject matter of any of Examples 1-4 and may further specify that the optical component is coupled to the interposer by optical adhesive or by fusion bonding.

[0127] Example 6 may include the subject matter of any of Examples 1-5 and may further specify that the PIC is a first PIC, the hybrid bond interconnects are first hybrid bond interconnects, the optical component is a first optical component, and the optical path is a first optical path, and the photonic assembly may further include: a second PIC optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by second hybrid bond interconnects; a second optical component coupled to the interposer, the second optical component optically coupled to the second PIC by a second optical path through the interposer.

[0128] Example 7 may include the subject matter of Example 6, and wherein the first PIC is optically coupled to the second PIC by a third optical path through the interposer.

[0129] Example 8 may include the subject matter of any of Examples 1-7 and may further specify that the hybrid bond interconnections are first hybrid bond interconnections, and the photonic assembly may further include: an IC electrically coupled to the TGVs in the interposer by second hybrid bond interconnections.

[0130] Example 9 may include the subject matter of Example 8, and may further specify that the IC includes an electrical integrated circuit or a processor integrated circuit.

[0131] Example 10 may include the subject matter of any of Examples 1-9 and may further specify that the surface of the interposer is a second surface, the interposer further includes a first surface opposite the second surface, and the photonic assembly may further include: a dielectric material on the first surface of the interposer, the dielectric material including conductive pathways electrically coupled to the TGVs in the interposer; and a circuit board electrically coupled to the conductive pathways in the dielectric material.

[0132] Example 11 may include the subject matter of any of Examples 1-5, and may further specify that the optical component is one of a plurality of optical components and the PIC is one of a plurality of PICs, and wherein individual ones of the plurality of optical components are coupled to individual ones of the plurality of PICs by optical paths through the interposer.

[0133] Example 12 is a photonic assembly including: an interposer having a first surface, an opposite second surface, and a lateral surface substantially perpendicular to the first and second surfaces, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) and an integrated circuit (IC) electrically coupled to the TGVs on the second surface of the interposer by interconnects having a pitch between 2 micrometers and 70 micrometers between adjacent interconnects, and the PIC optically coupled to the second surface of the interposer by optical adhesive or fusion bonding;and an optical component coupled to the lateral surface of the interposer, the optical component being optically coupled to the PIC by an optical path through the interposer;

[0134] Example 13 may include the subject matter of Example 12, and may further specify that the optical component is a fiber connector.

[0135] Example 14 may include the subject matter of Examples 12 or 13, and may further specify that the optical component is coupled to the lateral surface of the interposer by optical adhesive or by fusion bonding.

[0136] Example 15 may include the subject matter of any of Examples 12-14 and may further specify that the optical path includes a waveguide through the interposer.

[0137] Example 16 may include the subject matter of Example 15, and may further specify that the waveguide through the interposer is a laser-scribed waveguide.

[0138] Example 17 may include the subject matter of any of Examples 12-16 and may further specify that the PIC is electrically coupled to the IC through the TGVs.

[0139] Example 18 may include the subject matter of any of Examples 12-17 and may further specify that the optical component is a first optical component and the optical path is a first optical path, and the photonic assembly may further include: a second optical component on the lateral surface of the interposer, the second optical component optically coupled to the PIC by a second optical path through the interposer.

[0140] Example 19 is a photonic assembly including: an interposer having a first surface and an opposite second surface, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a plurality of photonic integrated circuits (PICs) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by interconnects; and a plurality of optical components coupled to the interposer, the plurality of optical components optically coupled to the plurality of PICs by optical paths through the interposer.

[0141] Example 20 may include the subject matter of Example 19, and may further specify that the plurality of optical components are fiber connectors.

[0142] Example 21 may include the subject matter of Examples 19 or 20, and may further specify that the optical paths include waveguides through the interposer.

[0143] Example 22 may include the subject matter of any of Examples 19-21 and may further specify that the plurality of optical components are coupled to the interposer by optical adhesive or by fusion bonding.

[0144] Example 23 may include the subject matter of any of Examples 19-22 and may further specify that the optical paths are first optical paths, and the photonic assembly may further include second optical paths through the interposer that optically couple respective ones of the plurality of PICs to other respective ones of the plurality of PICs.

[0145] Example 24 may include the subject matter of any of Examples 19-23 and may further specify that the interconnections are first interconnections, and the photonic assembly may further include an IC electrically coupled to the TGVs in the interposer by second interconnections.

[0146] Example 25 may include the subject matter of Example 24, and may further specify that the IC includes an electrical integrated circuit or a processor integrated circuit.

Claims

[1] Photonic assembly comprising: an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component coupled to the interposer, the optical component being optically coupled to the PIC by an optical path through the interposer. [2] The photonic assembly of claim 1, wherein the optical component is a fiber connector. [3] The photonic assembly of claim 1 or 2, wherein the hybrid bond interconnects have a pitch of 2 micrometers and 70 micrometers between adjacent interconnects. [4] A photonic assembly according to any one of claims 1-3, wherein the optical path includes a waveguide through the interposer. [5] Photonic assembly according to any one of claims 1-4, wherein the optical component is coupled to the interposer by optical adhesive or by fusion bonding. [6] The photonic assembly of any one of claims 1-5, wherein the PIC is a first PIC, the hybrid bond interconnects are first hybrid bond interconnects, the optical component is a first optical component, and the optical path is a first optical path, and the photonic assembly further comprises: a second PIC optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by second hybrid bond interconnections; and a second optical component coupled to the interposer, the second optical component being optically coupled to the second PIC by a second optical path through the interposer. [7] The photonic assembly of claim 6, and wherein the first PIC is optically coupled to the second PIC by a third optical path through the interposer. [8] The photonic assembly of any one of claims 1-7, wherein the hybrid bond interconnections are first hybrid bond interconnections and the photonic assembly further comprises: an IC electrically coupled to the TGVs in the interposer through second hybrid bond interconnections. [9] The photonic assembly of claim 8, wherein the IC includes an electrical integrated circuit or a processor integrated circuit. [10] The photonic assembly of any one of claims 1-9, wherein the surface of the interposer is a second surface, the interposer further includes a first surface opposite the second surface, and the photonic assembly further comprises: a dielectric material on the first surface of the interposer, the dielectric material including conductive paths electrically coupled to the TGVs in the interposer; and a circuit board electrically coupled to the conductive paths in the dielectric material. [11] The photonic assembly of any of claims 1-5, wherein the optical component is one of a plurality of optical components and the PIC is one of a plurality of PICs, and wherein individual ones of the plurality of optical components are coupled to individual ones of the plurality of PICs by optical paths through the interposer. [12] Integrated circuit (IC) package comprising: an interposer having a first surface, an opposite second surface, and a lateral surface substantially perpendicular to the first and second surfaces, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a photonic integrated circuit (PIC) and an integrated circuit (IC) electrically coupled to the TGVs on the second surface of the interposer by interconnects having a pitch of between 2 micrometers and 70 micrometers between adjacent interconnects, and the PIC optically coupled to the second surface of the interposer by optical adhesive or fusion bonding; and an optical component coupled to the lateral surface of the interposer, the optical component being optically coupled to the PIC by an optical path through the interposer. [13] The IC package of claim 12, wherein the optical component is a fiber connector. [14] The IC package of claim 12 or 13, wherein the optical component is coupled to the lateral surface of the interposer by optical adhesive or by fusion bonding. [15] The IC package of any of claims 12-14, wherein the optical path includes a waveguide through the interposer. [16] The IC package of claim 15, wherein the waveguide through the interposer is a laser-scribed waveguide. [17] The IC package of any of claims 12-16, wherein the PIC is electrically coupled to the IC by the TGVs. [18] The IC package of any one of claims 12-17, wherein the optical component is a first optical component and the optical path is a first optical path, and the IC package further comprises: a second optical component on the lateral surface of the interposer, the second optical component being optically coupled to the PIC by a second optical path through the interposer. [19] Microelectronic assembly comprising: an interposer having a first surface and an opposite second surface, wherein a material of the interposer includes glass and the interposer includes glass vias (TGVs); a plurality of photonic integrated circuits (PICs) optically coupled to the surface of the interposer by optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by interconnects; and a plurality of optical components coupled to the interposer, wherein the plurality of optical components are optically coupled to the plurality of PICs by optical paths through the interposer. [20] The microelectronic assembly of claim 19, wherein the plurality of optical components are fiber connectors. [21] The microelectronic assembly of claim 19 or 20, wherein the optical path includes a waveguide through the interposer. [22] The microelectronic assembly of any of claims 19-21, wherein the plurality of optical components are coupled to the interposer by optical adhesive or by fusion bonding. [23] The microelectronic assembly of any one of claims 19-22, wherein the optical paths are first optical paths and the microelectronic assembly further comprises: second optical paths through the interposer that optically couple respective ones of the plurality of PICs to other respective ones of the plurality of PICs. [24] A microelectronic assembly according to any one of claims 19-23, wherein the interconnections are first interconnections and the microelectronic assembly further comprises: an IC that is electrically coupled to the TGVs in the interposer through second interconnections. [25] The microelectronic assembly of claim 24, wherein the IC includes an electrical integrated circuit or a processor integrated circuit.

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