Display substrate, display field and display device

Abstract

A display substrate, a display field, and a display device are provided. The display substrate comprises: several subpixels provided on the base substrate; a first initialization voltage signal line provided on the base substrate; a first electrode provided on the base substrate; and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel includes a pixel opening located on the pixel boundary layer. The first initialization voltage signal line comprises a first initialization voltage signal subline and a second initialization voltage signal subline, wherein a main body section of the first initialization voltage signal subline extends along the first direction, and a main body section of the second initialization voltage signal subline extends along the second direction.An orthogonal projection of one of the second initialization voltage signal sublines onto the base substrate lies on a first side of a center of a pixel opening of one of the first two subpixels, and an orthogonal projection of another of the second initialization voltage signal sublines onto the base substrate lies on a second side of a center of a pixel opening of another of the first two subpixels.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of display technology, specifically to a display substrate, a display field and a display device. STATE OF THE ART

[0002] Organic light-emitting diode (OLED) displays are a type of display device that uses light-emitting OLEDs to display information such as images. OLED displays are characterized by features such as low power consumption, high brightness, and fast response times. With the development of OLED technology, the demands on display performance are constantly increasing, and performance parameters, such as color accuracy, must be continuously improved. Many factors affect a product's color accuracy, and from a substrate design perspective, the flatness of the planar layer or pixel electrode has a significant impact.

[0003] The above information disclosed in this part is intended only to provide background information on the technical concept of the present disclosure and may therefore contain information that is not part of the prior art. REVELATION OF THE INVENTION

[0004] In one aspect, a display substrate is provided comprising: a base substrate; several subpixels provided on the base substrate, wherein the several subpixels are arranged in an array along a first direction and a second direction to form several rows of subpixels and several columns of subpixels, each comprising at least one of the subpixels comprising a light-emitting element; a first initialization voltage signal line provided on the base substrate, wherein the first initialization voltage signal line is used to transmit a first initialization voltage signal; a first electrode layer provided on the base substrate, wherein the light-emitting element of the at least one subpixel comprises a first electrode located on the first electrode layer;and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel comprises a pixel aperture located on the pixel boundary layer, wherein an orthogonal projection of the pixel aperture of the at least one subpixel onto the base substrate coincides with an orthogonal projection of the first electrode of the at least one subpixel onto the base substrate, wherein the first initialization voltage signal line comprises a first initialization voltage signal sub-line and a second initialization voltage signal sub-line, wherein a main body section of the first initialization voltage signal sub-line extends along the first direction, and a main body section of the second initialization voltage signal sub-line extends along the second direction;wherein the at least one subpixel comprises several first subpixels, the several first subpixels being subpixels of a first color; wherein orthogonal projections of several of the second initialization voltage signal sub-lines onto the base substrate each partially overlap with orthogonal projections of the first electrodes of the several first subpixels onto the base substrate;wherein orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a first side and a second side, wherein the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a center, wherein the center is a center of an orthogonal projection of the pixel opening onto the base substrate on a virtual line segment extending along the first direction, wherein the first side and the second side are opposite sides in the first direction relative to the center;wherein for at least two first subpixels an orthogonal projection of one of the second initialization voltage signal sublines onto the base substrate lies on a first side of a center of a pixel opening of one of the two first subpixels, and an orthogonal projection of another of the second initialization voltage signal sublines onto the base substrate lies on a second side of a center of a pixel opening of another of the two first subpixels.

[0005] According to some exemplary embodiments, the first two subpixels are any two first subpixels that are arranged in the same row and adjacent to each other.

[0006] According to some exemplary embodiments, several of the first initialization voltage signal sub-lines and several of the second initialization voltage signal sub-lines are crossed and connected, so that the first initialization voltage signal lines form a network structure.

[0007] According to some exemplary embodiments, the orthogonal projections of the several second initialization voltage signal sub-lines onto the base substrate each partially overlap with the orthogonal projections of the pixel openings of the several first subpixels onto the base substrate.

[0008] According to some exemplary embodiments, for any two first subpixels arranged in the same row and adjacent to each other, orthogonal projections of two of the second initialization voltage signal sub-lines onto the base substrate, which partially overlap with the first electrodes of the two first subpixels, are symmetrical relative to a first axis of symmetry, wherein the first axis of symmetry passes through a midpoint of a connecting line between the centers of the pixel openings of the two first subpixels and extends along the second direction.

[0009] According to some exemplary embodiments, for any two first subpixels arranged in the same column and adjacent to each other, the orthogonal projection of one second initialization voltage signal sub-line onto the base substrate lies on a first side of an orthogonal projection of a pixel opening of one of the two first subpixels onto the base substrate, and the orthogonal projection of the other second initialization voltage signal sub-line onto the base substrate lies on a second side of an orthogonal projection of a pixel opening of another of the two first subpixels onto the base substrate.

[0010] According to some exemplary embodiments, the multiple rows of subpixels comprise multiple rows of first subpixels, and the multiple columns of subpixels comprise multiple columns of first subpixels; wherein positions of a second initialization voltage signal sub-line partially overlapping with a first electrode of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal sub-line partially overlapping with a first electrode of a first subpixel located in an i+4-th row and a j-th column, are oriented in the second direction, where i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1.

[0011] According to some exemplary embodiments, the multiple rows of subpixels comprise multiple rows of first subpixels, and the multiple columns of subpixels comprise multiple columns of first subpixels; wherein positions of a second initialization voltage signal sub-line partially overlapping with a first electrode of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal sub-line partially overlapping with a first electrode of a first subpixel located in an i+2-th row and a j-th column, are oriented in the second direction, where i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1.

[0012] According to some exemplary embodiments, at least one of the second initialization voltage signal sub-lines lies between two adjacent first initialization voltage signal sub-lines; wherein the at least one second initialization voltage signal sub-line comprises a first section, a second section and a third section, the second section being located between the first section and the third section, the first section and the third section extending along the second direction, and the second section extending along a third direction, the third direction intersecting with both the first direction and the second direction.

[0013] According to some exemplary embodiments, a distance between the center of the pixel opening of the first subpixel and a first section of the next second initialization voltage signal sub-line in the first direction is a first distance, and a distance between the center of the pixel opening of the first subpixel and a third section of the next second initialization voltage signal sub-line in the first direction is a second distance, wherein the first distance is smaller than the second distance.

[0014] According to some exemplary embodiments, the display substrate comprises a first electrically conductive layer and a second electrically conductive layer provided on the base substrate, the second electrically conductive layer being located between the first electrically conductive layer and the first electrode layer, the first initialization voltage signal line being located on the first electrically conductive layer; the display substrate further comprising a data line located on the second electrically conductive layer, the data line being used to transmit a data signal; the display substrate further comprising a data signal adapter section located on the first electrically conductive layer, the data signal adapter section being electrically connected to the data line;wherein an extension line of a first section of the at least one second initialization voltage signal sub-line runs along the second direction through at least one of the data signal adapter sections, wherein a third section of the at least one second initialization voltage signal sub-line and the at least one data signal adapter section are spaced apart in the first direction.

[0015] According to some exemplary embodiments, the display substrate further comprises a first insulating layer located between the first electrically conductive layer and the second electrically conductive layer; and several through-holes located in the first insulating layer; wherein, for any two first subpixels arranged in the same row and adjacent to each other, orthogonal projections of some of the several through-holes onto the base substrate lie on the first side of the orthogonal projection of the pixel opening of one of the two first subpixels onto the base substrate, and orthogonal projections of some other of the several through-holes onto the base substrate lie on the second side of the orthogonal projection of the pixel opening of the other of the two first subpixels onto the base substrate.

[0016] According to some exemplary embodiments, for any two first subpixels arranged in the same row and adjacent to each other, orthogonal projections of some and some other through-holes onto the base substrate are symmetrical relative to the first axis of symmetry, the first axis of symmetry passing through the midpoint of the connecting line between the centers of the pixel openings of the two first subpixels and extending along the second direction.

[0017] According to some exemplary embodiments, the display substrate further comprises a first electrode adapter section located on the first electrically conductive layer and a second electrode adapter section located on the second electrically conductive layer, wherein the multiple through-holes located in the first insulating layer include a first through-hole; wherein the first electrode is electrically connected to the second electrode adapter section, and the second electrode adapter section is electrically connected to the first electrode adapter section through the first through-hole; wherein the some through-holes include at least one first through-hole, and the some other through-holes include at least one first through-hole.

[0018] According to some exemplary embodiments, the some through holes comprise two first through holes, and the some other through holes comprise two first through holes.

[0019] According to some exemplary embodiments, the display substrate further comprises a voltage signal adapter section located on the first electrically conductive layer and a first voltage signal line located on the second electrically conductive layer, wherein the multiple through-holes located in the first insulating layer include a second through-hole, and wherein the first voltage signal line is electrically connected to the voltage signal adapter section through the second through-hole; wherein some of the through-holes include at least one second through-hole, and some of the other through-holes include at least one second through-hole.

[0020] According to some exemplary embodiments, the voltage signal adapter section comprises a first voltage signal adapter section, wherein the first voltage signal adapter section comprises a first section, a second section and a third section, wherein the second section extends along the second direction, wherein the first section and the third section each extend along the first direction, and wherein the first section and the third section each extend from the second section along opposite directions;wherein an orthogonal projection of an end of the first section facing away from the second section onto the base substrate overlaps at least partially with an orthogonal projection of one of the second through-holes onto the base substrate, and an orthogonal projection of an end of the third section facing away from the second section onto the base substrate overlaps at least partially with an orthogonal projection of another of the second through-holes onto the base substrate.

[0021] According to some exemplary embodiments, the voltage signal adapter section comprises a second voltage signal adapter section, wherein the second voltage signal adapter section comprises a first section and a second section, the second section extending along the second direction, and the first section extending along the first direction, the first section extending from the second section to one side; wherein an orthogonal projection of an end of the first section facing away from the second section onto the base substrate overlaps at least partially with the orthogonal projection of one of the second through-holes onto the base substrate.

[0022] According to some exemplary embodiments, the voltage signal adapter section comprises a third voltage signal adapter section, wherein the third voltage signal adapter section comprises a second section and a third section, the second section extending along the second direction, and the third section extending along the first direction, the third section extending from the second section to another side; wherein an orthogonal projection of an end of the third section facing away from the second section onto the base substrate overlaps at least partially with the orthogonal projection of one of the second through-holes onto the base substrate.

[0023] According to some exemplary embodiments, the first voltage signal adapter section is provided between a second voltage signal adapter section and a third voltage signal adapter section, which are arranged adjacent in the first direction.

[0024] According to some exemplary embodiments, the display substrate comprises several pixel driver circuits provided on the base substrate, wherein the several pixel driver circuits are arranged in an array along the first and second directions, the several pixel driver circuits being used to drive the light-emitting elements of the several subpixels; wherein the display substrate further comprises: a first semiconductor layer provided on the base substrate; a third electrically conductive layer provided on a side of the first semiconductor layer facing away from the base substrate; a fourth electrically conductive layer provided on a side of the third electrically conductive layer facing away from the base substrate; a second semiconductor layer provided on a side of the fourth electrically conductive layer facing away from the base substrate;a fifth electrically conductive layer provided on a side of the second semiconductor layer facing away from the base substrate; and a second insulating layer provided between the fifth electrically conductive layer and the first electrically conductive layer; wherein the pixel driver circuit comprises a first reset transistor, the first reset transistor comprising an active layer, a gate, a source, and a drain, the active layer of the first reset transistor being located on the first semiconductor layer; wherein the display substrate further comprises a third through-hole located on the second insulating layer, the first initialization voltage signal line being electrically connected through the third through-hole to the source or the drain of the first reset transistor.

[0025] According to some exemplary embodiments, the pixel driver circuit further comprises a second reset transistor, wherein the second reset transistor comprises an active layer, a gate, a source, and a drain, the active layer of the second reset transistor being located on the second semiconductor layer; and wherein the display substrate further comprises a second initialization voltage signal line provided on the base substrate, the second initialization voltage signal line being used to transmit a second initialization voltage signal, the second initialization voltage signal line being electrically connected to the source or the drain of the second reset transistor; the second initialization voltage signal line being located on the fourth electrically conductive layer, the second initialization voltage signal line extending along the first direction.

[0026] According to some exemplary embodiments, the multiple subpixels further comprise a second subpixel and a third subpixel; wherein the orthogonal projection of the second initialization voltage signal sub-conductor onto the base substrate does not overlap with an orthogonal projection of a first electrode of the second subpixel onto the base substrate, and the orthogonal projection of the second initialization voltage signal sub-conductor onto the base substrate does not overlap with an orthogonal projection of a first electrode of the third subpixel onto the base substrate.

[0027] According to some exemplary embodiments, orthogonal projections of several of the first initialization voltage signal sub-lines onto the base substrate each partially overlap with an orthogonal projection of a first electrode of at least one of the third subpixels onto the base substrate; and / or wherein the orthogonal projection of the first initialization voltage signal sub-line onto the base substrate does not overlap with the orthogonal projection of the first electrode of the first subpixel onto the base substrate; and / or wherein the orthogonal projection of the first initialization voltage signal sub-line onto the base substrate does not overlap with the orthogonal projection of the first electrode of the second subpixel onto the base substrate.

[0028] According to some exemplary embodiments, the first subpixel is a red subpixel, the second subpixel is a blue subpixel, and the third subpixel is a green subpixel.

[0029] In another aspect, a display substrate is provided, comprising: a base substrate; several subpixels provided on the base substrate, wherein the several subpixels are arranged in an array along a first direction and a second direction to form several rows of subpixels and several columns of subpixels, each comprising at least one of the subpixels a light-emitting element; a first initialization voltage signal line provided on the base substrate, wherein the first initialization voltage signal line is used to transmit a first initialization voltage signal; a first electrode layer provided on the base substrate, wherein the light-emitting element of the at least one subpixel comprises a first electrode located on the first electrode layer;and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel comprises a pixel aperture located on the pixel boundary layer, wherein an orthogonal projection of the pixel aperture of the at least one subpixel onto the base substrate coincides with an orthogonal projection of the first electrode of the at least one subpixel onto the base substrate, wherein the at least one subpixel comprises several first subpixels, the several first subpixels being subpixels of a first color; wherein orthogonal projections of several of the second initialization voltage signal sub-lines onto the base substrate each partially overlap with orthogonal projections of the first electrodes of the several first subpixels onto the base substrate;wherein orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a first side and a second side, wherein the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a center, the center being the center of an orthogonal projection of the pixel opening onto the base substrate on a virtual line segment extending along the first direction, the first side and the second side being opposite sides in the first direction relative to the center; wherein the display substrate further comprises: a first electrically conductive layer and a second electrically conductive layer provided on the base substrate; a first insulating layer located between the first electrically conductive layer and the second electrically conductive layer; and multiple through-holes located in the first insulating layer;wherein the second electrically conductive layer lies between the first electrically conductive layer and the first electrode layer, wherein the first initialization voltage signal line lies on the first electrically conductive layer; wherein for at least two first subpixels, orthogonal projections of some of the multiple through holes onto the base substrate lie on a first side of a center of a pixel opening of one of the two first subpixels, and orthogonal projections of some other of the multiple through holes onto the base substrate lie on a second side of a center of a pixel opening of another of the two first subpixels.

[0030] In another aspect, a display device is provided which includes a display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The features and advantages of the present disclosure become clearer by describing in detail exemplary embodiments of the present disclosure with reference to the drawings. Fig. Figure 1 is a schematic top view of a display substrate according to an embodiment of the present disclosure. Fig. Figure 2 is an equivalent circuit diagram of a pixel driver circuit of a display substrate according to some exemplary embodiments of the present disclosure. Fig. Figure 3 is a cross-sectional view of a display substrate along a line AA' in Fig. 1 according to some exemplary embodiments of the present disclosure. Fig. Figure 4 schematically shows a light path of light reflected from a first electrode into a display substrate. Fig. Figure 5A schematically shows a light path of light reflected from a first electrode in a display substrate, the first electrode having a local protrusion. Fig. Figure 5B schematically shows a light path of light reflected from a first electrode in a display substrate, the first electrode having a local depression. Fig. Figure 6 is a partial top view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a first electrode and a signal line arranged under the first electrode. Fig. Figure 7 is a cross-sectional view along a line BB' and a line CC' in Fig. 6, which schematically represents a light path of a light emitted from a first electrode in a display substrate in Fig. 6 reflected light is shown. Fig. Figure 8 is a partial top view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a first electrode, a signal line arranged under the first electrode and a through hole arranged in a planarization layer. Fig. Figure 9 is a cross-sectional view along a line DD' and a line EE' in Fig. 8, which schematically represents a light path of a light emitted from a first electrode in a display substrate in Fig. 8 reflected light is shown. Fig. Figure 10 is a partial top view of a display substrate according to some other exemplary embodiments of the present disclosure, which schematically shows a first electrode and a signal line arranged under the first electrode. Fig. 11 to Fig. Figures 27 are each a partial top view of an indicator substrate according to some exemplary embodiments of the present disclosure, wherein Fig. 11 is a partial top view of a light-shielding layer of the display substrate; Fig. 12 is a partial top view of a first semiconductor layer of the display substrate; Fig. 13 a partial top view of a third electrically conductive layer of the display substrate; Fig. 14 is a partial top view of a fourth electrically conductive layer of the display substrate; Fig. 15 is a partial top view of a second semiconductor layer of the display substrate; Fig. 16 is a partial top view of a fifth electrically conductive layer of the display substrate; Fig. 17 is a partial top view of a first dielectric intermediate layer of the display substrate, which schematically shows several through holes in the first dielectric intermediate layer; Fig. 18 is a partial top view of a second dielectric intermediate layer of the display substrate, which schematically shows several through holes in the second dielectric intermediate layer; Fig. 19 is a partial top view of a first electrically conductive layer of the display substrate; Fig. 20 is a partial top view of the display substrate, which schematically shows a superposition of the light-shielding layer to the first electrically conductive layer; Fig. 21 is a partial top view of a passivation layer of the display substrate, which schematically shows several through holes in the passivation layer; Fig. 22 is a partial top view of a first planarization layer of the display substrate, which schematically shows several through holes in the first planarization layer; Fig. 23 is a partial top view of a second electrically conductive layer of the display substrate; Fig. 24 is a partial top view of a second planarization layer of the display substrate, which schematically shows several through holes in the second planarization layer; Fig. 25 is a partial top view of a first electrode layer of the display substrate; Fig. 26 is a partial top view of a pixel boundary layer of the display substrate, which schematically shows several pixel openings in the pixel boundary layer; Fig. 27 is a partial top view of the display substrate, which schematically shows a superposition from the first electrically conductive layer to the pixel boundary layer. Fig. Figure 28 is a schematic cross-sectional view of a display substrate along a line FF' in Fig. 1 according to some exemplary embodiments of the present disclosure, which schematically shows the positions of the individual film layers of the display substrate in the cross-sectional view. Fig. Figure 29 is a partial top view of the display substrate, which schematically shows a superposition of the light shielding layer to the pixel boundary layer. Fig. Figure 30A schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal sub-line according to some other embodiments of the present disclosure. Fig. Figure 30B schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal sub-line according to some further embodiments of the present disclosure. Fig. Figure 30C schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal sub-line according to some other embodiments of the present disclosure. Fig. Figure 30D schematically shows the interconnections of several second capacitive electrodes arranged in the same row according to some other embodiments of the present disclosure. FORMS OF EXECUTION OF THE INVENTION

[0032] To clarify the problem, the technical solutions, and the advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure are described clearly and completely below in conjunction with drawings. Obviously, the described embodiments represent a subset of the embodiments of this disclosure, but not all of them. Starting from the described embodiments of this disclosure, all other embodiments that a person skilled in the art obtains without inventive step fall within the scope of protection of this disclosure.

[0033] It should be noted that the dimensions and relative dimensions of elements in the drawings may be enlarged for clarity and / or illustration. In this way, features such as dimensions, relative dimensions, and overlapping relationships of parts in the drawings can be incorporated as technical features into the description or claims. In the description and the drawings, identical or similar reference numerals indicate identical or similar parts.

[0034] When an element is described as lying "on" another element, "connected" to another element, or "bound" to another element, the element may lie directly on top of, be directly connected to, or be directly bound to the other element, or an intermediate element may be present. However, when an element is described as lying "directly" "on" another element, "directly" "connected" to another element, or "directly" "bound" to another element, there is no intermediate element. Other terms and / or expressions used to describe the relationships between elements should be interpreted similarly, e.g., "between..." versus "directly between...", "adjacent" versus "directly adjacent", or "on" versus "directly on...", etc.Furthermore, the term “connection” can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other or represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one of the groups consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ.The term “and / or” used here includes any combination of one or more of the listed objects and all combinations thereof.

[0035] It should be noted that while the terms "first," "second," etc., may be used here to represent different parts, components, elements, areas, layers, and / or sections, these parts, components, elements, areas, layers, and / or sections should not be restricted by these terms. Rather, these terms are used to distinguish one part, component, element, area, layer, and / or section from another. Thus, for example, a first part, component, element, area, layer, and / or section described below may also be referred to as a second part, component, element, area, layer, and / or section without this deviating from the teaching of the present disclosure.

[0036] To simplify the presentation, terms for spatial relationships, such as "above," "below," "left," "right," etc., can be used here to describe the relationship of one element or feature to another, as shown in the figures. It is understood that these terms for spatial relationships serve to cover not only the orientations described in the figures but also other various orientations of the device in use or operation. For example, if the device is inverted in the figures, an element described as "below" or "underneath" another element or feature is oriented "above" or "on top" of that other element or feature.

[0037] In the present context, the terms "essentially," "about," "approximately," "about," etc., are used as approximations rather than degrees, and they are intended to explain inherent deviations of the measured or calculated value that would be recognized by a person skilled in the art. Taking into account factors such as process variations, measurement problems, and errors related to measuring a particular quantity (namely, limitations of the measuring system), "about" or "approximately," as used here, includes the stated value and means that a particular value, as determined by a person skilled in the art, lies within an acceptable range of deviation. For example, "about" may mean that the value lies within one or more standard deviations or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0038] It should be noted that the expression "same layer" in this text refers to a layered structure formed by creating a film layer to form a specific pattern using the same film formation process, and then structuring the film layer using the same mask through a single patterning process. Depending on the specific pattern, the single patterning process may involve multiple exposure, development, or etching processes, and the specific patterns in the resulting layered structure may be continuous or discontinuous. That is to say, several elements, parts, structures, and / or sections lying on "the same layer" are made of the same material and are formed by the same single patterning process. Most often, the several elements, parts, structures, and / or sections lying on "the same layer" have approximately the same thickness.

[0039] The directional terms "first direction" and "second direction" are used here to describe different arrangement directions along the subpixels, e.g., a longitudinal direction and a transverse direction of the arrangement of subpixels, or a row direction and a column direction of the arrangement of subpixels. It is understood that such terms are only exemplary representations and not limitations of the present disclosure.

[0040] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Because the source and drain of the thin-film transistor used here are symmetrical, its source and drain can be interchangeable. In the embodiments of this disclosure, the transistor can comprise a gate, a first pole, and a second pole, wherein the first pole can represent one of the source and drain, and the second pole can represent the other of the source and drain. In the following examples, a P-type thin-film transistor is mainly described as the driver transistor, and other transistors are of the same or a different type as the driver transistor, depending on the circuit design.Similarly, in other embodiments, the driver transistor can also be represented as an N-type thin-film transistor.

[0041] The embodiments of the present disclosure at least provide a display substrate, i.e., the display substrate which comprises: a base substrate; several subpixels provided on the base substrate, wherein the several subpixels are arranged in an array along a first direction and a second direction to form several rows of subpixels and several columns of subpixels, wherein at least one of the subpixels comprises a light-emitting element; a first initialization voltage signal line provided on the base substrate, wherein the first initialization voltage signal line is used to transmit a first initialization voltage signal; a first electrode layer provided on the base substrate, wherein the light-emitting element of the at least one subpixel comprises a first electrode located on the first electrode layer;and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel comprises a pixel aperture located on the pixel boundary layer, wherein an orthogonal projection of the pixel aperture of the at least one subpixel onto the base substrate coincides with an orthogonal projection of the first electrode of this at least one subpixel onto the base substrate, wherein the first initialization voltage signal line comprises a first initialization voltage signal sub-line and a second initialization voltage signal sub-line, wherein a main body section of the first initialization voltage signal sub-line extends along the first direction, and a main body section of the second initialization voltage signal sub-line extends along the second direction;wherein the at least one subpixel comprises several first subpixels, the several first subpixels being subpixels of a first color; wherein orthogonal projections of several of the second initialization voltage signal sub-lines onto the base substrate each partially overlap with orthogonal projections of the first electrodes of the several first subpixels onto the base substrate;wherein orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a first side and a second side, wherein the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a center, wherein the center is a center of an orthogonal projection of the pixel opening onto the base substrate on a virtual line segment extending along the first direction, wherein the first side and the second side are opposite sides in the first direction relative to the center;wherein, for at least two first subpixels, an orthogonal projection of one of the second initialization voltage signal sublines onto the base substrate lies on a first side of the center of a pixel opening of one of the two first subpixels, and an orthogonal projection of another of the second initialization voltage signal sublines onto the base substrate lies on a second side of the center of a pixel opening of another of the two first subpixels. In the display substrate provided in the embodiments of the present disclosure, there is almost no color deviation between adjacent subpixels in the row direction, i.e., the display substrate has a good display effect without a color deviation problem.

[0042] Fig. Figure 1 is a schematic top view of a display substrate according to an embodiment of the present disclosure. Referring to Fig. 1 The display substrate according to the embodiment of the present disclosure can comprise a base substrate 10 and a pixel unit PX provided on the base substrate 10.

[0043] The display substrate can comprise a display area AA and a non-display area NA. The display area AA can be an area where pixel units PX are provided for displaying images. Each pixel unit PX is described below. The non-display area NA is an area where no pixel unit PX is provided; that is, it can be an area where no image is displayed. The non-display area NA corresponds to a frame in the final display device, and the width of the frame can be determined based on the width of the non-display area NA.

[0044] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes such as a polygon (e.g., a rectangle) in a closed shape with straight edges, a circle, an ellipse, etc., with curved edges, and a semicircle, a semi-ellipse, etc., with both straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as an area in a quadrilateral shape with straight edges. It is understood that this is only an exemplary embodiment of the present disclosure and not a limitation of the present disclosure.

[0045] The non-display area NA can be provided on at least one side of the display area AA. In the embodiment of the present disclosure, the non-display area NA can surround an outer circumference of the display area AA. In the embodiment of the present disclosure, the non-display area NA can comprise a transverse section extending in a first direction X and a longitudinal section extending in a second direction Y.

[0046] The pixel unit PX is located in display area AA. The pixel unit PX is the smallest unit for displaying images, and multiple pixel units may be used. For example, the pixel unit PX may include a light-emitting element that emits white light and / or colored light.

[0047] Several pixel units PX can be provided to be arranged in a matrix form along rows extending in the first direction X and columns extending in the second direction Y. However, the embodiment of the present disclosure does not specifically restrict the arrangement of the pixel units PX, and the pixel units PX can be arranged in various forms. For example, the pixel units PX can be arranged such that a direction inclined relative to the first direction X and the second direction Y is a column direction, and a direction intersecting the column direction is a row direction.

[0048] This means that multiple pixel units PX are arranged along the first direction X and the second direction Y in an array to form multiple rows of pixel units and multiple columns of pixel units.

[0049] A pixel unit PX can contain multiple subpixels. For example, a pixel unit PX can contain three subpixels: a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. For example, the first subpixel SP1 can be a red subpixel, the second subpixel SP2 can be a blue subpixel, and the third subpixel SP3 can be a green subpixel.

[0050] It should be noted that in the embodiments of the present disclosure, the number of subpixels contained in a pixel unit is not specifically defined and is not limited to 3, as described above.

[0051] In the Fig. In the exemplary embodiment shown in Figure 1, a scanning control signal line GL and a data line DL are schematically represented. That is, the display substrate can further comprise: multiple scanning control signal lines GL and multiple data lines DL provided on the base substrate, wherein the multiple scanning control signal lines GL each supply scanning control signals to multiple rows of pixel units, and the multiple data lines DL each supply data signals to multiple columns of pixel units. The scanning control signal lines GL extend along the first direction X, and the multiple scanning control signal lines GL are spaced apart along the second direction Y. The data lines DL extend along the second direction Y, and the multiple data lines DL are spaced apart along the first direction X.

[0052] For example, the sampling control signal line GL can represent cross-wiring, and the data line DL can represent longitudinal wiring. It is understood that cross-wiring can also include other types of wiring or wiring for delivering other signals, and longitudinal wiring can also include other types of wiring or wiring for delivering other signals.

[0053] Each subpixel can comprise a light-emitting element and a pixel driver circuit for controlling the light-emitting element. In an OLED display substrate or display panel, for example, the light-emitting element of the subpixel can comprise an anode, a light-emitting material layer, and a cathode stacked together. The anodes of the light-emitting elements of the respective subpixels are spaced apart in a matrix configuration along the rows extending in the first direction X and the columns extending in the first direction Y.

[0054] In the following, a 7T1C (namely seven transistors and one capacitor) pixel driver circuit serves as an example to describe the structure of the pixel driver circuit in detail. However, the embodiments of this disclosure are not limited to the 7T1C pixel driver circuit, and other known structures of pixel driver circuits can be applied to the embodiments of this disclosure without conflict. It should be noted that in the embodiments of this disclosure, the individual pixel driver circuit, in addition to the one described in Fig. The 7T1C structure shown in Figure 2 can also be a structure with a different number of transistors, such as an 8T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments shown in the present disclosure are not limited to these.

[0055] Fig. Figure 2 is an equivalent circuit diagram of a pixel driver circuit of a display substrate according to some exemplary embodiments of the present disclosure. The pixel driver circuit is used to control a light-emitting element, e.g., an organic light-emitting diode (namely, an OLED). Referring to Fig. 2. The pixel driver circuit can comprise a second reset transistor T1, a compensation transistor T2, a driver transistor T3, a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T7, and a storage capacitor Cst. The display substrate further comprises a first sampling control signal line GL1 (corresponding to a first sampling control signal PGate in Fig. 2), a second sampling control signal line GL2 (corresponding to a second sampling control signal NGate in Fig. 2), a first reset control signal line PRT1 (corresponding to a first reset control signal RST2 in Fig. 2), a second reset control signal line PRT2 (corresponding to a second reset control signal NReset in Fig. 2) a light emission control signal line EML (corresponding to a light emission control signal EM in Fig. 2), a first initialization voltage signal line VIL1 (corresponding to a first initialization voltage signal Vinit1 in Fig. 2), a second initialization voltage signal line VIL2 (corresponding to a second initialization voltage signal Vinit2 in Fig. 2), a data line DL (corresponding to a data signal Data in Fig. 2), a first voltage signal line VDL (corresponding to a first voltage signal ELVDD in Fig. 2) and a second voltage signal line VSL (corresponding to a second voltage signal ELVSS in Fig. 2).

[0056] Referring further to Fig. 2. The first pole (e.g., the source S1) of the second reset transistor T1 is electrically connected to the second initialization voltage signal line VIL2; the second pole (e.g., the drain D1) of the second reset transistor T1 is electrically connected to the gate of the driver transistor T3, namely node N1; and the gate G1 of the second reset transistor T1 is electrically connected to the second reset control signal line PRT2, and under the control of the second reset control signal line PRT2, the second initialization voltage signal Vinit2, which is transmitted from the second initialization voltage signal line VIL2, is selectively written to node N1.

[0057] The first pole (e.g., the source S2) of the compensation transistor T2 is electrically connected to the first pole (e.g., the drain D3) of the driver transistor T3, namely a node N3; the second pole (e.g., the drain D2) of the compensation transistor T2 is electrically connected to the gate G1 of the driver transistor T3, namely a node N1; and the gate G2 of the compensation transistor T2 is electrically connected to the second sampling control signal line GL2 to receive the compensation control signal.

[0058] The first pole (e.g., the drain D3) of the driver transistor T3 is electrically connected to the first pole (e.g., the source S2) of the compensation transistor T2, namely node N3; the second pole (e.g., the source S3) of the driver transistor T3 is electrically connected to the second pole (e.g., the drain D5) of the first light emission control transistor T5, namely node N2; and the gate G3 of the driver transistor T3 is electrically connected to node N1.

[0059] The first terminal (e.g., source S4) of the data write transistor T4 is electrically connected to the second terminal (e.g., source S3) of the driver transistor T3, namely node N2; the second terminal (e.g., drain D4) of the data write transistor T4 is electrically connected to the data line DL to receive the data signal, and the gate G4 of the data write transistor T4 is electrically connected to the first sampling control signal line GL1 to receive the first sampling control signal. Under the control of the first sampling control signal, the data signal is selectively written to node N2.

[0060] The first pole (e.g., the source S5) of the first light emission control transistor T5 is electrically connected to the first voltage signal line VDL to receive the first voltage signal ELVDD; the second pole (e.g., the drain D5) of the first light emission control transistor T5 is electrically connected to the second pole (e.g., the source S3) of the driver transistor T3, namely a node N2; and the gate G5 of the first light emission control transistor T5 is electrically connected to the light emission control signal line EML to receive the light emission control signal EM.

[0061] The first pole (e.g., the source S6) of the second light emission control transistor T6 is electrically connected to the first pole (e.g., the drain D3) of the driver transistor T3, namely a node N3; the second pole (e.g., the drain D6) of the second light emission control transistor T6 is electrically connected to the first electrode (e.g., the anode) of the light-emitting element OLED, namely a node N4; and the gate G6 of the second light emission control transistor T6 is electrically connected to the light emission control signal line EML to receive the light emission control signal EM.

[0062] The first pole (e.g., the source S7) of the first reset transistor T7 is electrically connected to the first initialization voltage signal line VIL1 to receive the first initialization voltage signal Vinit1; the second pole (e.g., the drain D7) of the first reset transistor T7 is electrically connected to the first electrode of the light-emitting element OLED, namely node N4; and the gate G7 of the first reset transistor T7 is electrically connected to the first reset control signal line PRT1 to receive the first reset control signal.

[0063] One end of the storage capacitor Cst (hereinafter referred to as the first capacitive electrode) Cst1 is electrically connected to the gate G3 of the driver transistor T3 (namely, node N1), and another end of the storage capacitor Cst (hereinafter referred to as the second capacitive electrode) Cst2 is electrically connected to the first voltage signal line VDL. The second electrode (e.g., the cathode) of the light-emitting element OLED is electrically connected to the second voltage signal line VSL to receive the second voltage signal ELVSS. Accordingly, the light-emitting element OLED receives a driver current Id from the driver transistor T3 to emit light to display the images.

[0064] The first voltage signal line VDL and the second voltage signal line VSL described above can, for example, be signal lines for transmitting the voltage signals ELVDD and ELVSS respectively, which can be connected to the voltage source to output constant voltage signals, e.g. positive voltage signals and negative voltage signals.

[0065] It should be noted that transistors can be divided into N-type and P-type transistors based on their different semiconductor properties. When used as a switching transistor, an N-type switching transistor is controlled by a high-level switching signal to turn on and a low-level switching signal to turn off. A P-type switching transistor is controlled by a low-level switching signal to turn on and a high-level switching signal to turn off.

[0066] In the embodiment of the present disclosure, the pixel driver circuit can use an LTPO circuit, i.e., the LTPO circuit is fabricated using low-temperature polysilicon (LTPS) technology and indium gallium zinc oxide (IGZO), and the low-temperature polysilicon thin-film transistor (LTPS) uses polysilicon deposition to form an active layer. LTPS has higher electron mobility and a higher response rate, and offers the advantages of high brightness, high resolution, and low power consumption, among others. The oxide thin-film transistor (oxide TFT), for example, uses an oxide semiconductor as the active layer of the TFT, e.g., indium gallium zinc oxide (IGZO). The oxide semiconductor has high electron mobility and good turn-off characteristics.Compared to LTPS, the manufacturing process for oxide semiconductors is simpler and more compatible with the manufacturing process for amorphous silicon. Obviously, oxide thin-film transistors can also use other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO), etc. By using oxide thin-film transistors, the transistor's dimensions can be effectively reduced and leakage current prevented, making the pixel circuit suitable for low-frequency driving and also increasing the resolution of the display substrate.

[0067] In some exemplary embodiments of the present disclosure, the exemplary 7T1C circuit includes seven thin-film transistors (T1-T8), wherein T1 and T2 are N-type thin-film transistors (NMOS) using oxide thin-film transistors, and the remaining T8 are P-type thin-film transistors (PMOS) using low-temperature polysilicon thin-film transistors. Accordingly, a reset control signal applied to the gate of transistor T1 is referred to as NReset, a sampling control signal applied to the gate of transistor T2 is referred to as NGate, a sampling control signal applied to the gate of transistor T4 is referred to as PGate, and a reset control signal applied to the gate of transistor T7 is referred to as Preset (namely, RST2).

[0068] It should be noted that in the above specification, nodes N1, N2, N3 and N4 do not represent actual existing parts, but rather the meeting points of the connections of the respective circuits in the circuit diagram.

[0069] It should also be noted that in the embodiments of this disclosure, a valid signal (level) is a signal (level) for switching on the corresponding switching element, and an invalid signal (level) is a signal (level) for switching off the corresponding switching element. This is also interpreted in the same way in other embodiments of this disclosure. The valid level and the invalid level only mean that the level of the signal has two state variables and do not mean that the valid level or the invalid level has a specific value in the full text.

[0070] Fig. Figure 3 is a cross-sectional view of a display substrate along a line AA' in Fig. 1 according to some exemplary embodiments of the present disclosure. Referring to Fig. 3. The display substrate can comprise: a base substrate 10; a driver circuit layer 101 provided on the base substrate 10; and a light-emitting element layer 102 provided on a side of the driver circuit layer 101 facing away from the base substrate 10. For example, individual elements, parts, or patterns of the pixel driver circuit can be located on the driver circuit layer 101. The individual elements, parts, or patterns of the pixel driver circuit can include: an active layer, a gate, a source, and a drain of individual thin-film transistors of the pixel driver circuit, individual signal lines for supplying the signal to the pixel driver circuit, and the like. Individual elements, parts, or patterns of the light-emitting element can be located on the light-emitting element layer 102. The individual elements, parts, or patterns of the light-emitting element can be a first electrode (e.g.,an anode), a light-emitting layer and a second electrode (e.g. a cathode) etc. of an organic light-emitting diode.

[0071] Referring further to Fig. 3. The display substrate can further comprise several insulating layers located between the driver circuit layer 101 and the light-emitting element layer 102, wherein the multiple insulating layers can, for example, comprise first planarization layers PLN1 and second planarization layers PLN2. For example, the second planarization layer PLN2 can be located on a side of the first planarization layer PLN1 facing away from the base substrate 10. The layer on which the first electrode is located (namely, the first electrode layer 6) can be located on the side of the second planarization layer PLN2 facing away from the base substrate 10. For example, the first electrode can be located directly on a surface of the second planarization layer PLN2 facing away from the base substrate 10.

[0072] Fig. Figure 4 schematically shows a light path of light reflected from a first electrode in a display substrate. The OLED display typically adopts a top-emission mode, meaning that the first electrode (e.g., the anode) of the light-emitting element is a film layer with a high reflectance, and part of the light emitted from the light-emitting layer of the light-emitting element radiates directly, while another part radiates after reflection from the first electrode 61, as shown in Figure 61. Fig. 4 shown. Theoretically, after planarizing the first planarization layer PLN1 and the second planarization layer PLN2, the surface facing away from the base substrate 10 (namely the upper surface in Fig. 4) the second planarization layer PLN2 has a high degree of flatness, as in Fig. 4 shown, and is essentially a horizontal plane. In this way, the first electrode, which is formed on the surface of the second planarization layer PLN2 facing away from the base substrate 10, has a high degree of flatness. In this case, as shown in Fig. Figure 4 shows that the reflection light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are essentially the same. For example, for the left subpixel in Fig. 4. The light beam RL1 falls on a position of the first electrode 61, and after reflection from the first electrode 61, it emits as a light beam RL1'; for the right subpixel in Fig. 4. The light beam RL2 strikes the corresponding position of the first electrode 61, and after reflection from the first electrode 61, it emits as the light beam RL2'. Since the first electrode has a high flatness, the reflection light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are essentially the same, and the symmetry of the two relative to the midline between the two subpixels is high; for example, the emitted light beams RL1' and RL2' are in Fig. 4. Essentially symmetrical. Thus, there is almost no color deviation between neighboring subpixels, meaning the display substrate has a good display effect without color deviation problems.

[0073] However, the inventor discovered during his research that several elements, parts, patterns, through holes, or grooves are present below the first electrode of the light-emitting element, located in the driver circuit layer 101, and that during the manufacturing of the display substrate, due to the morphology preservation properties of the machining process, these elements, parts, patterns, through holes, or grooves located in the driver circuit layer 101 can affect the flatness of the upper surfaces of the first planarization layer PLN1 and the second planarization layer PLN2, and thus the flatness of the first electrode 61. For example, Fig. 5A schematically represents a light path of light reflected from a first electrode in a display substrate, wherein the first electrode has a local protrusion; Fig. Figure 5B schematically shows a light path of light reflected from a first electrode in a display substrate, the first electrode having a local depression.

[0074] Referring to Fig. 5A, a signal line SL is present at the first position under the first electrode of the light-emitting element. The signal line SL is a pattern with a specific thickness, and its presence causes the upper surfaces of the first planarization layer PLN1 and the second planarization layer PLN2 to protrude locally at the first position, resulting in a local protrusion of the first electrode 61 at the first position P1. In this case, as in Fig. Figure 5A shows that the reflection light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are unequal. For example, for the left subpixel in Fig. 5A The light beam RL1 falls on a position of the first electrode 61, and after reflection from the first electrode 61, it emits as a light beam RL1'; for the right subpixel in Fig. At position 5A, the light beam RL2 strikes the corresponding position of the first electrode 61, and after reflection from the first electrode 61, it emits as the light beam RL2'. Since the first electrode has a local protrusion, the reflected light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are unequal, and the two are asymmetrical relative to the midline between the two subpixels; for example, the emitted light beams RL1' and RL2' are in Fig. 5A is asymmetrical. Therefore, there is a color deviation between adjacent subpixels.

[0075] Referring to Fig. In Figure 5B, as a further example, a through-hole or groove VH is present at the second position beneath the first electrode of the light-emitting element. The through-hole or groove is a pattern of material with a specific remote thickness, and the presence of this through-hole or groove causes the upper surfaces of the first planarization layer PLN1 and the second planarization layer PLN2 at the second position to be locally recessed, resulting in a local depression of the first electrode 61 at the second position. In this case, as in Fig. Figure 5B shows that the reflection light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are unequal. For example, for the left subpixel in Fig. 5B, the light beam RL1 strikes a position of the first electrode 61, and after reflection from the first electrode 61, it emits as the light beam RL1'; for the right subpixel in Fig. In 5B, the light beam RL2 strikes the corresponding position of the first electrode 61, and after reflection from the first electrode 61, it emits as the light beam RL2'. Since the first electrode has a local depression, the reflected light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels are unequal, and the two are asymmetrical relative to the midline between the two subpixels; for example, the emitted light beams RL1' and RL2' are in Fig. 5B is asymmetrical. Therefore, there is a color deviation between adjacent subpixels.

[0076] In the above case, the positions of the multiple elements, parts, patterns, through-holes, or slots are configured in the embodiments of the present disclosure, which are located in the driver circuit layer 101 below the first electrode of the light-emitting element. For example, for two subpixels of the same color that are arranged in the same row and adjacent to each other, the multiple elements, parts, patterns, through-holes, or slots located in the driver circuit layer 101 below the first electrode of the light-emitting element are each provided on opposite sides of the first electrodes or pixel openings of the corresponding subpixels, so that the first electrodes of the light-emitting elements of the adjacent subpixels can still be approximately symmetrical with respect to the center line between two subpixels.In this way, the reflected light paths of the first electrodes of the light-emitting elements of the two adjacent subpixels can still remain essentially the same, and the symmetry of the two is high relative to the midline between the two subpixels. Thus, there is almost no color deviation between adjacent subpixels, meaning the display substrate has a good display effect without color deviation problems.

[0077] Fig. Figure 6 is a partial top view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a first electrode and a signal line arranged under the first electrode. Fig. Figure 7 is a cross-sectional view along a line BB' and a line CC' in Fig. 6, which schematically represents a light path of a light emitted from a first electrode in a display substrate in Fig. 6 reflected light shows. Referring to Fig. 6 and Fig. 7. The display substrate can comprise: a base substrate 10; several subpixels SP1, SP2, SP3 provided on the base substrate 10, wherein the several subpixels are arranged in an array along a first direction X and a second direction Y to form several rows of subpixels and several columns of subpixels; a first initialization voltage signal line VIL1 provided on the base substrate 10, wherein the first initialization voltage signal line VIL1 is used to transmit a first initialization voltage signal Vinit1; a first electrode layer 6 provided on the base substrate 10, wherein the light-emitting element of the at least one subpixel comprises a first electrode 61 located on the first electrode layer 6;and a pixel boundary layer PDL provided on the base substrate 10, wherein the at least one subpixel comprises a pixel aperture 20 located on the pixel boundary layer PDL, wherein an orthogonal projection of the pixel aperture 20 of the at least one subpixel onto the base substrate 10 coincides with an orthogonal projection of the first electrode 61 of the at least one subpixel onto the base substrate 10.

[0078] For example, the display substrate can comprise multiple pixel units provided on the base substrate 10 and arranged in an array, and each pixel unit can comprise multiple subpixels. For example, the multiple subpixels can comprise a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. In the Fig. In the embodiment shown in Figure 6, a pixel unit can comprise four subpixels. For example, a pixel unit can use an RGBG arrangement. By way of example, the first subpixel SP1 can be a red subpixel, the second subpixel SP2 can be a blue subpixel, and the third subpixel SP3 can be a green subpixel. A pixel unit can comprise a first subpixel SP1, a second subpixel SP2, and two third subpixels SP3. It should be noted that the embodiments of the present disclosure do not refer to the one in Figure 6. Fig. 6 pixel arrangement shown are limited, and the arrangement of the subpixels in the pixel unit can refer to conventional pixel arrangements, such as GGRB, RGB and other arrangements, and the embodiments of the present disclosure are not specifically limited to them.

[0079] It should also be noted that in the Fig. In the embodiment shown in Figure 6, the pixel opening 20 has the shape of a rounded rectangle, and in the embodiments of the present disclosure, the pixel opening is not limited to this shape and can be chosen in any suitable shape, such as a circular shape, an elliptical shape, a rhombus-shaped shape, a square shape, a pentagonal shape, a hexagonal shape, an octagonal shape and the like.

[0080] In the embodiment of the present disclosure, the first initialization voltage signal line VIL1 comprises a first initialization voltage signal sub-line VIL11 and a second initialization voltage signal sub-line VIL12, wherein a main body section of the first initialization voltage signal sub-line VIL11 extends along the first direction X, and a main body section of the second initialization voltage signal sub-line VIL12 extends along the second direction Y.

[0081] It should be noted that in this text the expression “main body section of the first initialization voltage signal sub-line” can represent a section that is more than 50% of the total length of the first initialization voltage signal sub-line, and the expression “main body section of the second initialization voltage signal sub-line” can similarly represent a section that is more than 50% of the total length of the second initialization voltage signal sub-line.

[0082] For example, as in Fig. Figure 6 shows that the first initialization voltage signal line VIL1 comprises several first initialization voltage signal sub-lines VIL11 and several second initialization voltage signal sub-lines VIL12, wherein the several first initialization voltage signal sub-lines VIL11 and the several second initialization voltage signal sub-lines VIL12 are crossed and connected, so that the first initialization voltage signal lines VIL1 form a net structure.

[0083] Referring to Fig. 6 The orthogonal projections of the multiple second initialization voltage signal sublines VIL12 onto the base substrate 10 each partially overlap with the orthogonal projections of the first electrodes 61 of the multiple first subpixels SP1 onto the base substrate 10. For example, the orthogonal projections of the multiple second initialization voltage signal sublines VIL12 onto the base substrate 10 are line segments that extend substantially along the second direction Y and pass through a boundary of the orthogonal projection of the first electrode 61 of the at least one first subpixel SP1 onto the base substrate 10.

[0084] The first electrodes 61 of the multiple first subpixels SP1 each have a first side and a second side in the first direction X. For example, the first side can be one of the left and one of the right sides, and the second side can be the other of the left and right sides. That is, the first side and the second side can be opposite sides of the first electrode 61 in the first direction X. Similarly, the pixel openings 20 of the multiple first subpixels SP1 each have a first side and a second side in the first direction X. For example, the first side can be one of the left and one of the right sides, and the second side can be the other of the left and right sides. That is, the first side and the second side can be opposite sides of the pixel opening 20 in the first direction X.

[0085] Referring to Fig. 6 passes through a boundary section of the first side of the orthogonal projection of the first electrode 61 of one of the two first subpixels SP1, which are arranged in the same row and adjacent, for any two first subpixels SP1 that are arranged in the same row and adjacent, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the second side of the orthogonal projection of the first electrode 61 of the other of the two first subpixels SP1 onto the base substrate 10.

[0086] Referring further to Fig. 6 For any two first subpixels SP1 that are arranged in the same row and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a first side of the orthogonal projection of the pixel opening 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a second side of the orthogonal projection of the pixel opening 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0087] In the Fig. In the embodiment shown in Figure 6, for example, the orthogonal projection of a second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel opening 20 of the first first sub-pixel SP1 onto the base substrate 10 for the 1st and the 2nd first sub-pixel SP1, which are counted in the second row from the left; and the orthogonal projection of another second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel opening 20 of the second first sub-pixel SP1 onto the base substrate 10;For the 2nd and 3rd first subpixel SP1, which are counted in the second row from the left, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel aperture 20 of the 2nd first subpixel SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel aperture 20 of the 3rd first subpixel SP1 onto the base substrate 10.

[0088] Referring to Fig. 6 and Fig. In the embodiments described in this disclosure, for any two first subpixels arranged in the same row and adjacent to each other, the second initialization voltage signal sub-lines VIL12, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels, so that the first electrodes 61 of the light-emitting elements of the row-adjacent subpixels can still be approximately symmetrical with respect to the midline AXL between two subpixels. In this way, the reflected light paths of the first electrodes 61 of the light-emitting elements of the two row-adjacent subpixels can still remain substantially the same, and the symmetry of the two is high with respect to the midline AXL between two subpixels.Thus, there is almost no color deviation between the subpixels adjacent in the row direction, i.e., the display substrate has a good display effect without a color deviation problem.

[0089] Furthermore, in the embodiments of the present disclosure, for any two first subpixels SP1, which are arranged in the same row and adjacent to each other, orthogonal projections of two of the second initialization voltage signal sublines VIL12 onto the base substrate 10, which partially overlap with first electrodes 61 of the two first subpixels, are symmetrical relative to a first axis of symmetry AX1, wherein the first axis of symmetry AX1 is defined by the midpoint of a connecting line between centers (e.g., center O1, center O2 in Fig. 6) of the pixel openings 20 of the first two subpixels runs and extends along the second direction Y.

[0090] Unless explicitly stated otherwise, the term "center of pixel opening" in this text represents the geometric center or the center of the orthogonal projection of that pixel opening onto the base substrate. For example, if the pixel opening is a rectangle or a rounded rectangle, the center of the pixel opening is the intersection of two diagonals of the rectangle; if the pixel opening is a circle, the center of the pixel opening is the center of the circle; and if the pixel opening is an ellipse, the center of the pixel opening is the center of the ellipse, namely the intersection of the long and short axes of the ellipse.

[0091] By symmetrically designing the second initialization voltage signal sub-lines VIL12, the symmetry of the reflection light paths of the first electrodes 61 of the light-emitting elements of the two subpixels adjacent in the series direction can be further improved, thereby further improving or even eliminating the problem of color deviation between the subpixels adjacent in the series direction and improving the display effect.

[0092] Referring further to Fig. 6, for any two first subpixels SP1 that are arranged in the same column and adjacent, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the first side of the orthogonal projection of the first electrode 61 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the second side of the orthogonal projection of the first electrode 61 of the other of the two first subpixels SP1 onto the base substrate 10.

[0093] For any two first subpixels SP1 that are arranged in the same column and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a first side of the orthogonal projection of the pixel aperture 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a second side of the orthogonal projection of the pixel aperture 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0094] In the Fig. In the embodiment shown in Figure 6, for example, the orthogonal projection of a second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel opening 20 of the first first sub-pixel SP1 onto the base substrate 10 for the 1st and the 2nd first sub-pixel SP1, which are counted in the second column from the top; and the orthogonal projection of another second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel opening 20 of the 2nd first sub-pixel SP1 onto the base substrate 10;For the 2nd and 3rd first subpixel SP1, which are counted in the second column from the top, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel aperture 20 of the 2nd first subpixel SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel aperture 20 of the 3rd first subpixel SP1 onto the base substrate 10.

[0095] In the embodiments described in the present disclosure, for any two first subpixels arranged in the same column and adjacent to each other, the second initialization voltage signal sub-lines VIL12, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels. Thus, there is almost no color deviation between subpixels adjacent in the column direction; that is, the display substrate has a good display effect without any color deviation problems.

[0096] Fig. Figure 8 is a partial top view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a first electrode, a signal line arranged under the first electrode and a through hole arranged in a planarization layer. Fig. Figure 9 is a cross-sectional view along a line DD' and a line EE' in Fig. 8, which schematically represents a light path of a light emitted from a first electrode in a display substrate in Fig. 8 reflected light shows. It should be noted that the differences between the in Fig. The embodiment shown in Figure 8 and the various embodiments described above are mainly described, and reference can be made to the above description for their similarities, which are not repeated here. It is understood that the various embodiments of this disclosure may be combined arbitrarily without conflict.

[0097] Referring to Fig. 8 and Fig. 9. The display substrate can further comprise: a first insulating layer provided between the base substrate 10 and the layer on which the first electrode 61 is located (namely, the first electrode layer 6). For example, the first insulating layer can comprise at least one planarization layer, e.g., a planarization layer PLN1. The display substrate can further comprise several through-holes located in the first insulating layer. The several through-holes can be located in the at least one planarization layer, for example, or can extend through the at least one planarization layer. For example, the several through-holes can comprise at least one first through-hole VH11 and at least one second through-hole VH12.

[0098] Referring further to Fig. For any two first subpixels SP1 that are arranged in the same row and adjacent to each other, orthogonal projections of some of the multiple through holes onto the base substrate 10 lie on the first side of the orthogonal projection of the pixel opening 20 of one of the two first subpixels SP1 onto the base substrate 10, and orthogonal projections of some other of the multiple through holes onto the base substrate 10 lie on the second side of the orthogonal projection of the pixel opening 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0099] In the embodiment of the present disclosure, the number of some of the multiple through-holes located on the first side of the pixel opening 20 of a first subpixel can be equal to the number of some other multiple through-holes located on the second side of the pixel opening 20 of another first subpixel. In the embodiment described in Fig. In the embodiment shown in Figure 8, for example, for any two first subpixels SP1 that are arranged in the same row and adjacent to each other, the orthogonal projections of three through holes (e.g., two first through holes VH11 and one second through hole VH12) in the first insulating layer IL1 onto the base substrate 10 lie on the first side of the orthogonal projection of the pixel opening 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projections of other three through holes (e.g., two first through holes VH11 and one second through hole VH12) in the first insulating layer IL1 onto the base substrate 10 lie on the second side of the orthogonal projection of the pixel opening 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0100] In the Fig. In the embodiment shown in Figure 8, for example, the orthogonal projections of a second through-hole VH12 and two first through-holes VH11 (three through-holes enclosed by a dashed box I) onto the base substrate 10 for the 1st and 2nd first subpixels SP1, which are counted in the second row from the left, are located to the right of the orthogonal projection of the pixel opening 20 of the 1st first subpixel SP1 onto the base substrate 10, and the orthogonal projections of two first through-holes VH11 and a second through-hole VH12 (three through-holes enclosed by a dashed box II) onto the base substrate 10 are located to the left of the orthogonal projection of the pixel opening 20 of the 2nd first subpixel SP1 onto the base substrate 10.

[0101] Referring to Fig. 8 and Fig. In the embodiments described in this disclosure, for any two first subpixels arranged in the same row and adjacent to each other, the through-holes in the first insulating layer, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels, so that the first electrodes 61 of the light-emitting elements of the row-adjacent subpixels can still be approximately symmetrical with respect to the midline AXL between two subpixels. In this way, the reflected light paths of the first electrodes 61 of the light-emitting elements of the two row-adjacent subpixels can still remain substantially the same, and the symmetry of the two is high with respect to the midline AXL between two subpixels.Thus, there is almost no color deviation between the subpixels adjacent in the row direction, i.e., the display substrate has a good display effect without a color deviation problem.

[0102] Furthermore, in the embodiments of the present disclosure, for the two arbitrary first subpixels SP1, which are arranged in the same row and adjacent to each other, the orthogonal projections of some through holes (e.g. a second through hole VH12 and two first through holes VH11) are Fig. 8) and some other through holes (e.g. two first through holes VH11 and a second through hole VH12 in Fig. 8) on the base substrate 10 symmetrically relative to the first axis of symmetry AX1, wherein the first axis of symmetry AX1 passes through the midpoint of the connecting line between the centers of the pixel openings 20 of the first two subpixels and extends along the second direction Y.

[0103] The symmetrical design of the through-holes in the planarization layer below the first electrode allows the symmetry of the reflection light paths of the first electrodes 61 of the light-emitting elements of the two subpixels adjacent in the row direction to be further improved, thereby further improving or even eliminating the problem of color deviation between the subpixels adjacent in the row direction and improving the display effect.

[0104] In the embodiments described in this disclosure, the position of the second initialization voltage signal sub-line VIL12 varies periodically relative to the pixel aperture in each row of the first subpixels SP1. Referring to Fig. 6 and Fig. 8. The position of the second initialization voltage signal subline VIL12 relative to the pixel opening is varied periodically, for example, with a period of four rows of the first subpixels. Specifically, the positions of a second initialization voltage signal subline VIL12, which partially overlaps with the first electrode 61 of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal subline VIL12, which partially overlaps with the first electrode 61 of a first subpixel located in an i+4-th row and a j-th column, are aligned in the second direction Y, where i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1. As, for example, in Fig. Figure 6 shows the positions of a second initialization voltage signal sub-line VIL12, which partially overlaps with the first electrode 61 of the first subpixel SP1 in the first row, and a second initialization voltage signal sub-line VIL12, which partially overlaps with the first electrode 61 of the first subpixel SP1 in the fifth row, aligned in the second direction Y.

[0105] Fig. Figure 10 is a partial top view of a display substrate according to some other exemplary embodiments of the present disclosure, which schematically shows a first electrode and a signal line arranged below the first electrode. Referring to Fig. 10. The position of the second initialization voltage signal subline VIL12 relative to the pixel opening varies periodically with a period of two rows of the first subpixels. Specifically, the positions of a second initialization voltage signal subline VIL12, which partially overlaps with the first electrode 61 of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal subline VIL12, which partially overlaps with the first electrode 61 of a first subpixel located in an i+2-th row and a j-th column, are oriented in the second direction Y, where i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1. As, for example, in Fig. Figure 10 shows the positions of a second initialization voltage signal sub-line VIL12, which partially overlaps with the first electrode 61 of the first subpixel SP1 in the first row, and a second initialization voltage signal sub-line VIL12, which partially overlaps with the first electrode 61 of the first subpixel SP1 in the third row, aligned in the second direction Y.

[0106] In the embodiments of the present disclosure, the relative positions of the second initialization voltage signal sub-lines VIL12 vary periodically in the second direction Y relative to the first electrodes of the subpixels, thereby further improving the symmetry of the first electrodes 61 of the light-emitting elements of the subpixels and also reducing the difficulties in manufacturing the second initialization voltage signal sub-lines.

[0107] Fig. 11 to Fig. Figures 27 are each a partial top view of an indicator substrate according to some exemplary embodiments of the present disclosure, wherein Fig. 11 is a partial top view of a light-shielding layer of the display substrate; Fig. 12 is a partial top view of a first semiconductor layer of the display substrate; Fig. 13 a partial top view of a third electrically conductive layer of the display substrate; Fig. 14 is a partial top view of a fourth electrically conductive layer of the display substrate; Fig. 15 is a partial top view of a second semiconductor layer of the display substrate; Fig. 16 is a partial top view of a fifth electrically conductive layer of the display substrate; Fig. 17 is a partial top view of a first dielectric intermediate layer of the display substrate, which schematically shows several through holes in the first dielectric intermediate layer; Fig. 18 is a partial top view of a second dielectric intermediate layer of the display substrate, which schematically shows several through holes in the second dielectric intermediate layer; Fig. 19 is a partial top view of a first electrically conductive layer of the display substrate; Fig. 20 is a partial top view of the display substrate, which schematically shows a superposition of the light-shielding layer to the first electrically conductive layer; Fig. 21 is a partial top view of a passivation layer of the display substrate, which schematically shows several through holes in the passivation layer; Fig. 22 is a partial top view of a first planarization layer of the display substrate, which schematically shows several through holes in the first planarization layer; Fig. 23 is a partial top view of a second electrically conductive layer of the display substrate; Fig. 24 is a partial top view of a second planarization layer of the display substrate, which schematically shows several through holes in the second planarization layer; Fig. 25 is a partial top view of a first electrode layer of the display substrate; Fig. 26 is a partial top view of a pixel boundary layer of the display substrate, which schematically shows several pixel openings in the pixel boundary layer; Fig. 27 is a partial top view of the display substrate, which schematically shows a superposition from the first electrically conductive layer to the pixel boundary layer. Fig. Figure 28 is a schematic cross-sectional view of a display substrate along a line FF' in Fig. 1 according to some exemplary embodiments of the present disclosure, which schematically shows the positions of the individual film layers of the display substrate in the cross-sectional view. Fig. Figure 29 is a partial top view of the display substrate, which schematically shows a superposition of the light shielding layer to the pixel boundary layer.

[0108] Referring to Fig. 11 to Fig. 29 The display substrate can together comprise: a base substrate 10, a light shielding layer LS provided on the base substrate 10, a first semiconductor layer 7 provided on a side of the light shielding layer LS facing away from the base substrate, a third electrically conductive layer 3 provided on a side of the first semiconductor layer 7 facing away from the base substrate, a fourth electrically conductive layer 4 provided on a side of the third electrically conductive layer 3 facing away from the base substrate, a second semiconductor layer 8 provided on a side of the fourth electrically conductive layer 4 facing away from the base substrate, a fifth electrically conductive layer 5 provided on a side of the second semiconductor layer 8 facing away from the base substrate, a first electrically conductive layer 1 provided on a side of the fifth electrically conductive layer 5 facing away from the base substrate,as well as a second electrically conductive layer 2, which is provided on a side of the first electrically conductive layer 1 facing away from the base substrate.

[0109] For example, the third electrically conductive layer 3, the fourth electrically conductive layer 4, and the fifth electrically conductive layer 5 can be electrically conductive layers made of a gate material, such as Mo. For example, the first electrically conductive layer 1 and the second electrically conductive layer 2 can be electrically conductive layers made of a source-drain material, such as Ti / Al / Ti.

[0110] The semiconductor material that makes up the active layer can include, for example, amorphous silicon, polycrystalline silicon, oxide semiconductors, etc. The oxide semiconductor material can include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), etc.

[0111] In the embodiments described in the present disclosure, at least one insulating layer can be provided between two adjacent electrically conductive layers, wherein the insulating layer can consist of an inorganic material, such as silicon nitride, silicon oxide, or silicon nitride oxide, etc., or the insulating layer can consist of an organic material, such as a resin, etc. The insulating layer can have a single film layer structure or a stacked layer structure with multiple film layers.In the embodiments shown in the figures, the display substrate can, for example, comprise: a first insulating layer IL1 provided between the first electrically conductive layer 1 and the second electrically conductive layer 2; a second insulating layer IL2 provided between the fifth electrically conductive layer 5 and the first electrically conductive layer 1; and a third insulating layer IL3 provided between the second electrically conductive layer 2 and the first electrode layer 6. For example, the first insulating layer IL1 can comprise a passivation layer PVX and a first planarization layer PLN1, the second insulating layer IL2 can comprise a first dielectric intermediate layer ILD1 and a second dielectric intermediate layer ILD2, and the third insulating layer IL3 can comprise a second planarization layer PLN2.

[0112] It is understood that the display substrate may also have several insulating layers. For the structures of the insulating layers, reference can be made to the structures of the insulating layers in existing display substrates, which are not repeated here.

[0113] Fig. Figure 12 shows a first semiconductor layer 7. As in Fig. As shown in Figure 12, the first semiconductor layer 7 can, for example, be used to fabricate the active layer of the aforementioned driver transistor T3, data write transistor T4, first light emission control transistor T5, second light emission control transistor T6, and first reset transistor T7 to form the channel region of the aforementioned transistors. The first semiconductor layer 7 can comprise the pattern of an active region (channel region) and the pattern of a doped region (source-drain region) of the aforementioned transistors of each subpixel, and the pattern of the active region and the pattern of the doped region of the aforementioned transistors in the same pixel driver circuit are provided as a single unit.

[0114] For example, the first semiconductor layer 7 can comprise a single-piece, low-temperature polysilicon layer, and the source and drain regions can be made conductive by doping or the like to achieve electrical connections between the individual structures. For example, the aforementioned source and drain regions can be regions doped with p-type impurities.

[0115] Fig. Figure 11 shows a light-shielding layer LS. The light-shielding layer LS can, for example, consist of a metallic material. An orthogonal projection of the light-shielding layer LS onto the base substrate 10 can overlap at least partially with orthogonal projections of the channel regions of at least some transistors onto the base substrate 10, so that the light-shielding layer LS can prevent interference of external light on the channel regions of the transistors.

[0116] Fig. Figure 13 shows a third electrically conductive layer 3, which lies on a side of the first semiconductor layer 7 facing away from the base substrate. As in Fig. As shown in Figure 13, for example, the first sampling control signal line GL1, the first capacitive electrode Cst1 of the storage capacitor Cst, the light emission control signal line EML, and the first reset control signal line PRT1 can be located in the third electrically conductive layer 3. For example, the third electrically conductive layer 3 can include a gate of the driver transistor T3, the data write transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the first reset transistor T7.

[0117] It should be noted that the single dashed rectangular box in Fig. Figure 12 illustrates the individual overlap section of the first semiconductor layer 7 and the third electrically conductive layer 3, namely a channel region. The active semiconductor layers on both sides of each channel region are made conductive by a process such as ion doping, forming the first and second poles of the transistor. The source and drain of the transistor can be structurally symmetrical, so that the source and drain of the transistor are indistinguishable from each other in their physical structure.In the embodiments of the present disclosure, to distinguish the transistors, one of the poles is directly designated as a first pole and another of the poles as a second pole, with the exception of the gate, which serves as a control pole, so that the first poles and the second poles of all or part of the transistors in the embodiments of the present disclosure are interchangeable as required.

[0118] Referring to Fig. 12, Fig. 13 and Fig. For example, the gate of data write transistor T4 can be an overlap section of the first sampling control signal line GL1 and the first semiconductor layer 7. The gate of the second light emission control transistor T6 can be a first overlap section of the light emission control signal line EML and the first semiconductor layer 7, and the gate of the first light emission control transistor T5 can be a second overlap section of the light emission control signal line EML and the first semiconductor layer 7. The gate of the first reset transistor T7 is an overlap section of the first reset control signal line PRT1 and the first semiconductor layer 7.

[0119] Fig. Figure 14 shows a fourth electrically conductive layer 4, which lies on a side of the third electrically conductive layer 3 facing away from the base substrate. As in Fig. As shown in Figure 14, the second sampling control signal line GL2, the second capacitive electrode Cst2 of the storage capacitor Cst, the second reset control signal line PRT2 and the second initialization voltage signal line VIL2 can, for example, be located in the fourth electrically conductive layer 4.

[0120] Fig. Figure 15 shows a second semiconductor layer 8 located on the side of the fourth electrically conductive layer 4 facing away from the base substrate. As in Fig. As shown in Figure 15, the second semiconductor layer 8, for example, comprises a channel region of the second reset transistor T1 and the compensation transistor T2. For example, if an oxide semiconductor is used for the active layers in the second reset transistor T1 and the compensation transistor T2, because the transistor with the oxide semiconductor has good hysteresis properties and low leakage current, it is possible to use the transistor with the oxide semiconductor instead of the low-temperature polysilicon material in the transistor to form a pixel driver circuit made of low-temperature polysilicon oxide (LTPO), thereby achieving the low leakage current and being advantageous for improving the stability of the gate voltage of the transistor.

[0121] As in Fig. 14, Fig. 15 and Fig. As shown in Figure 20, for example, the gate of the second reset transistor T1 can be an overlap section of the second reset control signal line PRT2 and the second semiconductor layer 8, and the gate of the compensation transistor T2 can be an overlap section of the second sampling control signal line GL2 and the second semiconductor layer 8.

[0122] Fig. Figure 16 shows a fifth electrically conductive layer 5, which lies on a side of the second semiconductor layer 8 facing away from the base substrate. As in Fig. As shown in Figure 16, another second scanning control signal line GL2, and another second reset control signal line PRT2, for example, can be located in the fifth electrically conductive layer 5.

[0123] As in Fig. 12 to Fig. As shown in Figure 20, for example, the other second reset control signal line PRT2 is superimposed on the channel region of the second reset transistor T1, wherein the second reset transistor T1 has an upper gate and a lower gate provided on both sides of the active layer; the other second sampling control signal line GL2 is superimposed on the channel region of the compensation transistor T2, wherein the compensation transistor T2 has an upper gate and a lower gate provided on both sides of the active layer. That is to say, in the embodiments of the present disclosure, the second reset transistor T1 and the compensation transistor T2 can have a dual-gate structure, namely, each comprising an upper gate and a lower gate.

[0124] In the embodiments described in this disclosure, the second reset control signal line PRT2 can comprise a first reset control signal sub-line PRT21 and a second reset control signal sub-line PRT22, wherein the second reset control signal line located in the fourth electrically conductive layer 4 is referred to as a first reset control signal sub-line PRT21, and the second reset control signal line located in the fifth electrically conductive layer 5 is referred to as a second reset control signal sub-line PRT22. The overlapping section of the first reset control signal sub-line PRT21 and the second semiconductor layer 8 forms a lower gate of the second reset transistor T1, and the overlapping section of the second reset control signal sub-line PRT22 and the second semiconductor layer 8 forms an upper gate of the second reset transistor T1.

[0125] The second sampling control signal line GL2 can comprise a first sampling control signal subline GL21 and a second sampling control signal subline GL22, wherein the second sampling control signal line located in the fourth electrically conductive layer 4 is designated as the first sampling control signal subline GL21, and the second sampling control signal line located in the fifth electrically conductive layer 5 is designated as the second sampling control signal subline GL22. The overlapping section of the first sampling control signal subline GL21 and the second semiconductor layer 8 forms a lower gate of the compensation transistor T2, and the overlapping section of the second sampling control signal subline GL22 and the second semiconductor layer 8 forms an upper gate of the compensation transistor T2.

[0126] For example, the second reset transistor T1 and the compensation transistor T2 can be N-type transistors. The driver transistor T3, the data write transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the first reset transistor T7 can be P-type transistors.

[0127] Fig. Figure 19 shows a first electrically conductive layer 1, which lies on a side of the fifth electrically conductive layer 5 facing away from the base substrate. As in Fig. As shown in Figure 19, for example, the first initialization voltage signal line VIL1 can be located in the first electrically conductive layer 1. The display substrate can further comprise several interconnect sections or adapter sections located in the first electrically conductive layer 1. The following describes the multiple interconnect sections or adapter sections located in the first electrically conductive layer 1 in combination with a specific electrical interconnection relationship.

[0128] As in Fig. As shown in Figure 19, the first initialization voltage signal line VIL1 comprises a first initialization voltage signal sub-line VIL11 and a second initialization voltage signal sub-line VIL12, wherein a main body section of the first initialization voltage signal sub-line VIL11 extends along the first direction X, and a main body section of the second initialization voltage signal sub-line VIL12 extends along the second direction Y.

[0129] For example, as in Fig. Figure 19 shows that the first initialization voltage signal line VIL1 comprises several first initialization voltage signal sub-lines VIL11 and several second initialization voltage signal sub-lines VIL12, wherein the several first initialization voltage signal sub-lines VIL11 and the several second initialization voltage signal sub-lines VIL12 are crossed and connected, so that the first initialization voltage signal lines VIL1 form a net structure.

[0130] The first initialization voltage signal subline VIL11 can comprise a first section VIL111, a second section VIL112, and a third section VIL113. The second section VIL112 is located between the first section VIL111 and the third section VIL113, with one end of the second section VIL112 connected to the first section VIL111 and another end of the second section VIL112 connected to the third section VIL113. The first section VIL111 and the third section VIL113 extend along the first direction X, and the second section VIL112 extends along the second direction Y. For example, a first initialization voltage signal subline VIL11 can comprise multiple first sections VIL111, multiple second sections VIL112, and multiple third sections VIL113.The extension length of a first section VIL111 along the first direction X is greater than the extension length of a third section VIL113 along the first direction X.

[0131] The second initialization voltage signal sub-line VIL12 comprises a first section VIL121, a second section VIL122, and a third section VIL123, wherein the second section VIL122 is located between the first section VIL121 and the third section VIL123, with one end of the second section VIL122 connected to the first section VIL121 and another end of the second section VIL122 connected to the third section VIL123. Both the first section VIL121 and the third section VIL123 extend along the second direction Y, and the second section VIL122 extends along a third direction D3, with the third direction D3 intersecting both the first direction X and the second direction Y.

[0132] At least one second initialization voltage signal sub-line VIL12 is located between two adjacent first initialization voltage signal sub-lines VIL11; for example, the multiple second initialization voltage signal sub-lines VIL12 are each located between two adjacent first initialization voltage signal sub-lines VIL11. In the embodiment of the present disclosure, one end of the first section VIL121 of the second initialization voltage signal sub-line VIL12 is connected to the third section VIL113 of the first initialization voltage signal sub-line VIL11, and one end of the third section VIL121 of the second initialization voltage signal sub-line VIL12 is connected to the junction of the first section VIL111 and the second section VIL112 of the first initialization voltage signal sub-line VIL11.

[0133] Referring to Fig. 27 The orthogonal projections of the multiple second initialization voltage signal sublines VIL12 onto the base substrate 10 each partially overlap with the orthogonal projections of the first electrodes 61 of the multiple first subpixels SP1 onto the base substrate 10. For example, the orthogonal projections of the multiple second initialization voltage signal sublines VIL12 onto the base substrate 10 are line segments that extend substantially along the second direction Y and pass through a boundary of the orthogonal projection of the first electrode 61 of the at least one first subpixel SP1 onto the base substrate 10.

[0134] The first electrodes 61 of the multiple first subpixels SP1 each have a first side and a second side in the first direction X. For example, the first side can be one of the left and one of the right sides, and the second side can be the other of the left and right sides. That is, the first side and the second side can be opposite sides of the first electrode 61 in the first direction X. Similarly, the pixel openings 20 of the multiple first subpixels SP1 each have a first side and a second side in the first direction X. For example, the first side can be one of the left and one of the right sides, and the second side can be the other of the left and right sides. That is, the first side and the second side can be opposite sides of the pixel opening 20 in the first direction X.

[0135] Referring to Fig. 27 For any two first subpixels SP1 that are arranged in the same row and adjacent, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the first side of the orthogonal projection of the first electrode 61 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the second side of the orthogonal projection of the first electrode 61 of the other of the two first subpixels SP1 onto the base substrate 10.

[0136] Referring further to Fig. 27 For any two first subpixels SP1 that are arranged in the same row and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a first side of the orthogonal projection of the pixel aperture 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a second side of the orthogonal projection of the pixel aperture 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0137] In the Fig. In the embodiment shown in Figure 27, for example, the orthogonal projection of a second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel opening 20 of the first first sub-pixel SP1 onto the base substrate 10 for the 1st and the 2nd first sub-pixel SP1, which are counted in the third row from the left, and the orthogonal projection of another second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel opening 20 of the second first sub-pixel SP1 onto the base substrate 10.

[0138] Referring to Fig. 27 and Fig. In the embodiments described in this disclosure, for any two first subpixels arranged in the same row and adjacent to each other, the second initialization voltage signal sub-lines VIL12, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels, so that the first electrodes 61 of the light-emitting elements of the row-adjacent subpixels can still be approximately symmetrical with respect to the midline AXL between two subpixels. In this way, the reflected light paths of the first electrodes 61 of the light-emitting elements of the two row-adjacent subpixels can still remain substantially the same, and the symmetry of the two is high with respect to the midline AXL between two subpixels.Thus, there is almost no color deviation between the subpixels adjacent in the row direction, i.e., the display substrate has a good display effect without a color deviation problem.

[0139] Furthermore, in the embodiments of the present disclosure, for any two first subpixels SP1, which are arranged in the same row and adjacent to each other, orthogonal projections of two of the second initialization voltage signal sublines VIL12 onto the base substrate 10, which partially overlap with the first electrodes 61 of the two first subpixels, are symmetrical relative to a first axis of symmetry AX1, wherein the first axis of symmetry AX1 passes through a midpoint of a connecting line between the centers of the pixel openings 20 of the two first subpixels and extends along the second direction Y.

[0140] By symmetrically designing the second initialization voltage signal sub-lines VIL12, the symmetry of the reflection light paths of the first electrodes 61 of the light-emitting elements of the two subpixels adjacent in the series direction can be further improved, thereby further improving or even eliminating the problem of color deviation between the subpixels adjacent in the series direction and improving the display effect.

[0141] Referring further to Fig. 27 For any two first subpixels SP1 that are arranged in the same column and adjacent, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the first side of the orthogonal projection of the first electrode 61 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the second side of the orthogonal projection of the first electrode 61 of the other of the two first subpixels SP1 onto the base substrate 10.

[0142] For any two first subpixels SP1 that are arranged in the same column and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a first side of the orthogonal projection of the pixel aperture 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a second side of the orthogonal projection of the pixel aperture 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0143] In the Fig. In the embodiment shown in Figure 27, for example, the orthogonal projection of a second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the left of the orthogonal projection of the pixel opening 20 of the first first sub-pixel SP1 onto the base substrate 10 for the 1st and the 2nd first sub-pixel SP1, which are counted in the third column from the top, and the orthogonal projection of another second initialization voltage signal sub-line VIL12 onto the base substrate 10 lies to the right of the orthogonal projection of the pixel opening 20 of the 2nd first sub-pixel SP1 onto the base substrate 10.

[0144] In the embodiments described in the present disclosure, for any two first subpixels arranged in the same column and adjacent to each other, the second initialization voltage signal sub-lines VIL12, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels. Thus, there is almost no color deviation between subpixels adjacent in the column direction; that is, the display substrate has a good display effect without any color deviation problems.

[0145] Referring further to Fig. 27 The orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate 10 does not overlap with the orthogonal projection of the first electrode 61 of the second subpixel SP2 onto the base substrate 10, i.e. the orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate 10 does not pass through the orthogonal projection of the first electrode 61 of the second subpixel SP2 onto the base substrate 10.

[0146] The orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate 10 does not overlap with the orthogonal projection of the first electrode 61 of the third subpixel SP3 onto the base substrate 10, i.e., the orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate 10 does not pass through the orthogonal projection of the first electrode 61 of the third subpixel SP3 onto the base substrate 10.

[0147] By such provision, the second initialization voltage signal sub-conductor VIL12, which lies in the first electrically conductive layer 1, does not cause a problem of unevenness in the planarization layer at the corresponding position of the first electrode 61 of the second subpixel SP2 or the first electrode 61 of the third subpixel SP3, which is favorable for improving the problem of color deviation of the second subpixel SP2 or the third subpixel SP3.

[0148] In the embodiments described in this disclosure, the orthogonal projections of the several first initialization voltage signal sublines VIL11 onto the base substrate 10 each partially overlap with the orthogonal projection of the first electrode 61 of the at least one third subpixel SP3 onto the base substrate 10. The orthogonal projection of the first initialization voltage signal subline VIL11 onto the base substrate 10 does not overlap with the orthogonal projection of the first electrode 61 of the first subpixel SP1 onto the base substrate 10. The orthogonal projection of the first initialization voltage signal subline VIL11 onto the base substrate 10 does not overlap with the orthogonal projection of the first electrode 61 of the second subpixel SP2 onto the base substrate 10.

[0149] For example, the orthogonal projection of the first electrode 61 of the third subpixel SP3 onto the base substrate 10 overlaps at least partially with the orthogonal projection of the first voltage signal line VDL onto the base substrate 10.

[0150] By such a design, the first initialization voltage signal sub-conductor VIL11, which lies in the first electrically conductive layer 1, does not cause a problem of unevenness in the planarization layer at the corresponding position of the first electrode 61 of the first subpixel SP1 or the first electrode 61 of the second subpixel SP2, which is favorable for improving the problem of the color deviation of the first subpixel SP1 or the second subpixel SP2.Because the orthogonal projection of the first electrode 61 of the third subpixel SP3 onto the base substrate 10 overlaps at least partially with the orthogonal projection of the first voltage signal line VDL, which is provided in the second electrically conductive layer 2, onto the base substrate 10, the first initialization voltage signal subline VIL11, which is provided in the first electrically conductive layer 1, does not have an excessive influence on the planarization problem in the planarization layer at the corresponding position of the first electrode 61 of the third subpixel SP3.

[0151] Fig. Figure 23 shows a second electrically conductive layer 2, which lies on a side of the first electrically conductive layer 1 facing away from the base substrate. As in Fig. As shown in Figure 23, for example the data line DL and the first voltage signal line VDL can be located in the second electrically conductive layer 2.

[0152] The data line DL extends essentially along the second direction Y, and the multiple data lines DL are spaced apart in the first direction X. For example, the multiple data lines DL each correspond to multiple columns of subpixels, in order to deliver the data signals to the pixel driver circuits of the multiple columns of subpixels.

[0153] The main body section of the first voltage signal line VDL extends along the second direction Y. A section of the first voltage signal line VDL has a greater width in the first direction X. For simplicity, the section of the first voltage signal line VDL that has an increased width is called the broadening section VDLW (as in Fig. (23 shown), and the widening section VDLW projects relative to the main body section of the first voltage signal line VDL in the first direction X. For example, the widening section VDLW projects relative to both sides of the main body section of the first voltage signal line VDL in the first direction X. In the embodiment of the present disclosure, two adjacent columns of subpixels can share a first voltage signal line VDL.

[0154] Fig. Figure 25 shows a first electrode layer 6, which lies on a side of the second electrically conductive layer 2 facing away from the base substrate. As in Fig. As shown in Figure 25, for example, the first electrode 61 of the individual subpixel can be located in the first electrode layer 6. The first electrode 61 can comprise an electrode body section 611 and an electrode connection section 612. In the Fig. In the embodiment shown in Figure 25, the orthogonal projection of the electrode body section 611 onto the base substrate 10 is, for example, circular or approximately circular. The electrode connection section 612 projects relative to the electrode body section 611 to one side, and the orthogonal projection of the electrode connection section 612 onto the base substrate 10 overlaps at least partially with the orthogonal projection of the electrode connection hole (which is described in more detail below) onto the base substrate 10 in order to electrically connect the first electrode 61 to the pixel driver circuit below.

[0155] Referring to Fig. The display substrate can further comprise several adapter sections located in the first electrically conductive layer 1. For example, the multiple adapter sections can include a first electrode adapter section 11, a voltage signal adapter section 12, a data signal adapter section 13, a first adapter section 14, a second adapter section 15, and a third adapter section 16.

[0156] Referring to Fig. 23 The display substrate can further comprise a second electrode adapter section 22, which is located in the second electrically conductive layer 2.

[0157] Referring to Fig. 21 and Fig. 22 The display substrate can include multiple through-holes located in the first insulating layer IL1. In some exemplary embodiments, the first insulating layer IL1 can include a passivation layer PVX and a first planarization layer PLN1. The multiple through-holes located in the first insulating layer IL1 can include: a first through-hole VH11, a second through-hole VH12, and a data signal connection hole VH13 located in the first planarization layer PLN1, as well as a first through-hole VH11', a second through-hole VH12', and a data signal connection hole VH13' located in the passivation layer PVX.In this embodiment, the first through-hole VH11, the second through-hole VH12, and the data signal connection hole VH13, located in the first planarization layer PLN1, each correspond to the first through-hole VH11', the second through-hole VH12', and the data signal connection hole VH13' located in the passivation layer PVX. For example, the positions of the first through-hole VH11, the second through-hole VH12, and the data signal connection hole VH13, located in the first planarization layer PLN1, each overlap with the positions of the first through-hole VH11', the second through-hole VH12', and the data signal connection hole VH13' located in the passivation layer PVX.The orthogonal projections of the first through hole VH11, the second through hole VH12 and the data signal connection hole VH13, which lie in the first planarization layer PLN1, onto the base substrate 10 superimpose or overlap with the orthogonal projections of the first through hole VH11', the second through hole VH12' and the data signal connection hole VH13' onto the base substrate 10, which lie in the passivation layer PVX.

[0158] It should be noted that in some other embodiments the first insulating layer IL1 may only comprise a film layer, for example a first planarizing layer PLN1.

[0159] For clarity, both the through-hole VH11 located in the first planarization layer PLN1 and the through-hole VH11' located in the passivation layer PVX are referred to as first through-holes, both the through-hole VH12 located in the first planarization layer PLN1 and the through-hole VH12' located in the passivation layer PVX are referred to as second through-holes, and both the through-hole VH13 located in the first planarization layer PLN1 and the through-hole VH13' located in the passivation layer PVX are referred to as data signal connection holes.

[0160] Referring to Fig. 17 and Fig. 18 The display substrate can include several through-holes located in the second insulating layer IL2. In some exemplary embodiments, the second insulating layer IL2 can include a first dielectric intermediate layer ILD1 and a second dielectric intermediate layer ILD2. The multiple through-holes located in the second insulating layer IL2 can include: a third through-hole VH21 located in the first dielectric intermediate layer ILD1, a fourth through-hole VH22 located in the first dielectric intermediate layer ILD1, a fifth through-hole VH23 located in the first dielectric intermediate layer ILD1, a sixth through-hole VH24 located in the first dielectric intermediate layer ILD1, a seventh through-hole VH25 located in the first dielectric intermediate layer ILD1, an eighth through-hole VH26 located in the first dielectric intermediate layer ILD1, and a ninth through-hole VH27.that lies in the first dielectric intermediate layer ILD1, a twelfth through hole VH30 that lies in the first dielectric intermediate layer ILD1; and a tenth through hole VH28 that lies in the second dielectric intermediate layer ILD2, an eleventh through hole VH29 that lies in the second dielectric intermediate layer ILD2, and a thirteenth through hole VH31 that lies in the second dielectric intermediate layer ILD2.

[0161] Referring to Fig. 24 The display substrate can include several electrode connection holes 31 located in the third insulating layer IL3 (e.g., the second planarization layer PLN2).

[0162] Referring to Fig. 11 to Fig. In 27, the first electrode 61 of each subpixel is electrically connected to the second electrode adapter section 22 by several electrode connection holes 31. Specifically, an orthogonal projection of the electrode connection section 612 of the first electrode 61 onto the base substrate 10 overlaps at least partially with an orthogonal projection of the second electrode adapter section 22 onto the base substrate 10, and an orthogonal projection of the electrode connection hole 31 onto the base substrate falls into an overlapping section of the electrode connection section 612 of the first electrode 61 and the second electrode adapter section 22.

[0163] The second electrode adapter section 22 is electrically connected to the first electrode adapter section 11 via the first through-hole VH11. Specifically, an orthogonal projection of the second electrode adapter section 22 onto the base substrate 10 overlaps at least partially with an orthogonal projection of the first electrode adapter section 11 onto the base substrate 10, and an orthogonal projection of the first through-hole VH11 onto the base substrate falls into an overlapping section of the second electrode adapter section 22 and the first electrode adapter section 11.

[0164] The first electrode adapter section 11 is electrically connected to the second pole (e.g., drain D6) of the second light emission control transistor T6 via the fifth through-hole VH23. Specifically, an orthogonal projection of the first electrode adapter section 11 onto the base substrate 10 overlaps at least partially with an orthogonal projection of the second pole of the second light emission control transistor T6 onto the base substrate 10, and an orthogonal projection of the fifth through-hole VH23 onto the base substrate falls into an overlapping section of the first electrode adapter section 11 and the second light emission control transistor T6.

[0165] Through such an adapter method, the first electrode 61 in the first electrode layer 6 can be electrically connected to the second pole (e.g., drain D6) of the second light emission control transistor T6, i.e., it corresponds to a node N4 in Fig. 2.

[0166] In the embodiments of the present disclosure, the first voltage signal line VDL is electrically connected to the voltage signal adapter section 12 through the second through-hole VH12.

[0167] As in Fig. As shown in Figure 19, the voltage signal adapter section 12 can comprise three structures. For simplicity, the voltage signal adapter section 12 with three structures is referred to as a first voltage signal adapter section 121, a second voltage signal adapter section 122, and a third voltage signal adapter section 123.

[0168] For example, the first voltage signal adapter section 121 can comprise a first section 1211, a second section 1212, and a third section 1213, wherein the second section 1212 extends along the second direction Y, and the first section 1211 and the third section 1213 each extend along the first direction X, with the first section 1211 and the third section 1213 each extending from the second section 1212 in opposite directions. The first section 1211, the second section 1212, and the third section 1213 of the first voltage signal adapter section 121 are joined in one piece and form an "inverted T-shaped" structure.In this case, an orthogonal projection of an end of the first section 1211 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a second through-hole VH12 onto the base substrate 10, and an orthogonal projection of an end of the third section 1213 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of another second through-hole VH12 onto the base substrate 10.For example, the orthogonal projection of an end of the first section 1211 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a widening section VDLW onto the base substrate 10, and the first voltage signal adapter section 121 is electrically connected to the widening section VDLW of the first voltage signal line VDL through the second through-hole VH12, thereby achieving an electrical connection between the first voltage signal adapter section 121 and the first voltage signal line VDL.The orthogonal projection of an end of the third section 1213 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of another widening section VDLW onto the base substrate 10, and the first voltage signal adapter section 121 is electrically connected to a widening section VDLW of another first voltage signal line VDL through another second through-hole VH12, thereby achieving an electrical connection between the first voltage signal adapter section 121 and the other first voltage signal line VDL.

[0169] The second voltage signal adapter section 122 can comprise a first section 1221 and a second section 1222, the second section 1222 extending along the second direction Y, and the first section 1221 extending along the first direction X, with the first section 1221 extending laterally from the second section 1222. The first section 1221 and the second section 1222 of the second voltage signal adapter section 122 are joined in one piece and form an "L-shaped" structure. In this case, an orthogonal projection of an end of the first section 1221 facing away from the second section 1222 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a second through-hole VH12 onto the base substrate 10.For example, the orthogonal projection of an end of the first section 1211 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a widening section VDLW onto the base substrate 10, and the second voltage signal adapter section 122 is electrically connected to the widening section VDLW of the first voltage signal line VDL through the second through-hole VH12, thereby achieving an electrical connection between the second voltage signal adapter section 122 and the first voltage signal line VDL.

[0170] In this embodiment, the second voltage signal adapter section 122 forms an "L-shaped" structure. Compared to the "inverted T-shaped" structure of the first voltage signal adapter section 121, the second voltage signal adapter section 122 has one less transverse section. Referring to Fig. 19 On the left side of the second voltage signal adapter section 122 of the “L-shaped” structure, a second initialization voltage signal sub-line VIL12 is provided, extending along the second direction Y. By providing a smaller transverse extension section, a short-circuit connection between the second voltage signal adapter section 122 and the second initialization voltage signal sub-line VIL12 can be avoided.

[0171] The third voltage signal adapter section 123 can comprise a second section 1232 and a third section 1233, wherein the second section 1232 extends along the second direction Y, and the third section 1233 extends along the first direction X, with the third section 1233 extending from the second section 1232 to a different side. The second section 1232 and the third section 1233 of the third voltage signal adapter section 123 are joined in one piece and form an "inverted L-shaped" structure. In this case, an orthogonal projection of an end of the third section 1233 facing away from the second section 1222 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a second through-hole VH12 onto the base substrate 10.For example, the orthogonal projection of an end of the third section 1213 facing away from the second section 1212 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a widening section VDLW onto the base substrate 10, and the third voltage signal adapter section 123 is electrically connected to the widening section VDLW of the first voltage signal line VDL through the second through-hole VH12, thereby achieving an electrical connection between the third voltage signal adapter section 123 and the first voltage signal line VDL.

[0172] In this embodiment, the third voltage signal adapter section 123 is configured in an "inverted L-shaped" structure. Compared to the "inverted T-shaped" structure of the first voltage signal adapter section 121, the third voltage signal adapter section 123 has one less transverse section. Referring to Fig. 19 On the right side of the third voltage signal adapter section 123 with the "inverted L-shaped" structure, a second initialization voltage signal sub-line VIL12 is provided, extending along the second direction Y. By providing a smaller transverse extension section, a short-circuit connection between the third voltage signal adapter section 123 and the second initialization voltage signal sub-line VIL12 can be avoided.

[0173] In the embodiments of the present disclosure, the voltage signal adapter section 12 is electrically connected to the second capacitive electrode Cst2, which is located in the second electrically conductive layer 32, through the ninth through-hole VH27.For example, an orthogonal projection of an end of the second section of each of the first voltage signal adapter section 121, the second voltage signal adapter section 122 and the third voltage signal adapter section 123, facing away from the first section or the third section, onto the base substrate 10 overlaps at least partially with an orthogonal projection of the second capacitive electrode Cst2 onto the base substrate 10, and an orthogonal projection of the ninth through hole VH27 onto the base substrate 10 lies within the overlap section of the second section of each of the first voltage signal adapter section 121, the second voltage signal adapter section 122 and the third voltage signal adapter section 123 and the second capacitive electrode Cst2.

[0174] The voltage signal adapter section 12 is also electrically connected to the first pole (e.g., of the source S5) of the first light emission control transistor T5 via the twelfth through hole VH30.For example, an orthogonal projection of an end of the second section of each of the first voltage signal adapter section 121, the second voltage signal adapter section 122 and the third voltage signal adapter section 123 connected to the first section or the third section onto the base substrate 10 overlaps at least partially with an orthogonal projection of the first pole of the first light emission control transistor T5 onto the base substrate 10, and an orthogonal projection of the twelfth through hole VH30 onto the base substrate 10 lies within the overlap section of the second section of each of the first voltage signal adapter section 121, the second voltage signal adapter section 122 and the third voltage signal adapter section 123 and the first pole of the first light emission control transistor T5.

[0175] Through such connections the electrical connections of the first voltage signal line VDL with the second capacitive electrode Cst2 and with the first pole of the first light emission control transistor T5 are achieved.

[0176] Referring to Fig. 21 to Fig. 27 For any two first subpixels SP1 that are arranged in the same row and adjacent to each other, orthogonal projections of some of the multiple through holes onto the base substrate 10 lie on the first side of the orthogonal projection of the pixel opening 20 of one of the two first subpixels SP1 onto the base substrate 10, and orthogonal projections of some other of the multiple through holes onto the base substrate 10 lie on the second side of the orthogonal projection of the pixel opening 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0177] In the embodiments of the present disclosure, the number of some of the multiple through-holes located on the first side of the pixel opening 20 of a first subpixel can be equal to the number of some other multiple through-holes located on the second side of the pixel opening 20 of another first subpixel. In the Fig. 21 to Fig. In the embodiments shown in Figure 27, for example, for any two first subpixels SP1 that are arranged in the same row and adjacent to each other, the orthogonal projections of three through holes (e.g., two first through holes VH11 and one second through hole VH12) in the first insulating layer IL1 onto the base substrate 10 are located on the first side of the orthogonal projection of the pixel opening 20 of one of the two first subpixels SP1 onto the base substrate 10, and the orthogonal projections of other three through holes (e.g., two first through holes VH11 and one second through hole VH12) in the first insulating layer IL1 onto the base substrate 10 are located on the second side of the orthogonal projection of the pixel opening 20 of the other of the two first subpixels SP1 onto the base substrate 10.

[0178] In the Fig. In the embodiment shown in Figure 27, for example, the orthogonal projections of a second through-hole VH12 and two first through-holes VH11 onto the base substrate 10 for the 1st and the 2nd first subpixel SP1, which are counted in the third row from the left, are located to the right of the orthogonal projection of the pixel opening 20 of the 1st first subpixel SP1 onto the base substrate 10, and the orthogonal projections of two first through-holes VH11 and a second through-hole VH12 onto the base substrate 10 are located to the left of the orthogonal projection of the pixel opening 20 of the 2nd first subpixel SP1 onto the base substrate 10.

[0179] In the embodiments described in the present disclosure, for any two first subpixels arranged in the same row and adjacent to each other, the through-holes in the first insulating layer, located below the first electrode 61 of the light-emitting element, are provided on opposite sides of the first electrodes 61 or the pixel openings 20 of the corresponding subpixels, so that the first electrodes 61 of the light-emitting elements of the row-adjacent subpixels can still be approximately symmetrical with respect to the midline AXL between two subpixels. In this way, the reflected light paths of the first electrodes 61 of the light-emitting elements of the two row-adjacent subpixels can still remain substantially the same, and the symmetry of the two is high with respect to the midline AXL between two subpixels.Thus, there is almost no color deviation between the subpixels adjacent in the row direction, i.e., the display substrate has a good display effect without a color deviation problem.

[0180] Furthermore, in the embodiments of the present disclosure, for the two arbitrary first subpixels SP1, which are arranged in the same row and adjacent to each other, the orthogonal projections of some through holes (e.g. a second through hole VH12 and two first through holes VH11) are Fig. 27) and some other through holes (e.g. two first through holes VH11 and a second through hole VH12 in Fig. 27) on the base substrate 10 symmetrically relative to the first axis of symmetry AX1, wherein the first axis of symmetry AX1 passes through the midpoint of the connecting line between the centers of the pixel openings 20 of the first two subpixels and extends along the second direction Y.

[0181] The symmetrical design of the through-holes in the planarization layer below the first electrode allows the symmetry of the reflection light paths of the first electrodes 61 of the light-emitting elements of the two subpixels adjacent in the row direction to be further improved, thereby further improving or even eliminating the problem of color deviation between the subpixels adjacent in the row direction and improving the display effect.

[0182] In the embodiments described in the present disclosure, the first voltage signal adapter section 121 is provided between a second voltage signal adapter section 122 and a third voltage signal adapter section 133, which are arranged adjacent to each other in the first direction X. In the embodiment described in Fig. In the embodiment shown in Figure 27, for example, for the row in which the first subpixel SP1 of the first row is located, the voltage signal adapter sections can be arranged periodically in the sequence of the third voltage signal adapter section 123, the first voltage signal adapter section 121, the second voltage signal adapter section 122, and the first voltage signal adapter section 121. By such a periodic arrangement of the voltage signal adapter sections, the second through-holes VH12 near the first electrode of the first subpixel SP1 can be designed symmetrically, so that a good display effect of the display substrate is achieved without color deviation problems.

[0183] The data line DL is electrically connected to the data signal adapter section 13 via the data signal connection hole VH13, and the data signal adapter section 13 is electrically connected to the second terminal (e.g., the drain D4) of the data write transistor T4 via the seventh through-hole VH25. This connection allows the data signal transmitted from the data line DL to be transferred to the second terminal of the data write transistor T4.

[0184] In the embodiments described in the present disclosure, the first initialization voltage signal line VIL1 is electrically connected to the first pole (e.g., of the source S7) of the first reset transistor T7 via the third through-hole VH21. For example, an orthogonal projection of a connecting section of the first section VIL111 with the second section VIL112 of the first initialization voltage signal sub-line VIL11 onto the base substrate 10 overlaps at least partially with an orthogonal projection of the first pole of the first reset transistor T7 onto the base substrate 10, and an orthogonal projection of the third through-hole VH21 onto the base substrate 10 falls into an overlapping section of the connecting section of the first section VIL111 with the second section VIL112 and the first pole of the first reset transistor T7;Alternatively, an orthogonal projection of a connecting section of the third section VIL113 with the second section VIL112 of the first initialization voltage signal sub-line VIL11 onto the base substrate 10 overlaps at least partially with the orthogonal projection of the first pole of the first reset transistor T7 onto the base substrate 10, and the orthogonal projection of the third through-hole VH21 onto the base substrate 10 falls into an overlap section of the connecting section of the third section VIL113 with the second section VIL112 and the first pole of the first reset transistor T7.

[0185] The first adapter section 14 is electrically connected to the second initialization voltage signal line VIL2 via the fourth through-hole VH22, and the first adapter section 14 is also electrically connected to the first pole (e.g., the source S1) of the second reset transistor T1 via the tenth through-hole VH28. For example, the first adapter section 14 comprises an intermediate first section 141, as well as a second section 142 and a third section 143, each arranged at two ends. An orthogonal projection of the first section 141 onto the base substrate 10 overlaps at least partially with an orthogonal projection of the fourth through-hole VH22 onto the base substrate 10, and the first section 141 of the first adapter section 14 is electrically connected to the second initialization voltage signal line VIL2 via the fourth through-hole VH22.An orthogonal projection of the second section 142 onto the base substrate 10 overlaps at least partially with an orthogonal projection of a tenth through-hole VH28 onto the base substrate 10, and the second section 142 of the first adapter section 14 is electrically connected via a tenth through-hole VH28 to the first pole (e.g., source S1) of the second reset transistor T1 of the pixel driver circuit of a subpixel. An orthogonal projection of the third section 143 onto the base substrate 10 overlaps at least partially with an orthogonal projection of another tenth through-hole VH28 onto the base substrate 10, and the third section 143 of the first adapter section 14 is electrically connected via another tenth through-hole VH28 to the first pole (e.g., source S1) of the second reset transistor T1 of the pixel driver circuit of another subpixel.

[0186] In the embodiments described in this disclosure, at least a portion of the first capacitive electrode Cst1 is simultaneously used as the gate G3 of the driver transistor T3. One end of the second adapter section 15 is electrically connected to the first capacitive electrode Cst1 via the sixth through-hole VH24, and the other end of the second adapter section 15 is electrically connected via VH29 to the second terminal (e.g., drain D1) of the second reset transistor T1 or the second terminal (e.g., drain D2) of the compensation transistor T2. This connection establishes an electrical connection at node N1.

[0187] One end of the third adapter section 16 is electrically connected via the eighth through-hole VH26 to the first pole (e.g., source S6) of the second light emission control transistor T6, and the other end of the third adapter section 16 is electrically connected via the thirteenth through-hole VH31 to the first pole (e.g., source S2) of the compensation transistor T2. This connection establishes an electrical connection at node N3.

[0188] Referring to Fig. Figure 26 schematically shows the pixel openings of the multiple subpixels. In the section on Fig. In the embodiment shown in Figure 26, for example, the shape of the orthogonal projection of the pixel openings 20 onto the base substrate 10 is circular or approximately circular. It should be noted that in other embodiments, the shape of the orthogonal projection of the pixel openings 20 onto the base substrate 10 may be different, and the embodiments of the present disclosure are not specifically limited in this respect.

[0189] Referring to Fig. For example, 26 is the orthogonal projection of the pixel opening of the first subpixel SP1 onto the base substrate 10 approximately circular.

[0190] For example, using a first straight line XL1, serving as a dividing line, which runs through the center of the pixel opening and extends parallel to the first direction X, the orthogonal projection of the pixel opening of the first subpixel SP1 onto the base substrate 10 can be divided into a first section and a second section. In the Fig. In the embodiment shown in Figure 26, the first section refers to an upper half, and the second section refers to a lower half. The area of ​​the first section of the orthogonal projection of the pixel opening of at least some first subpixels SP1 onto the base substrate 10 is not equal to the area of ​​the second section. For example, the area of ​​the first section of the orthogonal projection of the pixel opening of some first subpixels SP1 onto the base substrate 10 is larger than the area of ​​the second section, i.e., a shape with "a large top and a small bottom" is shown; the area of ​​the first section of the orthogonal projection of the pixel opening of the other some first subpixels SP1 onto the base substrate 10 is smaller than the area of ​​the second section, i.e., a shape with "a small top and a large bottom" is shown.For example, for two first subpixels SP1 that are adjacent in the second direction Y, the pixel opening of one first subpixel SP1 has the shape "with a large top and a small bottom," and the pixel opening of the other first subpixel SP1 has the shape "with a small top and a large bottom." This arrangement improves the uniformity of the red light in the second direction Y.

[0191] For example, using a second straight line YL1, serving as a dividing line, which runs through the center of the pixel opening and extends parallel to the second direction Y, the orthogonal projection of the pixel opening of the first subpixel SP1 onto the base substrate 10 can be divided into a third section and a fourth section. In the Fig. In the embodiment shown in Figure 26, the third section refers to a left half, and the fourth section refers to a right half. The area of ​​the third section of the orthogonal projection of the pixel opening of at least some first subpixels SP1 onto the base substrate 10 is not equal to the area of ​​the fourth section. For example, the area of ​​the third section of the orthogonal projection of the pixel opening of some first subpixels SP1 onto the base substrate 10 is larger than the area of ​​the fourth section, i.e., a shape with "a large left side and a small right side" is shown; the area of ​​the third section of the orthogonal projection of the pixel opening of the other some first subpixels SP1 onto the base substrate 10 is smaller than the area of ​​the fourth section, i.e., a shape with "a small left side and a large right side" is shown.For example, for two first subpixels SP1 that are adjacent in the first direction X, the pixel opening of one first subpixel SP1 has the form "with a large left side and a small right side", and the pixel opening of the other first subpixel SP1 has the form "with a small left side and a large right side". By providing it in this way, the uniformity of the red light in the first direction X can be improved. Referring to... Fig. 27 the orthogonal projections of the pixel openings 20 of the individual subpixels onto the base substrate 10 each fall into the orthogonal projections of the first electrodes 61 of the corresponding subpixels onto the base substrate 10.

[0192] Referring to Fig. 27, the vertical distance between the center of the pixel aperture 20 of the first subpixel and the first section VIL121 of the nearest second initialization voltage signal sub-line is a first distance d1, and the vertical distance between the center of the pixel aperture 20 of the first subpixel and the third section VIL123 of the nearest second initialization voltage signal sub-line is a second distance d2, where the first distance d1 is smaller than the second distance d2.

[0193] Specifically, an extension line (e.g., the straight line L1 in) runs Fig. 27) of a first section VIL121 of the at least one second initialization voltage signal sub-conductor along the second direction Y through at least one data signal adapter section 13, wherein a third section VIL123 of the at least one second initialization voltage signal sub-conductor and the at least one data signal adapter section 13 are spaced apart in the first direction X.

[0194] That is, in the embodiments of the present disclosure, the first section VIL121 of the second initialization voltage signal sub-line, which is arranged under the first electrode of the first subpixel, is located closer to the center of the pixel opening 20 of this first subpixel than the third section VIL123. In order to avoid interference between the first section VIL121 of the second initialization voltage signal sub-line and the data signal adapter section 13, the second section VIL122 is positioned further away from the center of the pixel opening 20 of the first subpixel by means of an oblique extension along the extension of the second initialization voltage signal sub-line, so that the third section VIL123 and the at least one data signal adapter section 13 are spaced apart in the first direction X.

[0195] Referring further to Fig. 27. The orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate does not overlap with an orthogonal projection of a first electrode of the second subpixel SP2 onto the base substrate, and the orthogonal projection of the second initialization voltage signal sub-conductor VIL12 onto the base substrate does not overlap with an orthogonal projection of a first electrode of the third subpixel SP3 onto the base substrate.

[0196] Fig. Figure 30A schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal subline according to some other embodiments of the present disclosure. As in Fig. Figure 30A shows that for any two second subpixels SP2 that are arranged in the same column and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the first side of the orthogonal projection of the first electrode 61 of one of the two second subpixels SP2 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 passes through a boundary section of the second side of the orthogonal projection of the first electrode 61 of the other of the two second subpixels SP2 onto the base substrate 10.

[0197] For any two second subpixels SP2 that are arranged in the same column and adjacent to each other, the orthogonal projection of a second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a first side of the orthogonal projection of the pixel aperture 20 of one of the two second subpixels SP2 onto the base substrate 10, and the orthogonal projection of another second initialization voltage signal subline VIL12 onto the base substrate 10 lies on a second side of the orthogonal projection of the pixel aperture 20 of the other of the two second subpixels SP2 onto the base substrate 10.

[0198] Fig. Figure 30B schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal subline according to some further embodiments of the present disclosure. As in Fig. As shown in Figure 30B, the orthogonal projections of the two second initialization voltage signal sublines VIL12 onto the base substrate 10 each pass through a boundary section of the first side and a boundary section of the second side of the orthogonal projection of the first electrode 61 of the same first subpixel SP1 onto the base substrate 10. For example, the orthogonal projections of the two second initialization voltage signal sublines VIL12 onto the base substrate 10 are symmetrical relative to a center line of the orthogonal projection of the first electrode 61 of the same first subpixel SP1 onto the base substrate 10. This configuration improves the flatness of the first electrode 61 of the first subpixel SP1.

[0199] Referring to Fig. 19, Fig. 27 and Fig. 30B together will be in the Fig. In the embodiment shown in Figure 30B, the transverse extension section of the second voltage signal adapter section 122 is further reduced, i.e., the first section 1221 thereof is removed; and the transverse extension section of the third voltage signal adapter section 123 is further reduced, i.e., the third section 1233 thereof is removed. In this way, the short-circuit connection of the second voltage signal adapter section 122 or the third voltage signal adapter section 123 with the two second initialization voltage signal sub-leads VIL12 can be avoided. In this case, a plurality of second capacitive electrodes Cst2 located in the same series can be connected to each other, as shown in Figure 30B. Fig. Figure 30D shows that the second capacitive electrode Cst2 is electrically connected to the first voltage signal line VDL, depending on the actual wiring space. In this way, the electrical connection between the first voltage signal line VDL, the second capacitive electrode Cst2, and the first pole (e.g., source S5) of the first light emission control transistor T5 is realized.

[0200] Fig. Figure 30C schematically shows a relative positional relationship between a subpixel and a second initialization voltage signal subline according to some other embodiments of the present disclosure. As in Fig. As shown in Figure 30C, the orthogonal projections of the two second initialization voltage signal sublines VIL12 onto the base substrate 10 each pass through a boundary section of the first side and a boundary section of the second side of the orthogonal projection of the first electrode 61 of the same second subpixel SP2 onto the base substrate 10. For example, the orthogonal projections of the two second initialization voltage signal sublines VIL12 onto the base substrate 10 are symmetrical relative to a center line of the orthogonal projection of the first electrode 61 of the same second subpixel SP2 onto the base substrate 10. This configuration improves the flatness of the first electrode 61 of the second subpixel SP2.

[0201] Referring to Fig. 19, Fig. 27 and Fig. 30°C together can be found in the Fig. In the embodiment shown in Figure 30C, two transverse sections of the first voltage signal adapter section 121 are reduced, i.e., the first section 1211 and the third section 1213 thereof are removed to avoid the short-circuit connection of the first voltage signal adapter section 121 with the two second initialization voltage signal sub-lines VIL12. In this case, a plurality of second capacitive electrodes Cst2 located in the same series can be connected to each other, as shown in Fig. Figure 30D shows that the second capacitive electrode Cst2 is electrically connected to the first voltage signal line VDL, depending on the actual wiring space. In this way, the electrical connection between the first voltage signal line VDL, the second capacitive electrode Cst2, and the first pole (e.g., source S5) of the first light emission control transistor T5 is realized.

[0202] At least some embodiments of the present disclosure further provide a display field, wherein the display field comprises a display substrate as described above. For example, the display field can be an OLED display field.

[0203] Referring to Fig. 1. At least some embodiments of the present disclosure further provide a display device. The display device may comprise a display substrate as described above. The display device comprises a display area AA and a non-display area NA.

[0204] The display device can include any device or product with a display function. Examples of display devices include a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., headset, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television, and the like.

[0205] It is understood that the display field and the display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above, which are described in detail above and are not repeated here.

[0206] Although some embodiments of the general technical concept of the present disclosure have been illustrated and described, it will be clear to a person skilled in the art that variations of these embodiments are possible without departing from the principles and spirit of the general technical concept of the present disclosure. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

Display substrate, wherein the display substrate comprises: a base substrate; several subpixels provided on the base substrate, the several subpixels being arranged in an array along a first direction and a second direction to form several rows of subpixels and several columns of subpixels, each comprising at least one of the subpixels comprising a light-emitting element; a first initialization voltage signal line provided on the base substrate, the first initialization voltage signal line being used to transmit a first initialization voltage signal; a first electrode layer provided on the base substrate, the light-emitting element of the at least one subpixel comprising a first electrode located on the first electrode layer;and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel comprises a pixel aperture located on the pixel boundary layer, wherein an orthogonal projection of the pixel aperture of the at least one subpixel onto the base substrate coincides with an orthogonal projection of the first electrode of the at least one subpixel onto the base substrate, wherein the first initialization voltage signal line comprises a first initialization voltage signal sub-line and a second initialization voltage signal sub-line, wherein a main body section of the first initialization voltage signal sub-line extends along the first direction, and a main body section of the second initialization voltage signal sub-line extends along the second direction;wherein the at least one subpixel comprises several first subpixels, the several first subpixels being subpixels of a first color; wherein orthogonal projections of several of the second initialization voltage signal subleads onto the base substrate each partially overlap with orthogonal projections of the first electrodes of the several first subpixels onto the base substrate;wherein orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a first side and a second side, wherein the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a center, wherein the center is a center of an orthogonal projection of the pixel opening onto the base substrate on a virtual line segment extending along the first direction, wherein the first side and the second side are opposite sides in the first direction relative to the center;wherein for at least two first subpixels an orthogonal projection of one of the second initialization voltage signal sublines onto the base substrate lies on a first side of a center of a pixel opening of one of the two first subpixels, and an orthogonal projection of another of the second initialization voltage signal sublines onto the base substrate lies on a second side of a center of a pixel opening of another of the two first subpixels. Display substrate according to claim 1, wherein the two first subpixels are any two first subpixels arranged in the same row and adjacent to each other. Display substrate according to claim 2, wherein several of the first initialization voltage signal sub-lines and several of the second initialization voltage signal sub-lines are crossed and connected, such that the first initialization voltage signal lines form a net structure. Display substrate according to claim 3, wherein the orthogonal projections of the multiple second initialization voltage signal sub-lines onto the base substrate each partially overlap with the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate. Display substrate according to one of claims 2 to 4, wherein for any two first subpixels arranged in the same row and adjacent to each other, orthogonal projections of two of the second initialization voltage signal sub-lines onto the base substrate, which partially overlap with the first electrodes of the two first subpixels, are symmetrical relative to a first axis of symmetry, wherein the first axis of symmetry passes through a midpoint of a connecting line between the centers of the pixel openings of the two first subpixels and extends along the second direction. Display substrate according to any one of claims 1 to 5, wherein for any two first subpixels arranged in the same column and adjacent to each other, the orthogonal projection of one second initialization voltage signal sub-line onto the base substrate lies on a first side of an orthogonal projection of a pixel opening of one of the two first subpixels onto the base substrate, and the orthogonal projection of the other second initialization voltage signal sub-line onto the base substrate lies on a second side of an orthogonal projection of a pixel opening of another of the two first subpixels onto the base substrate. Display substrate according to any one of claims 1 to 6, wherein the multiple rows of subpixels comprise multiple rows of first subpixels, and the multiple columns of subpixels comprise multiple columns of first subpixels; wherein positions of a second initialization voltage signal sub-line, which partially overlaps with a first electrode of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal sub-line, which partially overlaps with a first electrode of a first subpixel located in an i+4-th row and a j-th column, are oriented in the second direction, wherein i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1. Display substrate according to any one of claims 1 to 6, wherein the multiple rows of subpixels comprise multiple rows of first subpixels, and the multiple columns of subpixels comprise multiple columns of first subpixels; wherein positions of a second initialization voltage signal sub-line, which partially overlaps with a first electrode of a first subpixel located in an i-th row and a j-th column, and a second initialization voltage signal sub-line, which partially overlaps with a first electrode of a first subpixel located in an i+2-th row and a j-th column, are oriented in the second direction, wherein i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1. Display substrate according to one of claims 1-8, wherein at least one of the second initialization voltage signal sub-lines is located between two adjacent of the first initialization voltage signal sub-lines; wherein the at least one second initialization voltage signal sub-line comprises a first section, a second section and a third section, wherein the second section is located between the first section and the third section, wherein the first section and the third section extend along the second direction, and the second section extends along a third direction, wherein the third direction intersects with both the first direction and the second direction. Display substrate according to claim 9, wherein a distance between a center of the pixel opening of the first subpixel and a first section of a next second initialization voltage signal sub-line in the first direction is a first distance, and a distance between the center of the pixel opening of the first subpixel and a third section of the next second initialization voltage signal sub-line in the first direction is a second distance, wherein the first distance is smaller than the second distance. Display substrate according to claim 9, wherein the display substrate comprises a first electrically conductive layer and a second electrically conductive layer provided on the base substrate, the second electrically conductive layer being located between the first electrically conductive layer and the first electrode layer, the first initialization voltage signal line being located on the first electrically conductive layer; wherein the display substrate further comprises a data line located on the second electrically conductive layer, the data line being used to transmit a data signal; wherein the display substrate further comprises a data signal adapter section located on the first electrically conductive layer, the data signal adapter section being electrically connected to the data line;wherein an extension line of a first section of the at least one second initialization voltage signal sub-line runs along the second direction through at least one of the data signal adapter sections, wherein a third section of the at least one second initialization voltage signal sub-line and the at least one data signal adapter section are spaced apart in the first direction. Display substrate according to any one of claims 1 to 11, wherein the display substrate further comprises: a first insulating layer located between the first electrically conductive layer and the second electrically conductive layer; and several through-holes located in the first insulating layer; wherein, for any two first subpixels arranged in the same row and adjacent to each other, orthogonal projections of some of the several through-holes onto the base substrate lie on the first side of the orthogonal projection of the pixel opening of one of the two first subpixels onto the base substrate, and orthogonal projections of some other of the several through-holes onto the base substrate lie on the second side of the orthogonal projection of the pixel opening of the other of the two first subpixels onto the base substrate. Display substrate according to claim 12, wherein for any two first subpixels arranged in the same row and adjacent, orthogonal projections of some and some other through-holes onto the base substrate are symmetrical relative to the first axis of symmetry, the first axis of symmetry passing through the midpoint of the connecting line between the centers of the pixel openings of the two first subpixels and extending along the second direction. Display substrate according to claim 12 or 13, wherein the display substrate further comprises a first electrode adapter section located on the first electrically conductive layer and a second electrode adapter section located on the second electrically conductive layer, wherein the multiple through-holes located in the first insulating layer comprise a first through-hole; wherein the first electrode is electrically connected to the second electrode adapter section, and the second electrode adapter section is electrically connected to the first electrode adapter section through the first through-hole; wherein the some through-holes comprise at least one first through-hole, and the some other through-holes comprise at least one first through-hole. Display substrate according to claim 14, wherein the some through-holes comprise two first through-holes, and the some other through-holes comprise two first through-holes. Display substrate according to claim 15, wherein the display substrate further comprises a voltage signal adapter section located on the first electrically conductive layer and a first voltage signal line located on the second electrically conductive layer, wherein the multiple through-holes located in the first insulating layer comprise a second through-hole, wherein the first voltage signal line is electrically connected to the voltage signal adapter section through the second through-hole; wherein the some through-holes comprise at least one second through-hole, and the some other through-holes comprise at least one second through-hole. Display substrate according to claim 16, wherein the voltage signal adapter section comprises a first voltage signal adapter section, wherein the first voltage signal adapter section comprises a first section, a second section and a third section, wherein the second section extends along the second direction, wherein the first section and the third section each extend along the first direction, and wherein the first section and the third section each extend from the second section along opposite directions;wherein an orthogonal projection of an end of the first section facing away from the second section onto the base substrate overlaps at least partially with an orthogonal projection of one of the second through-holes onto the base substrate, and an orthogonal projection of an end of the third section facing away from the second section onto the base substrate overlaps at least partially with an orthogonal projection of another of the second through-holes onto the base substrate. Display substrate according to claim 17, wherein the voltage signal adapter section comprises a second voltage signal adapter section, wherein the second voltage signal adapter section comprises a first section and a second section, the second section extending along the second direction, and the first section extending along the first direction, the first section extending from the second section to one side; wherein an orthogonal projection of an end of the first section facing away from the second section onto the base substrate overlaps at least partially with the orthogonal projection of one of the second through-holes onto the base substrate. Display substrate according to claim 18, wherein the voltage signal adapter section comprises a third voltage signal adapter section, wherein the third voltage signal adapter section comprises a second section and a third section, the second section extending along the second direction, and the third section extending along the first direction, the third section extending from the second section to another side; wherein an orthogonal projection of an end of the third section facing away from the second section onto the base substrate overlaps at least partially with the orthogonal projection of one of the second through-holes onto the base substrate. Display substrate according to claim 19, wherein the first voltage signal adapter section is provided between a second voltage signal adapter section and a third voltage signal adapter section, which are arranged adjacent in the first direction.Display substrate according to any one of claims 1 to 20, wherein the display substrate comprises multiple pixel driver circuits provided on the base substrate, the multiple pixel driver circuits being arranged in an array along the first direction and the second direction, the multiple pixel driver circuits being used to drive the light-emitting elements of the multiple subpixels; wherein the display substrate further comprises: a first semiconductor layer provided on the base substrate; a third electrically conductive layer provided on a side of the first semiconductor layer facing away from the base substrate; a fourth electrically conductive layer provided on a side of the third electrically conductive layer facing away from the base substrate; a second semiconductor layer provided on a side of the fourth electrically conductive layer facing away from the base substrate;a fifth electrically conductive layer provided on a side of the second semiconductor layer facing away from the base substrate; and a second insulating layer provided between the fifth electrically conductive layer and the first electrically conductive layer; wherein the pixel driver circuit comprises a first reset transistor, the first reset transistor comprising an active layer, a gate, a source, and a drain, the active layer of the first reset transistor being located on the first semiconductor layer; wherein the display substrate further comprises a third through-hole located on the second insulating layer, the first initialization voltage signal line being electrically connected through the third through-hole to the source or the drain of the first reset transistor. Display substrate according to claim 21, wherein the pixel driver circuit further comprises a second reset transistor, the second reset transistor comprising an active layer, a gate, a source and a drain, the active layer of the second reset transistor being located on the second semiconductor layer; and wherein the display substrate further comprises a second initialization voltage signal line provided on the base substrate, the second initialization voltage signal line being used to transmit a second initialization voltage signal, the second initialization voltage signal line being electrically connected to the source or the drain of the second reset transistor; the second initialization voltage signal line being located on the fourth electrically conductive layer, the second initialization voltage signal line extending along the first direction. Display substrate according to one of claims 1-22, wherein the multiple subpixels further comprise a second subpixel and a third subpixel; wherein the orthogonal projection of the second initialization voltage signal sub-conductor onto the base substrate does not overlap with an orthogonal projection of a first electrode of the second subpixel onto the base substrate, and the orthogonal projection of the second initialization voltage signal sub-conductor onto the base substrate does not overlap with an orthogonal projection of a first electrode of the third subpixel onto the base substrate. Display substrate according to claim 23, wherein orthogonal projections of several of the first initialization voltage signal sub-lines onto the base substrate each partially overlap with an orthogonal projection of a first electrode of at least one of the third subpixels onto the base substrate; and / or wherein the orthogonal projection of the first initialization voltage signal sub-line onto the base substrate does not overlap with the orthogonal projection of the first electrode of the first subpixel onto the base substrate; and / or wherein the orthogonal projection of the first initialization voltage signal sub-line onto the base substrate does not overlap with the orthogonal projection of the first electrode of the second subpixel onto the base substrate. Display substrate according to claim 24, wherein the first subpixel is a red subpixel, the second subpixel is a blue subpixel and the third subpixel is a green subpixel. Display substrate, wherein the display substrate comprises: a base substrate; several subpixels provided on the base substrate, the several subpixels being arranged in an array along a first direction and a second direction to form several rows of subpixels and several columns of subpixels, each comprising at least one of the subpixels comprising a light-emitting element; a first initialization voltage signal line provided on the base substrate, the first initialization voltage signal line being used to transmit a first initialization voltage signal; a first electrode layer provided on the base substrate, the light-emitting element of the at least one subpixel comprising a first electrode located on the first electrode layer;and a pixel boundary layer provided on a side of the first electrode layer facing away from the base substrate, wherein the at least one subpixel comprises a pixel aperture located on the pixel boundary layer, wherein an orthogonal projection of the pixel aperture of the at least one subpixel onto the base substrate coincides with an orthogonal projection of the first electrode of the at least one subpixel onto the base substrate, wherein the at least one subpixel comprises several first subpixels, the several first subpixels being subpixels of a first color; wherein orthogonal projections of several of the second initialization voltage signal sub-lines onto the base substrate each partially overlap with orthogonal projections of the first electrodes of the several first subpixels onto the base substrate;wherein orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a first side and a second side, wherein the orthogonal projections of the pixel openings of the multiple first subpixels onto the base substrate each have a center, the center being the center of an orthogonal projection of the pixel opening onto the base substrate on a virtual line segment extending along the first direction, the first side and the second side being opposite sides in the first direction relative to the center; wherein the display substrate further comprises: a first electrically conductive layer and a second electrically conductive layer provided on the base substrate; a first insulating layer situated between the first electrically conductive layer and the second electrically conductive layer; and multiple through-holes situated in the first insulating layer;wherein the second electrically conductive layer lies between the first electrically conductive layer and the first electrode layer, wherein the first initialization voltage signal line lies on the first electrically conductive layer; wherein for at least two first subpixels, orthogonal projections of some of the multiple through holes onto the base substrate lie on a first side of a center of a pixel opening of one of the two first subpixels, and orthogonal projections of some other of the multiple through holes onto the base substrate lie on a second side of a center of a pixel opening of another of the two first subpixels. Display device comprising a display substrate according to any one of claims 1-26.

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