Driver device for backward conducting semiconductor switching element and power converter device utilizing it

Abstract

A driver device for a reverse-conducting semiconductor switching element (90), wherein a semiconductor switching element (Z1) and a rectifier element (D1) are connected in antiparallel and are integrated, comprises: a turn-on enable signal generation unit (60) that receives a turn-on / turn-off command signal (SIN) to turn on or off the reverse-conducting semiconductor switching element (90) and generates a turn-on enable signal (SGD); and a gate driver unit (70A) that receives the turn-on enable signal (SGD) and generates a driver voltage to be applied to a gate terminal (Gs) of a semiconductor switching element (Z1).If a voltage between the main terminals - between a first main terminal (Cs) and a second main terminal (Es) of the semiconductor switching element (Z1) - is greater than a first reference voltage (VrefH) during a period when the reverse-conducting semiconductor switching element (90) is off, the turn-on allow signal (SGD) is set to a turn-on state, and if the voltage between the main terminals is less than a second reference voltage (VrefL) that is different from the first reference voltage, the turn-on allow signal (SGD) is set to a turn-off state.

Description

Technical field

[0001] The present invention relates to a driver device for a backward conducting semiconductor switching element and a power converter device that uses this. State of the art

[0002] A power converter device, comprising a power converter unit and a control unit for controlling the power converter unit, such as an inverter device, performs energy conversion by switching semiconductor switching devices on and off. It is widely used in household appliances, industrial applications, automotive applications, railway applications, and the like. Examples of semiconductor switching devices include voltage-driven semiconductor switching devices, such as IGBTs (insulated-gate bipolar transistors) and MOSFETs (metal-oxide-semiconductor field-effect transistors). To control such a semiconductor switching device, a driver device is necessary. Generally, such a driver device controls the conduction state of the semiconductor switching device by applying a voltage to its gate.

[0003] Recently, a reverse-conducting IGBT has been increasingly used, in which an IGBT and a diode connected antiparallel to the IGBT are integrated, thus reducing the chip size, which leads to a cost reduction, and reducing the thermal resistance, which leads to a reduction in the size of the power converter.

[0004] In a driver circuit for the semiconductor switching element in the power converter device, a control is used that does not depend on the direction of the load current in order to simplify the control of the semiconductor switching element, and in general the gate of the IGBT is turned on even when the diode of the reverse-conducting IGBT is in the conducting state.

[0005] However, if the IGBT gate is switched on while the diode is conducting, a parasitic n-channel MOSFET acts, hindering the diode's bipolar operation and increasing the forward voltage. Therefore, a separate, reverse-conducting IGBT is generally used, featuring a separation between the IGBT and diode sections to prevent mutual interference.

[0006] In this respect, a driver method was developed to improve the current density by eliminating the separation region, which prevents the gate of the IGBT from being switched on when the diode of the reverse-conducting IGBT is in the conducting state, and consequently the application of a non-separated reverse-conducting IGBT is being attempted.

[0007] In such a non-isolated reverse-conducting IGBT, a sensor diode is added to monitor the current flowing through the diode when the reverse-conducting IGBT's diode is in a conducting state, and control is implemented so that the IGBT's gate is not turned on when the reverse-conducting IGBT's diode is in a conducting state. This suppresses an increase in the diode's forward voltage resulting from the operation of a parasitic n-channel MOSFET (see, for example, patent document 1).

[0008] The method disclosed in patent document 1 has the following characteristics: Since the current flowing through the diode is directly detected, the gate is accurately prevented from being switched on when the diode is in the conducting state. However, because the sensor diode is added for monitoring, the chip area of ​​the reverse-conducting IGBT increases, leading to a cost increase.

[0009] The following method is known for a non-isolated reverse-conducting IGBT where such a sensor diode is not necessary for monitoring. During a period in which both the upper and lower branches of a leg circuit formed by connecting a plurality of reverse-conducting IGBTs in series are switched off, the gate is switched on based on a main terminal voltage of the reverse-conducting IGBT, and the gate's on state is maintained until a switch-off command for the reverse-conducting IGBT is input from a higher-order control unit. This prevents an increase in the diode's forward voltage due to the operation of the parasitic n-channel MOSFET (see, for example, patent document 2).

[0010] However, it is known that the operation of the parasitic n-channel MOSFET when the diode is conducting causes a reduction in the short-circuit withstand capability, which is a problem specific to IGBTs. In general, the modes in which the upper and lower branches of the leg circuit are short-circuited include: a short circuit that occurs when an IGBT is turned on (Type 1 short circuit), a short circuit that occurs when an IGBT is conducting (Type 2 short circuit), and a short circuit that occurs during a period when the gate of an IGBT is turned on while the diode is conducting (Type 3 short circuit).

[0011] Here, in an IGBT operating in MOSFET mode, where the hole injection efficiency from a collector p-channel layer is reduced and the electron current ratio is increased, the space charge in a drift layer becomes negative during the short circuit. This increases the electric field strength on the back side, leading to a reduction in the short-circuit withstand capacitance, as indicated (see, for example, non-patent document 1). A similar situation occurs during the type 3 short circuit of the reverse-conducting IGBT.

[0012] This means that in the reverse-conducting IGBT, the operation of the parasitic n-channel MOSFET, when the diode connected antiparallel to the IGBT is in the conducting state, causes a reduction in the short-circuit withstand capability during this period, which is a new problem, and depending on the element design, it can be assumed that a breakdown will occur as a result of the time constants, which make it difficult to implement protection using a known short-circuit protection technology.

[0013] In particular, a collector voltage detection (DESAT) configuration, which is a general short-circuit protection technology, can be easily implemented at low cost, but it has a large detection delay, and therefore it is difficult to implement protection against a Type 3 short circuit of the reverse-conducting IGBT. To implement protection in this short-circuit mode, a cost-effective short-circuit detection method must be adopted. Bibliography Patent document Patent document 1: Japanese patent application disclosure JP 2008 - 72 848 A Patent document 2: Japanese patent application disclosure JP 2014 - 216 932 A Non-patent document

[0014] Non-patent document 1: “Simulation studies for short-circuit current crowding of MOSFET-Mode IGBT”, ISPSD, 2014 Summary of the invention Problem to be solved with the invention

[0015] In the method disclosed in patent document 1, a sensor diode is added for monitoring, thus increasing the chip area of ​​the backward conducting IGBT, which leads to an increase in cost.

[0016] In the method disclosed in patent document 2, a sensor diode is not required for monitoring, but the collector voltage is only determined during a period when both the upper and lower branches forming the leg circuit are switched off. Therefore, at the time of commutation from the conduction state of the diode to the conduction state of the IGBT, the gate cannot be properly switched on.

[0017] Furthermore, the gate-on state is maintained until a turn-off command for the reverse-conducting IGBT is issued by the higher-order control unit. Therefore, when the current is commutated from the direction flowing to the IGBT to the direction flowing to the diode during the gate-on state, an increase in the diode's forward voltage inevitably occurs as a result of the operation of the parasitic n-channel MOSFET.

[0018] At this time, the forward voltage can reach several tens to hundreds of volts, which not only causes an increase in losses but also a problem regarding reliability.

[0019] Furthermore, as a result of the operation of the parasitic n-channel MOSFET when the diode is in the conducting state, the short-circuit resistance capacitance is reduced, which can cause a reduction in the resistance capacitance against a type 3 short circuit of the reverse-conducting IGBT.

[0020] The present invention was designed to solve the above problem, and it is an object of the present invention to provide such a configuration that prevents a gate from being turned on when a diode of a reverse-conducting IGBT is in a conducting state, and even if a current is commutated to the diode during a gate turn-on period, prevents a forward voltage of the diode and prevents a breakdown due to a type 3 short circuit occurring during a gate turn-on period when the diode is in a conducting state. Ways to solve the problem

[0021] A driver device for a reverse-conducting semiconductor switching element according to the present invention is a driver device for a reverse-conducting semiconductor switching element, wherein a semiconductor switching element and a rectifier element connected antiparallel to the semiconductor switching element are integrated, the driver device comprising: a turn-on enable signal generation unit that receives a turn-on / turn-off command signal to turn on or off the reverse-conducting semiconductor switching element and generates a turn-on enable signal; a gate driver unit that receives the turn-on enable signal and generates a driver voltage to be applied to a gate terminal of the semiconductor switching element;and a voltage determination unit that performs a comparison and determination of a voltage between the main terminals - between the first and second main terminals of the semiconductor switching element - using a first reference voltage and a second reference voltage that is different from the first reference voltage.

[0022] By logically combining a determination signal from the voltage determination unit and the on / off command signal, if the voltage between the main terminals is greater than the first reference voltage during a period when the reverse-conducting semiconductor switching element is off, the on-enable signal is set to an on state, and if the voltage between the main terminals is less than the second reference voltage during a period when the reverse-conducting semiconductor switching element is off, the on-enable signal is set to an off state.

[0023] A power converter device according to the present invention is configured such that - for each of the backward conducting semiconductor switching elements of an upper branch and a lower branch connected in series - the driver devices for the backward conducting semiconductor switching elements according to the present invention are provided. Effect of the invention

[0024] The driver device for a reverse-conducting semiconductor switching element according to the present invention prevents a gate from being turned on when a diode of a reverse-conducting semiconductor switching element is in a conducting state, and even if a current is commutated to the diode during a gate turn-on period, an increase in the forward voltage of the diode can be prevented, and a breakdown due to a type 3 short circuit that occurs during a gate turn-on period when the diode is in a conducting state can be prevented. Brief description of the drawings Fig. Figure 1 is a block diagram showing a configuration example of a driver device for a reverse-conducting semiconductor switching element according to embodiment 1. Fig. Figure 2 is a block diagram showing a specific example of the driver device for the reverse conducting semiconductor switching element according to embodiment 1. Fig. Figure 3 shows an example of a timing diagram of signals in a normal state in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 1. Fig. Figure 4 shows an example of a timing diagram of a second voltage determination signal in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 1. Fig. Figure 5 shows an example of a timing diagram of signals in a case of a short circuit in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 1. Fig. Figure 6 is a block diagram showing a configuration example of a driver device for a reverse-conducting semiconductor switching element according to embodiment 2. Fig. Figure 7 is a block diagram showing a specific example of the driver device for the reverse conducting semiconductor switching element according to embodiment 2. Fig. Figure 8 shows an example of a timing diagram of signals in a normal state in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 2. Fig. Figure 9 is a block diagram showing a configuration example of a driver device for a reverse-conducting semiconductor switching element according to embodiment 3. Fig. Figure 10 is a block diagram showing a specific example of the driver device for the reverse conducting semiconductor switching element according to embodiment 3. Fig. Figure 11 shows an example of timing diagrams of signals in a normal state in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 3. Fig. Figure 12 is a block diagram showing a configuration example of a driver device for a reverse conducting semiconductor switching element according to embodiment 4. Fig. Figure 13 is a block diagram showing a specific example of the driver device for the reverse conducting semiconductor switching element according to embodiment 4. Fig. Figure 14 shows an example of timing diagrams of signals in a normal state in the specific example of the driver device for the backward conducting semiconductor switching element according to embodiment 4. Fig. Figure 15 shows a configuration example of a power converter device that uses a driver device for a backward conducting semiconductor switching element according to embodiment 5. Fig. Figure 16 shows a configuration example of a power converter device that uses a driver device for a backward conducting semiconductor switching element according to embodiment 6. Fig. Figure 17 shows a configuration example of a power converter device that uses a driver device for a backward conducting semiconductor switching element according to embodiment 7. Description of embodiments

[0025] The following descriptions of embodiments refer to the drawings. In the drawings, identical reference numerals denote identical or corresponding parts. Fig. 1 to Fig. Figure 17 relates to exemplary embodiments, and the present invention is not limited by the drawings. Design 1

[0026] Fig. Figure 1 is a block diagram showing a configuration of a driver device 10A for a reverse-conducting semiconductor switching element according to embodiment 1. It is assumed that the following example is applied to a configuration of a leg circuit 91 in which a plurality of reverse-conducting semiconductor switching elements 90 are connected in series, as shown in Figure 1. Fig. 15 to Fig. 17 shown.

[0027] As an example of the reverse-conducting semiconductor switching element 90, a reverse-conducting IGBT is shown, incorporating an IGBT_Z1 and a diode D1. The reverse-conducting semiconductor switching element 90 has a collector sensor terminal Cs, which is a first main terminal, and an emitter control terminal Es, which is a second main terminal, and the conducting / non-conducting state between a collector C and an emitter E is controlled according to a gate voltage Vge applied between a gate terminal Gs and the emitter control terminal Es.

[0028] In the example shown, the driver assembly 10A for the reverse conducting semiconductor switching element comprises the following: a voltage reduction unit 20, a first voltage determination unit 30, a second voltage determination unit 40, a short-circuit detection unit 50, a generation unit 60 for turn-on allow signals, and a gate driver unit 70A, and a positive power supply voltage VP, which is generated with the emitter control terminal Es as a reference, is applied to the gate terminal Gs as a gate driver power supply.

[0029] In the present embodiment, during the period when the gate is off, the voltage applied to the gate terminal Gs is zero, but the gate driver power supply can be configured to apply a negative power supply voltage VN. In addition to the gate driver power supply, a separate control power supply for operating a logic circuit or the like may be provided. In the present embodiment, a 5V control power supply is provided, but this is not shown for the sake of simplicity.

[0030] The driver unit 10A for the reverse conducting semiconductor switching element receives a turn-on / turn-off command signal SIN to turn on or off the reverse conducting semiconductor switching element 90, which is supplied by a higher-order logic unit, such as a microcomputer, and on the basis of the voltage of the collector sensor terminal Cs of the reverse conducting semiconductor switching element 90, it generates a suitable turn-on allow signal SGD for the reverse conducting semiconductor switching element 90, and it detects a short circuit of the reverse conducting semiconductor switching element 90, so that it consequently functions in such a way that it appropriately performs a protective function.

[0031] The voltage of the collector sensor terminal Cs, i.e. the voltage between the main terminals Vce - between the first main terminal and the second main terminal - is reduced to a signal level by the voltage reduction unit 20, and the resulting signals SDE and SDD are input to the first voltage determination unit 30 and the second voltage determination unit 40, respectively.

[0032] The first voltage determination unit 30 transmits a first voltage determination signal SCH to the generation unit 60 for enable signals. This signal is derived from the determination that the input signal SDE is not less than a first reference value during a period in which the enable / disable command signal SIN indicates "off". The second voltage determination unit 40 transmits a second voltage determination signal SGC to the generation unit 60 for enable signals. This second voltage determination signal is derived from the determination that the voltage of the input signal SDD is not greater than a second reference value.In response to the generation of the first voltage determination signal SCH, the generation unit 60 for switch-on permission signals changes the switch-on permission signal SGD to a switch-on state and holds this state by means of an internal holding circuit, and in response to the generation of the second voltage determination signal SGC or a change in the specification of the switch-on / switch-off command signal from "switched on" to "switched off", the generation unit 60 for switch-on permission signals changes the switch-on permission signal SGD to a switch-off state.

[0033] During a period in which the turn-on allow signal SGD indicates a turn-on state, the following applies: If the first voltage determination signal SCH has been generated for a predetermined time or longer, the short-circuit detection unit 50 determines that the reverse-conducting semiconductor switching element 90 is short-circuited and transmits a short-circuit detection signal SSC, which has been held for a predetermined period, to the gate driver unit 70A and the turn-on allow signal generation unit 60.

[0034] The generated enable signal SGD is logically combined with the short-circuit detection signal SSC by the gate driver unit 70A. If a short circuit is not detected, the current of the enable signal SGD is amplified, and the gate terminal Gs is driven. If the short-circuit detection unit 50 detects a short circuit, the enable signal SGD and the short-circuit detection signal SSC are logically combined in the gate driver unit 70A, and the gate terminal Gs is controlled to turn off the gate. At the same time, the short-circuit detection signal SSC is transmitted to the enable signal generator 60, and the enable signal SGD is switched off.

[0035] The 70A gate driver unit has a soft-stop function, so that when the short-circuit detection signal SSC is generated, the 70A gate driver unit changes the gate drive force to reduce the resulting surge voltage by interrupting the short-circuit current when necessary. However, a configuration for implementing this is not shown for the sake of simplicity. The blocks that transmit / receive signals and the block that logically combines signals are not limited to the configuration shown in Fig. Figure 1 shows that the combination of blocks and the transmission / reception of signals can be modified in various ways.

[0036] The turn-on / turn-off command signal SIN is transmitted between a reference potential of a higher-order logic unit, such as a microcomputer, and the emitter reference potential Es. Therefore, it is transmitted / received via separate communication using an optical conversion module, an optocoupler, a pulse transformer, or another level-shifting IC. This is not shown for simplicity. Similarly, the gate driver power supply 11 is provided as a separate isolation power supply, but the details of its generation circuitry and the like are omitted for simplicity.

[0037] Fig. Figure 2 shows a specific example of the driver device 10A for the reverse-conducting semiconductor switching element 90 according to embodiment 1. The voltage reduction unit 20 has a configuration for reducing the potential of the collector sensor terminal Cs by rectifying a high-voltage diode D20 and dividing the voltage by resistors R20 to R22, as one example. However, various known configurations can be used, such as a configuration for dividing the voltage by means of only one resistor and a configuration that uses a constant-voltage diode or the like.

[0038] The first voltage determination unit 30 has a filter characteristic based on a charging time constant of a filter capacitor C30 and a constant current diode D30 and a discharging time constant defined by the filter capacitor C30 and the resistors R20 and R22, and when the first voltage determination unit 30 determines by means of a comparator 31 that the input signal SDE is greater (higher) than the first reference voltage VrefH, then the first voltage determination unit 30 generates a first voltage determination signal SCH.

[0039] The second voltage determination unit 40 has a filter characteristic based on a discharge time constant defined by a filter capacitor C40 and the resistor R20, and a charge time constant defined by a filter capacitor C40 and a resistor R40, and when the second voltage determination unit 40 determines by means of a comparator 41 that the input signal SDD is smaller (lower) than the second reference voltage VrefL, then the second voltage determination unit 40 generates a second voltage determination signal SGC.

[0040] In the generation unit 60 for turn-on permission signals, when the turn-on / turn-off command signal indicates "turned on" and the short-circuit detection signal SSC is at a low level (Lo), the first voltage determination signal SCH is input into a preset input unit of a flip-flop circuit 66 by means of an internal logic circuit, so that it is logically combined, so that the turn-on permission signal SGD is kept at a high level (Hi).

[0041] When the second voltage determination signal SGC is generated, or at the time when the on / off command signal indicates "off", or when the short circuit detection signal SSC is generated, a reset input is performed on the flip-flop circuit 66 so that it is logically combined, so that the on-enabling signal SGD is kept in an off state.

[0042] In the short-circuit detection unit 50, the first voltage determination signal SCH is subjected to filter masking with a time constant of a resistor R50 and a filter capacitor C50 by means of an internal logic circuit, and if this is exceeded, a predetermined input is applied to the flip-flop circuit 51 so that the short-circuit detection state is maintained.

[0043] Regarding the reset of the flip-flop circuit 51, a configuration for performing the reset by means of a command from a microcomputer or the like, or a configuration for performing the reset with a predetermined time constant, can be used, or the flip-flop circuit 51 itself can be of a time-limited type, such as a monostable multivibrator. During a delay period until the turn-on / turn-off command signal SIN indicates a shift from "off" to "on" and the turn-on allow signal SGD indicates a shift from "off" to "on" by determination in the first voltage determination unit 30, if the first voltage determination signal SCH is held in a high-level state for the time constant of the filter or longer, a normal state will be erroneously detected as a short circuit.To prevent this, a short-circuit detection input signal SSS is logically combined with the switch-on enable signal SGD using a diode D50.

[0044] The gate driver unit 70A logically combines the enable signal SGD and the short-circuit detection signal SSC using an internal logic circuit, thus generating a buffer input signal GDD. The level of this buffer signal is shifted from a logic level to a level of the gate driver power supply VP by a level shifter circuit 72A, and its current is amplified by a buffer circuit 71A to charge / discharge the gate. The charge / discharge time constant is set by means of an enable gate resistor R70A and an enable gate resistor R71A. The configuration of the buffer circuit 71A and the setting procedure for charging / discharging the gate are not limited to those described above, and various configurations are possible, such as a buffer formed by a bipolar transistor and a constant-current driver circuit.

[0045] Fig. Figure 3 shows an example of a timing diagram of signals in a normal state in a specific example 1 of the driver device 10A for the reverse-conducting semiconductor switching element 90 according to embodiment 1. A period in which a load current Im is negative corresponds to a state in which the current flows through the diode D1 of the reverse-conducting semiconductor switching element 90. According to the present invention, the enable signal SGD can also indicate "off" even if the enable / disable command signal SIN is at a high level (Hi) during the above period.

[0046] Time t3 is the commutation point from the diode D1 lead to the IGBT_Z1 lead. Since a configuration is used where the turn-on enable signal SGD is changed to a turn-on state based on the first voltage determination signal SCH during a period when IGBT_Z1 is off, it is possible to adjust the timing as needed when a change from "off" to "on" is required. Conversely, time t11 is the transition point from a state where current flows through IGBT_Z1 of the reverse-conducting semiconductor switching element 90 to a state where current flows through diode D1. Because the turn-on enable signal SGD was in the turn-on state, the diode's forward voltage increases, causing the collector voltage Vce to assume a large negative value.This is detected by the second voltage determination unit 40, and at time t12 the switch-on allow signal SGD is changed to a switch-off state.

[0047] It is desirable that the first reference voltage VrefH, which is a reference value for the first voltage determination unit 30, is greater than the second reference voltage VrefL, which is a reference value for the second voltage determination unit 40. Fig. Figure 4 illustrates the reason and shows the collector voltage Vce and the second voltage determination signal SGC in the vicinity of time t12, at which the current from IGBT_Z1 to diode D1 is commutated.

[0048] Fig. Figure 4A shows a waveform in a case where the first reference voltage VrefH and the second reference voltage VrefL are equal. A case where the first reference voltage VrefH is smaller than the second reference voltage VrefL shows the same result as in the case above and is therefore not shown. Here, at time t12, it is detected that the forward voltage has increased as a result of the operation of the parasitic n-channel MOSFET, and the turn-on enable signal SGD transitions to an off state. As a result, the forward voltage decreases, so the turn-on enable signal SGD returns to an on state by the determination in the first voltage determination unit 30. Consequently, the forward voltage increases again.

[0049] The drawing shows a start signal SGS (allowance signal), a second voltage input signal SDD, a stop signal SGR (allowance signal), and a short circuit detection input signal SSS.

[0050] As described above, the following applies: If the voltage between the main terminals Vce of the reverse-conducting semiconductor switching element 90 is compared and determined using only a single reference voltage, there is the disadvantage that this potentially leads to oscillation, for example in the method disclosed in patent document 2. On the other hand, in Fig. 4B the first reference voltage VrefH is set so that it is greater than the second reference voltage VrefL, and the difference between them is set so that it is greater than the difference between the forward voltages that occur in the on and off states of the gate, so that it is possible to prevent oscillation of the turn-on allow signal SGD.

[0051] Fig. Figure 5 shows an example of a timing diagram of signals in a short-circuit case in specific Example 1 of the driver device 10A for the reverse-conducting semiconductor switching element 90 according to embodiment 1. If the upper branch and the lower branch forming the leg circuit are short-circuited at time t9, the collector voltage Vce, i.e., the first voltage input signal SDE, is held at a high level, so that the first voltage determination signal SCH assumes a high level (Hi) for a predetermined time. Consequently, the short-circuit detection signal SSC is generated, and the turn-on allow signal SGD is changed to a turn-off state.

[0052] The enable start signal SGS, the second voltage input signal SDD, the enable stop signal SGR and the short circuit detection input signal SSS are as shown in the drawing.

[0053] As described above, in the driver device 10A for the reverse-conducting semiconductor switching element 90 according to embodiment 1, the gate is prevented from being turned on when the diode D1 of the reverse-conducting semiconductor switching element 90 is in the conducting state, and even if the current is commutated to the diode D1 during the gate turn-on period, an increase in the forward voltage of the diode D1 can be prevented, and a breakdown due to a short circuit of type 3, which occurs during the gate turn-on period when the diode D1 is in the conducting state, can be prevented.

[0054] In particular, the first voltage determination unit 30 is formed by a general collector voltage detection (desat) configuration, and using this, both a function for changing the enable signal to a turn-on state and a function for detecting a short circuit are implemented, thus achieving further cost reduction. Furthermore, the gate turn-on time during the conducting state of diode D1 can be reduced to an extremely short time, e.g., a few hundred nanoseconds, so that breakdown due to a type 3 short circuit, which is a problem with reverse-conducting IGBTs, can be reliably prevented. Therefore, it is possible to adopt a highly versatile, low-cost collector voltage detection configuration without using an expensive short-circuit detection circuit. Design 2

[0055] Fig. Figure 6 is a block diagram showing a configuration of a driver unit 10B for a reverse-conducting semiconductor switching element 90 according to embodiment 2. Embodiment 2 differs from embodiment 1 in that the turn-on / turn-off command signal SIN is input to a gate driver unit 70B. The gate driver unit 70B drives the gate terminal Gs based on the turn-on / turn-off command signal SIN, in addition to the turn-on enable signal SGD. Consequently, by means of an operating mode of the reverse-conducting semiconductor switching element 90, which is obtained from a comparison between the above signals, the driver function for the gate terminal Gs can be implemented in such a way that the switching losses are reduced.

[0056] For example, Fig. Figure 7 is a block diagram showing a specific example 1 of the driver device 10B for the reverse-conducting semiconductor switching element. In a state where the turn-on enable signal SGD indicates an off state and the short-circuit detection signal SSC does not indicate short-circuit detection, the following applies: When the turn-on enable signal SGD transitions from an on state to an off state, i.e., at the timing when the conducting state of diode D1 ends, a pulse generation circuit 76B, for the falling edge receiving the turn-on / turn-off command signal SIN, generates a turn-on pulse of a predetermined width, so that the gate is turned on for a predetermined period.

[0057] Consequently, the parasitic n-channel MOSFET of the reverse-conducting semiconductor switching element 90 operates, and charge carriers accumulating inside are reduced, thus decreasing the recovery current in subsequent recovery operation and therefore reducing recovery losses. The width of the turn-on pulse is equal to or longer than the time required to reduce the accumulated charge carriers, and it is short, so the influence of the forward voltage rise on the losses is negligible.

[0058] To prevent a branch short circuit in a type 3 short circuit, the dead time provided between the upper branch and the lower branch of the leg circuit must be longer than the inrush pulse width. Fig. Figure 8 shows an example of a timing diagram of signals. At time t13, when the turn-on / turn-off command signal SIN indicates "off" during the conducting state of diode D1, a turn-on pulse with a predetermined width is output as a signal from buffer 71B. embodiment 3

[0059] Fig. Figure 9 is a block diagram showing a configuration example of a driver unit 10C for a reverse-conducting semiconductor switching element 90 according to embodiment 3. Compared with embodiment 1, in embodiment 3 the IGBT_Z1 to be driven is a dual-gate semiconductor switching element having two gate terminals Gs1 and Gs2, and accordingly, two gate driver units 70C1 and 70C2 are provided. Fig. Figure 10 is a block diagram showing a specific example of the driver device 10C for the reverse conducting semiconductor switching element.

[0060] The first gate driver unit 70C1, for driving the first gate terminal Gs1, has a fall-off delay circuit 75C1 on its input side and is therefore configured to delay the fall-off time of the turn-on enable signal SGD. The second gate driver unit 70C2, for driving the second gate terminal Gs2, has a rise-off delay circuit 75C2 on its input side and is therefore configured to delay the rise-off enable signal SGD.

[0061] In a time diagram of the signals, shown in Fig. 11, consequently, at times t5 and t8, the switch-off time of the output voltage of buffer 71C1 is delayed relative to the switch-off time of the output voltage of buffer 71C2, and at times t4 and t7, the switch-on time of the output voltage of buffer 71C2 is delayed relative to the switch-on time of the output voltage of buffer 71C1. In the dual-gate semiconductor switching element, a time difference between the two gate voltages is provided, as described above, so that switch-off and switch-on losses can be reduced, and embodiment 3 is a configuration to implement this. Design 4

[0062] Fig. Figure 12 is a block diagram showing a configuration example of a driver device 10D for a reverse-conducting semiconductor switching element 90 according to embodiment 4. Embodiment 3 uses a parallel-type configuration in which, through the respective gate voltages of the dual-gate semiconductor switching element, cells connected to the respective gate terminals independently form channels, whereas embodiment 4 differs in that a series-type split-gate configuration is used, in which channels are formed in a state where both split gates are switched on.

[0063] Compared to the driver unit 10C for the reverse-conducting semiconductor switching element according to embodiment 3, the driver unit 10D for the reverse-conducting semiconductor switching element according to embodiment 4 has a configuration in which an input signal to the first gate driver unit 70D1, which is one of the gate driver units, is the turn-on / turn-off command signal SIN from a higher-order logic unit, instead of the turn-on enable signal SGD. The configuration of the second gate driver unit 70D2 is equivalent to that of the gate driver unit 70A according to embodiment 1.

[0064] Fig. Figure 13 is a block diagram showing a specific example 1 of the driver device 10D for the reverse-conducting semiconductor switching element 90 according to embodiment 4, and the difference from embodiment 3 is that the turn-on / turn-off command signal SIN is directly input into a level shifter circuit 72D1 of the first gate driver unit 70D1. In a timing diagram of the signals, as in Fig. As shown in Figure 14, the on / off command signal SIN is therefore reproduced as it is, specifically for buffer 71D1.

[0065] The output voltage of buffer 71D1 is generated appropriately by a method based on comparing and determining the voltage between the main terminals Vce with two reference voltages VrefH and VrefL, as in the present invention. Therefore, the effects of preventing a rise in forward voltage and preventing breakdown due to a type 3 short circuit can be achieved even with the series-type split-gate semiconductor switching element, as described above.

[0066] In embodiments 1 to 4, the driver device for the reverse-conducting semiconductor switching element according to the present invention is described. The following describes power converter devices, such as an inverter, a boost converter, and a boost converter inverter obtained by combining these, configured using the driver device for the reverse-conducting semiconductor switching element, with reference to Fig. 15 to Fig. 17 described.

[0067] Power converter devices, such as an inverter, shown in Fig. 15, a boost converter, shown in Fig. 16, and a boost converter inverter, shown in Fig. 17, which is obtained by combining these, are configured using one or a plurality of leg circuits 91, each formed from an upper branch and a lower branch, wherein a plurality of reverse-conducting semiconductor switching elements 90 are connected in series. The reverse-conducting semiconductor switching element 90 is configured, as an example, as an IGBT module in which an IGBT and a diode are connected antiparallel, and the current flows alternately through the IGBT or diode of the upper branch and the diode or IGBT of the lower branch, according to the direction of the load current. Design 5

[0068] Fig. Figure 15 shows a configuration of a power converter device as an inverter according to embodiment 5. A power converter device 100A comprises a power converter 101 with a plurality of reverse-conducting semiconductor switching elements 90, and a driver device 10X for reverse-conducting semiconductor switching elements, each of which drives each of the reverse-conducting semiconductor switching elements 90 in the power converter 101. In this case, the power converter device 100A is an inverter that converts DC energy from a DC power supply 94 into AC energy and supplies the AC energy to an AC motor 92.

[0069] For each of the backward conducting semiconductor switching elements 90, the driver device 10A for the backward conducting semiconductor switching element is arranged according to embodiment 1, and a set of driver devices 10A for the backward conducting semiconductor switching elements is defined as the driver device 10X in the present embodiment.

[0070] The power converter 101 has a three-phase (U, V, W) configuration and is an inverter circuit that includes a smoothing capacitor 93 between the DC buses and the leg circuits 91 for the respective phases. The leg circuit 91 for each phase is configured such that the upper branch and the lower branch, each having the reverse-conducting semiconductor switching element 90, are connected in series.

[0071] In the present embodiment, the reverse-conducting semiconductor switching elements 90 in the power converter 101 are driven by the driver device 10X, which comprises a plurality of the driver devices 10A for the reverse-conducting semiconductor switching elements according to embodiment 1. Consequently, with a low-cost configuration, an increase in forward voltage due to gate turn-on when the diode is in the conducting state can be prevented, and breakdown due to a type 3 short circuit can be prevented, so that the power converter device 100A is obtained with low losses and high reliability.

[0072] In the example above, the power converter 101 outputs the AC voltage at two levels, positive and negative. However, the power converter 101 can also be an inverter, having any number of reverse-conducting semiconductor switching elements 90 connected in series and parallel, and capable of multi-level voltage output. In this case as well, the power converter 101 has a configuration featuring the leg circuit 91, in which the upper and lower branches, each having the reverse-conducting semiconductor switching element 90, are connected in series. Design 6

[0073] Fig. Figure 16 shows a configuration of a power converter device as a boost converter according to embodiment 6. A power converter device 100B has a power converter 102 with a plurality of backward conducting semiconductor switching elements 90, and the backward conducting semiconductor switching element driver device 10X, which drives each of the backward conducting semiconductor switching elements 90 in the power converter 102.

[0074] In this case, the power converter unit 100B operates as a boost converter, which steps up the DC voltage of the DC power supply 94 and supplies the stepped-up DC voltage to the DC load 92A. As described above, the driver unit 10X for the reverse-conducting semiconductor switching elements is a set of driver units 10A for the reverse-conducting semiconductor switching elements, each of which drives the reverse-conducting semiconductor switching elements 90.

[0075] The power converter 102 has a smoothing capacitor 95 on the input side, a smoothing capacitor 97 on the output side, the leg circuit 91, and a boost-conversion coil 96. The leg circuit 91 is configured such that the upper branch and the lower branch, each having the reverse-conducting semiconductor switching element 90, are connected in series.

[0076] In this case too, a low-cost configuration can prevent an increase in forward voltage due to gate activation when the diode is in the conducting state, and a breakdown due to a type 3 short circuit can be prevented, thus obtaining the 100B power converter device with low losses and high reliability.

[0077] Although the boost converter in Fig. As shown in Figure 16, a step-down converter or a step-down-boost converter, which is obtained by combining a step-up converter and a step-down converter, can also be used. Design 7

[0078] Fig. Figure 17 shows a configuration of a power converter device as a boost-conversion inverter, formed by combining an inverter and a boost-conversion power converter, according to embodiment 7. A power converter device 100C has a main circuit (power converter), wherein the power converter 102, shown in Fig. 16, with the DC side of the power converter 101, shown in Fig.15, is connected, and the driver unit 10X, which drives the reverse-conducting semiconductor switching elements 90. In this case, in the converter unit 100C, the DC voltage of the DC power supply 94 is step-up by the converter 102, the step-up DC energy is converted into AC energy by the converter 101, and the AC energy is supplied to the AC motor 92. The converter unit 100C operates as a step-up inverter system and is used, for example, in an electric vehicle.

[0079] In this case too, a low-cost configuration can prevent an increase in forward voltage due to gate activation when the diode is in the conducting state, and a breakdown due to a type 3 short circuit can be prevented, thus obtaining the 100C power converter device with low losses and high reliability.

[0080] The converter 101 in the converter unit 100C can be an inverter capable of multi-level voltage output. The converter 102 in the converter unit 100C is not limited to a boost converter and can be a buck converter or a buck-boost converter obtained by combining a boost converter and a buck converter.

[0081] The driver device 10A for the reverse conducting semiconductor switching element according to embodiment 1 is used as an example for the driver device 10X for the reverse conducting semiconductor switching elements. However, the driver devices 10B to 10D for the reverse conducting semiconductor switching element according to embodiments 2 to 4 can also be used to achieve the same effects. In this case as well, the driver device 10X for the reverse conducting semiconductor switching elements is a set of driver devices 10B to 10D for the reverse conducting semiconductor switching elements, each of which drives the reverse conducting semiconductor switching elements 90.

[0082] In the embodiments described above, all reverse-conducting semiconductor switching elements 90 are described as reverse-conducting IGBTs. However, a wide-bandgap semiconductor material can also be used for some of the reverse-conducting semiconductor switching elements 90. In this case, the switching operations of the reverse-conducting semiconductor switching elements 90 can be performed quickly, and the boost-conversion coil 96 can be made smaller. Silicon carbide (SiC), gallium nitride, a gallium oxide-based material, or diamond can be used as a wide-bandgap semiconductor material.

[0083] Although the invention is described above in the form of various exemplary embodiments and implementations, it is understood that the various features, aspects and functions described in one or more of the individual embodiments are not limited in their applicability to the individual embodiment in which they are described, but can instead be applied - alone or in various combinations - to one or more of the embodiments of the invention.

[0084] It is therefore understood that numerous modifications can be used that are not described by way of example without deviating from the scope of the present invention. For example, at least one of the components can be modified, added, or omitted. At least one of the components described in at least one of the preferred embodiments can be selected and combined with the components mentioned in another preferred embodiment. Description of the reference symbols 10A to 10D, 10X driver device for reverse conducting semiconductor switching element 20 voltage reduction units 30 first voltage determination unit 40 second voltage determination unit 50 Short-circuit detection unit 60 Generation unit for switch-on permission signals 70A, 70B Gate Driver Unit 70C1, 70D1 first gate driver unit 70C2, 70D2 second gate driver unit 90 reverse-conducting semiconductor switching element 91 Leg shift 92 AC motor 92A DC load 93, 95, 97 Smoothing capacitor 94 DC power supply 96 Upward conversion coil 100A to 100C power converter unit 101, 102 Power converters SIN On / Off Command Signal SDE first voltage input signal SCH first voltage determination signal SGS activation authorization start signal SDD second voltage input signal SGC second voltage determination signal SGR activation permission stop signal SSS short-circuit detection input signal SSC short-circuit detection signal SGD activation permission signal GDD buffer input signal QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2008 - 72 848 A

[0013] Cited non-patent literature

[0000] Simulation studies for short-circuit current crowding of MOSFET-Mode IGBT", ISPSD, 2014

[0014]

Claims

[1] Driver device for a reverse conducting semiconductor switching element, comprising a semiconductor switching element having a first main terminal, a second main terminal and a gate terminal and a rectifier element connected antiparallel to the semiconductor switching element, wherein the driver device comprises: a power-on enable signal generation unit that receives a power-on / power-off command signal to turn on or off the reverse-conducting semiconductor switching element and generates a power-on enable signal; a gate driver unit that receives the enable signal and generates a driver voltage to be applied to the gate terminal; and a voltage determination unit which receives a voltage between the main terminals - between the first main terminal and the second main terminal - and performs a comparison and a determination each with a first reference voltage and a second reference voltage which is different from the first reference voltage, wherein The enable signal generation unit is configured to logically combine a determination signal from the voltage determination unit and the enable / disable command signal. If the voltage between the main terminals is greater than the first reference voltage during a period when the reverse-conducting semiconductor switching element is off, the enable signal is set to an enable state. If the voltage between the main terminals is less than the second reference voltage during a period when the reverse-conducting semiconductor switching element is off, the enable signal is set to an off state. [2] Driver device for a backward conducting semiconductor switching element according to claim 1, the voltage determination unit has the following features: a first voltage determination unit comprising a comparator and performing a comparison and determination between the voltage between the main terminals and the first reference voltage, and a second voltage determination unit, which includes a comparator and performs a comparison and determination between the voltage between the main terminals and the second reference voltage, and wherein the enable signal generation unit brings the enable signal into an enable state or an off state based on a logical combination of a first voltage determination signal from the first voltage determination unit and the enable / disable command signal, and a logical combination of a second voltage determination signal from the second voltage determination unit and the enable / disable command signal. [3] Driver device for a backward conducting semiconductor switching element according to claim 1 or 2, wherein the generation unit for enable signals has a state-hold circuit, and If the enable signal is changed to an enable state, the enable signal is held in the enable state by the state-hold circuit until the enable signal changes to an off state or the enable / disable command signal indicates off, and if the enable signal is changed to an off state, the enable signal is held in the off state by the state-hold circuit until the enable signal changes to an enable state. [4] Driver device for a backward conducting semiconductor switching element according to one of claims 1 to 3, wherein the first reference voltage of the voltage determination unit is greater than the second reference voltage. [5] Driver device for a backward conducting semiconductor switching element according to one of claims 1 to 4, wherein the second reference voltage of the voltage determination unit is zero or a negative value. [6] Driver device for a backward conducting semiconductor switching element according to any one of claims 1 to 5, further comprising a short-circuit detection unit which receives the enable signal and the determination signal from the voltage determination unit and, when the enable signal is in an enable state and the voltage between the main terminals is greater than the first reference voltage, determines a short-circuit state of the reverse-conducting semiconductor switching element, and The enable signal generation unit receives a detection signal from the short-circuit detection unit, and if a short circuit of the reverse-conducting semiconductor switching element is detected, the enable signal generation unit changes the enable signal to an off state. [7] Driver device for a backward conducting semiconductor switching element according to claim 6, wherein the short-circuit detection unit has a state-holding circuit which maintains a state in which the short circuit of the backward conducting semiconductor switching element is detected for at least a predetermined period of time. [8] Driver device for a reverse conducting semiconductor switching element according to claim 6 or 7, wherein the gate driver unit generates the driver voltage to be applied to the gate terminal by logically combining the detection signal from the short-circuit detection unit and the enable signal. [9] Driver device for a backward conducting semiconductor switching element according to one of claims 1 to 8, wherein a voltage reduction unit is arranged between the voltage determination unit and the first main terminal and reduces the voltage between the main terminals that is to be applied to the voltage determination unit. [10] Driver device for a backward conducting semiconductor switching element according to any one of claims 1 to 9, wherein the gate driver unit receives the turn-on enable signal and the turn-on / turn-off command signal and generates the driver voltage to be applied to the gate terminal, and If the enable signal is in the off state and the enable / disable command signal has transitioned from a state indicating that it is on to a state indicating that it is off, the enable signal is brought into an enable state for an initial holding period. [11] Driver device for a reverse conducting semiconductor switching element according to one of claims 1 to 10, wherein the reverse conducting semiconductor switching element is a multi-gate semiconductor switching element in which the gate terminal has at least one first gate terminal and at least one second gate terminal which is different from the first gate terminal. [12] Driver device for a backward conducting semiconductor switching element according to claim 11, the gate driver unit has the following features: a first gate driver unit that receives the turn-on enable signal or the turn-on / turn-off command signal and generates the driver voltage to be applied to the first gate terminal, and a second gate driver unit that receives the power-on enable signal and generates the driver voltage to be applied to the second gate terminal, and The first and second gate driver units have different timings of the driver voltages that are to be applied to the first and second gate terminals, respectively. [13] Driver device for a reverse-conducting semiconductor switching element according to claim 12, wherein the first gate driver unit has a delay circuit which delays the turn-off time of the turn-on enable signal, and wherein the second gate driver unit has a delay circuit which delays the turn-on time of the turn-on enable signal. [14] Power converter device comprising the following: reverse-conducting semiconductor switching elements, each of which incorporates a semiconductor switching element with a first main terminal, a second main terminal and a gate terminal, and a rectifier element connected antiparallel to the semiconductor switching element; at least one leg circuit in which an upper branch and a lower branch, each comprising the reverse-conducting semiconductor switching element, are connected in series; and Driver devices for backward conducting semiconductor switching elements, each arranged for the backward conducting semiconductor switching elements of the upper branch and the lower branch, wherein Each of the driver devices for the reverse-conducting semiconductor switching elements has the following features: a power-on enable signal generation unit that receives a power-on / power-off command signal to turn on or off the reverse-conducting semiconductor switching element and generates a power-on enable signal, and a gate driver unit that receives the power-on enable signal and generates a driver voltage to be applied to the gate terminal, and wherein, if the voltage between the main terminals - between the first main terminal and the second main terminal - is greater than the first reference voltage during a period in which the reverse-conducting semiconductor switching element is off, the enable signal generator sets the enable signal to an on state, and if the voltage between the main terminals is less than the second reference voltage, which is different from the first reference voltage, the enable signal generator sets the enable signal to an off state. [15] Power converter device according to claim 14, wherein a dead time provided between the on / off command signal for the upper branch and the on / off command signal for the lower branch is specified such that it is longer than a predetermined time, and The time is an initial hold time to keep the power-on allow signal in the power-on state when the power-on allow signal is in an off state and the power-on / off command signal has transitioned from a state indicating power-on to a state indicating power-off.

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