N-conducting transistor fabrication in complementary FET (CFET) devices

Abstract

N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs), vertically stacked on p-type GAAFETs in complementary FET (CFET) devices, comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. These non-crystalline silicon layers can be formed via deposition, which can provide a simplified processing flow for creating the intermediate dielectric layer between the n-type and p-type GAAFETs compared to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over US patent application number 18 / 346,106, filed on June 30, 2023, entitled “N-TYPE TRANSISTOR MANUFACTURING IN COMPLEMENTARY FET (CFET) DEVICES”, which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] In some proposed complementary field-effect transistor (CFET) devices, an n-type gate all-around (nanoband, nanosheet, nanowire) field-effect transistor (GAAFET) is vertically stacked with a p-type GAAFET. The vertical stacking of n-type and p-type GAAFETs in CFET devices can enable increased transistor packing density in the x and y dimensions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figures 1A-1C are cross-sectional views of exemplary CFET devices incorporating HPTFT materials. Fig. Figures 2 to 7A-7C illustrate an exemplary simplified process sequence for forming the exemplary CFET structures, which include HPTFT materials, as described in Fig. 1A-1C are illustrated. Fig. Figure 8 is an exemplary method for forming a CFET device using HPTFT materials. Fig. Figure 9 is a top view of a wafer and dies that may be included in a microelectronic assembly according to any of the embodiments disclosed herein. Fig. Figure 10 is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly disclosed herein. Fig. Figures 11A-11D are perspective views of exemplary planar, FinFET, gate all-around and stacked gate all-around transistors. Fig. 12A and Fig. Figure 12B shows perspective and cross-sectional views of exemplary forksheet gate all-around transistors. Fig. 13A and Fig. Figure 13B shows perspective and cross-sectional views of an exemplary complementary field-effect transistor (CFET) architecture. Fig. Figure 14 is a cross-sectional side view of an assembly of an integrated circuit device, which may include one or more of the microelectronic assemblies disclosed herein. Fig. Figure 15 is a block diagram of an exemplary electrical device which may include a microelectronic assembly, according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0003] Complementary field-effect transistor (CFET) devices are being considered to enable the continuous scaling of transistor packing density in future semiconductor manufacturing technology nodes. In CFET devices, an n-type gate all-around FET (GAAFET) is vertically stacked with a p-type GAAFET. Integrating a monolithic CFET device formation (where both the n-type and p-type GAAFETs are formed on the same substrate) into semiconductor fabrication processes presents significant challenges. One challenge is integrating an intermediate dielectric layer positioned between the p-type and n-type GAAFETs. In some proposed CFET processing flows, the formation of an intermediate dielectric layer begins with the formation of a sacrificial layer on the p-type GAAFET.The sacrificial layer acts as a nucleation layer for the epitaxial growth of silicon-based source, drain, and channel regions of the n-type GAAFET and intervening sacrificial layers. The sacrificial layer and intervening sacrificial layers can, for example, consist of silicon germanium. The sacrificial layer is eventually removed by etching, and the resulting cavity is filled with dielectric material to create the middle dielectric layer. Forming the middle dielectric layer in such processes can present challenges. For example, the sacrificial layer must be removed from a trench without affecting the channel regions of the n-type and p-type GAAFETs above and below the sacrificial layer.

[0004] This document discloses CFET devices that can be formed using high-performance thin-film transistor (HPTFT) materials for the source, drain, and channel regions of an n-type GAAFET, wherein the n-type GAAFET is stacked on a p-type GAAFET. These HPTFT materials, comprising non-crystalline silicon, can be formed by deposition. The deposited HPTFT layers can form the n-type GAAFET source, drain, and channel regions, or these regions can be formed by structuring a deposited HPTFT layer. These non-crystalline silicon HPTFT materials are back-end-of-line (BEOL) compatible. The use of non-crystalline silicon for the n-conducting GAAFET source, drain, and channel regions can provide process simplicity compared to the sacrificial layer approach in generating a middle dielectric layer described above.Nanoribbons of non-crystalline silicon form the n-conducting transistor source, drain, and channel regions, and the dielectric sacrificial layers formed between the nanoribbons during GAAFET formation can be formed by deposition rather than epitaxial growth, which requires the growth of a sacrificial layer to act as the seed layer for the epitaxially grown films, followed by removal of the sacrificial layer and refilling with the desired dielectric material to form the middle dielectric layer.

[0005] The following description sets out specific details; however, embodiments of the technologies described herein can be implemented without these specific details. Well-known circuits, structures, and techniques have not been shown in detail so as not to complicate the understanding of the present description. Expressions such as "one embodiment," "different embodiments," "some embodiments," and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the specific features, structures, or characteristics.

[0006] Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of the same object being referred to. Such adjectives do not imply that objects so described must be present in any given sequence, whether temporally or spatially, in any order of precedence, or in any other way. “Connected” may indicate that elements are in direct physical or electrical contact with one another, and “coupled” may indicate that elements work together or interact, although they may, but need not, be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0007] Terms modified by the phrase "essentially" include arrangements, orientations, spacings, or positions that differ slightly from the meaning of the unmodified term. For example, the section of a first layer or feature that is essentially perpendicular to a second layer or feature may include a first layer or feature located ±20 degrees from a second layer or feature; a first surface that is essentially parallel to a second surface may include a first surface that is within several degrees of the second surface; and a layer that is essentially planar may include layers that contain some depressions, contact bumps, or other non-planar features resulting from processing variations and / or constraints.

[0008] The term “positioned between” used here in the context of a first layer or component positioned between a second layer or component and a third layer or component refers to the first layer or component being directly physically attached to the second and third parts or components (no layers or components between the first and second layer or component or the first and third layer or component) or being physically attached to the second and third layer or component with one or more intervening layers or components.

[0009] As used herein, the term "adjacent" refers to layers or components that are in physical contact with one another. That is, there is no layer or component between the aforementioned adjacent layers or components. For example, a layer X positioned adjacent to a layer Y refers to a layer that is in physical contact with layer Y.

[0010] Certain terminology may be used here solely for the purpose of reference and is therefore not intended to be restrictive. For example, expressions such as "upper," "lower," "above," "below," "below," "above," "lateral," and "vertical" refer to directions within the figures being referenced. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of parts of the component within a consistent but arbitrary frame of reference, which is clarified by referring to the text and the associated figures that describe the component under discussion. This terminology may include the words specifically mentioned above, derivatives thereof, and words with similar meanings.

[0011] As used here, the term "integrated circuit component" refers to a packaged or unpackaged integrated circuit product. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, with the integrated circuit dies and the package substrate encapsulated in an encapsulation material such as metal, plastic, glass, or ceramic. In one example, a packaged integrated circuit component contains one or more processor units mounted on a substrate, with one outer surface of the substrate comprising a solder ball grid array (BGA). In an example of an unpackaged integrated circuit component, a single monolithic integrated circuit die comprises solder pad mounds attached to contacts on the die. The solder pad mounds allow the die to be mounted directly onto a printed circuit board.An integrated circuit component may include one or more of the computer system components described or referenced herein, or any other computer system component, such as a processing unit (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller.

[0012] Reference is now made to the drawings, which are not necessarily drawn to scale, and which may use similar or identical numbers to denote the same or similar parts in different figures. The use of similar or identical numbers in different figures does not imply that all figures containing similar or identical numbers represent a single or identical embodiment. Identical reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not as a limitation, various embodiments discussed in this document.

[0013] The following description presents numerous specific details for illustrative purposes, in order to provide a comprehensive understanding. However, it may be obvious that the novel embodiments can be implemented without these specific details. In other cases, known structures and devices are shown in block diagram form to simplify their description. It is understood that all modifications, equivalences, and alternatives are covered by the scope of protection of the claims.

[0014] Fig. Figures 1A-1C are cross-sectional views of exemplary CFET devices incorporating HPTFT materials. Fig. Figure 1A illustrates a cross-sectional view of a structure 200, which includes adjacent CFET devices 100 and 102, and CFET device 1300, which is located in Fig. 13A illustrates a similar situation. The cross-sectional view from Fig. 1A is taken along a line extending through the source, drain, and gate regions of CFET devices 100 and 102, and is similar to a cross-sectional view of CFET device 1300 along line CC' in Fig. 13A. The cross-sectional view from Fig. 1B is taken along a line extending through a source or drain region of the CFET device 100 and is similar to a cross-sectional view of the CFET device 1300 along line DD' in Fig. 13A is taken. The cross-sectional view from Fig. 1C is taken along a line extending through the gate region of CFET device 100 and is similar to a cross-sectional view taken along line BB' of CFET device 1300 in Fig. 13A is taken.

[0015] Each of the CFET devices 100 and 102 comprises an n-type GAAFET 104 and a p-type GAAFET 106 stacked vertically over a substrate 108, with the n-type GAAFET 104 positioned above the p-type GAAFET 106. A middle dielectric layer 112 is positioned between the GAAFETs 104 and 106 to insulate them from each other. Each p-type GAAFET 106 comprises nanoribbons (layers, nanosheets, nanowires) 114 (114a-114d) stacked vertically with respect to a surface 116 of the substrate 108. The nanoribbons 114 are substantially planar and substantially parallel to each other. Each nanoband 114 comprises silicon and includes a p-conducting source region 118, a p-conducting drain region 120 and a channel region 123, which is positioned laterally between the p-conducting source region and the p-conducting drain region 118 and 120.The p-type source and drain regions 118 and 120 comprise a p-type dopant. The channel regions 123 are further positioned vertically between two gate regions 124. Each gate region 124 comprises a dielectric gate layer 128 surrounding a gate electrode 126. The p-type drain regions 120 are conductively coupled via ends 169 of the p-type drain regions 120, which are positioned adjacent to a first source or drain contact region. The p-type source regions 118 are conductively coupled via ends 171 of the p-type source regions 118, which are adjacent to a second source or drain contact region (in ). Fig. 1A). The first source or drain contact area is located in Fig. 1A is also not illustrated and is adjacent to a region 184, which may contain a conductive material (such as n-doped silicon), along a first distance on the x-axis that differs from a second distance along the x-axis where the third and fourth drain or source contact regions (explained below) are located (such as the point along the x-axis where the cross-sectional view of Fig. 1A is taken), positioned. This is because the first and second source or drain contact regions must extend through n-type GAAFETs to reach the source and drain regions of the p-type GAAFET 106.

[0016] Each p-type GAAFET 106 further comprises several spacer regions 180a-180e, which are stacked vertically with respect to the substrate surface 116, are substantially planar, and substantially parallel to each other. The spacer regions 180a-180e isolate the gate regions 124 from source or drain contacts. A bottommost spacer region 180e (the spacer region 122 closest to the substrate 108) is positioned between a section of the bottommost nanoband 114d (the nanoband 114 closest to the substrate 108) and the substrate surface 116. A first section 130 of the lowest spacer region 180e is positioned between a p-conducting source region 118 of the lowest nanoband 114d and the substrate 108, and a second section 132 of the lowest spacer region 180e is positioned between the p-conducting drain region 120 of the lowest nanoband 114d and the substrate 108.An uppermost spacer region 180a (the spacer region 122 closest to the middle dielectric layer 112) is positioned between a section of the uppermost nanoband 114a (the nanoband 114 closest to the middle dielectric layer 112) and the middle dielectric layer 112. A first section 134 of the uppermost spacer region 180a is positioned between the p-type source region 118 of the uppermost nanoband 114a and the middle dielectric layer 112, and a second section 136 of the uppermost spacer region 180a is positioned between the p-type drain region 120 of the uppermost nanoband 114a and the middle dielectric layer 112.For each of the spacer regions 180b, 180c, and 180d, a first section 138 of these spacer regions is positioned adjacent to at least one section of the p-conducting source regions 118 of two of the nanobands 114, and a second section 140 of these spacer regions is positioned adjacent to at least one section of the p-conducting drain regions 120 of two of the nanobands 114. Alternatively, the first and second sections of each of the spacer regions 180a-180e are located on either side of a gate region 124.

[0017] Each n-type GAAFET 104 comprises four nanobands 142 (142a-142d) stacked vertically with respect to the substrate surface 116. The nanobands 142 are essentially planar and substantially parallel to each other. Each nanoband 142 comprises silicon and includes an n-type source region 144, an n-type drain region 146, and a channel region 148 positioned laterally between the n-type source and drain regions 144 and 146. The channel regions 148 are further positioned vertically between two gate regions 150. Each gate region 150 comprises a dielectric gate layer 154 and a gate electrode 152. For the uppermost gate region 150 (the gate region furthest from the substrate 108), the dielectric gate layer 154 is positioned between the gate electrode 152 and the uppermost channel region 148. For the other gate regions 150, the dielectric gate layer 154 surrounds the gate electrode 152.In some embodiments, the uppermost gate region may not include a gate electrode 152, and the uppermost gate dielectric region may be positioned adjacent to a gate contact region (e.g., 178, 179). The gate regions 150 and 124 of the CFET devices 100 and 102 are conductively coupled by gate contact regions 178 and 179, respectively. A portion of the gate contact regions 178 and 179 is positioned adjacent to the nanoribbon 142a, with the nanoribbon 142a being positioned furthest from the middle dielectric layer 112. The n-conducting source areas 144 are conductively coupled via ends 189 of the n-conducting source areas 144, which are positioned adjacent to a third source or drain contact area 186, and the n-conducting drain areas 146 are conductively coupled via ends 181 of the n-conducting source areas, which are positioned adjacent to a fourth source or drain contact area (in . Fig. 1A). A dielectric region 182 is located between the third source or drain contact region 186 and region 184 (which may include epitaxially grown n-doped silicon).

[0018] Each n-type GAAFET 104 further comprises several spacer regions 180f-180i, which are stacked vertically with respect to the substrate surface 116, are substantially planar and substantially parallel to each other. A bottommost spacer region 180i (the spacer region 168 that is positioned closest to the middle dielectric layer 112) is positioned between a section of the bottommost nanoband 142d (the nanoband 142 that is positioned closest to the middle dielectric layer 112) and the middle dielectric layer 112. A first section 170 of the bottom spacer region 180i is positioned between an n-conducting source region 144 of the bottom nanoband 142d and the middle dielectric layer 112, and a second section 172 of the bottom spacer region 180i is positioned between the n-conducting source region 146 of the bottom nanoband 142d and the middle dielectric layer 112.For each of the spacer regions 180f, 180g, and 180h, a first section 174 of these spacer regions is positioned adjacent to at least one section of the n-conducting source regions 144 of any two of the nanobands 142, and a second section 176 of these spacer regions is positioned adjacent to at least one section of the n-conducting drain regions 146 of any two of the nanobands 142. Alternatively, the first and second sections of each of the spacer regions 180f-180i are located on either side of a gate region 150. The spacer regions 180j-m for separating the gate contact regions 178 and 179 from source or drain contacts (e.g., 186) are positioned adjacent to the gate contact regions 178 and 179.

[0019] The nanobands 142, which form the source, drain, and channel regions of the n-type GAAFET 106, comprise non-crystalline silicon, an HPTFT material. The non-crystalline silicon can comprise amorphous and / or polycrystalline silicon. The n-type source and drain regions 144 and 146 of the nanobands 142 of the n-type GAAFETs 104 comprise an n-type dopant, such as phosphorus, arsenic, antimony, or another suitable n-type silicon dopant. The p-type source and drain regions 118 and 120 of the nanobands 114 of the p-type GAAFETs 106 comprise a p-type dopant, such as boron, gallium, or any other suitable p-type silicon dopant.

[0020] The dielectric layers 180a-180e, 142a-142d, 180 and 182 can be coated with a suitable nitride or oxide such as silicon nitride (Si3N4), silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, a material comprising silicon, oxygen and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, a material comprising fluorine, silicon and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, a material comprising silicon, oxygen and hydrogen).

[0021] The dielectric gate layers 128 and 154 can comprise one or more layers comprising any of the materials that can be part of any dielectric gate layer described or referenced herein, such as the gate dielectric of gate 1122. The dielectric gate layers 128 can comprise the same or different materials as the dielectric layers 154. The gate electrodes 126 for the p-type GAAFETs 106 can comprise any material that can be part of any gate electrode for a p-type transistor described herein, such as the gate dielectric of gate 1022 for a p-type (PMOS) transistor. The gate electrodes 152 for the n-type GAAFETs 104 can comprise any material that can be part of any gate electrode for an n-type transistor described herein, such as the gate dielectric of gate 1022 for an n-type (NMOS) transistor.

[0022] The first, second, third, and fourth source or drain contacts (e.g., 186) and the gate contact regions 178 and 179 may comprise one or more metal layers. In some embodiments, these source, drain, and gate contacts may include a filler layer (trench, plug) comprising tungsten, cobalt, titanium, gold, aluminum, molybdenum, chromium, nickel, or another suitable metal. The source, drain, and gate contacts disclosed herein may include one or more additional metal layers for other purposes, such as one or more barrier layers positioned between a filler metal layer and a source or drain region, and a contact metal layer positioned adjacent to a source or drain region.A barrier layer can reduce the amount of metal that diffuses from the filler metal layer to a source or drain region and / or prevent or reduce oxidation of a contact metal layer between the formation of the contact metal layer and the formation of the filler metal layer. A barrier layer can be cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (a material comprising titanium and nitrogen (e.g., Tan, Ta₂N, Ta₃N₅)), indium oxide (In₂O₃, a material comprising indium and oxygen), tungsten nitride (a material comprising tungsten and nitrogen (e.g., W₂N, W₃N₅), titanium nitride (TiN, a material comprising titanium and nitrogen), or another suitable material. A contact metal layer can be titanium, tantalum, hafnium, zirconium, niobium, or another suitable metal.Substrate 108 can comprise any of the materials that can be part of any substrate described or referenced herein, such as substrate 1002.

[0023] Fig. Figures 2 to 7A-7C illustrate an exemplary simplified process sequence for forming the exemplary CFET structures, which include HPTFT materials, as described in Fig. 1A-1C are illustrated.

[0024] Fig. Figure 2 is a cross-sectional view of an exemplary structure 200 after the formation of vertically stacked first sacrificial layers 202, which are nested with the first layers 114 on the substrate 108. The substrate 108 can comprise silicon, and the first sacrificial layers 202 can comprise silicon germanium. The first layers 114 and the first sacrificial layers 202 can be grown epitaxially. The first layers 114 comprise silicon and a p-type dopant, which can be incorporated into the first layers during or after (e.g., via an implantation step) epitaxial growth.

[0025] Fig. Figure 3 is a cross-sectional view of the structure 200 after the formation of the middle dielectric layer 112, the second layers 142, and the second sacrificial layers 204. The middle dielectric layer 112 is formed on top of the first sacrificial layer 202. The second layers 142 are nested with the second sacrificial layers. The second sacrificial layers 204 comprise a dielectric (such as an oxide and nitride dielectric). The second layers 142 comprise non-crystalline silicon. The second layers 142 and the second sacrificial layers 204 are formed by deposition. The second sacrificial layer 204 closest to the middle dielectric layer 112 is deposited on top of the middle dielectric layer 112, and each of the second layers 142 is deposited on top of one of the second sacrificial layers 204.As previously mentioned, the ability to epitaxially grow the silicon layers (second layers 142a-142d), which become the source, drain, and channel regions of the n-type GAAFET in a CFET structure, can provide processing advantages over processes that epitaxially grow the second layers 142. The second layers 142 comprise an n-type dopant that can be incorporated into the first layers during or after epitaxial growth of the second layers 142.

[0026] Fig. 4A and Fig. Figure 4B illustrates cross-sectional views of the structure 200 after the formation of trenches 208 via etching to create columns 210 and 212, which eventually become CFET devices 100 and 102. Fig. 4A-4B, 5A-5C, 6A-6C and 7A-7C, these are figures “A”, “B” and “C”, cross-sectional views of structure 200 along lines similar to those shown in the cross-sectional views from Fig. 1A, Fig. 1B and 1C are linked.

[0027] Fig. Figures 5A-5C illustrate cross-sectional views of the structure 200 after removal of the first and second sacrificial layers 202 and 204 in the source and drain regions 222 and refilling with spacer layers 180a-180e and 180f-180i, formation of region 184, formation of dummy gate regions 230 and formation of dielectric regions 180j-m and 182.

[0028] Fig. Figures 6A-6C illustrate cross-sectional views of the structure 200 after removal of the dummy gate 230 and formation of the gate regions 124 of the p-type GAAFET 106. Each of the gate regions 124 of the p-type GAAFETs comprises a dielectric gate layer 128 surrounding a gate electrode 126. Each of the nanoribbons 114a-114d comprises a p-type source region 118, a p-type drain region 120, and a channel region 123. Each channel region 123 is positioned vertically between two gate regions 124 and laterally between a p-type source region 118 and a p-type drain region 120.

[0029] Fig. Figures 7A-7C illustrate cross-sectional views of the structure 200 after the formation of the gate regions 150 of the n-type GAAFETs 106 and the gate contact regions 178 and 179. Each of the gate regions 150 of the n-type GAAFETs comprises a dielectric gate layer 154 surrounding a gate electrode 152. Each of the nanoribbons 142a-142d comprises an n-type source region 144, an n-type drain region 146, and a channel region 148. Each channel region 148 is positioned vertically between two gate regions 150 and laterally between an n-type source region 144 and an n-type drain region 146.

[0030] With renewed reference to Fig. Figures 1A-1C illustrate cross-sectional views of the structure 200 after etching the dielectric region 182 and forming the third source or drain contact region 186 to form CFET devices 100 and 102 with n-type GAAFETs 104 stacked vertically above p-type GAAFETs 106.

[0031] Any of the manufacturing processes described herein for the fabrication of CFET devices, including Process 800, can be performed using any suitable microelectronic fabrication techniques. For example, film deposition—such as layer deposition, backfilling of portions of layers (e.g., backfilling of removed sections of layers or removed layers), and backfilling of through-holes or contact openings—can be performed using any suitable deposition techniques, including, for example, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), sputtering, and / or physical vapor deposition (PVD).Furthermore, layer structuring – such as structuring the dielectric, ferromagnetic, magnetoelectric layer – can be carried out using any suitable techniques, such as photolithography-based structuring and etching (e.g., dry etching or wet etching).

[0032] Although non-crystalline silicon is used as the HPTFT material for layers 142a-142b, which form the n-conducting GAAFET source, drain, and channel regions, other HPTFT materials can be used in other embodiments. In various embodiments, the HPTFT material can be a material exhibiting a charge carrier mobility greater than 5 cm⁻¹. 2 / (V·s), higher than 20 cm 2 / (V·s), higher than 50 cm 2 / (V·s) or higher than 100 cm 2 exhibits / (V·s). In various embodiments, the HPTFT material can be a material that exhibits a load carrier mobility between 5 cm. 2 / (V·s) and 700 cm 2 / (V·s) exhibits, including all values ​​and ranges therein (including the range of 100 cm 2 / (V·s) up to 700 cm 2 / (V·s)).

[0033] In various embodiments, the HPTFT material is a material exhibiting a bandgap voltage greater than that of silicon (e.g., 1.14 eV at 300 K). In some examples, the HPTFT material is a material exhibiting a bandgap voltage significantly higher than that of silicon (e.g., higher than 1.2 eV at 300 K). In certain embodiments, the HPTFT material is a material whose bandgap voltage is greater than that of silicon but lower than 6.5 eV at 300 K, including all values ​​and ranges within that range. In various embodiments, the HPTFT material is a material exhibiting a bandgap voltage greater than that of a substrate on which a transistor comprising the HPTFT material is formed.

[0034] In various embodiments, the HPTFT material comprises an oxide (e.g., a metal oxide), such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, gallium oxide, copper oxide, tin oxide, or another suitable oxide. With some oxides, a material exhibiting insulating properties can be introduced into the oxide to increase the bandgap stress. For example, doping indium oxide with hafnium oxide (which exhibits insulating properties) will result in an HPTFT composite material with a larger bandgap than indium oxide alone. Similarly, indium oxide or zinc oxide can be doped with gallium oxide (which exhibits insulating properties) to produce an HPTFT composite material with a larger bandgap stress.

[0035] In some embodiments, the HPTFT material comprises a nitride (e.g., a metal nitride), such as zinc nitride, indium nitride, gallium nitride, copper nitride, aluminum nitride, or another suitable nitride. With some nitrides, a material with insulating properties can be introduced into the nitride to increase the bandgap stress. For example, aluminum nitride (which exhibits insulating properties) can be added to indium nitride, zinc nitride, or gallium nitride to create an HPTFT composite material with an increased bandgap stress.

[0036] In some embodiments, the HPTFT material comprises a chalcogenide, such as a selenide or sulfide of molybdenum, tungsten, indium, gallium, zinc, copper, hafnium, aluminum or germanium.

[0037] In some embodiments, the HPTFT material comprises any other suitable material, such as black phosphorus, graphene, carbon nanotubes, polygermanium, poly(3,5) (gallium arsenide, etc.). While some of these materials exhibit a narrower bandgap strain than silicon in certain compositions, the concentration of certain elements (e.g., gallium) can be increased to improve the bandgap strain of the resulting HPTFT material.

[0038] Fig. Figure 8 is an exemplary method for forming a CFET device using HPTFT materials. Method 800, for example, can be carried out by a manufacturer of integrated circuit components. In Figure 804, several first layers are formed above a substrate, the first layers being stacked vertically relative to a surface of the substrate. Individual first layers comprise silicon, and individual first layers comprise a first region, a second region, and a third region, with the first region being positioned laterally between the second and third regions. The second and third regions comprise a p-type dopant. In Figure 808, a middle dielectric layer is formed above the multiple first layers.In 812, several second layers and several spacer regions are deposited on or above the middle dielectric layer, a bottommost spacer region is deposited on the middle dielectric layer, some of the second layers are deposited on one of the spacer regions, some of the second layers comprise non-crystalline silicon, some of the second layers comprise a first region, a second region, and a third region, wherein the first region is positioned laterally between the second and third regions, and wherein the second and third regions comprise an n-type dopant. In 816, the first layers, the middle dielectric layer, the spacer regions, and the second layers are etched to form a column. In 820, several first-gate regions are formed, wherein some of the first regions of the first layers are positioned vertically between two first-gate regions.At 824, several second gate areas are formed, with some of the first areas of the second layers being positioned vertically between two second gate areas.

[0039] In other embodiments, the method 800 may include additional elements. For example, the method 800 may further include forming a first contact region positioned adjacent to an end of any of the first sections of the first layers, and forming a second contact region positioned adjacent to an end of any of the second sections of the first layers. In another example, the method 800 may further include forming a second contact region positioned adjacent to an end of any of the first sections of the second layers, and forming a second contact region positioned adjacent to an end of any of the second sections of the second layers. In yet another example, the method 800 may further include forming a gate contact region positioned adjacent to an uppermost first gate region.

[0040] The CFET devices described herein may be used in any processor unit or integrated circuit component described or referenced herein. An integrated circuit component comprising CFET devices may be mounted on a printed circuit board (motherboard, mainboard). In some embodiments, one or more additional integrated circuit components or other components (e.g., battery, memory, antenna) may be mounted on the printed circuit board. In some embodiments, the printed circuit board and the integrated circuit component may be located in a computing device comprising a housing that encloses the printed circuit board and the integrated circuit component.

[0041] Fig. Figure 9 is a top view of a wafer 900 and dies 902, which may be included in any of the microelectronic assemblies described herein. The wafer 900 may be composed of semiconductor material and may have one or more dies 902 with integrated circuit structures formed on a surface of the wafer 900. The individual dies 902 may form a repeating unit of an integrated circuit product comprising any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer 900 may undergo a singulation process in which the dies 902 are separated from one another to provide discrete “chips” of the integrated circuit product. The die 902 may contain one or more transistors (e.g., some of the CFET devices disclosed herein, some of the transistors 1040 discussed below). Fig. 10), a support circuit arrangement for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 900 or the die 902 may include a memory device (e.g., a random-access memory (RAM) device such as a static RAM (SRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a conductive bridge RAM (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Several of these devices may be combined on a single die 902. For example, a memory array formed by several memory devices may be placed on the same die 902 as a processor unit (e.g., the processor unit 1502 from Fig. 15) or other logic configured to store information in the storage devices or to execute instructions stored in the storage array. Several of the microelectronic assemblies disclosed herein can be fabricated using a die-to-wafer assembly technique in which some dies 902 are attached to a wafer 900, the other dies are attached to the wafer 900, and the wafer 900 is subsequently singulated.

[0042] Fig. Figure 10 is a cross-sectional side view of an integrated circuit device 1000, which may be enclosed in one of the microelectronic assemblies disclosed herein. One or more of the integrated circuit devices 1000 may be enclosed in one or more Dies 902 ( Fig. 9) be included. The integrated circuit device 1000 can be mounted on a die substrate 1002 (e.g., the wafer 900 made of Fig. 9) be formed and can be in a Die (e.g. the Die 902 from Fig. 9) included. The die substrate 1002 may be a semiconductor substrate composed of semiconductor material systems comprising, for example, n-type or p-type material systems (or a combination of both). The die substrate 1002 may, for example, comprise a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon, comprising, but not limited to, germanium, carbon, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or diamond. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002.Although some examples of materials from which the die substrate 1002 may be formed are described herein, any material that can serve as a basis for an integrated circuit device 1000 may be used. The die substrate 1002 may be part of a discrete die (e.g., the die 902 from ). Fig. 9) or a wafer (e.g., wafer 900 from Fig. 9) be.

[0043] The integrated circuit device 1000 can have one or more device layers 1004 arranged on the die substrate 1002. The device layer 1004 can have features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The transistors 1040 can, for example, have one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for conducting electrical signals to / from the S / D regions 1020. The 1040 transistors may have additional features, such as device isolation areas, gate contacts, and the like, which are not shown for clarity. The 1040 transistors are not specified in Fig. The type and configuration shown are limited and can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors (such as dual-gate or tri-gate transistors) and wrap-around or all-around-gate transistors (such as nanoband, nanoplate, or nanowire transistors). Devices include non-planar transistors, which may include forksheet transistors and complementary FET (CFET) devices.

[0044] Fig. Figures 11A-11D are simplified perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The figures shown in Fig. The transistors illustrated in 11A to 11D are formed on a substrate 1116 which has a surface area 1108. Insulation regions 1114 separate the source and drain regions of the transistors from other transistors and from a volume region 1118 of the substrate 1116.

[0045] Fig. Figure 11A is a perspective view of an exemplary planar transistor 1100, comprising a gate 1102 that controls current flow between a source region 1104 and a drain region 1106. The transistor 1100 is planar in that the source region 1104 and the drain region 1106 are planar with respect to the substrate surface 1108.

[0046] Fig. Figure 11B is a perspective view of an exemplary planar transistor 1120, which includes a gate 1122 that controls current flow between a source region 1124 and a drain region 1126. The transistor 1120 is non-planar in that the source region 1124 and the drain region 1126 include "fins" that extend upward from the substrate surface 1128. Since the gate 1122 encloses three sides of the semiconductor fin extending from the source region 1124 to the drain region 1126, the transistor 1120 can be considered a tri-gate transistor. Fig. Figure 11B illustrates an S / D fin extending through gate 1122, but multiple S / D fins can extend through the gate of a FinFET transistor.

[0047] Fig. Figure 11C is a perspective view of a gate all-around transistor (GAA) (GAAFET) 1140 with a gate 1142 that controls the current flow between a source region 1144 and a drain region 1146 of a strip 1148 comprising a semiconductor (semiconductor strip). The transistor 1140 is non-planar in that the strip 1148 is raised from the substrate surface 1128.

[0048] Fig. Figure 11D is a perspective view of a GAA transistor 1160 with a gate 1162 that controls the current flow between source regions 1164 and drain regions 1166 of several raised semiconductor strips 1168. The transistor 1160 is a stacked GAA transistor because the gate controls the current flow between several raised S / D regions stacked on top of each other. The transistors 1140 and 1160 can be described as gate-all-around transistors because the gates encompass all sides of the sections of the semiconductor strips that extend from the source regions to the drain regions. The transistors 1140 and 1160 can alternatively be described as nanowire, nanosheet, or nanoribbon transistors, and the semiconductor strips that pass through the gate region can be described as nanowires, nanosheets, or nanoribbons.

[0049] Fig. 12A and Fig. Figure 12B shows perspective and cross-sectional views of an exemplary forksheet transistor device. In general, a forksheet transistor device comprises an n-type stacked GAAFET adjacent to a p-type stacked GAAFET with a dielectric region separating the nanobands (nanoplates, nanowires) that form the source, drain, and channel regions of the two GAAFETs. The forksheet transistor device 1260 is formed on a substrate 1216 with a surface area 1208. The n-type and p-type GAAFETs comprise three vertically stacked nanobands 1290 and 1291, respectively. Each nanoband 1290 of the n-type GAAFET is coplanar with a nanoband 1291 of the p-type GAAFET. The substrate 1216 comprises an insulating region 1214 located on a volume region 1218. A dielectric region 1298 separates the nanobands 1290 of the n-type GAAFET from the nanobands 1291 of the p-type GAAFET.A first section 1270 of the dielectric region 1298 is positioned between n-conducting source regions 1264 and p-conducting source regions 1272, a second section 1282 of the dielectric region 1298 is located between n-conducting drain regions 1266 (in . Fig. 12A) and p-type drain regions 1274, and a third section 1280 of the dielectric region 1298 is located between channel regions 1265 of the nanobands 1290 and channel regions 1273 of the nanobands 1291. In some embodiments, the dielectric region 1298 can be an extension of the substrate insulation region 1214. The gate 1262 controls a current flow between the n-type source 1264 and drain 1266 regions and the p-type source 1272 and drain 1274 regions.

[0050] Fig. Figure 12B is a cross-sectional view of the gate region of the forksheet transistor device 1260 along line AA'. Fig. 12A. The channel regions 1265 connect n-type source regions 1264 with n-type drain regions 1266, the channel regions 1273 connect p-type source regions 1272 with p-type drain regions 1274, and the third section 1280 of the dielectric region 1298 separates the channel regions 1265 from the channel regions 1273 and connects the first section 1270 of the dielectric region 1298 with the second section 1282 of the dielectric region 1298. Thus, the forksheet transistor device 1260 comprises an n-type transistor comprising n-type source regions 1264, channel region 1265, n-type drain regions 1266, and gate 1262; and a p-type transistor comprising p-type source regions 1272, channel regions 1273, p-type drain regions 1274, and gate 1262. Gate 1262 is shared by the n-type and p-type GAAFETs.The forksheet transistor architecture can provide a reduced distance between n-type and p-type S / D regions in adjacent GAAFETs relative to that in adjacent independent GAAFETs of the same type. Fig. 11D illustrates the type. The forksheet transistor architecture can thus enable an increased transistor packing density relative to packing independent GAAFETs or an increased active transistor width with the same transistor packing density as independent GAAFETs.

[0051] Fig. Figures 13A-13B are simplified perspective or cross-sectional views of an exemplary complementary field-effect transistor (CFET) device. Fig. 13B is a cross-sectional view of the CFET device 1300, taken through the gate area and along line BB'. Fig. 13A is taken. The CFET device 1300 comprises vertically stacked GAAFETs 1342 and 1344. In Fig. 13A and Fig. In 13B, transistor 1342 is an n-type transistor and transistor 1344 is a p-type transistor, but in other embodiments, a CFET device may include a p-type transistor located above an n-type transistor. Transistors 1342 and 1344 are formed on a substrate 1316 with a surface area 1308. The substrate 1316 includes an insulating region 1314 located on a volume region 1318.

[0052] The n-type and p-type transistors 1342 and 1344 include a gate 1382, shared by both transistors, which controls current flow between the source and drain regions of the nanobands 1310 and 1320, respectively. Transistors 1342 and 1344 each comprise three nanobands, but the transistors in a CFET device can have any number of nanobands, and different transistors in a CFET device can have different numbers of nanobands. The n-type transistor 1342 comprises n-type source regions 1364 connected to n-type drain regions 1366 via channel regions 1363, and the p-type transistor 1344 comprises p-type source regions 1372 connected to p-type drain regions 1374 via channel regions 1373.The transistor stacking employed by the CFET device architecture can provide improved transistor density in the x and y dimensions or increased transistor width at the same transistor density relative to other gate-all-around transistor architectures, such as those in . Fig. 11D, Fig. Figures 12A and 12B illustrate this. In some embodiments, the CFET device 1300 can be formed monolithically, with the upper and lower transistors formed on the same substrate, or sequentially, with the lower transistor (e.g., 1344) formed on a first substrate and the upper transistor (e.g., 1342) formed on a second substrate, the upper transistor being integrated with the lower transistor by transferring the upper transistor from the second substrate to the first substrate.

[0053] With renewed reference to Fig. A transistor 1040 can have a gate 1022 formed from at least two layers: a gate dielectric and a gate electrode. The gate dielectric can have a single layer or a stack of layers. The one or more layers can consist of silicon dioxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. A high-k dielectric material is a material with a dielectric constant greater than that of silicon dioxide.

[0054] The high-k dielectric material can contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate. In some embodiments, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used.

[0055] The gate electrode can be formed on the gate dielectric and, depending on whether the 1040 transistor is intended to be a p-type metal-oxide semiconductor (PMOS) or an n-type metal-oxide semiconductor (NMOS) transistor, may have at least one p-type or n-type outlet metal. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are outlet metal layers and at least one metal layer is a filler metal layer. Additional metal layers may be included for other purposes, such as serving as a depletion layer.

[0056] In a PMOS transistor, metals that can be used for the gate electrode, without limitation, include ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). In an NMOS transistor, metals that can be used for the gate electrode, without limitation, include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0057] In some embodiments, the gate electrode, viewed as a cross-section of the transistor 1040 along the source-channel-drain direction, can consist of a U-shaped structure comprising a lower section that is substantially parallel to the surface of the die substrate 1002 and two side wall sections that are substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the die substrate 1002 and does not include any side wall sections that are substantially perpendicular to the top surface of the die substrate 1002. In still other embodiments, the gate electrode can consist of a combination of U-shaped structures and planar, non-U-shaped structures.For example, the gate electrode can consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0058] In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers can be made of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally involve deposition and etching process steps. In some embodiments, multiple pairs of spacers can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0059] The S / D regions 1020 can be formed in the die substrate 1002 adjacent to the gate 1022 of the individual transistors 1040. The S / D regions 1020 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 1002 to form the S / D regions 1020. The ion implantation process can be followed by an annealing process, which activates the dopants and causes them to diffuse further into the die substrate 1002. In the latter process, the die substrate 1002 can first be etched to form depressions at the locations of the S / D regions 1020. An epitaxial deposition process can then be carried out to fill the depressions with a material used to fabricate the S / D areas 1020.In some implementations, the S / D regions 1020 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1020 can be formed using one or more alternative semiconductor materials such as germanium or a material or alloy of Group III-V. In further embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1020.

[0060] Electrical signals, such as power and / or input / output (I / O) signals, can be transmitted through one or more interconnection layers arranged on the device layer 1004 (in Fig. 10 (illustrated as interconnection layers 1006 to 1010) to and / or from the devices (e.g., transistors 1040) of device layer 1004. For example, electrically conductive features of device layer 1004 (e.g., the gate 1022 and the S / D contacts 1024) can be electrically coupled to the interconnection structures 1028 of interconnection layers 1006 to 1010. One or more interconnection layers 1006-1010 can form a metallization stack (also referred to as an "ILD stack") 1019 of the integrated circuit device 1000.

[0061] The interconnection structures 1028 can be arranged in the interconnection layers 1006 to 1010 to conduct electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the one shown in Fig. The special configuration of intermediate connection structures shown in section 10 is limited to 1028. Even if in Fig. 10 where a specific number of interconnect layers 1006-1010 is shown, embodiments of the present disclosure include IC devices with more or fewer interconnect layers than shown.

[0062] In some embodiments, the interconnection structures 1028 may include conductors 1028a and / or vias 1028b filled with an electrically conductive material such as a metal. The conductors 1028a may be arranged to conduct electrical signals in a direction along a plane that is substantially parallel to a surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the conductors 1028a may be arranged from the perspective of Fig. The vias 1028b conduct electrical signals in one direction into and out of the side and / or in one direction across the side. They can be arranged to conduct electrical signals in one direction along a plane that is substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, the vias 1028b can electrically couple conductors 1028a of different interconnection layers 1006-1010.

[0063] The intermediate interconnection layers 1006 to 1010 can have a dielectric material 1026 arranged between the intermediate interconnection structures 1028, as shown in Fig. Figure 10 shows. In some embodiments, the dielectric material 1026 arranged between the interconnection structures 1028 in different interconnection layers 1006 to 1010 can have different compositions; in other embodiments, the composition of the dielectric material 1026 can be the same between different interconnection layers 1006 to 1010. The device layer 1004 can have a dielectric material 1026 that is also arranged between the transistors 1040 and a lower layer of the metallization stack.The dielectric material 1026 contained in the device layer 1004 may have a different composition than the dielectric material 1026 contained in the intermediate compound layers 1006 to 1010; in other embodiments, the composition of the dielectric material 1026 in the device layer 1004 may be the same as that of a dielectric material 1026 contained in any of the intermediate compound layers 1006 to 1010.

[0064] A first interconnect layer 1006 (designated as metal 1 or "M1") can be formed directly on the device layer 1004. In some embodiments, the first interconnect layer 1006 can, as shown, have conductors 1028a and / or vias 1028b. The conductors 1028a of the first interconnect layer 1006 can be coupled to contacts (e.g., S / D contacts 1024) of the device layer 1004. The vias 1028b of the first interconnect layer 1006 can be coupled to the conductors 1028a of a second interconnect layer 1008.

[0065] The second interconnect layer 1008 (designated as metal 2 or “M2”) can be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 can have a via 1028b to couple the conductors 1028 of the second interconnect layer 1008 to the conductors 1028a of a third interconnect layer 1010. Although the conductors 1028a and the vias 1028b are structurally separated by a line within individual interconnect layers for clarity, in some embodiments the conductors 1028a and the vias 1028b can be structurally and / or materially connected (e.g., filled simultaneously during a dual-damascene process).

[0066] The third interconnect layer 1010 (designated as Metal 3 or “M3”) (and, if required, additional interconnect layers) can be formed sequentially on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 and the first interconnect layer 1006. In some embodiments, the interconnect layers located “higher up” in the metallization stack 1019 in the integrated circuit device 1000 (i.e., farther from the device layer 1004) can be thicker than the interconnect layers located lower in the metallization stack 1019, with the conductors 1028a and vias 1028b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0067] The integrated circuit device 1000 can have a solder mask material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interlinking layers 1006-1010. Fig. Figure 10 illustrates the conductive contacts 1036 taking the form of bond pads. The conductive contacts 1036 can be electrically coupled to the interconnection structures 1028 and configured to conduct the electrical signals from the transistor(s) 1040 to external devices. For example, solder bonds can be formed on one or more of the conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die comprising the integrated circuit device 1000 to another component (e.g., a printed circuit board). The integrated circuit device 1000 can have additional or alternative structures to conduct the electrical signals from the interconnection layers 1006-1010; for example, the conductive contacts 1036 can have other analog features (e.g., pins) that conduct the electrical signals to external components.

[0068] In some embodiments where the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may have another (not shown) metallization stack on the opposite side of the device layer(s) 1004. This metallization stack may have several interconnection layers, as explained above with reference to interconnection layers 1006 to 1010, to provide conductive paths (e.g., including conductive traces and vias) between the device layer(s) 1004 and (not shown) additional conductive contacts on the side of the IC device 1000 opposite the conductive contacts 1036.

[0069] In other embodiments, in which the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may have one or more silicon vias (TSVs) through the die substrate 1002; these TSVs may make contact with the device layer(s) 1004 and may provide conductive paths between the device layer(s) 1004 and (not shown) additional conductive contacts on the side of the integrated circuit device 1000 opposite the conductive contacts 1036.In some embodiments, TSVs extending through the substrate can be used to conduct power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1000 from the conductive contacts 1036 to the transistors 1040 and any other components in the 1000 integrated components, and the metallization stack 1019 can be used to conduct I / O signals from the conductive contacts 1036 to the transistors 1040 and any other components in the 1000 integrated components.

[0070] Multiple Integrated Circuit Device 1000s can be stacked with one or more TSVs in each stacked device, providing a connection between any one of the devices and any of the other devices in the stack. For example, one or more High Bandwidth Memory (HBM) dies can be stacked on top of an Integrated Circuit Base die, and TSVs in the HBM dies can provide a connection between the individual HBM and the Integrated Circuit Base die. Conductive contacts can provide additional connections between adjacent Integrated Circuit Dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (micro-bumpers).

[0071] Fig. Figure 14 is a side cross-sectional view of an integrated circuit device assembly 1400, which may include any of the microelectronic assemblies disclosed herein. The integrated circuit device assembly 1400 comprises a number of components arranged on a printed circuit board 1402 (which may be a motherboard, a system board, a main board, etc.). The integrated circuit device assembly 1400 comprises components arranged on a first surface 1440 of the printed circuit board 1402 and an opposing second surface 1442 of the printed circuit board 1402; components may generally be arranged on one or both surfaces 1440 and 1442.

[0072] In some embodiments, the circuit board 1402 can be a printed circuit board (PCB) comprising several metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers include conductive traces. Any number of the metal layers can be formed in a desired circuit structure to transmit electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1402. In other embodiments, the circuit board 1402 can be a non-PCB substrate. The in Fig. Figure 14 illustrates the integrated circuit device assembly 1400, which has a package-on-interposer structure 1436 coupled to the first surface 1440 of the printed circuit board 1402 by coupling components 1416. The coupling components 1416 can electrically and mechanically couple the package-on-interposer structure 1436 to the printed circuit board 1402 and can be solder balls (as in Fig. 14 shown), pins (e.g., as a section of a pin grid array (PGA)), contacts (e.g., as parts of a contact plate grid array (LGA)), male and female sections of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure. The coupling components 1416 may optionally serve as the coupling components illustrated or described for any of the substrate assembly or substrate assembly components described herein.

[0073] The package-on-interposer structure 1436 can include an integrated circuit component 1420 coupled to an interposer 1404 by coupling components 1418. The coupling components 1418 can take any form suitable for the application, such as the forms discussed above with reference to the coupling components 1416. Although a single integrated circuit component 1420 in Fig. As shown in Figure 14, several integrated circuit components can be coupled to the interposer 1404; in fact, additional interposers can be coupled to the interposer 1404. The interposer 1404 can provide an intermediate substrate that is used to form a bridge between the printed circuit board 1402 and the integrated circuit component 1420.

[0074] The integrated circuit component 1420 can be a packaged or unpackaged integrated circuit product containing one or more integrated circuit dies (e.g., the die 902 from Fig. 9, the integrated circuit device 1000 from Fig. 10) and / or includes one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit dies and the package substrate are encapsulated in an encapsulation material such as metal, plastic, glass, or ceramic. In an example of an unencapsulated integrated circuit component 1420, a single monolithic integrated circuit die comprises solder pad mounds attached to contacts on the die. The solder pad mounds allow the die to be mounted directly to the interposer 1404. The integrated circuit component 1420 can include one or more computing system components, such as one or more processor units (e.g.,The integrated circuit component 1420 may include a system-on-a-chip (SoC), a processor core, a graphics processing unit (GPU), an accelerator, a chipset processor, an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1420 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0075] In embodiments where the integrated circuit component 1420 comprises multiple integrated circuit dies, the dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

[0076] In addition to containing one or more processor units, the Integrated Circuit Component 1420 can include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controls, or memory controls. Any of these additional components can be placed on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies that are separate from the integrated circuit dies containing the processor units. These separate integrated circuit dies can be referred to as "chiplets."In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between the dies can be provided through the package substrate, through one or more silicon interposers, through one or more silicon bridges embedded in the package substrate (such as Intel® Embedded Multi-die Interconnect Bridges (EMIBs)), or combinations thereof.

[0077] In general, the interposer 1404 can spread connections to a wider grid spacing or redirect one connection to another. For example, the interposer 1404 can couple the integrated circuit component 1420 to a set of conductive ball grid array (BGA) contacts of the coupling components 1416 for coupling to the printed circuit board 1402. In the Fig. In the illustrated embodiment 14, the integrated circuit component 1420 and the printed circuit board 1402 are mounted on opposite sides of the interposer 1404; in other embodiments, the integrated circuit component 1420 and the printed circuit board 1402 can be mounted on the same side of the interposer 1404. In some embodiments, three or more components can be interconnected using the interposer 1404.

[0078] In some embodiments, the interposer 1404 can be formed as a PCB comprising several metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1404 can be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1404 can be formed from alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other materials of Groups III-V and IV.The interposer 1404 can have metal interconnections 1408 and vias 1410, including vias 1410-1 (extending from a first face 1450 of the interposer 1404 to a second face 1454 of the interposer 1404), blind contacts 1410-2 (extending from the first or second face 1450 or 1454 of the interposer 1404 to an internal metal layer) and buried vias 1410-3 (connecting internal metal layers).

[0079] In some embodiments, the interposer 1404 may include a silicon interposer. The silicon vias (TSVs) extending through the silicon interposer may connect a first face of the silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 1404 comprising a silicon interposer may further include one or more conductor guide layers to guide connections on a first face of the interposer 1404 to an opposing second face of the interposer 1404.

[0080] The interposer 1404 can further include embedded devices 1414, which may comprise both passive and active devices. Such devices may include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1404. The package-on-interposer structure 1436 can take the form of any package-on-interposer structure known in the prior art.

[0081] The integrated circuit device assembly 1400 can include an integrated circuit component 1424, which is coupled to the first surface 1440 of the printed circuit board 1402 by coupling components 1422. The coupling components 1422 can take the form of any of the embodiments discussed above with reference to the coupling components 1416, and the integrated circuit component 1424 can take the form of any of the embodiments discussed above with reference to the integrated circuit component 1420.

[0082] The in Fig. Figure 14 illustrates the integrated circuit device assembly 1400, which has a case-on-case structure 1434 coupled to the second surface 1442 of the printed circuit board 1402 by coupling components 1428. The case-on-case structure 1434 can include an integrated circuit component 1426 and an integrated circuit component 1432, which are coupled to each other by coupling components 1430 such that the integrated circuit component 1426 is located between the printed circuit board 1402 and the integrated circuit component 1432. The coupling components 1428 and 1430 can take the form of any embodiment of the coupling components 1416 discussed above, and the integrated circuit components 1426 and 1432 can take the form of any embodiment of the integrated circuit component 1420 discussed above.The case-on-case structure 1434 can be configured according to any of the case-on-case structures known in the prior art.

[0083] Fig. Figure 15 is a block diagram of an exemplary electrical device 1500, which may comprise one or more of the microelectronic assemblies disclosed herein. For example, any suitable component of the electrical device 1500 may comprise one or more of the integrated circuit device assemblies 1400, integrated circuit components 1420, integrated circuit devices 1000, or integrated circuit dies 902 disclosed herein, and they may be arranged in any of the microelectronic assemblies disclosed herein. A number of components are shown in Fig. Figure 15 illustrates the electrical device 1500 as containing components, but any or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1500 may be mounted on one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components may be fabricated on a single system-on-chip (SoC) die.

[0084] Additionally, the electrical device 1500 can, in various embodiments, incorporate one or more of the features described in Fig.The electrical device 1500 may not have all of the components illustrated in Figure 15, but it may have an interface circuit arrangement for coupling with one or more of the components. For example, the electrical device 1500 may not have a display device 1506, but it may have a display device interface circuit arrangement (e.g., a connector and a driver circuit arrangement) to which a display device 1506 can be coupled. In another set of examples, the electrical device 1500 may not have an audio input device 1524 or an audio output device 1508, but it may have an audio input or output device interface circuit arrangement (e.g., a connector and a support circuit arrangement) to which an audio input device 1524 or an audio output device 1508 can be coupled.

[0085] The electrical device 1500 can comprise one or more processor units 1502 (e.g., one or more processor units). As used herein, the terms "processor unit," "processing unit," or "processor" can refer to any device or any section of a device that processes electronic data from registers and / or a memory to transform such electronic data into other electronic data that can be stored in registers and / or a memory. The processor unit 1502 can comprise one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g.,Graphics accelerators, compression accelerators, artificial intelligence accelerators), control cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit can be referred to as an XPU (or xPU).

[0086] The electrical device 1500 can include a memory 1504, which in turn can include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based voltage-free phase-change memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1504 can include memory located on the same integrated circuit die as the processor unit 1502. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last-Level Cache (LLC)) and can include embedded dynamic random access memory (eDRAM) or magnetic spin transfer torque random access memory (STT-MRAM).

[0087] In some embodiments, the electrical device 1500 may comprise one or more processor units 1502 that are heterogeneous or asymmetric with respect to any other processor unit 1502 in the electrical device 1500. There may be a multitude of differences between the processing units 1502 in a system with respect to a spectrum of quality metrics, exhibiting architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity among the processor units 1502 in the electrical device 1500.

[0088] In some embodiments, the electrical device 1500 may include a communication component 1512 (e.g., one or more communication components). For example, the communication component 1512 may manage wireless communications for the transfer of data to and from the electrical device 1500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices contain no wires whatsoever, although in some embodiments they may not.

[0089] The 1512 communication component can implement any number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) Project along with all amendments, updates, and / or revisions (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) Project (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a certification mark for products that pass compliance and interoperability tests according to IEEE 802.16 standards.The 1512 communication component can operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 1512 communication component can also operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 1512 communication component can operate in accordance with Code-Division Multiple Access (CDMA), Time-Division Multiple Access (TDMA), Digital-Enhanced Cordless Telecommunications (DECT), Evolution Data-Optimized (EV-DO) and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G and beyond. The 1512 communication component can also operate in accordance with other wireless protocols in other embodiments.The electrical device 1500 can have an antenna 1522 to enable wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0090] In some embodiments, the communication component 1512 can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As mentioned above, the communication component 1512 can include multiple communication components. For example, a first communication component 1512 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1512 can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1512 can be dedicated to wireless communications, and a second communication component 1512 can be dedicated to wired communications.

[0091] The electrical device 1500 may include a battery / power circuit arrangement 1514. The battery / power circuit arrangement 1514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 1500 to a power source separate from the electrical device 1500 (e.g., AC mains power).

[0092] The electrical device 1500 may include a display device 1506 (or a corresponding interface circuit arrangement as discussed above). The display device 1506 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a field-of-view display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0093] The electrical device 1500 may include an audio output device 1508 (or a corresponding interface circuit arrangement as discussed above). The audio output device 1508 may include any embedded, wired, or wirelessly connected external device that produces an acoustic indicator, such as a loudspeaker, headphones, or earphones.

[0094] The electrical device 1500 may include an audio input device 1524 (or a corresponding interface circuit arrangement as discussed above). The audio input device 1524 may include any embedded, wired, or wirelessly connected device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1500 may include a device 1518 for the global navigation satellite system (GNSS) (or a corresponding interface circuit arrangement as discussed above), such as a device for the global positioning system (GPS).The GNSS device 1518 can communicate with a satellite-based system and can determine a geographic location of the electrical device 1500 based on information received from one or more GNSS satellites, as is known in the prior art.

[0095] The electrical device 1500 may include another output device 1510 (or a corresponding interface circuit arrangement as discussed above). Examples of the other output device 1510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0096] The electrical device 1500 may include another input device 1520 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 1520 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0097] The 1500 electrical device can have any desired form factor, such as a portable or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computer solution (e.g.,Blade, tray, or sled computer systems), a workstation or other networked computer component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a home gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a portable electrical device, or an embedded computing system (e.g., computing systems that are part of a vehicle, a smart home appliance, a consumer electronics product or equipment, or manufacturing equipment). In some embodiments, the electrical device 1500 may be any other electronic device that processes data. In some embodiments, the electrical device 1500 may comprise several discrete physical components.In view of the variety of devices that the electrical device 1500 can manifest itself in in different embodiments, the electrical device 1500 can be referred to as a calculating device or calculating system in some embodiments.

[0098] As used in this application and the claims, a list of elements joined by the expression "and / or" can mean any combination of the listed elements. For example, the expression "A, B and / or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and the claims, a list of elements joined by the term "at least one of" can mean any combination of the listed terms. For example, the expression "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. Furthermore, as used in this application and the claims, a list of elements joined by the term "one or more of" can mean any combination of the listed terms.The expression “one or more of A, B and C” can, for example, mean A; B; C; A and B; A and C; B and C; or A, B and C. Furthermore, as used in this application and in the claims, a list of elements joined by the term “one of” can mean any of the listed elements. For example, the expression “one of A, B and C” can mean A, B, or C.

[0099] As used in this application and the claims, the phrase “a single one of” or “a respective one of”, followed by a list of elements that have been named or indicated as having a property, feature, etc., means that all elements in the list possess the named or indicated property, feature, etc. For example, the phrase “single one of A, B or C comprising a side wall” or “respective one of A, B or C comprising a side wall” means that A comprises a side wall, B comprises a side wall, and C comprises a side wall.

[0100] The disclosed methods, devices, and systems are in no way to be considered limiting. Instead, the present disclosure is directed to all new and non-obvious features and aspects of the various disclosed embodiments, both individually and in various combinations and sub-combinations. The disclosed methods, devices, and systems are neither limited to any specific aspect or feature, nor do the disclosed embodiments require that any specific advantages or problems be present or solved.

[0101] Furthermore, operating theories, scientific principles, or other theoretical descriptions presented herein with reference to the devices or methods of this disclosure are provided for better understanding and are not intended to limit the scope of protection. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such operating theories.

[0102] Although the operations of some of the disclosed methods are described in a particular sequential order for the sake of convenience, it is understood that this type of description involves rearranging them unless a specific order is necessary according to the specific statements set forth herein. For example, sequentially described operations may, in some cases, be rearranged or performed concurrently. Furthermore, for the sake of simplicity, the accompanying figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods.

[0103] The following examples relate to additional embodiments of the technologies disclosed herein.

[0104] Example 1 is a device comprising a substrate including silicon; several first layers stacked vertically with respect to a surface of the substrate, wherein individual first layers include a first source or drain (S / D) region, a second S / D region, and a first channel region positioned between the first S / D region and the second S / D region, wherein individual first layers include non-crystalline silicon, and wherein the first S / D region and the second S / D region of each first layer include an n-type dopant; and several second layers stacked vertically with respect to the surface of the substrate, wherein individual second layers include a third S / D region, a fourth S / D region, and a second channel region, wherein individual second layers include silicon, and wherein the third S / D region and the fourth S / D region of each second layer include a p-type dopant.a middle dielectric layer positioned between the multiple first layers and the multiple second layers; multiple first gate regions stacked vertically with respect to the surface of the substrate, the first gate regions comprising a first dielectric gate layer, and all but the uppermost first gate regions further comprising a first gate electrode surrounded by the first dielectric gate layer, the first gate electrodes comprising a first metal, and some of the first channel regions being positioned adjacent to two first gate regions;and several second gate regions stacked vertically with respect to the surface of the substrate, wherein individual second gate regions comprise a second dielectric gate layer and a second gate electrode, the second dielectric gate layer surrounding the second gate electrode, the second gate electrode comprising a first metal or a second metal, and wherein individual second channel regions are positioned adjacent to two second gate regions.

[0105] Example 2 includes the subject matter of Example 1 and further includes: several first spacer regions stacked vertically with respect to the surface of the substrate, wherein a first section of one of the first spacer regions is positioned between the middle dielectric layer and at least one section of the first S / D region of the first layer that is closest to the middle dielectric layer; a second section of one of the first spacer regions is positioned between the middle dielectric layer and at least one section of the second S / D region of the first layer that is closest to the middle dielectric layer; wherein a first section of one of the other first spacer regions is positioned adjacent to at least one section of the first S / D region of two of the first layers; and a second section of one of the other first spacer regions.which are positioned adjacent to at least one section of the second S / D region of two of the first layers; and several second spacer regions stacked vertically with respect to the surface of the substrate, wherein a first section of one of the second spacer regions is positioned between the middle dielectric layer and at least one section of the third S / D region of the second layer that is positioned closest to the middle dielectric layer, a second section of one of the second spacer regions is positioned between the middle dielectric layer and at least one section of the fourth S / D region of the second layer that is positioned closest to the middle dielectric layer, a first section of one of the other second spacer regions that are positioned adjacent to at least one section of the third S / D region of two of the second layers,and a second section of individual second spacer areas that are positioned adjacent to at least one section of the second S / D area of ​​two of the second layers.

[0106] Example 3 includes the subject matter of Example 1 or 2, further comprising a contact region encompassing the first metal, the second metal or another metal, wherein individual first S / D regions of the first layers include an end positioned adjacent to the contact region.

[0107] Example 4 includes the subject of Example 3, wherein the contact area is a first contact area, wherein the setup further includes a second contact area comprising the first metal, the second metal or another metal, wherein individual third S / D areas of the second layers include an end positioned adjacent to the second contact area.

[0108] Example 5 includes the subject of Example 3, wherein the contact area comprises tungsten, cobalt, titanium, gold, aluminium, molybdenum, chromium or nickel.

[0109] Example 6 includes the subject matter of Example 1 or 2, further comprising a gate contact region comprising the first metal, the second metal or another metal, wherein the gate contact region is positioned adjacent to the first gate region which is positioned furthest from the middle dielectric layer.

[0110] Example 7 is a device comprising a substrate comprising silicon; several first layers stacked vertically with respect to a surface of the substrate, wherein some of the first layers comprise non-crystalline silicon and an n-type dopant; several second layers stacked vertically with respect to the surface of the substrate, wherein some of the second layers comprise silicon and a p-type dopant; and a middle dielectric layer positioned between the several first layers and the several second layers.

[0111] Example 8 includes the subject matter of Example 7 and further includes several first spacer regions stacked vertically with respect to the surface of the substrate, wherein a first spacer region is positioned between the middle dielectric layer and a first layer that is positioned closest to the middle dielectric layer, the other first spacer regions being positioned adjacent to two of the first layers; and several second spacer regions stacked vertically with respect to the surface of the substrate, wherein a second spacer region is positioned between the middle dielectric layer and a second layer that is positioned closest to the middle dielectric layer, the other second spacer regions being positioned adjacent to two of the second layers.

[0112] Example 9 includes the subject of one of Examples 1 to 8, wherein the non-crystalline silicon of the first layers comprises amorphous silicon.

[0113] Example 10 includes the subject of one of Examples 1 to 8, wherein the non-crystalline silicon of the first layers comprises polycrystalline silicon.

[0114] Example 11 includes the subject of Example 2 or 8, wherein the first spacer regions comprise silicon and oxygen; silicon, oxygen and carbon; fluorine and hydrogen; or silicon and nitrogen.

[0115] Example 12 includes the subject of Example 2 or 8, wherein the second spacer regions comprise silicon and oxygen; silicon, oxygen and carbon; fluorine and hydrogen; or silicon and nitrogen.

[0116] Example 13 includes the subject of one of Examples 1 to 12, wherein the n-conducting dopant is phosphorus, arsenic or antimony.

[0117] Example 14 includes the subject of one of Examples 1 to 13, wherein the p-conducting dopant is boron or gallium.

[0118] Example 15 includes the subject matter of any of Examples 1 to 14, wherein the middle dielectric layer comprises silicon and oxygen; silicon, oxygen and carbon, fluorine or hydrogen; or silicon and nitrogen.

[0119] Example 16 includes the subject matter of one of Examples 1 to 15, the first metal comprising hafnium, zirconium, titanium, tantalum, and aluminum.

[0120] Example 17 includes the subject of Example 16, wherein the first metal further comprises carbon.

[0121] Example 18 includes the subject matter of one of Examples 1 to 15, wherein the first metal comprises ruthenium, palladium, platinum, cobalt or nickel.

[0122] Example 19 includes the subject matter of one of Examples 1 to 18, wherein the second metal comprises hafnium, zirconium, titanium, tantalum or aluminium.

[0123] Example 20 includes the subject of Example 19, wherein the second metal further comprises carbon.

[0124] Example 21 includes the subject matter of one of Examples 1 to 18, wherein the second metal comprises ruthenium, palladium, platinum, cobalt or nickel.

[0125] Example 22 includes the subject matter of Examples 1 to 15, wherein the first metal and / or the second metal comprises oxygen and a metal.

[0126] Example 23 includes the subject matter of Examples 1 to 22, wherein the first dielectric gate layers comprise a first dielectric material having a dielectric constant greater than silicon dioxide and the second dielectric layers comprise the first dielectric material or a second dielectric material having a dielectric constant greater than silicon dioxide.

[0127] Example 24 includes the subject matter of Examples 1 to 22, wherein the first dielectric gate layers comprise hafnium and oxygen; hafnium, oxygen and silicon; lanthanum and oxygen; lanthanum, oxygen and aluminium; zirconium and oxygen; zirconium, oxygen and silicon; tantalum and oxygen; titanium and oxygen; barium, strontium, titanium and oxygen; barium, titanium, and oxygen; strontium, titanium and oxygen; yttrium and oxygen; aluminium and oxygen; lead, scandium, tantalum and oxygen; or lead, zinc and niobium.

[0128] Example 25 includes the subject matter of Examples 1 to 12, wherein the second dielectric gate layers comprise hafnium and oxygen; hafnium, oxygen and silicon; lanthanum and oxygen; lanthanum, oxygen and aluminium; zirconium and oxygen; zirconium, oxygen and silicon; tantalum and oxygen; titanium and oxygen; barium, strontium, titanium and oxygen; barium, titanium, and oxygen; strontium, titanium and oxygen; yttrium and oxygen; aluminium and oxygen; lead, scandium, tantalum and oxygen; or lead, zinc and niobium.

[0129] Example 26 includes the subject of one of Examples 1 to 25, wherein the multiple second layers are positioned between the middle dielectric layer and the substrate.

[0130] Example 27 includes the subject of one of Examples 1 to 25, wherein the multiple first layers are positioned between the middle dielectric layer and the substrate.

[0131] Example 28 includes the subject of one of Examples 1 to 27, wherein the device is a wafer.

[0132] Example 29 includes the subject of one of Examples 1 to 27, wherein the device is an integrated circuit component.

[0133] Example 30 includes the subject matter of one of Examples 1 to 29, further comprising a printed circuit board, wherein the integrated circuit component is attached to the printed circuit board.

[0134] Example 31 includes the subject of Example 30, wherein a memory is attached to the circuit board.

[0135] Example 32 includes the subject matter of Example 30 and further includes a housing of a computing device surrounding the circuit board.

[0136] Example 33 includes a method comprising forming several first layers above a substrate, wherein the first layers are stacked vertically relative to a surface of the substrate, wherein individual first layers comprise silicon, wherein individual first layers comprise a first region, a second region and a third region, wherein the first region is positioned laterally between the second and third regions, and wherein the second and third regions comprise a p-type dopant; forming a middle dielectric layer over the several first layers;Deposition of multiple second layers and multiple spacer regions on or above the middle dielectric layer, a bottommost spacer region deposited on the middle dielectric layer, individual second layers deposited on one of the spacer regions, individual second layers comprising non-crystalline silicon, wherein individual second layers comprising a first region, a second region, and a third region, the first region being positioned laterally between the second and third regions, the second and third regions comprising an n-type dopant; etching the first layers, the middle dielectric layer, the spacer regions, and the second layers to form a column; forming multiple first-gate regions, wherein individual first regions of the first layers are positioned vertically between two first-gate regions;and forming multiple second-gate regions, with individual first-gate regions of the second layers positioned vertically between two second-gate regions.

[0137] Example 34 includes the subject of Example 33 and further includes the formation of a first contact area positioned adjacent to an end of some of the first areas of the first layers; and the formation of a second contact area positioned adjacent to an end of some of the second areas of the first layers.

[0138] Example 35 includes the subject of one of Examples 33 and 34 and further includes the formation of a first contact area positioned adjacent to an end of any of the first areas of the second layers; and the formation of a second contact area positioned adjacent to an end of any of the second areas of the second layers.

[0139] Example 36 includes the subject of Example 34 or 35, wherein the first contact area and the second contact area comprise tungsten, cobalt, titanium, gold, aluminium, molybdenum, chromium or nickel.

[0140] Example 37 includes the subject matter of one of Examples 33 to 36, further comprising the formation of a gate contact region positioned adjacent to the first gate region positioned furthest from the middle dielectric layer.

[0141] Example 38 includes the subject of one of Examples 33 to 37, wherein the non-crystalline silicon of the second layers comprises amorphous silicon.

[0142] Example 39 includes the subject matter of one of Examples 33 to 37, wherein the non-crystalline silicon of the second layers comprises polycrystalline silicon.

[0143] Example 40 includes the subject of one of Examples 33 to 39, wherein the n-conducting dopant is phosphorus, arsenic or antimony.

[0144] Example 41 includes the subject of one of Examples 33 to 40, wherein the p-conducting dopant is boron or gallium.

[0145] Example 42 includes the subject matter of any of Examples 33 to 41, wherein the middle dielectric layer comprises silicon and oxygen; silicon, oxygen and carbon, fluorine or hydrogen; or silicon and nitrogen.

[0146] Example 43 includes the subject of Example 33, wherein some of the first gate regions comprise a dielectric gate layer and a gate electrode.

[0147] Example 44 includes the subject of Example 33, wherein some of the second gate regions comprise a dielectric gate layer and a gate electrode.

[0148] Example 45 includes the subject of Example 43 or 44, wherein the gate electrode comprises hafnium, zirconium, titanium, tantalum, or aluminum.

[0149] Example 46 includes the subject of Example 44, wherein the gate electrode further comprises carbon.

[0150] Example 47 includes the subject of any one of Example 43 or 44, wherein the gate electrode comprises ruthenium, palladium, platinum, cobalt or nickel.

[0151] Example 48 includes the subject of Example 43 or 44, wherein the dielectric gate layer comprises a dielectric material having a dielectric constant greater than silicon dioxide.

[0152] Example 49 includes the subject matter of Example 33, wherein the dielectric gate layer comprises hafnium and oxygen; hafnium, oxygen and silicon; lanthanum and oxygen; lanthanum, oxygen and aluminium; zirconium and oxygen; zirconium, oxygen and silicon; tantalum and oxygen; titanium and oxygen; barium, strontium, titanium and oxygen; barium, titanium, and oxygen; strontium, titanium and oxygen; yttrium and oxygen; aluminium and oxygen; lead, scandium, tantalum and oxygen; or lead, zinc and niobium. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 346,106

[0001]

Claims

[1] Institution, encompassing: a substrate that includes silicon; several first layers stacked vertically with respect to a surface of the substrate, wherein individual first layers comprise a first source or drain (S / D) region, a second S / D region and a first channel region positioned between the first S / D region and the second S / D region, wherein individual first layers comprise non-crystalline silicon and wherein the first S / D region and the second S / D region of each first layer comprise an n-conducting dopant; several second layers stacked vertically with respect to the surface of the substrate, wherein individual second layers comprise a third S / D region, a fourth S / D region and a second channel region, wherein individual second layers comprise silicon and wherein the third S / D region and the fourth S / D region of the individual second layers comprise a p-conducting dopant; a middle dielectric layer positioned between the multiple first layers and the multiple second layers; several first gate regions stacked vertically with respect to the surface of the substrate, the first gate regions comprising a first dielectric gate layer and all but one uppermost first gate region of the several first gate regions, further comprising a first gate electrode surrounded by the first dielectric gate layer, the first gate electrodes comprising a first metal, and wherein individual first channel regions are positioned adjacent to two first gate regions; and several second gate regions stacked vertically with respect to the surface of the substrate, wherein individual second gate regions comprise a second dielectric gate layer and a second gate electrode, wherein the second dielectric gate layer surrounds the second gate electrode, wherein the second gate electrode comprises a first metal or a second metal, and wherein individual second channel regions are positioned adjacent to two second gate regions. [2] Device according to claim 1, further comprising: several first spacer regions stacked vertically with respect to the surface of the substrate, wherein a first section of one of the first spacer regions is positioned between the middle dielectric layer and at least one section of the first S / D region of the first layer that is positioned closest to the middle dielectric layer, a second section of one of the first spacer regions is positioned between the middle dielectric layer and at least one section of the second S / D region of the first layer that is positioned closest to the middle dielectric layer, wherein a first section of individual first spacer regions other than the first layer is positioned closest to the middle dielectric layer,which is positioned adjacent to at least one section of the first S / D area of ​​two of the first layers, and a second section of one of the other first spacer areas is positioned adjacent to at least one section of the second S / D area of ​​two of the first layers; and, several second spacer regions stacked vertically with respect to the surface of the substrate, wherein a first section of one of the second spacer regions is positioned between the middle dielectric layer and at least one section of the third S / D region of the second layer, which is positioned closest to the middle dielectric layer, and a second section of one of the second spacer regions is positioned between the middle dielectric layer and at least one section of the fourth S / D region of the second layer, which is positioned closest to the middle dielectric layer.wherein a first section of one of the other second spacer areas is positioned adjacent to at least one section of the third S / D area of ​​two of the second layers, and a second section of one of the other second spacer areas is positioned adjacent to at least one section of the second S / D area of ​​two of the second layers. [3] Device according to claim 1 or 2, further comprising a contact region comprising the first metal, the second metal or another metal, wherein individual S / D regions of the first layers comprise an end positioned adjacent to the contact region. [4] Device according to claim 3, wherein the contact area is a first contact area, wherein the device further comprises a second contact area comprising the first metal, the second metal or another metal, wherein individual third S / D areas of the second layers comprise an end positioned adjacent to the second contact area. [5] Device according to claim 3, wherein the contact area comprises tungsten, cobalt, titanium, gold, aluminium, molybdenum, chromium or nickel. [6] Device according to claim 1 or 2, further comprising a gate contact region comprising the first metal, the second metal or another metal, wherein the gate contact region is positioned adjacent to the first gate region which is positioned furthest from the middle dielectric layer. [7] Institution, comprehensive: a substrate that includes silicon; several first layers stacked vertically with respect to a surface of the substrate, wherein individual first layers comprise non-crystalline silicon and an n-conducting dopant; several second layers stacked vertically with respect to the surface of the substrate, with individual second layers comprising silicon and a p-type dopant; and a middle dielectric layer positioned between the multiple first layers and the multiple second layers. [8] Device according to claim 7, further comprising: several first spacer regions stacked vertically with respect to the surface of the substrate, wherein a first spacer region is positioned between the middle dielectric layer and a first layer positioned closest to the middle dielectric layer, wherein the first spacer regions that differ from the first layer positioned closest to the middle dielectric layer are positioned adjacent to two of the first layers; and several second spacer regions stacked vertically with respect to the surface of the substrate, wherein one second spacer region is positioned between the middle dielectric layer and a second layer positioned closest to the middle dielectric layer, and wherein the other second spacer regions are positioned adjacent to two of the second layers. [9] Device according to any one of claims 1 to 8, wherein the non-crystalline silicon of the first layers comprises amorphous silicon. [10] Device according to any one of claims 1 to 8, wherein the non-crystalline silicon of the first layers comprises polycrystalline silicon. [11] Device according to claim 2 or 8, wherein the first spacer areas and the second spacer areas comprise: Silicon and oxygen; Silicon, oxygen and carbon, fluorine and hydrogen; or Silicon and nitrogen. [12] Device according to any one of claims 1 to 11, wherein the n-conducting dopant is phosphorus, arsenic or antimony. [13] Device according to any one of claims 1 to 12, wherein the p-conducting dopant is boron or gallium. [14] Device according to any one of claims 1 to 13, wherein the middle dielectric layer comprises: Silicon and oxygen; Silicon, oxygen and carbon, fluorine or hydrogen; or Silicon and nitrogen. [15] Device according to any one of claims 1 to 14, wherein the first metal comprises hafnium, zirconium, titanium, tantalum, aluminium. [16] Device according to claim 15, wherein the first metal further comprises carbon. [17] Device according to any one of claims 1 to 14, wherein the first metal comprises ruthenium, palladium, platinum, cobalt or nickel. [18] Device according to any one of claims 1 to 14, wherein the first metal and / or the second metal comprises oxygen and a metal. [19] Device according to any one of claims 1 to 18, wherein the first dielectric gate layers comprise a first dielectric material having a dielectric constant greater than silicon dioxide and the second dielectric layers comprise the first dielectric material or a second dielectric material having a dielectric constant greater than silicon dioxide. [20] Device according to claims 1 to 18, wherein the first dielectric gate layers comprise: Hafnium and oxygen; Hafnium, oxygen and silicon; Lanthanum and oxygen; Lanthanum, oxygen and aluminum; Zirconium and oxygen; Zirconium, oxygen and silicon; Tantalum and oxygen; Titanium and oxygen; Barium, strontium, titanium and oxygen; Barium, titanium and oxygen; Strontium, titanium and oxygen; Yttrium and oxygen; Aluminum and oxygen; Lead, scandium, tantalum and oxygen; or Lead, zinc, and niobium. [21] Device according to any one of claims 1 to 20, wherein the device is a wafer. [22] Device according to any one of claims 1 to 20, wherein the device is an integrated circuit component. [23] Device according to claim 22, further comprising a printed circuit board, wherein the integrated circuit component is attached to the printed circuit board. [24] Procedures, including: Forming several first layers above a substrate, wherein the first layers are stacked vertically relative to a surface of the substrate, wherein individual first layers comprise silicon, wherein individual first layers comprise a first region, a second region and a third region, wherein the first region is positioned laterally between the second and third regions, and wherein the second and third regions comprise a p-conducting dopant; Formation of a middle dielectric layer over the several first layers; Depositing several second layers and several spacer regions on or above the middle dielectric layer, a bottommost spacer region deposited on the middle dielectric layer, individual second layers deposited on one of the spacer regions, individual second layers comprising non-crystalline silicon, wherein individual second layers comprising a first region, a second region and a third region, the first region being positioned laterally between the second and third regions, the second and third regions comprising an n-conducting dopant; Etching of the first layers, the middle dielectric layer, the spacer regions and the second layers to form a column; Forming multiple first gate regions, with individual first gate regions of the first layers positioned vertically between two first gate regions; and Forming multiple second gate regions, with individual first regions of the second layers positioned vertically between two second gate regions. [25] The method of claim 24, further comprising: Forming an initial contact zone positioned adjacent to an end of one of the initial zones of the initial layers; and Formation of a second contact area positioned adjacent to one end of individual second areas of the first layers.

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