Semiconductor device, method for operating a semiconductor device and method for manufacturing a semiconductor device

Abstract

According to one embodiment, the semiconductor device (100) comprises a semiconductor body (1) with a contact region (11) of a first type and conductivity of a first type, a contact region (12) of a second type and conductivity of a second type, and a drift region (14) of the first type. The semiconductor device further comprises a main electrode (2) and a gate electrode (3). A barrier region (42) of the second type is arranged vertically between the drift region and the contact region of the second type. The barrier region of the second type forms a barrier to charge carriers of the second type. The contact region of the first type and the contact region of the second type are laterally spaced apart from each other by a portion of the drift region. The gate electrode is arranged at least partially laterally between the contact region of the first type and the contact region of the second type.The contact region of the second type is arranged vertically between a top surface (10) of the semiconductor body and the barrier region of the second type. The main electrode electrically contacts the contact region of the first type and the contact region of the second type. The region arranged vertically between the top surface of the semiconductor body and the barrier region of the second type allows only a current of charge carriers of the second type to flow between the main electrode and the part of the drift region located laterally between the contact regions.

Description

[0001] The present disclosure relates to a semiconductor device, a method for operating a semiconductor device and a method for manufacturing a semiconductor device.

[0002] One challenge to be solved is to provide a semiconductor device that contributes to an improved plasma profile and / or an improved injection enhancement effect, particularly while reducing the possibility of latch-up during shutdown and thus improving RBSOA capability.

[0003] First, the semiconductor device will be described in more detail.

[0004] According to one embodiment, the semiconductor device comprises a semiconductor body with a contact region of a first type of conductivity, a contact region of a second type of conductivity, and a drift region of the first type of conductivity. The semiconductor device further comprises a main electrode and a gate electrode. A barrier region of a second type is arranged vertically between the drift region and the contact region of the second type. The barrier region of the second type forms a barrier to charge carriers of the second type. The contact region of the first type and the contact region of the second type are laterally separated from each other by a portion of the drift region. The gate electrode is arranged at least partially laterally between the contact region of the first type and the contact region of the second type.The contact region of the second type is arranged vertically between a top surface of the semiconductor body and the barrier region of the second type. The main electrode electrically contacts the contact region of the first type and the contact region of the second type. The region arranged vertically between the top surface of the semiconductor body and the barrier region of the second type allows only a current of charge carriers of the second type to flow between the main electrode and the portion of the drift region arranged laterally between the contact regions.

[0005] The present invention is based, among other things, on the concept of providing an additional second-type charge carrier extraction unit. Since the second-type charge carriers could be holes, this unit is also referred to as a "hole extracting accumulation-mode FET," or HEAF for short, or a "hole extracting enhancement-mode FET," or HEEF for short. This extraction unit provides an alternative path for second-type charge carrier extraction, and since this alternative path is located away from the contact area of ​​the first type, the entire device is less susceptible to parasitic thyristor latch-up and thus offers improved immunity to RBSOA failure.

[0006] The semiconductor body can comprise or consist of Si or SiC. The semiconductor body has a top and a bottom opposite the top. Furthermore, the semiconductor body has a principal extent plane, whereby the top and / or bottom may be at least partially parallel to the principal extent plane. Here, lateral directions are defined as directions parallel to the principal extent plane, and the vertical direction is defined as a direction perpendicular to the principal extent plane.

[0007] The contact area of ​​the first type is of a first conductivity type, which is, for example, an n-type, i.e., n-doped. The second conductivity type is the opposite of the first conductivity type, i.e., it could be a p-type or p-doped. The maximum or mean doping concentrations in the contact area of ​​the first type and / or the second type are, for example, at least 10 18 cm-3 or at least 10 19 cm -3 or at least 10 20 cm -3 The contact regions can also be referred to as "source regions". The contact region of the first type and / or the second type can be adjacent to the top surface of the semiconductor body, i.e., form part of it.

[0008] The drift region has the same conductivity profile as the contact region of the first type. Its maximum and / or mean doping concentration is, for example, at least 10, 100, or 1000 times lower than that of the contact region of the first and / or second type.

[0009] The main electrode, also referred to here as the "first main electrode," can be located on the top surface of the semiconductor body. It contacts both the first-type contact area and the second-type contact area. In particular, the main electrode borders the contact areas of both the first and second types. The main electrode can be made of metal. For example, the main electrode can be an emitter electrode.

[0010] A second main electrode, also called a "second main electrode," can be located on the underside of the semiconductor body and make contact with it. This second main electrode can be a collector electrode.

[0011] The second-type barrier region forms a barrier to second-type charge carriers. Therefore, during normal operation of the semiconductor device, no second-type charge carriers can pass through the second-type barrier region. The second-type barrier region can be formed from highly doped semiconductor material of the first conductivity type or from an electrically insulating material, such as an oxide like SiO₂. The second-type barrier region can border the drift region on one side and / or the second-type contact region on the other.

[0012] It is possible that the barrier region of the second type runs parallel to the top surface. For example, the length and width of the barrier region of the second type, measured laterally, exceed the thickness of the barrier region of the second type, measured vertically, by a factor of at least five or by a factor of at least ten and / or by a factor of at most 50.

[0013] The contact region of the first type and the contact region of the second type are spaced apart in a lateral direction, also referred to here as the "first lateral direction". A portion of the drift region is located laterally, i.e., in the first lateral direction, between the contact regions. This portion of the drift region is also referred to here as the "intermediate part". The intermediate part may be adjacent to the top surface of the semiconductor body.

[0014] In the first lateral direction, at least part of the gate electrode is located between the contact regions. The gate electrode can be made of metal or highly doped polysilicon. For example, the gate electrode is electrically isolated from the semiconductor body. In this case, the semiconductor device can be a gate-insulated device. In a top view of the semiconductor body, the gate electrode can overlap laterally between the contact regions with part of the drift region. Furthermore, in this top view, the gate electrode can overlap at least partially with the barrier region of the second type. The gate electrode can overlap at least partially with the contact region of the first type and the contact region of the second type in this top view.

[0015] Furthermore, the contact area of ​​the second type is arranged vertically, i.e., in a vertical direction, between the top surface and the barrier area of ​​the second type. In a top view of the top surface, the contact area of ​​the second type overlaps with the barrier area of ​​the second type.

[0016] The entire area arranged vertically between the top surface of the semiconductor body and the barrier region of the second type allows only a current of charge carriers of the second type, but not of charge carriers of the first type, to flow between the main electrode and the portion of the drift region laterally between the contact regions. This refers to the area that overlaps with the barrier region of the second type when viewed from the top surface. In other words, the entire area arranged vertically between the top surface of the semiconductor body and the barrier region of the second type is configured such that during normal operation (i.e., in the on-state and during turn-off), no current of charge carriers of the first type flows between the main electrode and the intermediate portion of the drift region and through the contact region of the second type.For example, this area is free of contact regions of the first conductivity type that are in electrical contact with the main electrode. For example, only semiconductor material of the second conductivity type is contacted by the main electrode in this area.

[0017] The barrier region of the second type, as well as the contact regions, may have a principal extent in a second lateral direction perpendicular to the first lateral direction. For example, the length of the barrier region of the second type and the contact regions measured in this second lateral direction is greater, e.g., at least 2, 5, or 10 times greater than the widths and thicknesses of these regions measured in the first lateral direction and the vertical direction, respectively. The contact region of the second type and the barrier region of the second type may be continuous and uninterrupted. For example, the length of the contact region of the second type is substantially equal to the length of the barrier region of the second type, e.g., with a deviation of no more than 10%.

[0018] According to a further embodiment, the semiconductor device is configured to allow, during normal / intended operation, e.g., during the off state, a current of charge carriers of the second type to be released from the drift region via the contact region of the second type to the main electrode. In particular, during normal operation, a current of charge carriers of the second type is allowed from the intermediate part of the drift region to the main electrode via the contact region of the second type.

[0019] According to a further embodiment, each path of charge carriers of the second type from the drift region to the main electrode across the contact region of the second type has at least one section that is arranged vertically between the top surface and the barrier region of the second type and extends laterally, particularly in the first lateral direction. In other words, the current paths of charge carriers of the second type extend from the drift region (intermediate part of the drift region) across the contact region of the second type at least partially, preferably mainly, laterally. In particular, the current paths in the region arranged vertically between the top surface and the barrier region of the second type, which, viewed from above, overlaps with the gate electrode, run essentially laterally (in the first lateral direction).

[0020] This can be achieved, for example, by offsetting the electrical contact between the main electrode and the contact area of ​​the second type in the first lateral direction from the edges of the barrier area of ​​the second type. In particular, the contact area of ​​the second type is further away from the first contact area in the first lateral direction than the edge of the barrier area of ​​the second type that faces the first contact area.

[0021] The offset or difference in distance can be, for example, at least 1 µm or at least 2 µm. In particular, the width of the barrier region of the second type can be greater than the width of the contact region of the second type, with widths being measured here in the first lateral direction.

[0022] According to a further embodiment, the semiconductor body further comprises a base region of the second type, which is either of the first or the second conductivity type. The base region of the second type is, for example, arranged vertically between the barrier region of the second type and the top surface. In a top-view view of the top surface, the base region of the second type may overlap with the gate electrode and / or the barrier region of the second type. For example, the barrier region of the second type borders the top surface and / or the barrier region of the second type.

[0023] According to a further embodiment, the contact area of ​​the second type is separated from the drift area, particularly from the intermediate part of the drift area, by the base area of ​​the second type at least in the lateral direction, and in particular at least in the first lateral direction. The contact area of ​​the second type can be adjacent to the base area of ​​the second type. For example, the base area of ​​the second type is arranged only laterally next to the contact area of ​​the second type, but neither vertically above nor vertically below the contact area of ​​the second type.

[0024] According to another embodiment, the doping concentration, e.g. the maximum and / or average doping concentration, in the base region of the second type is, e.g., by a factor of at least 10 or at least 100 or at least 1000, lower than in the contact region of the second type.

[0025] According to another embodiment, the gate electrode, viewed from the top of the semiconductor body, overlaps with the base region of the second type. For example, in this top view, the gate electrode completely overlaps with the base region of the second type.

[0026] According to a further embodiment, the semiconductor device is configured such that, in an on-state (e.g., Vge ≥ 0), the base region of the second type is blocking charge carriers of the second type, thus preventing a current of charge carriers of the second type from the drift region, particularly its intermediate portion, through the contact region of the second type to the main electrode. For example, by appropriately designing the base region of the second type and by appropriately adjusting the electrical potentials of the gate electrode, the main electrode, and the further main electrode, charge carriers of the first type can be accumulated in the base region of the second type, preventing a current flow of charge carriers of the second type through the base region. For example, the base region of the second type remains completely depleted during the on-state.With this feature, no degradation of the on-state (Vce-sat) occurs during the on-state. In particular, the base region of the second type is designed such that it remains completely depleted during normal operation in the on-state. Thus, no current flow of the charge carrier of the second type is permitted. This can be achieved, for example, if the thickness of the base region of the second type is small (e.g., < 1 µm) and / or if its doping concentration is low (e.g., < 10). 15 cm -3 ) or both.

[0027] According to a further embodiment, the semiconductor device is configured such that, in an off-state (e.g., Vge < 0 V), the base region of the second type is permeable to charge carriers of the second type, allowing a current of charge carriers of the second type from the drift region, particularly from its intermediate portion, to flow through the contact region of the second type to the main electrode. For this to occur, the electrical potentials of the electrodes must also be adjusted accordingly. For example, the thickness and / or doping concentration of the base region of the second type mentioned above enables a current flow in the off-state. In particular, the semiconductor device is designed such that every current path of charge carriers of the second type from the intermediate portion of the drift region to the contact region of the second type must pass through the base region of the second type.For example, by appropriately adjusting the electrical potential of the gate electrode, charge carriers of the second type can be accumulated in a part of the base region of the second type facing the gate electrode, so that this part enables the formation of the current path.

[0028] According to a further embodiment, the semiconductor body comprises a base region of the first type, which is of the second conductivity type. This base region of the first type is also referred to as the "well region." The mean and / or maximum doping concentration in the base region of the first type is, for example, at least 10, 100, or 1000 times lower than in the contact region of the first type.

[0029] According to a further embodiment, the contact area of ​​the first type is separated from the drift area by the base area of ​​the first type. For example, the contact area of ​​the first type borders the base area of ​​the first type. The second contact area can be at least partially embedded in the base area of ​​the first type.

[0030] According to a further embodiment, the gate electrode overlaps the base region of the first type in a top view of the semiconductor body. In particular, in this top view, a portion of the base region of the first type, located laterally between the intermediate part of the drift region and the contact region of the first type, is overlapped by the gate electrode. The base region of the first type, especially the portion that overlaps with the gate electrode, is depleted, followed by an inversion in an on-state of the semiconductor device. This allows a current flow of charge carriers of the first type from the main electrode to the drift region via the contact region of the first type and the inverted base region of the first type in an on-state of the semiconductor device. For this to occur, the electrical potentials of the electrodes must also be adjusted accordingly.

[0031] The semiconductor device is in particular a so-called planar device with the gate electrode on the top side of the semiconductor body.

[0032] According to a further embodiment, the semiconductor device further comprises a barrier region of the first type, which is arranged vertically between the drift region and the contact region of the first type. The barrier region of the first type forms a barrier for charge carriers of the second type. In particular, in a top view, the contact region of the first type and, optionally, the base region of the first type overlap with the barrier region of the first type. With regard to the properties and dimensions of the barrier region of the first type, all features disclosed herein for the barrier region of the second type are also disclosed for the barrier region of the first type, and vice versa.

[0033] For example, the first-type contact area and / or the first-type base area border the first-type barrier area. The first-type barrier area may also border the drift area. The first-type contact area may be laterally offset from the edges of the first-type barrier area. In particular, the width of the first-type contact area is smaller than the width of the first-type barrier area.

[0034] According to another embodiment, the contact area of ​​the first type is arranged vertically between the top surface and the barrier area of ​​the first type and overlaps with the barrier area of ​​the first type in a top view of the top surface.

[0035] Recently, trench devices, such as trench IGBTs, have become widely regarded as the preferred design choice compared to planar devices due to their superior on-state performance and improved technology curve (Eoff-Vcesat compromise). The trench design benefits, among other things, from its superior plasma profile, which results from a closely spaced vertical flux of electrons and holes near the emitter junction, leading to an injection enhancement effect. The plasma profile, and thus its on-state performance in a trench structure, can be further improved by increasing the emitter junction length, L. pcontThe length of the emitter contact is reduced, or in other words, by decreasing the distance between the trenches. In conventional planar devices, however, injected electrons from planar channels force holes to enter laterally close to the edge of the emitter contact. Consequently, the plasma profile, and therefore Vce-sat, cannot be easily improved in the conventional planar design by shortening the emitter contact length as in a trench device. Planar devices, however, offer other advantages, such as better long-term reliability (lifetime) and robust (SOA) performance compared to the trench design, along with a less complex (and therefore less expensive) fabrication process.

[0036] With the barrier region of the first type and the contact region of the first type, also referred to here as a trench-like planar (TLP) design, it is possible to design the electron and hole flow in the planar design to achieve the same or even improved on-state performance compared to the trench design, while retaining the original advantages of the planar design. In short, a design is achieved that combines the best of both worlds (trench and planar).

[0037] According to a further embodiment, the barrier area of ​​the first type and the barrier area of ​​the second type are laterally spaced apart from each other, in particular in the first lateral direction. The barrier area of ​​the first type and the barrier area of ​​the second type can be arranged at the same height in the vertical direction.

[0038] Such a semiconductor device with a barrier region below the first-type contact region is also referred to here as a "trench-type semiconductor device." It uses a barrier region to block the vertical path of second-type charge carriers, such as holes, and instead redirects the holes so that they flow parallel to the first-type charge carriers. This feature makes it possible to reduce the injection enhancement effect by reducing a side-emitter contact dimension, such as L. pcont , to further improve and achieve improved on-state performance and technology curve similar to a trench-design device. In contrast to trench-design devices, the design described here also enables a true point-contact emitter device without any lithographic limitations by reducing the vertical dimension L. pcontto realize. In short, the introduction of the above feature leads to significantly reduced losses in the switched-on state and a significantly improved technology curve compared to, for example, the planar design, making it a potential candidate for the new next-generation planar technology suitable for both low-voltage and high-voltage platforms.

[0039] According to a further embodiment, the semiconductor device comprises a further barrier region of the second type, which is arranged vertically between the barrier region of the second type and the contact region of the second type. The further barrier region of the second type may overlap with the contact region of the second type and / or the barrier region of the second type and / or the gate electrode when viewed from the top surface of the semiconductor body. In particular, the barrier region of the second type and the further barrier region of the second type may have the same width and / or length within the limits of the manufacturing tolerance.

[0040] According to a further embodiment, a further contact region of the second type, of the second conductivity type, is arranged vertically between the barrier region of the second type and the further barrier region of the second type. In a top view, the further contact region of the second type can overlap with the contact region of the second type and / or the further barrier region of the second type. The main electrode can electrically contact the further contact region of the second type, e.g., on a lateral side thereof. The contact region of the second type can be separated and spaced apart from the drift region by a further base region of the second type. The features disclosed above for the contact region of the second type and the base region of the second type are also disclosed for the further contact region of the second type and the further base region of the second type.

[0041] According to a further embodiment, the main electrode electrically contacts the further contact area of ​​the second type, e.g., on a lateral side thereof. A lateral side is a side pointing in a lateral direction, i.e., running obliquely or perpendicular to the main extension plane or to the top surface.

[0042] The semiconductor device can comprise several, i.e., two or more, additional barrier regions of the second type, arranged vertically between the barrier region of the second type and the contact region of the second type. Between each pair of barrier regions of the second type, an additional contact region of the second type and, optionally, an additional base region of the second type can be formed vertically. All features disclosed for one additional barrier region of the second type and one additional contact region of the second type are also disclosed for the other additional barrier regions of the second type and the other additional contact regions of the second type.

[0043] Vertical stacking of multiple (HEAF) units further enhances the beneficial effect of the HEAF unit.

[0044] Similarly, the semiconductor device can include one or more additional barrier regions of the first type, arranged vertically between the barrier region of the first type and the contact region of the first type. In this case, one or more additional contact regions of the first type, and optionally one or more additional base regions of the first type, can be arranged vertically between the barrier region of the first type and the additional barrier region of the first type, or between any two additional barrier regions of the first type. Like the contact region of the first type, the additional contact region(s) of the first type can be in electrical contact with the main electrode.

[0045] According to a further embodiment, part of the main electrode extends in a vertical direction, passing through the multiple barrier regions of the second type and electrically contacts the further contact region of the second type, in particular on a lateral side of the further contact regions of the second type.

[0046] According to a further embodiment, the barrier region of the second type consists of, or comprises, an electrically insulating material, such as SiO2. Additionally or alternatively, the barrier region of the second type consists of, or comprises, a semiconductor material of the first conductivity type. In this case, the maximum and / or average doping concentration of the semiconductor material of the barrier region of the second type can be at least 10 16 cm -3 or at least 10 18 cm -3 or at least 10 20 cm -3 The same applies to the barrier area of ​​the first type.

[0047] According to a further embodiment, the further barrier region of the second type comprises an electrically conductive layer which is electrically insulated from the semiconductor body by a dielectric layer.

[0048] According to another embodiment, the electrically conductive layer is in electrical contact either with the gate electrode or with the main electrode. It is also possible for the electrically conductive layer to be floating.

[0049] According to another embodiment, the semiconductor device comprises a plug region of the second conductivity type laterally adjacent to the contact region of the first type. For example, the plug region borders the contact region of the first type. Furthermore, the plug region can border the base region of the first type. For example, the plug region, like the contact region of the first type, is embedded within the base region of the first type. The maximum and / or average doping concentration of the plug region can be greater than that of the base region of the first type, for example, by a factor of at least 10, 100, or 1000. The plug region enables the formation of an additional pathway for the extraction of charge carriers of the second type in an off-state.

[0050] According to another embodiment, the main electrode electrically contacts the plug area, for example bordering the plug area.

[0051] According to a further embodiment, the gate electrode comprises at least two sections, namely a first and a second section, which are at least partially laterally spaced apart from each other. In particular, the two parts can be at least partially spaced apart in the first lateral direction. With such a gate electrode, the gate capacitance can be reduced.

[0052] According to another embodiment, the first part of the gate electrode is associated with the contact region of the first type, and the second part of the gate electrode is associated with the contact region of the second type. For example, in a top view of the semiconductor body, the second part of the gate electrode overlaps with the barrier region of the second type, and the first part of the gate electrode overlaps with the barrier region of the first type in this top view. Furthermore, in this top view, the space between the two parts of the gate electrode can overlap with the intermediate part of the drift region.

[0053] According to another embodiment, the main electrode electrically contacts the contact area of ​​the first type on its lateral side and contacts the contact area of ​​the second type on the top surface of the semiconductor body. This type of contacting, particularly the contact on the lateral side of the contact area of ​​the first type, allows the emitter contact length at the contact area of ​​the first type to be reduced. In this way, the plasma profile and Vce-sat can be improved.

[0054] According to another embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured for a maximum voltage between the main electrodes of at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV. Alternatively or additionally, the semiconductor device is configured for a current between the main electrodes of at least 0.01 kA, or at least 0.1 kA, or at least 1 kA, and / or at most 100 kA, or at most 10 kA. That is, by means of the gate electrode and the respective voltages between the main electrodes, a current flow through the semiconductor device can be controlled and, in particular, can be switched on and off by switching a voltage on and off at the gate electrode.

[0055] The semiconductor device can be a transistor, e.g., a gate-isolated transistor. Specifically, the semiconductor device is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting IGBT (RC-IGBT). The IGBT can have a planar design.

[0056] The following is a detailed description of the procedure for operating a semiconductor device.

[0057] According to one embodiment, the method serves to operate a semiconductor device according to any of the embodiments described herein. The method comprises a step of operating the semiconductor device in an on-state, in which charge carriers of the first type are injected from the main electrode into the contact area of ​​the first type. In another step, e.g., after operating the semiconductor device in the on-state, the semiconductor device is operated in an off-state, i.e., it is switched off, whereby charge carriers of the second type are caused to leave the semiconductor body via the contact area of ​​the second type into the first main electrode.

[0058] For example, during device operation, the first main electrode is at a negative potential relative to the second main electrode. In the on state, the gate electrode can be at a positive potential relative to the first main electrode. In the off state, the gate electrode can then be at a negative potential relative to the first main electrode.

[0059] The following is a detailed description of the method for manufacturing a semiconductor device. The method is particularly suitable for manufacturing a semiconductor device according to any of the embodiments described herein. All features disclosed in connection with the semiconductor device are therefore also disclosed for the method, and vice versa.

[0060] According to one embodiment, the method comprises a step of providing a base semiconductor body with a drift region of a first conductivity type and a step of forming a barrier region of the second type. The method further comprises a step of fabricating a semiconductor body from the semiconductor base body by forming semiconductor regions, namely a contact region of the first type of conductivity and a contact region of the second type of conductivity. The semiconductor regions are formed such that the barrier region of the second type is arranged vertically between the drift region and the contact region of the second type and forms a barrier to charge carriers of the second type.The contact region of the first type and the contact region of the second type are laterally separated from each other by a portion of the drift region, and the contact region of the second type is arranged vertically between the top surface of the semiconductor body and the barrier region of the second type. The method further comprises the steps of attaching a gate electrode such that the gate electrode is arranged at least partially laterally between the contact regions, and attaching a main electrode such that the main electrode electrically contacts the contact region of the first type and the contact region of the second type.

[0061] The second type of contact region can be formed on or at the top of the base semiconductor body. For example, the second type of barrier region is formed by ion implantation into the semiconductor base body or by depositing an electrically insulating material onto the semiconductor base body.

[0062] According to a further embodiment, the method includes a step of growing semiconductor material on the barrier region of the second type. For example, by growing the semiconductor material, the barrier region of the second type is completely embedded in semiconductor material.

[0063] According to another embodiment, the contact region of the second type is formed in the grown semiconductor material. For example, the contact region of the second type is formed by ion implantation in the grown semiconductor material.

[0064] According to a further embodiment, the method comprises a step in which a sacrificial layer and a mask layer are applied to the barrier region of the second type in that order, i.e., the sacrificial layer is applied to the barrier region of the second type before the mask layer. For example, the sacrificial layer borders the barrier region of the second type, and / or the mask layer borders the sacrificial layer.

[0065] According to a further embodiment, the sacrificial layer is then at least partially removed between the mask layer and the barrier region of the second type. This can be achieved by etching. For example, the sacrificial layer is removed in such a way that the (intermediate) part of the drift region, which is arranged laterally between the contact region of the first type and the contact region of the second type, is exposed. For example, the mask layer and the barrier region of the second type are etched less by the etchant than the sacrificial layer, so that the sacrificial layer and the barrier region of the second type remain intact when the etching process is applied.

[0066] According to a further embodiment, semiconductor material is then grown between the mask layer and the barrier region of the second type, with one growth direction being at least partially lateral. For example, the growth process begins at the exposed (intermediate) part of the drift region. The semiconductor material can then grow in the first lateral direction until it protrudes above the mask layer.

[0067] This method eliminates the need for a subsequent polishing step to provide a flat top surface of the semiconductor body.

[0068] The following is a more detailed explanation of the semiconductor device, the method for operating a semiconductor device, and the method for manufacturing a semiconductor device, with reference to the drawings and exemplary embodiments. The accompanying figures are included for better understanding. In the figures, elements with the same structure and / or functionality may be designated by the same reference numerals. It is understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. If elements or components in different figures correspond in their function, their description is not repeated for each of the following figures. For the sake of clarity, elements may not appear with corresponding reference numerals in all figures. Fig. Figures 1 to 12, 22 and 23 show different embodiments of the semiconductor device in a cross-sectional view. Fig. Figure 13 shows a flowchart of an embodiment of the method for operating a semiconductor device, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 shows different states in a first embodiment of the method for manufacturing a semiconductor device, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33 to Fig. Figure 34 shows different states in a second embodiment of the method for manufacturing a semiconductor device, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39 to Fig. Figure 40 shows different states in a third embodiment of the method for manufacturing a semiconductor device, Fig. 41, Fig. 42, Fig. 43, Fig. 44, Fig. 45 to Fig. Figure 46 shows different states in a fourth embodiment of the method for manufacturing a semiconductor device.

[0069] Fig. Figure 1 shows a first embodiment of the semiconductor device 100 in a cross-sectional view. The semiconductor device 100 is an IGBT in a planar design. Fig. Figure 1 shows a vertical direction V and a first lateral direction L1. These directions are the same in the following figures, but are not shown again in the following figures.

[0070] The semiconductor device 100 comprises a semiconductor body 1 with a top surface 10 and a bottom surface 19. The semiconductor body 1 includes a drift region 14 of a first conductivity type, which is hereinafter referred to as the n-type. The bottom surface 19 of the semiconductor body 1 is formed by a contact layer 13 of a second conductivity type, which is accordingly referred to as the p-type.

[0071] On its upper surface 10, the semiconductor body 1 comprises a contact area 11 of the first type and a contact area 12 of the second type. The contact area 11 of the first type is of the first conductivity type, and the contact area 12 of the second type is of the second conductivity type. The contact areas 11 and 12 are spaced apart from each other in the first lateral direction L1.

[0072] A second-type barrier region 42 is arranged vertically, i.e., in the vertical direction V, between the second-type contact region 12 and the drift region 14. During normal operation of the semiconductor device 100, the second-type barrier region 42 is opaque to second-type charge carriers (holes). For example, the second-type barrier region 42 consists of highly n-doped semiconductor material or an oxide, such as SiO2.

[0073] The semiconductor device 100 further comprises a base region 15 of the first type, which is p-doped, and a base region 16 of the second type. In the exemplary embodiment of Fig. 1. The basal region 16 of the second type is also p-doped, i.e., of the same conductivity type as the contact region 12 of the second type.

[0074] The doping concentration of the first-type basal area 15, also referred to as "trough area 15", is lower than in the first-type contact area 11, e.g., by a factor of at least 100. The first-type contact area 11 is embedded in the first-type basal area 15 and separated from the drift area 14 by the first-type basal area 15.

[0075] The doping concentration in the basal region 16 of the second type is lower than in the contact region 12 of the second type, e.g. by a factor of at least 100. The basal region 16 of the second type separates the contact region 12 of the second type from the drift region 14.

[0076] On the top surface 10 of the semiconductor body 1, a gate electrode 3 and a first main electrode 2 are arranged. On the bottom surface 19 of the semiconductor body 1, a second main electrode 4 is arranged. The first main electrode 2 electrically contacts the contact area 11 of the first type and the contact area 12 of the second type. The second main electrode 4 electrically contacts the contact layer 13. The gate electrode 3 is electrically insulated from the semiconductor body 1 and the first main electrode 2 by means of an insulating material 23. In a top view of the top surface 10, the gate electrode 3 overlaps the base areas 15, 16, so that the base areas 15, 16 can be depleted / inverted by appropriately adjusting the electrical potential of the gate electrode 3.

[0077] The operation of the semiconductor device 100 of Fig. 1 can be as follows: In an on-state, the first main electrode 2 is at a negative electrical potential with respect to the second main electrode 4. The gate electrode 3 is at a positive electrical potential with respect to the first main electrode 2. Accordingly, the portion of the basal regions 15, 16 below the gate electrode 3 becomes depleted of holes, followed by inversion and formation of the n-channel region below the gate electrode. Electrons can therefore be injected from the main electrode 2 into the first-type contact region 11 and can flow through the inverted portion or channel region of the first-type basal region 15 into the drift region 14. In the drift region 14, the electrons can then recombine with holes injected from the second main electrode 4 through the p-type contact layer 13.It should be noted that during one-state operation (Vge > 0 V) ​​the base region 16 remains completely depleted and therefore no part of the hole current flows out via the second contact region 12.

[0078] When the semiconductor device 100 is switched off, i.e., in a switch-off state, the electrical potential of the gate electrode 3 can be negative with respect to the electrical potential of the first main electrode 2. Accordingly, holes accumulate in a part of the second base region 16 facing the gate electrode 3. Holes from the drift region 14 can migrate through the accumulation part of the second-type base region 16 into the second-type contact region 12 and can from there be injected into the main electrode 2. This is indicated by the arrow of Fig. Figure 1 is shown. The holes migrate through the base region 16 of the second type in a direction parallel to the first lateral direction L1. Thus, the contact region 12 of the second type, together with the base region 16 of the second type, forms an alternative path for holes to reduce the electron-hole plasma in the drift region 14. However, some of the holes are also extracted via the base region 15 of the first type, as indicated by the vertical arrow in Figure 1. Fig. 1 indicated.

[0079] The Fig. 2 and Fig. Figure 3 shows another embodiment of the semiconductor device 100. Here too, the semiconductor device 100 is a planar IGBT. In contrast to the embodiment of Fig. However, a barrier region 41 of the first type is arranged below the contact region 11 of the first type and the base region 15 of the first type. This barrier region 41 of the first type is opaque to holes during the normal operation of the semiconductor device 100. Thus, during turn-off operation (Vge < 0V) (as in Fig. (2 shown) Holes extracted via the first-type basal region 15 migrate laterally below the first-type contact region 11. The hole flow direction is therefore essentially parallel to the electron flow direction during the on-state. In other words, during the off-state (Vge < 0V), p-type channel formation (via accumulation or inversion) occurs in the second basal region 16, providing an alternative path for hole extraction in addition to the path via the first basal region 15, as indicated by arrows in Fig. 2. The direction of electron flow is indicated by the arrow in Fig. Figure 3 shows the semiconductor device 100 in the on-state.

[0080] Fig. Figure 4 illustrates an embodiment of the semiconductor device 100, in which the Fig. The structure shown in Figure 3 is mirrored on the right. There are now two contact areas 11 of the first type with associated basal areas 15 of the first type and barrier areas 41 of the first type. The contact area 12 of the second type is located laterally between the two contact areas 11 of the first type and is located laterally between two basal areas 16 of the second type. As in Fig. As can be seen in Figure 4, the width of the barrier area 42 of the second type is greater than the width of the contact area 12 of the second type, i.e., the barrier area 42 of the second type extends beyond the contact area 12 of the second type in the first lateral direction L1 and in the direction opposite to the direction of the first lateral direction L1.

[0081] In the preceding embodiments, the barrier regions 41, 42 are formed, for example, from electrically insulating material such as SiO2.

[0082] The exemplary embodiment of Fig. Figure 5 shows the case in which the barrier regions 41, 42 are formed from a highly doped n-type semiconductor material. This also forms a barrier against holes.

[0083] Fig. Figure 6 shows an embodiment of the semiconductor device 100 in which several further barrier regions 42' of the second type are arranged vertically between the contact region 12 of the second type and the barrier region 42 of the second type. The barrier region 42 of the second type projects beyond the further barrier regions 42' of the second type in the first lateral direction L1. Another contact region 12' of the second type is arranged between each pair of barrier regions 42' of the second type. Each further contact region 12' of the second type is separated from the drift region 14 in the first lateral direction by another base region 16' of the second type. Furthermore, another contact region 12' of the second type and another base region 16' of the second type are arranged between the barrier region 42' of the second type that is closest to the barrier region 42 of the second type and the barrier region 42 of the second type.The second-type contact regions 12' and the associated second-type base regions 16' can be identical to the second-type contact region 12 and the second-type base region 16, for example, with respect to doping concentrations and relative spatial arrangement. The first main electrode 2 extends vertically across the second-type contact regions 12, 12' and contacts them on their lateral sides. Each of the units comprising a second-type contact region 12, 12' and a second-type base region 16, 16' provides a different path for hole extraction during the off-state.

[0084] A similar structure is formed on the side of first-type regions 11, 41, and 16. Here, too, several further first-type barrier regions 41' are arranged vertically between first-type barrier region 41 and first-type contact region 11. Between each pair of further first-type barrier regions 41', at least one corresponding first-type contact region 11' and one corresponding first-type base region 15' are arranged. The first main electrode 2 extends vertically in direction V over first-type contact region 11 and the further first-type contact regions 11', making electrical contact with them on their lateral sides. Each of the units comprising another first-type base region 15' and another first-type contact region 11' provides a current path for electrons during the on-state of the semiconductor device 100.

[0085] The semiconductor device 100 of Fig. 6 can be considered as a multi-trench planar device, with barrier areas 41, 41', 42, 42' forming trench-like structures that extend in lateral directions rather than in the vertical direction.

[0086] In Fig. The further battery regions 41' and 42' each comprise an electrically conductive layer 47, which is electrically insulated from the semiconductor body 1 by means of a dielectric layer 48. The electrically conductive layer 47 can be at the same potential as the gate electrode 3 or the first main electrode 2, or it can be floating.

[0087] Fig. Figure 7 shows another embodiment of the semiconductor device 100. Here, a plug region 17 is provided vertically between the barrier region 41 of the first type and the top surface 10 of the semiconductor body 1. The plug region 17 is of the second conductivity type, i.e., p-doped, and has a higher doping concentration than the base region 15 of the first type. The first main electrode 2 electrically contacts the plug region 17.

[0088] This plug region 17 allows for improved coverage of the emitter metal of the first main electrode 2 across the base region 15 / plug region 17, resulting in reduced contact resistance compared to side-contacted designs only, particularly during a turn-off transient. In the latter case, Lpcont is still determined by the thickness of the base region 15, and therefore injection gain can still be achieved by reducing Lpcont. It should be noted that, unlike what is described in Fig. As shown in Figure 7, the plug area 17 could also extend under the contact area 11 of the first type, i.e. vertically between the contact area 11 of the first type and the barrier area 1 of the first type.

[0089] In the preceding embodiments, the gate electrode 3 was configured to extend uninterrupted in the first lateral direction L1 from the region of contact area 11 of the first type to the region of contact area 12 of the second type. In these embodiments, the gate electrode was configured with a bridge-like structure such that a portion of the gate electrode 3 is located laterally between the base regions 15, 16 further from the semiconductor body 1 than the portions that overlap with the base regions 15, 16. This reduces the gate capacitance.

[0090] In the embodiment of Fig. Instead, gate electrode 3 has a hole in the region laterally between base regions 15 and 16. Therefore, gate electrode 3 comprises two parts, 31 and 32, which are at least partially separated from each other in the first lateral direction L1. Each of the parts 31 and 32 is associated either with its contact region 11 of the first type and base region 15 of the first type, or with contact region 12 of the second type and base region 16 of the second type. Such a so-called split-gate electrode allows for a further reduction of the gate capacitance.

[0091] Fig. Figure 9 shows an embodiment of the semiconductor device 100 in which an electrically conductive element 33 is arranged laterally between the two parts 31, 32. The electrically conductive element 33 is floating or electrically connected to the first main electrode 2. Furthermore, the electrically conductive element 33 is located at a greater or the same distance from the semiconductor body 1 as the parts 31, 32 of the gate electrode 3.

[0092] In the preceding embodiments, the base region 16 of the second type was always formed from semiconductor material of the second conductivity type, i.e., of the p-type. In the embodiment of Fig. The basal region 16 of the second type is formed from semiconductor material of the first conductivity type, i.e., of the n-type. The doping concentration can be lower than in the contact region 12 of the second type. In the off state of the semiconductor device 100, the portion of the basal region 16 of the second type facing the gate electrode 3 is depleted, followed by an inversion, so that a channel for charge carriers of the second type is formed. In this way, during the off state, holes can be extracted from the drift region 14 via the inverted portion of the basal region 16 of the second type and via the contact region 12 of the second type and injected from there into the first main electrode 2.

[0093] In contrast to the previous embodiments, in which the first main electrode 2 was always designed such that it protrudes in the direction V opposite to the vertical direction V beyond the contact area 11 of the first type and has electrically contacted the contact area 11 of the first type on a lateral side thereof, Fig. Figure 12 shows an embodiment of the semiconductor device 100 in which the first main electrode 2 electrically contacts the contact area 11 of the first type on the top surface 10 of the semiconductor body 1. The barrier area 41 of the first type borders the lateral side of the contact area 11 of the first type and covers this lateral side. In particular, the contact area 11 of the first type and the barrier area 41 of the first type are arranged at least partially at the same height in the vertical direction.

[0094] Fig. Figure 12 shows an embodiment of the semiconductor device 100, wherein the first main electrode 2 is guided vertically over the contact area 12 of the second type, the contact area 12 of the second type is electrically contacted on a lateral side thereof and extends to the barrier area 42 of the second type.

[0095] Fig. Figure 13 shows a flowchart of an embodiment of the method for operating a semiconductor device, e.g., any of those associated with the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. 12 described semiconductor devices. In a step S1, the semiconductor device is operated in its on-state, in which charge carriers of the first type, e.g. electrons, are injected from the main electrode 2 into the contact area 11 of the first type (see e.g. Fig. 3) In step S2, the semiconductor device is then switched off, i.e., operated in its off state, in which charge carriers of the second type are caused to leave the semiconductor body via the contact area 12 of the second type into the first main electrode 2 (see, for example, Fig. 1 and Fig. 2).

[0096] Fig. Figure 14 shows a first state in a first embodiment of the method for fabricating a semiconductor device. A base semiconductor body 1' is provided, comprising a drift region 14 and a contact layer 13. The drift region 14 is of a first conductivity type, and the contact layer 13 is of a second conductivity type.

[0097] Fig. Figure 15 shows a state in which a barrier layer 40 is applied to the top of the base semiconductor body 1'.

[0098] In Fig. Figure 16 shows a state in which part of the barrier layer 40 has been removed, leaving two barrier areas, namely a barrier area 41 of the first type and a barrier area 42 of the second type, spaced apart from each other in the first lateral direction L1.

[0099] In the state of Fig. 17 Semiconductor material 18 was grown over the barrier region 18 of the first type 41 and the barrier region of the second type 42 and in the region laterally in between.

[0100] In the state of Fig. In step 18, a contact region 11 of the first type was formed by a first conductivity type, and a base region 15 of the first type was formed by a second conductivity type in the region of the barrier region 41 of the first type. Furthermore, a contact region 12 of the second type and a base region 16 of the second type were formed above the barrier region 42 of the second type. Both regions 12 and 16 are of the second conductivity type. In this way, a semiconductor body 1 was formed from the base semiconductor body 1'.

[0101] Fig. Figure 19 shows a state in which a layer of electrically insulating material 23, e.g. SiO2, has been applied to the top of the semiconductor body 1.

[0102] In the state of Fig. 20 a part of the semiconductor body 1 was removed, e.g. etched away, so that a lateral side of the contact area 11 of the first type and a lateral side of the base area 15 of the first type are exposed and so that a top side of the barrier area 41 of the first type is exposed.

[0103] Fig. Figure 21 shows a state after a gate electrode 3 has been applied to the electrically insulating material 23. In a top view of the top surface of the semiconductor body 1, the gate electrode 3 overlaps with the portion of the base region 15 of the first type that is located laterally between the contact region 11 of the first type and the contact region 12 of the second type, and in the same top view also overlaps with the base region 16 of the second type.

[0104] In the state of Fig. 22 the gate electrode 3 is covered by additional electrically insulating material 23.

[0105] In Fig. 23. A first main electrode 2 was deposited onto the top surface of the semiconductor body 1 such that it electrically contacts the contact area 11 of the first type and the base area 15 of the first type on their lateral sides, as well as the contact area 12 of the second type on its top surface. The first main electrode 2 extends laterally over the gate electrode 3.

[0106] Furthermore, a second main electrode 4 has been applied such that it contacts the contact layer 30 on the underside of the semiconductor body 1. At the same time, it shows Fig. 23 a completed semiconductor device 100 in the form of a planar IGBT.

[0107] Fig. 24 shows a first state in a second embodiment of the method, which is the same state as in Fig. 14 is shown.

[0108] In Fig. Figure 25 shows another state of the second embodiment of the method, which is the same state as in Figure 25. Fig. 15 is shown.

[0109] In the state of Fig. 26. Part of the barrier layer 40 was removed, as in connection with Fig. 16 explained. Furthermore, a sacrificial layer 5 was applied to the barrier regions 41, 42 and the exposed part of the base semiconductor body 1' laterally between them. The sacrificial layer 5 consists, for example, of carbon.

[0110] In the state of Fig. In step 27, a mask layer 6 was applied to the sacrificial layer 5. The mask layer 6 can be a photoresist layer or a hard mask layer, such as a metal layer.

[0111] In the state of Fig. In step 28, part of the mask layer 6 was removed, exposing the upper side of the sacrificial layer 5. This may have been done with an additional mask.

[0112] In Fig. 29. A part of the sacrificial layer 5 below the mask layer 6 was removed, e.g. by etching, and thereby a part of the drift area 14 and the barrier area 41 of the first type were exposed.

[0113] Fig. Figure 30 shows a state after the semiconductor material 18 has been grown on the exposed drift region 14 and the exposed barrier region 41 of the first type such that the semiconductor material 18 has been grown in a lateral direction between the barrier region 41 of the first type and the mask layer 6.

[0114] In Fig. 31 The remaining sacrificial layer 5 between the mask layer 6 and the contact area 42 of the second type was removed, e.g. again by etching, and a part of the drift area 14 and the barrier area 42 of the second type was thereby exposed again.

[0115] In Fig. 32 Another growth process was carried out such that semiconductor material 18 was grown between the mask layer 6 and the barrier region 42 of the second type with a growth direction in the first lateral direction.

[0116] In Fig. 33 The mask layer was removed, so that a top side of the grown semiconductor material 18 was exposed.

[0117] In Fig. 34. The contact area 11 of the first type, the base area 15 of the first type, the contact area 12 of the second type, and the base area 16 of the second type were formed in the grown part of the semiconductor material, e.g., by means of ion implantation. In this way, a semiconductor body 1 is produced, which can be used, for example, to expand the semiconductor device 100. Fig. to generate 23.

[0118] Fig. Figure 35 shows a state in the third embodiment of the method for manufacturing a semiconductor device. It is the same state as in Fig. 27 shown. However, the mask layer 6 is now left symmetrical, and the sacrificial layer below the mask layer 6 has been completely removed, e.g. by etching (see condition of Fig. 36).

[0119] In the state of Fig. 37 Semiconductor material 18 was grown on the exposed drift region 14 such that the semiconductor material grew in a lateral direction between the barrier region 41 of the first type and the mask layer 6 as well as between the barrier region 42 of the second type and the mask layer 6.

[0120] In the state of Fig. 38. Parts of the mask layer 6 and the grown semiconductor material 18 have been removed, e.g., by etching. The etching of the semiconductor material 18 can be carried out before or after the removal of the mask layer 6 (see condition of Fig. 39) will be carried out.

[0121] Fig. Figure 40 shows a position after the contact area 11 of the first type, the base area 15 of the first type, the contact area 12 of the second type, and the base area 16 of the second type have been formed in the grown part of the semiconductor material, e.g., by ion implantation. In this way, a semiconductor body 1 is produced, which can be used, for example, to mount the semiconductor device 100. Fig. to generate 23.

[0122] In contrast to the second embodiment, the third embodiment of the method uses only one growth step to produce the semiconductor body 1 from the semiconductor base body 1'.

[0123] Fig. Figure 41 shows a state in a fourth embodiment of the method for manufacturing a semiconductor device. This state is the same as in Figure 41. Fig. 28 shown.

[0124] In the state of Fig. 42. Part of the sacrificial layer 5 below the mask layer 6 was removed, e.g. by etching, and part of the drift area 14 and the barrier area 41 of the first type were thereby exposed.

[0125] In the state of Fig. 43 Semiconductor material 18 was grown on the exposed drift region 14 and the exposed barrier region 41 of the first type such that the semiconductor material 18 was grown laterally between the barrier region 41 of the first type and the mask layer 6. The semiconductor material was doped in situ, i.e., during growth, so that the base region 15 of the first type was formed.

[0126] Fig. Figure 44 shows a state in which the remaining sacrificial layer 5 between the mask layer 6 and the contact area 42 of the second type has been removed, e.g. again by etching, and again part of the drift area 14 and the barrier area 42 of the second type has been exposed.

[0127] In the state of Fig. 45 Another growth process was carried out such that semiconductor material 18 was grown between the mask layer 6 and the barrier region 42 of the second type with a growth direction in the first lateral direction. Here too, in-situ doping was carried out so that the base region 16 of the second type and the contact region 12 of the second type were formed during growth.

[0128] Fig. Figure 46 shows a state after removal of the mask layer 6 and after formation of the contact area 11 of the first type by implantation. In the fourth embodiment, therefore, only one implantation step is required. From the state of Fig. 46 can, for example, be a semiconductor device 100 as in Fig. 23 are shown to be generated.

[0129] The in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32, Fig. 33, Fig. 34, Fig. 35, Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43, Fig. 44, Fig. 45 to Fig. The embodiments shown in Figure 46, as indicated, represent exemplary embodiments of the semiconductor device, the method for operating a semiconductor device, and the method for manufacturing a semiconductor device; therefore, they do not constitute a complete list of all embodiments of the semiconductor device, the method for operating a semiconductor device, and the method for manufacturing a semiconductor device. Actual semiconductor devices, methods for operating a semiconductor device, and methods for manufacturing a semiconductor device may differ from the embodiments shown, for example, with regard to arrangements, elements, and the sequence of process steps. Reference sign 1 Semiconductor body 1' Semiconductor body 2 (first) main electrode 3 Gate electrode 4 additional / second main electrode 5. Victimhood layer 6 mask layers 10 Top 11 Type 1 contact area 11' further contact area of ​​the first type 12 Type II contact area 12' further contact area of ​​the second type 13 Contact layer 14 Drift area 15 Base area of ​​the first type 15' further base area of ​​the first type 16 Base area of ​​the second type 16' further base area of ​​the second type 17 Plug-in area 18 Semiconductor material 19 Subpage 23 electrically insulating material 31 first part of the gate electrode 32 second part of the gate electrode 33 electrically conductive element 40 barrier layer 41 Type 1 barrier area 41' further barrier area of ​​the first type 42 Type II barrier area 42' further barrier area of ​​the second type 47 electrically conductive layer 48 dielectric layer 100 semiconductor devices L1 first lateral direction V Vertical direction S1 Procedure step S2 process step

Claims

[1] Semiconductor device (100), comprising: - a semiconductor body (1) with a contact area (11) of a first type of conductivity type, a contact area (12) of a second type of conductivity type and a drift area (14) of the first conductivity type, - a main electrode (2) and a gate electrode (3), wherein - a barrier region (42) of the second type is arranged vertically between the drift region (14) and the contact region (12) of the second type, wherein the barrier region (42) of the second type forms a barrier for charge carriers of the second type, - the contact area (11) of the first type and the contact area (12) of the second type are laterally separated from each other by a part of the drift area (14), - the gate electrode (3) is arranged at least partially laterally between the contact areas (11, 12), - the contact area (12) of the second type is arranged vertically between a top surface (10) of the semiconductor body (1) and the barrier area (42) of the second type, - the main electrode (2) electrically contacts the contact area (11) of the first type and the contact area (12) of the second type, - the area arranged vertically between the top (10) of the semiconductor body (1) and the barrier region (42) of the second type only allows a current of charge carriers of the second type to flow between the main electrode (2) and the part of the drift region (14) arranged laterally between the contact regions (11, 12). [2] Semiconductor device (100) according to claim 1, wherein - the semiconductor device (100) is designed such that - during normal operation a current of charge carriers of the second type from the drift region (14) via the contact region (12) of the second type to the main electrode (2) is enabled, - each path of charge carriers of the second type from the drift region (14) via the contact region (12) of the second type to the first main electrode (2) has a section that is arranged vertically between the top (10) and the barrier region (42) of the second type and extends in a lateral direction. [3] Semiconductor device (100) according to claim 2, wherein - the semiconductor body (1) further comprises a base region (16) of the second type, which is either of the first or of the second conductivity type, - the contact area (12) of the second type is separated from the drift area (14) by the base area (16) of the second type at least in the lateral direction (L1), - the doping concentration in the base region (16) of the second type is lower than in the contact region (12) of the second type, - the gate electrode (3) overlaps with the base region (16) of the second type in a top view of the top surface (10) of the semiconductor body (1), such that - in an on-state of the semiconductor device (100) the base region (16) of the second type is blocking charge carriers of the second type, so that a current of charge carriers of the second type from the drift region (14) via the contact region (12) of the second type to the main electrode (2) is prevented, - in a switched-off state of the semiconductor device (100) the base region (16) of the second type is permeable to the charge carriers of the second type, so that a current of charge carriers of the second type from the drift region (14) via the contact region (12) of the second type to the first main electrode (2) is enabled, [4] Semiconductor device (100) according to any one of the preceding claims, wherein - the semiconductor body (1) comprises a base region (15) of the first type, which is of the second conductivity type, - the contact area (11) of the first type is separated from the drift area (14) by the base area (15) of the first type, - the gate electrode (3) overlaps the base region (15) of the first type in a top view of the top (10) of the semiconductor body (1), so that the base region (15) of the first type is depleted, followed by an inversion by appropriate adjustment of the electrical potential of the gate electrode (3) in order to allow, in an on-state of the semiconductor device (100), a current flow of charge carriers of the first type from the main electrode (2) via the contact region (11) of the first type and the inverted base region (15) of the first type to the drift region (14). [5] Semiconductor device (100) according to any one of the preceding claims, further comprising: - a barrier region (41) of the first type, which is arranged vertically between the drift region (14) and the contact region (11) of the first type and which forms a barrier for charge carriers of the second type, wherein - the contact area (11) of the first type is arranged vertically between the top surface (10) and the barrier area (41) of the first type and overlaps with the barrier area (41) of the first type in plan view of the top surface (10), - the barrier area of ​​the first type (41) and the barrier area of ​​the second type (42) are laterally separated from each other. [6] Semiconductor device (100) according to any one of the preceding claims, comprising: - a further barrier area (42') of the second type, arranged vertically between the barrier area (42) of the second type and the contact area (12) of the second type, wherein - at least one further barrier area (42') of the second type overlaps in plan view with the contact area (12) of the second type on the top surface (10), - wherein a further contact area (12') of the second type of conductivity is arranged vertically between the barrier area (42) of the second type and the further barrier area (42') of the second type, - the main electrode (2) electrically contacts the further contact area (12') of the second type. [7] Semiconductor device (100) according to claim 6, wherein - a part of the main electrode (2) extends in the vertical direction (V), thereby passing through the several barrier areas (42, 42') of the second type and electrically contacting the further contact area (12') of the second type. [8] Semiconductor device (100) according to any one of the preceding claims, wherein - the barrier area (42) of the second type consists of an electrically insulating material and / or - the barrier region (42) of the second type consists of semiconductor material of the first conductivity type. [9] Semiconductor device (100) according to claim 6 or one of claims 7 to 8 depending on claim 6, wherein: - the second barrier region (42') of the second type comprises an electrically conductive layer (47) which is electrically insulated from the semiconductor body (1) by means of a dielectric layer (48), - the electrically conductive layer (47) is in electrical contact either with the gate electrode (3) or with the main electrode (2). [10] Semiconductor device (100) according to any one of the preceding claims, further comprising: - a plug area (17) of the second conductivity type lateral to the contact area (11) of the first type, wherein - the main electrode (2) electrically contacts the plug area (17). [11] Semiconductor device (100) according to any one of the preceding claims, wherein - the gate electrode (3) comprises at least two parts (31, 32) which are at least partially laterally spaced apart from each other, - a first part (31) of the gate electrode (3) is assigned to the contact area (11) of the first type, - a second part (32) of the gate electrode (3) is assigned to the contact area (12) of the second type. [12] Semiconductor device (100) according to any one of the preceding claims, wherein - the main electrode (2) electrically contacts the contact area (11) of the first type on a lateral side of it and the contact area (12) of the second type contacts the top (10) of the semiconductor body (1). [13] Semiconductor device (100) according to any one of the preceding claims, wherein - the semiconductor device (100) is an IGBT. [14] Method for operating a semiconductor device (100) according to any one of the preceding claims, wherein the method comprises the following steps: - Operating the semiconductor device (100) in an on-state in which charge carriers of the first type are injected from the main electrode (2) into the contact area (11) of the first type, - Operating the semiconductor device (100) in a switched-off state in which charge carriers of the second type are caused to leave the semiconductor body (1) via the contact area (12) of the second type into the main electrode (2). [15] Method for manufacturing a semiconductor device (100) comprising the following steps: - Providing a base semiconductor body (1') with a drift region (14) of a first conductivity type, - Formation of a barrier area (42) of the second type, - Manufacturing a semiconductor body (1) from the semiconductor base body (1') by forming semiconductor regions, namely a contact region (11) of the first type of conductivity type and a contact region (12) of the second type of conductivity type, such that - the barrier region (42) of the second type is arranged vertically between the drift region (14) and the contact region (12) of the second type and forms a barrier for charge carriers of the second type, - the contact area (11) of the first type and the contact area (12) of the second type are laterally separated from each other by a part of the drift area (14), - the contact area (12) of the second type is arranged vertically between a top surface (10) of the semiconductor body (1) and the barrier area (42) of the second type, - Attaching a gate electrode (3) such that the gate electrode (3) is arranged at least partially laterally between the contact areas (11, 12), - Attaching a main electrode (2) such that the main electrode (2) electrically contacts the contact area (11) of the first type and the contact area (12) of the second type. [16] The method of claim 15, further comprising: - Growth of semiconductor material (18) on the barrier region (42) of the second type, wherein - the contact area (12) of the second type is formed in the grown semiconductor material (18). [17] Method according to claim 16, wherein - a sacrificial layer (5) and a mask layer (6) are applied in this order to the barrier area (42) of the second type, - the victim layer (5) is then at least partially removed between the mask layer (6) and the barrier area (42) of the second type, - then semiconductor material (18) is grown between the mask layer (6) and the barrier region (42) of the second type, with one growth direction being at least partially in the lateral direction.

Images