SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a SiC chip having a first main surface and a second main surface, an element structure formed in the first main surface, and an electrode formed on the second main surface and electrically connected to the element structure, and an arithmetic mean roughness (Ra) of the second main surface is not less than 30 nm. Thereby, a low-resistance ohmic contact can be formed on the second main surface on the side opposite to the element structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application corresponds to Japanese Patent Application No. 2023-004565 filed on January 16, 2023 with the Japan Patent Office, and Japanese Patent Application No. 2024-001479 filed on January 9, 2024 with the Japan Patent Office, and the entire disclosures of these applications are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device. State of the art

[0003] For example, Patent Literature 1 discloses a SiC semiconductor device including a SiC semiconductor layer having a laminate structure including a SiC semiconductor substrate and a SiC epitaxial layer, and having a first main surface (element formation surface) formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer, and a modified line formed on the side surface in a portion composed of the SiC semiconductor substrate at a distance from the SiC epitaxial layer and modified to have a property different from the SiC semiconductor substrate. List of citationsPatent literature

[0004] Patent Literature 1: Japanese Patent Application Publication No. 2022-166265 [Abstract] A semiconductor device according to a preferred embodiment of the present disclosure includes a SiC chip having a first main surface and a second main surface, an element structure formed on the first main surface, and an electrode formed on the second main surface and electrically connected to the element structure, and an arithmetic mean roughness (Ra) of the second main surface is not less than 30 nm.

[0005] In the semiconductor device according to the preferred embodiment of the present disclosure, since the arithmetic mean roughness (Ra) of the second main surface of the SiC chip is not less than 30 nm, a contact area between the SiC chip and the electrode can be made large. Consequently, the semiconductor device can be provided that enables the formation of a low-resistance ohmic contact on the second main surface on the side opposite the element structure. Brief description of the drawings [ Fig. 1] Fig. 1 is a diagram showing a unit cell of a 4H-SiC single crystal to which preferred embodiments of the present disclosure are applied. [ Fig. 2] Fig. Figure 2 is a plan view showing a silicon plane of the unit cell of the 4H-SiC single crystal of Fig. 1 shows. [ Fig. 3] Fig. 3 is a schematic perspective view of a semiconductor device according to a first preferred embodiment of the present disclosure. [ Fig. 4] Fig. 4 is a schematic plan view of the semiconductor device of Fig. 3. [ Fig. 5] Fig. 5 is a sectional view along the line VV of Fig. 4. [ Fig. 6] Fig. 6 is an enlarged view of a Fig. 5 shown area VI. [ Fig. 7] Fig. 7 is a schematic plan view of a semiconductor device according to a second preferred embodiment of the present disclosure. [ Fig. 8] Fig. Figure 8 is a sectional view along the line VIII-VIII of Fig. 7. [ Fig. 9] Fig. 9 is a schematic sectional view of a semiconductor device according to a third preferred embodiment of the present disclosure. [ Fig. 10] Fig. 10 is a schematic sectional view of a semiconductor device according to a fourth preferred embodiment of the present disclosure. [ Fig. 11] Fig. 11 is a schematic sectional view of a semiconductor device according to a fifth preferred embodiment of the present disclosure. [ Fig. 12] Fig. 12 is a perspective view showing a semiconductor wafer used in the manufacture of semiconductor devices. [ Fig. 13A] Fig. 13A is a diagram showing a portion of a manufacturing process of the semiconductor devices. [ Fig. 13B] Fig. 13B is a diagram showing one step after that of Fig. 13A shows. [ Fig. 13C] Fig. 13C is a diagram one step after that of Fig. 13B shows. [ Fig. 13D] Fig. 13D is a diagram one step after that of Fig. 13C shows. [ Fig. 13E] Fig. 13E is a diagram one step after that of Fig. 13D shows. [ Fig. 14] Fig. 14 is a diagram showing a first shape (square shape) of laser marks formed on a back surface of a chip. [ Fig. 15] Fig. 15 is a diagram showing a second shape (circular shape) of laser marks formed on the back surface of the chip. [ Fig. 16] Fig. 16 is a photographic illustration showing the first shape (square shape) of laser marks formed on the back surface of the chip. [ Fig. 17] Fig. 17 is a photographic illustration showing the second shape (circular shape) of laser marks formed on the back surface of the chip. [ Fig. 18] Fig. 18 is a photographic illustration showing a modification example of the first shape (square shape) of laser marks formed on the back surface of the chip. [ Fig. 19] Fig. 19 is a photographic illustration showing a modification example of the second shape (circular shape) of laser marks formed on the back surface of the chip. [ Fig. 20] Fig. 20 is a diagram showing a third shape (square shape) of laser marks formed on the back surface of the chip. [ Fig. 21] Fig. 21 is a diagram showing a fourth shape (square shape) of laser marks formed on the back surface of the chip. [ Fig. 22] Fig. 22 is a diagram showing a fifth shape (circular shape) of laser marks formed on the back surface of the chip. [ Fig. 23] Fig. 23 is a diagram showing a contact resistance distribution of a wafer back surface and a state of the wafer back surface according to Sample 1. [ Fig. 24] Fig. 24 is a diagram showing a contact resistance distribution of a wafer back surface and a wafer back surface state according to Sample 2. Description of Embodiments

[0006] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [Crystal structure of the SiC single crystal]

[0007] In each preferred embodiment of the present disclosure, a SiC single crystal (silicon carbide single crystal) composed of a hexagonal crystal is used. The SiC single crystal composed of the hexagonal crystal has a variety of polytypes, including a 2H (hexagonal) SiC single crystal, a 4H SiC single crystal, a 6H SiC single crystal, and so on, according to the period of the atomic arrangement. Although an example employing the 4H SiC single crystal is described in each preferred embodiment of the present disclosure, this does not exclude other polytypes from the present disclosure.

[0008] A crystal structure of the 4H-SiC single crystal is described below. Fig. 1 is a diagram showing a unit cell of the 4H-SiC single crystal (hereinafter referred to simply as “unit cell”) to which the preferred embodiments of the present disclosure are applied. Fig. Figure 2 is a plan view showing a silicon plane of the unit cell of the 4H-SiC single crystal of Fig. 1 shows.

[0009] With reference to Fig. 1 and Fig. 2, the unit cell includes tetrahedral structures in which four C atoms are bonded to a single Si atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell exhibits an atomic arrangement in which the tetrahedral structures are stacked in a period of four. The unit cell exhibits a hexagonal prism structure with a silicon plane of regular hexagonal shape, a carbon plane of regular hexagonal shape, and six side planes connecting the silicon plane and the carbon plane.

[0010] The silicon plane is a terminal plane terminated by Si atoms. On the silicon plane, a single Si atom is positioned at each of the six vertices of a regular hexagon, and a single Si atom is positioned at the center of the regular hexagon.

[0011] The carbon plane is an end plane terminated by C atoms. On the carbon plane, a single C atom is positioned at each of the six vertices of a regular hexagon, and a single C atom is positioned at the center of the regular hexagon.

[0012] Crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, and c), including an a1 axis, an a2 axis, an a3 axis, and a c axis. Of the four coordinate axes, a value of a3 takes the value -(a1+a2). The crystal planes of the 4H-SiC single crystal are described below, taking the silicon plane as an example of an end plane of the hexagonal crystal.

[0013] In a plan view of the silicon plane viewed from the c-axis, the a1-axis, a2-axis, and a3-axis are each defined along the arrangement directions of the nearest neighboring Si atoms (hereinafter referred to simply as "nearest neighbor directions"), based on the Si atom positioned at the center. The a1-axis, a2-axis, and a3-axis are each shifted by 120° according to the arrangement of the Si atoms.

[0014] The c-axis is aligned normal to the silicon plane, based on the Si atom positioned at the center. The silicon plane is a (0001) plane. The carbon plane is a (000-1) plane.

[0015] The side planes of the hexagonal prism enclose six crystal planes, which, in the plan view of the silicon plane from the c-axis, are aligned along the direction of the nearest neighboring atoms. Specifically, the side planes of the hexagonal prism enclose six crystal planes, each of which has two nearest neighboring Si atoms in the plan view of the silicon plane from the c-axis.

[0016] In the plan view of the silicon plane viewed from the c-axis, the side planes of the hexagonal prism include, clockwise from a vertex of the a1-axis, a (1-100) plane, a (0-110) plane, a (-1010) plane, a (-1100) plane, a (01-10) plane, and a (10-10) plane.

[0017] Diagonal planes aligned along diagonal lines of the hexagonal prism include six crystal planes aligned along intersecting directions that intersect the directions of the nearest neighbor atoms in the plan view of the silicon plane from the c-axis. More specifically, the diagonal planes of the hexagonal prism include six crystal planes, each containing two Si atoms that are not nearest neighbors in the plan view of the silicon plane from the c-axis. Based on the Si atom positioned at the center, the directions that intersect the directions of the nearest neighbor atoms are orthogonal directions, which are orthogonal to the directions of the nearest neighbor atoms.

[0018] In the plan view of the silicon plane viewed from the c-axis, the diagonal planes of the hexagonal prism include a (11-20) plane, a (1-210) plane, a (-2110) plane, a (-1-120) plane, a (-12-10) plane, and a (2-1-10) plane.

[0019] The crystal directions of the unit cell are defined by normal directions to the crystal planes. A normal direction to the (1-100) plane is a [1-100] direction. A normal direction to the (0-110) plane is a [0-110] direction. A normal direction to the (-1010) plane is a [-1010] direction. A normal direction to the (-1100) plane is a [-1100] direction. A normal direction to the (01-10) plane is a [01-10] direction. A normal direction to the (10-10) plane is a [10-10] direction.

[0020] A normal direction to the (11-20) plane is a [11-20] direction. A normal direction to the (1-210) plane is a [1-210] direction. A normal direction to the (-2110) plane is a [-2110] direction. A normal direction to the (-1-120) plane is a [-1-120] direction. A normal direction to the (-12-10) plane is a [-12-10] direction. A normal direction to the (2-1-10) plane is a [2-1-10] direction.

[0021] The hexagonal crystal has sixfold symmetry, with equivalent crystal planes and equivalent crystal directions occurring every 60°. For example, the (1-100) plane, the (0-110) plane, the (-1010) plane, the (-1100) plane, the (0-10) plane, and the (10-10) plane form equivalent crystal planes.

[0022] In addition, the [1-100] direction, the [0-110] direction, the [-1010] direction, the [-1100] direction, the [01-10] direction, and the [10-10] direction form equivalent crystal directions. Furthermore, the [11-20] direction, the [1-210] direction, the [-2110] direction, the [-1-120] direction, the [-12-10] direction, and the [2-1-10] direction form equivalent crystal directions.

[0023] The c-axis runs in the

[0001] direction ([000-1] direction). The a1-axis runs in the [2-1-10] direction ([-2110] direction). The a2-axis runs in the [-12-10] direction ([1-210] direction). The a3-axis runs in the [-1-120] direction ([11-20] direction).

[0024] The (0001) plane and the (000-1) plane are collectively called c-planes. The

[0001] direction and the [000-1] direction are collectively called c-axis directions. The (11-20) plane and the (-1-120) plane are collectively called a-planes. The [11-20] direction and the [-1-120] direction are collectively called a-axis directions. The (1-100) plane and the (-1100) plane are collectively called m-planes. The [1-100] direction and the [-1100] direction are collectively called m-axis directions. [Semiconductor Device 1A According to a First Preferred Embodiment]

[0025] Fig. 3 is a schematic perspective view of a semiconductor device 1A according to a first preferred embodiment of the present disclosure, viewed from an angle. Fig. 4 is a plan view of the Fig. 3 shown semiconductor device 1A. Fig. 5 is a sectional view along the Fig. 4 shown line VV.

[0026] With reference to Fig. 3 to Fig. 5, the semiconductor device 1A in this embodiment is a SiC semiconductor device and includes a SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a 4H-SiC single crystal as an example of a SiC single crystal composed of a hexagonal crystal. The SiC semiconductor layer 2 is formed in a chip shape with a rectangular parallelepiped shape.

[0027] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on another side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrilateral shape (a square shape in this embodiment) when viewed from a normal direction Z thereto in plan view (hereinafter simply referred to as "plan view").

[0028] The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is composed of a ground surface with grinding marks. The side surfaces 5A to 5D are each composed of a smooth cleavage surface arranged along a crystal plane of the SiC single crystal. The side surfaces 5A to 5D have no grinding marks.

[0029] A thickness TL of the SiC semiconductor layer 2 may be not less than 50 µm and not more than 350 µm. The thickness TL may be not less than 80 µm and not more than 350 µm, not less than 100 µm and not more than 350 µm, not less than 150 µm and not more than 350 µm, not less than 50 µm and not more than 300 µm, not less than 80 µm and not more than 300 µm, not less than 100 µm and not more than 300 µm, not less than 150 µm and not more than 300 µm, not less than 50 µm and not more than 250 µm, not less than 80 µm and not more than 250 µm, not less than 100 µm and not more than 250 µm or not less than 150 µm and not more than 250 µm. The thickness TL is preferably not less than 50 µm and not more than 350 µm, and more preferably not less than 50 µm and not more than 300 µm.As long as the thickness TL is within the above ranges, a series resistance of a Schottky barrier diode D can be reduced, and thus an on resistance of the Schottky barrier diode D can be reduced.

[0030] In this embodiment, the first main surface 3 and the second main surface 4 are arranged along c-planes of the SiC single crystal. The first main surface 3 is arranged along the (0001) plane (silicon plane). The second main surface 4 is arranged along the (000-1) plane (carbon plane) of the SiC single crystal.

[0031] The first main surface 3 and the second main surface 4 have an off-angle θ that is inclined by an angle of no more than 10° with respect to the c-planes of the SiC single crystal in the [11-20] direction. The normal direction Z is inclined by exactly the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0032] The deviation angle θ cannot be less than 0° and cannot be more than 5.0°. The deviation angle θ can be set in an angular range of not less than 0° and not more than 1.0°, not less than 1.0° and not more than 1.5°, not less than 1.5° and not more than 2.0°, not less than 2.0° and not more than 2.5°, not less than 2.5° and not more than 3.0°, not less than 3.0° and not more than 3.5°, not less than 3.5° and not more than 4.0°, not less than 4.0° and not more than 4.5°, or not less than 4.5° and not more than 5.0°. The deviation angle θ is preferably above 0°. The deviation angle θ can be less than 4.0°.

[0033] The deviation angle θ can be set within an angular range of not less than 3.0° and not more than 4.5°. In this case, the deviation angle θ is preferably set within an angular range of not less than 3.0° and not more than 3.5°, or not less than 3.5° and not more than 4.0°.

[0034] The deviation angle θ can be set within an angular range of not less than 1.5° and not more than 3.0°. In this case, the deviation angle θ is preferably set within an angular range of not less than 1.5° and not more than 2.0°, or not less than 2.0° and not more than 2.5°.

[0035] The first main surface 3 is a device formation surface. The first main surface 3 is a non-mounting surface. The second main surface 4 is a mounting surface. When the semiconductor device 1A is mounted on a bonding object, the SiC semiconductor layer 2 is mounted on the bonding object in an orientation in which the second main surface 4 faces the object. Examples of the bonding object include an electronic component, a lead frame, a printed circuit board, etc.

[0036] The second main surface 4 is constructed from a roughened surface that has been roughened. The second main surface 4 is roughened by irregularly shaped unevennesses. Preferably, an entire area of ​​the second main surface 4 is roughened. More preferably, the second main surface 4 is constructed from a roughened surface that has no grinding marks (in particular, a linear grinding mark). More specifically, the second main surface 4 is a crystal surface constructed from a Si single crystal. The second main surface 4 is thus constructed from a crystalline roughened surface in which the Si single crystal has been roughened.

[0037] An arithmetic mean roughness Ra of the second main surface 4 may be not less than 30 nm. The arithmetic mean roughness Ra of the second main surface 4 may be not less than 30 nm and not more than 1000 nm, not less than 50 nm and not more than 1000 nm, not less than 80 nm and not more than 1000 nm, not less than 100 nm and not more than 1000 nm, not less than 30 nm and not more than 800 nm, not less than 30 nm and not more than 600 nm, not less than 30 nm and not more than 400 nm, or not less than 30 nm and not more than 300 nm. The arithmetic mean roughness Ra of the second main surface 4 is preferably not less than 30 nm and not more than 300 nm.When the arithmetic mean roughness Ra of the second main surface 4 is not less than 30 nm and not more than 300 nm, a low-resistance ohmic contact can be achieved at the second main surface 4 as described below, while at the same time preventing deformation of a semiconductor wafer due to excessive surface roughness.

[0038] The lengths of the side surfaces 5A to 5D can be no less than 0.5 mm and no more than 10 mm, respectively. The surface areas of the side surfaces 5A to 5D are equal to each other in this embodiment. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in plan view, the surface areas of the side surfaces 5A and 5C can be smaller than the surface areas of the side surfaces 5B and 5D, or can exceed the surface areas of the side surfaces 5B and 5D.

[0039] In this embodiment, the side surface 5A and the side surface 5C extend in a first direction X and oppose each other in a second direction Y that intersects the first direction X. In this embodiment, the side surface 5B and the side surface 5D extend in the second direction Y and oppose each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0040] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0041] The side surface 5A and the side surface 5C are formed by the a-planes of the SiC single crystal and are opposite each other in the a-axis direction. The side surface 5A is formed by the (-1-120) plane of the SiC single crystal. The side surface 5C is formed by the (11-20) plane of the SiC single crystal.

[0042] The side surface 5B and the side surface 5D are formed by the m-planes of the SiC single crystal and are opposite each other in the m-axis direction. The side surface 5B is formed by the (-1100) plane of the SiC single crystal. The side surface 5D is formed by the (1-100) plane of the SiC single crystal.

[0043] The side surface 5A and the side surface 5C may form inclined surfaces which, when a normal to the first main surface 3 of the SiC semiconductor layer 2 is taken as a basis, are inclined with respect to the normal in the c-axis direction (

[0001] direction) of the SiC single crystal.

[0044] In this case, the side surface 5A and the side surface 5C may be inclined at an angle according to the deviation angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2 when the normal to the first main surface 3 of the SiC semiconductor layer 2 is 0°. The angle according to the deviation angle θ may be equal to the deviation angle θ or may be an angle greater than 0° and smaller than the deviation angle θ.

[0045] On the other hand, the side surface 5B and the side surface 5D extend as planes along the normal to the first main surface 3 of the SiC semiconductor layer 2. More specifically, the side surface 5B and the side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0046] In this embodiment, the SiC semiconductor layer 2 has a laminate structure including an n + -conductive SiC semiconductor substrate 6 and an n-conductive SiC epitaxial layer 7. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6.

[0047] The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The side surfaces 5A to 5D of the SiC semiconductor layer 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0048] A concentration of n-type impurities of the SiC epitaxial layer 7 is not more than a concentration of n-type impurities of the SiC semiconductor substrate 6. More specifically, the concentration of n-type impurities of the SiC epitaxial layer 7 is lower than the concentration of n-type impurities of the SiC semiconductor substrate 6. The concentration of n-type impurities of the SiC semiconductor substrate 6 may be not less than 1.0×10 ı8 cm -3 and not more than 1.0×10 21 cm -3 The concentration of n-type impurities of the SiC epitaxial layer 7 may not be less than 1.0×10 15 cm -3 and not more than 1.0×10 18 cm -3 be.

[0049] A thickness TS of the SiC semiconductor substrate 6 may be not less than 40 µm and not more than 150 µm. The thickness TS may be not less than 40 µm and not more than 50 µm, not less than 50 µm and not more than 60 µm, not less than 60 µm and not more than 70 µm, not less than 70 µm and not more than 80 µm, not less than 80 µm and not more than 90 µm, not less than 90 µm and not more than 100 µm, not less than 100 µm and not more than 110 µm, not less than 110 µm and not more than 120 µm, not less than 120 µm and not more than 130 µm, not less than 130 µm and not more than 140 µm or not less than 140 µm and not more than 150 µm. The thickness TS is preferably not less than 40 µm and not more than 130 µm. By thinning the SiC semiconductor substrate 6, a reduction in the resistance value can be achieved by shortening a current path.

[0050] A thickness TE of the SiC epitaxial layer 7 may be not less than 1 µm and not more than 50 µm. The thickness TE may be not less than 1 µm and not more than 5 µm, not less than 5 µm and not more than 10 µm, not less than 10 µm and not more than 15 µm, not less than 15 µm and not more than 20 µm, not less than 20 µm and not more than 25 µm, not less than 25 µm and not more than 30 µm, not less than 30 µm and not more than 35 µm, not less than 35 µm and not more than 40 µm, not less than 40 µm and not more than 45 µm or not less than 45 µm and not more than 50 µm. The thickness TE is preferably not less than 5 µm and not more than 15 µm.

[0051] An active region 8 and an outer region 9 are arranged in the SiC semiconductor layer 2. The active region 8 is a region in which the Schottky barrier diode D is formed as an example of an element structure. The outer region 9 is a region outside the active region 8.

[0052] The active region 8 is arranged in a central portion of the SiC semiconductor layer 2 at intervals toward an inner region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view. In plan view, the active region 8 has a quadrilateral shape with four sides parallel to the four side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0053] The outer region 9 is arranged in a region between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the peripheral edges of the active region 8. The outer region 9 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 8 in plan view.

[0054] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure composed of a silicon oxide layer (SiO2 layer) or a silicon nitride layer (SiN layer).

[0055] The main surface insulating layer 10 may have a laminate structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single-layer structure composed of the silicon oxide layer.

[0056] The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are adjacent to the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are composed of cleavage surfaces.

[0057] A thickness of the main surface insulating layer 10 may be not less than 1 µm and not more than 50 µm. The thickness of the main surface insulating layer 10 may be not less than 1 µm and not more than 10 µm, not less than 10 µm and not more than 20 µm, not less than 20 µm and not more than 30 µm, not less than 30 µm and not more than 40 µm, or not less than 40 µm and not more than 50 µm.

[0058] A first main surface electrode 12 is formed on the main surface insulating layer 10. The first main surface electrode 12 is formed in the central portion of the SiC semiconductor layer 2 at intervals toward the inner region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0059] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer.

[0060] The passivation layer 13 may have a laminate structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single-layer structure composed of the silicon nitride layer.

[0061] Side surfaces 14A, 14B, 14C, and 14D of the passivation layer 13 are formed, in plan view, at intervals toward the interior from the side surfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, the passivation layer 13 exposes a peripheral edge portion of the first main surface 3 of the SiC semiconductor layer 2. The passivation layer 13 exposes the main surface insulating layer 10.

[0062] A sub-pad opening 15 is formed in the passivation layer 13, exposing a portion of the first main surface electrode 12 as a pad region. The sub-pad opening 15 is formed in a quadrilateral shape with four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0063] The thickness of the passivation layer 13 may be not less than 1 µm and not more than 50 µm. The thickness of the passivation layer 13 may be not less than 1 µm and not more than 10 µm, not less than 10 µm and not more than 20 µm, not less than 20 µm and not more than 30 µm, not less than 30 µm and not more than 40 µm, or not less than 40 µm and not more than 50 µm.

[0064] A resin layer 16 is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form a single insulating laminate structure. Fig. 4, the resin layer 16 is shown with hatching.

[0065] Resin layer 16 may contain a negative-type or positive-type photosensitive resin. In this embodiment, resin layer 16 contains polybenzoxazole as an example of a positive-type photosensitive resin. Resin layer 16 may instead contain polyimide as an example of a negative-type photosensitive resin.

[0066] Side resin surfaces 17A, 17B, 17C, and 17D of the resin layer 16 are formed, in plan view, at intervals toward the interior from the side surfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, the resin layer 16 exposes the peripheral edge portion of the first main surface 3 of the SiC semiconductor layer 2. The resin layer 16, together with the passivation layer 13, exposes the main surface insulating layer 10. In this embodiment, the side resin surfaces 17A to 17D of the resin layer 16 are formed flush with the side surfaces 14A to 14D of the passivation layer 13.

[0067] The side resin surfaces 17A to 17D of the resin layer 16 are portions that define dicing lines when cutting out the semiconductor devices 1A to 1E from a single SiC semiconductor wafer. In this embodiment, the side surfaces 14A to 14D of the passivation layer 13 are also portions that define the dicing lines.

[0068] By exposing the peripheral edge portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is no longer necessary to physically cut the resin layer 16 and the passivation layer 13. This allows the SiC semiconductor device 1A to be easily cut out of the single SiC semiconductor wafer. Furthermore, the insulation distances from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

[0069] A distance between the side surfaces 5A to 5D and the side resin surfaces 17A to 17D (side surfaces 14A to 14D) may be not less than 1 µm and not more than 25 µm. The distance between the side surfaces 5A to 5D and the side resin surfaces 17A to 17D (side surfaces 14A to 14D) may be not less than 1 µm and not more than 5 µm, not less than 5 µm and not more than 10 µm, not less than 10 µm and not more than 15 µm, not less than 15 µm and not more than 20 µm, or not less than 20 µm and not more than 25 µm. Of course, the side surfaces 14A to 14D of the passivation layer 13 may be formed flush with respect to the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0070] A pad opening 18 is formed in the resin layer 16, exposing the portion of the first main surface electrode 12 as a pad region. The pad opening 18 is formed in a quadrilateral shape with four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view. The pad opening 18 is formed in a quadrilateral shape with four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0071] The pad opening 18 communicates with the sub-pad opening 15. Inner walls of the pad opening 18 are formed flush with the inner walls of the sub-pad opening 15. The inner walls of the pad opening 18 may be positioned toward the sides of the side surfaces 5A to 5D of the SiC semiconductor layer 2 with respect to the inner walls of the sub-pad opening 15. The inner walls of the pad opening 18 may be positioned toward the interior of the SiC semiconductor layer 2 with respect to the inner walls of the sub-pad opening 15. The resin layer 16 may cover the inner walls of the sub-pad opening 15.

[0072] A thickness of the resin layer 16 may be not less than 1 µm and not more than 50 µm. The thickness of the resin layer 16 may be not less than 1 µm and not more than 10 µm, not less than 10 µm and not more than 20 µm, not less than 20 µm and not more than 30 µm, not less than 30 µm and not more than 40 µm, or not less than 40 µm and not more than 50 µm.

[0073] A second main surface electrode 19 is formed on the second main surface 4 of the SiC semiconductor layer 2. The second main surface electrode 19 forms an ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

[0074] With reference to Fig. 6, the second main surface electrode 19 has a laminate structure including a plurality of electrode layers laminated on the second main surface 4. In this embodiment, the second main surface electrode 19 has the laminate structure including a metal layer 191, a first electrode layer 192, and a second electrode layer 193 laminated in this order from the second main surface 4 side.

[0075] The metal layer 191 is directly bonded to the roughened second main surface 4. The metal layer 191 preferably covers an entire area of ​​the second main surface 4. In this embodiment, the metal layer 191 is a base layer of the first electrode layer 192 and the second electrode layer 193 and may be referred to as a "metal base layer."

[0076] From a material perspective, the metal layer 191 in this embodiment may be a silicide layer. The metal layer 191 is a nickel silicide layer (NiSi, NiSi2, etc.), a titanium silicide layer (TiSi, TiSi2, Ti5Si3, etc.), a tungsten silicide layer (WSi2), a molybdenum silicide layer (MoSi2), a tantalum silicide layer (TaSi2), a cobalt silicide layer (CoSi2), or a platinum silicide layer (PtSi2). Among the above, the metal layer 191 is preferably a nickel silicide layer or a titanium silicide layer, and more preferably a nickel silicide layer.

[0077] The first electrode layer 192 is sandwiched between the metal layer 191 and the second electrode layer 193. The first electrode layer 192 preferably covers an entire surface of the metal layer 191. The first electrode layer 192 contains the same type of metal as the metal layer 191. In this embodiment, the first electrode layer 192 is a Ni layer.

[0078] The second electrode layer 193 is the outermost electrode layer of the second main surface electrode 19 and is the layer directly connected to the connection object of the semiconductor device 1A. The second electrode layer 193 may be referred to as the outermost electrode layer. The second electrode layer 193 preferably covers an entire area of ​​the first electrode layer 192. In this embodiment, the second electrode layer 193 is a Au layer.

[0079] With reference to Fig. 5, an n-type diode region 20 is formed in a surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 in the active region 8. In this embodiment, the diode region 20 is formed in a central portion of the first main surface 3 of the SiC semiconductor layer 2. In this embodiment, the diode region 20 is arranged in a quadrilateral shape with four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0080] The concentration of n-type impurities in the diode region 20 may not be lower than the concentration of n-type impurities in the SiC epitaxial layer 7. In this embodiment, the diode region 20 is formed using a portion of the SiC epitaxial layer 7. The concentration of n-type impurities in the diode region 20 is equal to the concentration of n-type impurities in the SiC epitaxial layer 7. The diode region 20 may be formed by introducing an n-type impurity into a surface layer portion of the SiC epitaxial layer 7.

[0081] A p + A conductive protective region 21 is formed in a surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 in the outer region 9. The protective region 21 is formed as a band extending along the diode region 20 in plan view.

[0082] More specifically, the protection region 21 is formed in an endless shape (for example, a square ring shape, a square ring shape with chamfered corners, or a circular ring shape) that surrounds the diode region 20 in plan view. The protection region 21 is thus formed as a guard ring region. In this embodiment, the diode region 20 is defined by the protection region 21. Furthermore, the active region 8 is defined by the protection region 21.

[0083] A p-type impurity in the protection region 21 does not need to be activated. In this case, the protection region 21 is formed as a non-semiconductor region. The p-type impurity in the protection region 21 can be activated. In this case, the protection region 21 is formed as a p-type semiconductor region.

[0084] The above-described main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 22 is formed in the main surface insulating layer 10, exposing the diode region 20. The diode opening 22 exposes, in addition to the diode region 20, an inner peripheral edge of the protection region 21. The diode opening 22 is formed in a quadrilateral shape with four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0085] The above-described first main surface electrode 12 is formed on the main surface insulating layer 10. The first main surface electrode 12 enters the diode opening 22 from above the insulating layer. Within the diode opening 22, the first main surface electrode 12 is electrically connected to the diode region 20. The first main surface electrode 12 is not particularly limited as long as it is a metal that forms a Schottky junction by joining with n-type SiC. For example, titanium (Ti), molybdenum (Mo), palladium (Pd), platinum (Pt), etc. can be used.

[0086] Specifically, the first main surface electrode 12 forms a Schottky junction with the diode region 20. This forms the Schottky barrier diode D, which has the first main surface electrode 12 as the anode and the diode region 20 as the cathode. The passivation layer 13 and the resin layer 16 described above are formed on the main surface insulating layer 10. [Semiconductor Device 1B According to the Second Preferred Embodiment]

[0087] Fig. 7 is a schematic plan view of a semiconductor device 1B according to a second preferred embodiment of the present disclosure. Fig. Figure 8 is a cross-sectional view along the line VIII-VIII of Fig. 7. Hereinafter, structures corresponding to those described in the preferred embodiment described above are designated by the same reference numerals, and their description is omitted.

[0088] In the semiconductor device 1B, a plurality of p + -conductive JBS structures (Junction Barrier Schottky structures) 23 are formed in a surface layer portion of the first main surface 3 of the diode region 20. In this embodiment, the plurality of JBS structures 23 are formed in stripes extending in plan view along the diode region 20. The plurality of JBS structures 23 are formed by a plurality of p + -conductive semiconductor regions arranged individually in the diode region 20. In addition to being arranged in stripes, the plurality of JBS structures 23 may also be arranged in an array or a staggered arrangement in the diode region 20. [Semiconductor Device 1C According to the Third Preferred Embodiment]

[0089] Fig. 9 is a schematic sectional view of a semiconductor device 1C according to a third preferred embodiment of the present disclosure. Hereinafter, structures corresponding to those described in the above-described preferred embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0090] The semiconductor device 1C includes, as an example of an element structure, a MOSFET with a trench-gate structure. Gate trenches 25, which define a plurality of unit cells 24, are formed in a surface layer portion of the first main surface 3 of the SiC epitaxial layer 7. The plurality of gate trenches 25 may be formed in stripes extending along the a-axis direction.

[0091] A bottom portion of each gate trench 25 is positioned in an intermediate portion of the SiC epitaxial layer 7 in the thickness direction. An edge portion where a side surface and the bottom portion of each gate trench 25 intersect is formed in a shape curved toward an outer side of each gate trench 25, and each gate trench 25 is formed in a U-shape in cross-sectional view. When the edge portion of each gate trench 25 is curved, an electric field concentrated at the edge portion can be relaxed.

[0092] A gate electrode 27 is embedded in each gate trench 25, with a gate insulating film 26 interposed therebetween. The gate electrode 27 has a front surface flush with the first main surface 3 of the SiC epitaxial layer 7. The gate insulating film 26 can be constructed, for example, from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an aluminum oxide film, a tantalum oxide film, etc. Furthermore, the gate electrode 27 can be constructed, for example, from polysilicon whose resistance has been kept low by implanting an impurity. In each region between adjacent gate trenches 25, a p-type body region 28 is formed, which forms the unit cell 24.

[0093] With respect to a thickness direction of the SiC epitaxial layer 7, a bottom portion of the body region 28 is positioned between the first main surface 3 of the SiC epitaxial layer 7 and the bottom portion of the gate trench 25. In the lateral direction along the first main surface 3 of the SiC epitaxial layer 7, an end portion of the body region 28 forms a portion of the gate trench 25. That is, the body region 28 faces the gate electrode 27 across the gate insulating film 26.

[0094] In this embodiment, the SiC semiconductor substrate 6 is an n + -conducting drain region 29, and a region between the body region 28 and the drain region 29 is an n - -conductive drift region 30.

[0095] An n-type source region 31 is formed in an inner region of the body region 28. With respect to the thickness direction of the SiC epitaxial layer 7, the source region 31 is formed shallower than the body region 28. In the lateral direction along the first main surface 3 of the SiC epitaxial layer 7, an end portion of the source region 31 forms a portion of the gate trench 25. That is, the source region 31 faces the gate electrode 27 across the gate insulating film 26.

[0096] With respect to the thickness direction of the SiC epitaxial layer 7, a region along the side surface of the gate trench 25 between a lower end of the source region 31 and a lower end of the body region 28 is a p-type channel region 32. A p + -conductive body contact region 33 is formed so that it penetrates the source region 31.

[0097] The body contact region 33 is formed to penetrate the source region 31 and cross a boundary between the source region 31 and the body region 28. The body contact region 33 has a higher impurity concentration than the body region 28.

[0098] An interlayer insulating film 34 is formed on the SiC epitaxial layer 7, covering the gate electrode 27. Contact holes 36 are formed in the interlayer insulating film 34, selectively exposing portions of the source region 31 and the body contact regions 33. A source electrode 35 is formed on the interlayer insulating film 34. The source electrode 35 may include, for example, at least one of a pure Al layer (an Al layer with a purity of not less than 99%), a pure Cu layer (a Cu layer with a purity of not less than 99%), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0099] Within each contact hole 36, the source electrode 35 forms an ohmic contact with the body region 28, a portion of the source region 31, and the body contact region 33. On the other hand, a drain electrode 37 is formed on the second main surface 4 of the SiC semiconductor substrate 6. The drain electrode 37 forms an ohmic contact with the drain electrode 29. The drain electrode 37 is formed of the same material as the second main surface electrode 19 described above. That is, the drain electrode 37 has the laminate structure including the metal layer 191, the first electrode layer 192, and the second electrode layer 193, as shown in Fig. 6 shown. [Semiconductor Device 1D According to the Fourth Preferred Embodiment]

[0100] Fig. 10 is a schematic sectional view of a semiconductor device 1D according to a fourth preferred embodiment of the present disclosure. Hereinafter, structures corresponding to those described in the above-described preferred embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0101] One point in which the semiconductor device 1D differs from the semiconductor device 1C described above is that, instead of the gate electrodes 27, a planar gate structure is formed in which gate electrodes 38 are formed along the first main surface 3. That is, the semiconductor device 1D includes a MOSFET with a planar gate structure as an example of an element structure.

[0102] Body regions 39 are formed at intervals on the SiC epitaxial layer 7, and source regions 40 are formed in inner regions thereof. Each source region 40 is formed at a position spaced apart from a peripheral edge portion of the body region 39. In the semiconductor device 1D, the p-type body regions 39 and the n-type source regions 40 are double-diffused into surface layer portions of the SiC epitaxial layer 7 (drift region 30). A region between a peripheral edge portion of each source region 40 and a peripheral edge portion of each body region 39 is a channel region 41.

[0103] The plurality of gate electrodes 38 facing the channel regions 41 and interposed between gate insulating films 42 are formed on the SiC epitaxial layer 7. The materials of the gate insulating films 42 and the gate electrodes 38 are the same as those of the semiconductor device 1C described above.

[0104] Each gate electrode 38 faces a region extending across the SiC epitaxial layer 7 outside the body regions 39, the body regions 39, and the source regions 40. Furthermore, the gate electrode 38 includes overlap portions projecting from the boundary lines between the source regions 40 and the body regions 39 to the sides of the source region 40. [Semiconductor Device 1E According to the Fifth Preferred Embodiment]

[0105] Fig. 11 is a schematic sectional view of a semiconductor device 1E according to a fifth preferred embodiment of the present disclosure. Hereinafter, structures corresponding to those described in the above-described preferred embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0106] One point in which the semiconductor device 1E differs from the semiconductor device 1C described above is that the semiconductor device 1E includes an IGBT (Insulated Gate Bipolar Transistor) as an example of an element structure by replacing the drain region 29 with a p + -conducting collector region 43. The body region 28, the source region 31, the source electrode 35, and the drain electrode 37 may each be a p-conducting base region 44, an n-conducting emitter region 45, an emitter electrode 46, and a collector electrode 47, respectively. [Method for manufacturing semiconductor devices 1A to 1E]

[0107] Fig. 12 is a perspective view showing a SiC semiconductor wafer 48 used in the manufacture of the semiconductor devices 1A to 1E. Fig. 13A to Fig. 13D are diagrams each showing a portion of a manufacturing process of the semiconductor devices 1A to 1E in the order of the process.

[0108] The SiC semiconductor wafer 48 is a component intended to serve as the base of the SiC semiconductor substrate 6. The SiC semiconductor wafer 48 includes a 4H-SiC single crystal as an example of a SiC single crystal composed of a hexagonal crystal. In this embodiment, the SiC semiconductor wafer 48 has a concentration of n-type impurities that corresponds to the concentration of n-type impurities of the SiC semiconductor substrate 6.

[0109] The SiC semiconductor wafer 48 is formed into a plate or disc-like shape. The SiC semiconductor wafer 48 may also be formed into a disc shape instead. The SiC semiconductor wafer 48 has a first wafer main surface 49 on one side, a second wafer main surface 50 on another side, and a wafer side surface 51 connecting the first wafer main surface 49 and the second wafer main surface 50.

[0110] A thickness TW of the SiC semiconductor wafer 48 exceeds the thickness TS of the SiC semiconductor substrate 6 (see Fig. 3) (TS < TW). The thickness TW of the SiC semiconductor wafer 48 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0111] The thickness TW may be more than 150 µm and not more than 750 µm. The thickness TW may be more than 150 µm and not more than 300 µm, not less than 300 µm and not more than 450 µm, not less than 450 µm and not more than 600 µm, or not less than 600 µm and not more than 750 µm. In view of the grinding time of the SiC semiconductor wafer 48, the thickness TW is preferably more than 150 µm and not more than 500 µm. The thickness TW is usually not less than 300 µm and not more than 450 µm.

[0112] In this embodiment, the first wafer main surface 49 and the second wafer main surface 50 are arranged along c-planes of the SiC single crystal. The first wafer main surface 49 is arranged along the (0001) plane (silicon plane). The second wafer main surface 50 is arranged along the (000-1) plane (carbon plane) of the SiC single crystal.

[0113] The first wafer main surface 49 and the second wafer main surface 50 have a deviation angle θ that is inclined by an angle of no more than 10° with respect to the c-planes of the SiC single crystal in the [11-20] direction. A normal direction Z to the first wafer main surface 49 is inclined by the deviation angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0114] The deviation angle θ cannot be less than 0° and cannot be more than 5.0°. The deviation angle θ can be set within an angular range of not less than 0° and not more than 1.0°, not less than 1.0° and not more than 1.5°, not less than 1.5° and not more than 2.0°, not less than 2.0° and not more than 2.5°, not less than 2.5° and not more than 3.0°, not less than 3.0° and not more than 3.5°, not less than 3.5° and not more than 4.0°, not less than 4.0° and not more than 4.5°, or not less than 4.5° and not more than 5.0°. The deviation angle θ is preferably above 0°. The deviation angle θ can be less than 4.0°.

[0115] The deviation angle θ can be set within an angular range of not less than 3.0° and not more than 4.5°. In this case, the deviation angle θ is preferably set within an angular range of not less than 3.0° and not more than 3.5°, or not less than 3.5° and not more than 4.0°.

[0116] The deviation angle θ can be set within an angular range of not less than 1.5° and not more than 3.0°. In this case, the deviation angle θ is preferably set within an angular range of not less than 1.5° and not more than 2.0°, or not less than 2.0° and not more than 2.5°.

[0117] The SiC semiconductor wafer 48 includes a first wafer corner portion 52 connecting the first wafer main surface 49 and the wafer side surface 51, and a second wafer corner portion 53 connecting the second wafer main surface 50 and the wafer side surface 51. The first wafer corner portion 52 has a first chamfered portion 54 that slopes downward from the first wafer main surface 49 toward the wafer side surface 51. The second wafer corner portion 53 has a second chamfered portion 55 that slopes downward from the second wafer main surface 50 toward the wafer side surface 51.

[0118] The first chamfered portion 54 may be formed as a convex curved shape. The second chamfered portion 55 may be formed as a convex curved shape. The first chamfered portion 54 and the second chamfered portion 55 prevent cracking of the SiC semiconductor wafer 48.

[0119] A single alignment flat 56, as an example of a mark indicating a crystal orientation of the SiC single crystal, is formed in the wafer-side surface 51 of the SiC semiconductor wafer 48. The alignment flat 56 is a notched portion formed in the wafer-side surface 51 of the SiC semiconductor wafer 48. In this embodiment, the alignment flat 56 extends rectilinearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0120] A plurality of (for example, two) alignment flats 56 may be formed in the wafer side surface 51 of the SiC semiconductor wafer 48, indicating the crystal orientation. The plurality of (for example, two) alignment flats 56 may include a first alignment flat and a second alignment flat.

[0121] The first alignment flattening may be a notched portion extending straight along the a-axis direction ([11-20] direction) of the SiC single crystal. The second alignment flattening may be a notched portion extending straight along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0122] A plurality of device formation regions 57, each corresponding to the SiC semiconductor devices 1A to 1E, are arranged in the first wafer main surface 49 of the SiC semiconductor wafer 48. The plurality of device formation regions 57 are arranged in a matrix arrangement at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0123] Each device formation region 57 has four sides 58A, 58B, 58C, and 58D aligned along the crystal orientation of the SiC single crystal. The four sides 58A to 58D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. That is, the four sides 58A to 58D include the two sides 58A and 58C aligned along the m-axis direction ([1-100] direction) and the two sides 58B and 58D aligned along the a-axis direction ([11-20] direction).

[0124] The plurality of device formation regions 57 are each defined by lattice-shaped cut lines 59 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The cut lines 59 include a plurality of first cut lines 60 and a plurality of second cut lines 61.

[0125] The plurality of first provided cutting lines 60 each extend along the m-axis direction ([1-100] direction). The plurality of second provided cutting lines 61 each extend along the a-axis direction ([11-20] direction).

[0126] With reference to Fig. 13A, in the manufacturing process of the semiconductor devices 1A to 1E, predetermined element structures 62 (the Schottky barrier diode D and the respective unit cells 24, etc., of the MOSFET with the trench gate structure, the MOSFET with the planar gate structure, and the IGBT with the trench gate structure, as described above) are formed in the plurality of device formation regions 57.

[0127] Next, with reference to Fig. 13B, the second main wafer surface 50 of the SiC semiconductor wafer 48 is ground. The second main wafer surface 50 of the SiC semiconductor wafer 48 can be ground using a CMP (chemical mechanical polishing) process. The SiC semiconductor wafer 48 is thereby thinned to a desired thickness.

[0128] Next, with reference to Fig. 13C, the second wafer main surface 50 of the SiC semiconductor wafer 48 is roughened. The second wafer main surface 50 is preferably roughened using an etching process. The second wafer main surface 50 may be roughened until it has an arithmetic mean roughness Ra of not less than 30 nm. The second wafer main surface 50 is preferably roughened until the arithmetic mean roughness Ra is not less than 30 nm and not more than 300 nm.

[0129] Next, with reference to Fig. 13D, a back surface electrode 63 is formed at once over an entire area of ​​the roughened second wafer main surface 50. The back surface electrode 63 closes the second main surface electrode 19 (see Fig. 5 and Fig. 8), the drain electrode 37 (see Fig. 9 and Fig. 10) and the collector electrode 47 (see Fig. 11) described above. For the back surface electrode 63, for example, electrode materials of the first electrode layer 192 and the second electrode layer 193 are sequentially laminated by a sputtering method.

[0130] Next, with reference to Fig. 13E, a contact portion of the first electrode layer 192 is annealed by irradiating a boundary surface 64 between the first electrode layer 192 and the second wafer main surface 50 with a laser. As a result, the material of the first electrode layer 192 (Ni in this embodiment) and the Si of the SiC semiconductor wafer 48 react, and the metal layer 191 (see Fig. 6) is formed between the first electrode layer 192 and the SiC semiconductor wafer 48.

[0131] During laser annealing, the laser is continuously irradiated over the entire area of ​​the second wafer main surface 50, so that the areas of an irradiation unit that can be processed by a single laser irradiation shot overlap. The irradiation area of ​​each laser shot differs depending on the pulse energy of each laser shot. For example, the higher the pulse energy, the more necessary it is to focus the energy on a narrow area, and therefore the narrower the irradiation area of ​​each shot.

[0132] The irradiation area of ​​the single shot differs depending on the laser irradiation device, and for example, with reference to Fig. 15, if the pulse energy of the single shot has a first energy of not less than 3.0 J / cm 2is, the irradiation area of ​​the single shot is a small circular shape 65. A size of the circular shape 65 can, for example, be not less than 10 µm in diameter (10 µm ϕ) and not more than 100 µm in diameter (100 µm ϕ). As in Fig. 15, the laser is irradiated in such a way that several circular shapes 65 overlap each other.

[0133] If, on the other hand, with reference to Fig. 14, the pulse energy of the single shot is a second energy that is smaller than the first energy, the irradiation area of ​​the single shot may be a quadrilateral shape 66 having a larger area than the circular shape 65. Regarding a size of the quadrilateral shape 66, the quadrilateral shape 66 may be, for example, a rectangle, and a length L1 of a long side 67 in any second direction Y may, for example, be not less than five times a length L2 of a short side 68 in a first direction X orthogonal to the second direction Y. More specifically, the length L2 of the short side 68 may be not less than 0.1 mm and not greater than 0.4 mm, and the length L1 of the long side 67 may be not less than 1.0 mm and not greater than 4.0 mm. Here, with respect to the first direction X and the second direction Y, mutually orthogonal directions are defined as the first direction X and the second direction Y merely for the sake of simplicity.The first direction X can be called the “transverse direction of the plate surface” or “second direction”, and the second direction Y can be called the “longitudinal direction of the plate surface” or “first direction”.

[0134] The Fig. 14 and Fig. The shapes of the individual laser shots shown in Fig. 15 remain as laser marks (processing marks) on the second wafer main surface 50 after the laser annealing treatment. The laser marks can be checked, for example, by observing the second main surface 4 after removing the back surface electrode 63 (the second main surface electrode 19, the drain electrode 37 or the collector electrode 47, etc.) of any of the semiconductor devices 1A to 1E after completion. In the case of Fig. 14, a plurality of processing units 69 remain, which are formed in a square shape in plan view and overlap each other on the second main surface 4 (second wafer main surface 50). In the case of Fig. 15, a plurality of processing units 70 remain, which are formed circularly in plan view and overlap each other on the second main surface 4 (second wafer main surface 50).

[0135] Fig. 16 is a photographic image showing the first shape (square shape) of laser marks 71 formed on the second main surface 4 (second wafer main surface 50). Fig. Fig. 17 is a photographic image showing the second shape (circular shape) of laser marks 72 formed on the second main surface 4 (second wafer main surface 50). That is, Fig. 16 and Fig. 17 are photographic images showing the laser markings 71 and 72 formed by overlapping the processing units 69 and 70 of Fig. 14 and Fig. 15 were formed.

[0136] With reference to Fig. 16 were treated with laser irradiation with a relatively low pulse energy (for example, not more than 2.0 J / cm 2 ) the plurality of band-shaped laser marks 71 are formed, which are blackish and extend thinly along the second direction Y of the second wafer main surface 50. The plurality of laser marks 71 are regularly arranged along the first direction X. In particular, in Fig. 16 the plurality of band-shaped laser markings 71 are aligned at substantially equal intervals along the first direction X.

[0137] With reference to Fig. 17 were treated with laser irradiation with a relatively high pulse energy (for example, not less than 3.0 J / cm 2 ) the plurality of elliptical laser markings 72 are formed, which are blackish and have a main axis along the second direction Y of the second wafer main surface 50. The plurality of laser markings 72 are regularly arranged along the first direction X. In particular, in Fig. 17 the plurality of elliptical laser markings 72 are aligned at substantially equal intervals along the first direction X.

[0138] Fig. 18 is a photographic illustration showing a modification example of the laser marks 71. Fig. 19 is a photographic illustration showing a modification example of the laser marks 72.

[0139] With reference to Fig. 18, the laser markings 71 may have a band shape that is shorter than that of the Fig. 16. The plurality of laser marks 71 may be selectively formed on the second main surface 4 (second wafer main surface 50), and a band-shaped region extending along the first direction X may be formed. The band-shaped region may be a dark region 74 formed by arranging the plurality of blackish laser marks 71. The dark region 74 is a region having a darker tone than a base region 73 of the second main surface 4 (second wafer main surface 50). In this embodiment, the base regions 73 and the dark regions 74 are alternately arranged along the second direction Y. In addition, an aspect ratio (W / L) of a length (L) in the first direction X and a width (W) in the second direction Y of each dark region 74 may be not more than 0.1.

[0140] With reference to Fig. 19, the laser marks 72 may have the shape of a curved line extending along the second direction Y (in other words, an arc shape extending along the second direction Y). The plurality of laser marks 72 may be selectively formed on the second main surface 4 (second wafer main surface 50), and a band-shaped region may be formed extending along the first direction X. The band-shaped region may be a dark region 76 formed by arranging the plurality of blackish laser marks 72. The dark region 76 is a region having a darker tone than a base region 75 of the second main surface 4 (second wafer main surface 50). In this embodiment, the base regions 75 and the dark regions 76 are alternately arranged along the second direction Y.In addition, an aspect ratio (W / L) of a length (L) in the first direction X and a width (W) in the second direction Y of each dark area 76 may be not more than 0.1.

[0141] In addition, while the processing units 69 of Fig. 14 have a rectangular shape, which in Fig. 20 shown processing units 69 with square shape or those in Fig. 21 can also be adopted as the processing units 69 with a square shape. In addition, while the processing units 70 of Fig. 15 have an elliptical shape, which in Fig. 22 shown processing units 70 with a perfect circular shape can also be adopted as the processing units 70 with a circular shape.

[0142] Subsequently, the plurality of semiconductor devices 1A to 1E are cut out by cutting the SiC semiconductor wafer 48 along the provided cutting lines 59. [Effect by roughening the second main surface 4]

[0143] As described above, in the semiconductor devices 1A to 1E, the second main surface 4 of the SiC semiconductor layer 2 is roughened so that the arithmetic mean roughness Ra is not less than 30 nm. As a result, even with a laser annealing treatment with comparatively low energy, a low-resistance ohmic contact can be formed between the back surface electrode 63 (the second main surface electrode 19, the drain electrode 37, or the collector electrode 47, etc.) and the second main surface 4. This effect can be appreciated, for example, by comparing Sample 1 and Sample 2 with reference to Fig. 23 and Fig. 24 be confirmed.

[0144] Although the arithmetic mean roughness Ra of the second wafer main surface 50 (second main surface 4) was different in Sample 1 and Sample 2, the back surface electrode 63 was formed on the second wafer main surface 50 under the same conditions. In both samples, the energy of a single laser shot during annealing of the back surface electrode 63 was no more than 2.0 J / cm 2 .

[0145] Fig. 23 is a diagram showing a contact resistance distribution of the second wafer main surface 50 of the SiC semiconductor wafer 48 and a state of the second wafer main surface 50 according to Sample 1. Fig. 24 is a diagram showing a contact resistance distribution of the second wafer main surface 50 of the SiC semiconductor wafer 48 and a state of the second wafer main surface 50 according to Sample 2.

[0146] In the SiC semiconductor wafer 48 on the right side of the sheet of Fig. 23, black dots indicate areas with higher contact resistance than the other white areas. The photographic image on the left side of the sheet of Fig. 23 shows the surface state of the second wafer main surface 50. Fig. 23 shows the surface state of the second wafer main surface 50 when the arithmetic mean roughness Ra of the second wafer main surface 50 has the value of 60 µm.

[0147] In the SiC semiconductor wafer 48 on the right side of the sheet of Fig. 24, black dots, cross-hatched areas, and diagonally hatched areas indicate areas with higher contact resistance than the other white areas. The resistance of the cross-hatched areas is particularly high. The photographic image on the left side of the sheet of Fig. 24 shows the surface state of the second wafer main surface 50. Fig. 24 shows the surface state of the second wafer main surface 50 when the arithmetic mean roughness Ra of the second wafer main surface 50 has the value of 15 µm.

[0148] When comparing Fig. 23 and Fig. 24 it was found that even with laser annealing treatment with low energy of not more than 2.0 J / cm 2 A low-resistance ohmic contact can be formed between the back surface electrode 63 and the second main surface 4 in Sample 1, in which roughening is performed to Ra of not less than 30 µm. In view of achieving this low resistance, the increase in the contact area between the second main surface 4 and the back surface electrode 63 by roughening the second main surface 4 is considered as a factor.

[0149] Since the ohmic contact with low resistance is thus achieved by the laser annealing treatment with the low energy of not more than 2.0 J / cm 2 can be obtained, the irradiation area per single laser shot can be made large, as in Fig. 14. For example, the processing units 69 can be realized that are larger than those shown in Fig. 15. Consequently, the laser annealing treatment can be performed efficiently, and thus the manufacturing efficiency of the semiconductor devices 1A to 1E can be improved.

[0150] Since the Ra in Sample 1 is about 60 µm, the SiC semiconductor wafer 48 hardly suffered any deformation, and no handling problems occurred during transfer during formation and after formation of the back surface electrode 63. Although the deformation of the SiC semiconductor wafer 48 can be effectively reduced when the second main surface 4 is Fig. On the other hand, since the second main surface 4 is flattened, it is difficult to obtain a low-resistance ohmic contact unless the laser annealing treatment is performed with high energy. That is, in Sample 1, deformation of the SiC semiconductor wafer 48 can be prevented and the low-resistance ohmic contact at the second main surface 4 can be reduced in a balanced manner.

[0151] Reducing the resistance of the ohmic contact at the second wafer main surface 50 (second main surface 4) as described above is effective for the semiconductor devices 1A to 1E including the comparatively thin SiC semiconductor layer 2 of not less than 50 μm and not more than 350 μm. In the case of a vertical-type device in which a current flows in the thickness direction of the SiC semiconductor layer 2, a series resistance in the thickness direction of the SiC semiconductor layer 2 is small when the thickness TL of the SiC semiconductor layer 2 is thin. Therefore, an influence of the resistance of the ohmic contact at the second wafer main surface 50 (second main surface 4) on the series resistance is large, and reducing the resistance of the ohmic contact at the second wafer main surface 50 (second main surface 4) as above is effective.

[0152] Particularly in a Schottky barrier diode such as semiconductor devices 1A and 1B, the element structure on the first main surface 3 side is simple, and there are few elements that would become a factor in increasing the series resistance. Therefore, the influence of the resistance of the ohmic contact at the second wafer main surface 50 (second main surface 4) on the series resistance is large compared to a MOSFET, etc., where the element structure is complex, and therefore, reducing the resistance of the ohmic contact at the second wafer main surface 50 (second main surface 4) as above is even more effective.

[0153] Although the preferred embodiments of the present disclosure have been described above, the present disclosure may be embodied in still other embodiments.

[0154] For example, in each of the preferred embodiments described above, a structure may be adopted in which the conductivity types of the respective semiconductor portions are reversed. For example, p-type portions may be changed to n-type, and n-type portions may be changed to p-type.

[0155] The above-described preferred embodiments of the present disclosure are exemplary in all aspects and should not be interpreted as limiting, and modifications are intended to be embraced in all aspects.

[0156] The following appendix features can be taken from the descriptions in this description and the drawings. [Appendix 1-1]

[0157] Semiconductor device (1A to 1E), including a SiC chip (2) having a first main surface (3) and a second main surface (4), an element structure (D, 24) formed in the first main surface (3), and an electrode (19, 37, 47) formed on the second main surface (4), electrically connected to the element structure (D, 24) and including a metal layer (191) bonded to the second main surface (4), and wherein an arithmetic mean roughness (Ra) of the second main surface (4) is not less than 30 nm and in the second main surface (4) laser markings are formed which are formed by mutual overlapping of a plurality of processing units (69, 70), each of which has a square shape or a circular shape in plan view.

[0158] Since, in this arrangement, the arithmetic mean roughness (Ra) of the second main surface (4) of the SiC chip (2) is not less than 30 nm, a contact area between the SiC chip (2) and the electrode (19, 37, 47) can be made large. Consequently, the semiconductor device (1A to 1E) can be provided, with which it is possible to form a low-resistance ohmic contact on the second main surface (4) on the side opposite the element structure (D, 24). [Appendix 1-2]

[0159] Semiconductor device (1A to 1E) according to Annex 1-1, wherein a thickness (TL) of the SiC chip (2) is not less than 50 µm and not more than 350 µm. [Appendix 1-3]

[0160] Semiconductor device (1A to 1E) according to Annex 1-2, wherein the thickness (TL) of the SiC chip (2) is not less than 100 µm and not more than 350 µm. [Appendix 1-4]

[0161] A semiconductor device (1A to 1E) according to any one of Appendix 1-1 to Appendix 1-3, wherein the Ra of the second main surface (4) is not more than 100 nm. [Appendix 1-5]

[0162] A semiconductor device (1A to 1E) according to any one of Appendix 1-1 to Appendix 1-4, wherein each of the processing units (69, 70) is formed in a rectangular shape in plan view including a short side (68) and a long side (67), and a length (L1) of the long side (67) is not less than five times a length (L2) of the short side (68). [Appendix 1-6]

[0163] A semiconductor device (1A to 1E) according to Appendix 1-5, wherein the length (L2) of the short side (68) of each of the processing units (69, 70) is not less than 0.1 mm and not more than 0.4 mm and the length (L1) of the long side (67) of each of the processing units (69, 70) is not less than 1.0 mm and not more than 4.0 mm. [Appendix 1-7]

[0164] A semiconductor device (1A to 1E) according to any one of Appendix 1-1 to Appendix 1-6, wherein the metal layer (191) is a silicide layer (191). [Appendix 1-8]

[0165] A semiconductor device (1A to 1E) according to Annex 17, wherein the silicide layer (191) is a nickel silicide layer (191) and the electrode (19, 37, 47) is formed of a metal including Ni. [Appendix 1-9]

[0166] A semiconductor device (1A to 1E) according to any one of Appendix 1-1 to Appendix 1-8, wherein the first main surface (3) is a silicon plane and the second main surface (4) is a carbon plane. [Appendix 1-10]

[0167] A semiconductor device (1A, 1B) according to any one of Appendix 1-1 to Appendix 1-9, wherein the element structure (D) includes a Schottky barrier diode (D) formed in the first main surface (3) and having a Schottky metal (19 / 12) forming a Schottky junction with the first main surface (3). [Appendix 1-11]

[0168] The semiconductor device (1B) according to Annex 110, wherein the SiC chip (2) includes a first semiconductor region (7) of a first conductivity type formed in a surface layer portion of the first main surface (3), and a JBS (Junction Barrier Schottky) structure (23) formed by a plurality of semiconductor regions of a second conductivity type selectively formed in a Schottky junction formation region (20) in the first main surface (3). [Appendix 1-12]

[0169] A semiconductor device (1C, 1E) according to any one of Appendix 1-1 to Appendix 1-9, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a gate trench (25) formed in the first main surface (3), a gate electrode (27) embedded in the gate trench (25) with a gate insulating film (26) interposed therebetween, and a second semiconductor region (31, 45) of the first conductivity type and a third semiconductor region (28, 44) of a second conductivity type formed sequentially from the first main surface (3) in the depth direction of the gate trench (25). [Appendix 1-13]

[0170] A semiconductor device (1C) according to Appendix 1-12, wherein the SiC chip (2) includes a drain region (29) of the first conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is a source region (31). [Appendix 1-14]

[0171] A semiconductor device (1E) according to Appendix 1-12, wherein the SiC chip (2) includes a collector region (43) of the second conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is an emitter region (45). [Appendix 1-15]

[0172] A semiconductor device (1D) according to any one of Appendix 1-1 to Appendix 1-9, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a body region (39) of a second conductivity type and a source region (40) of the first conductivity type inside the body region (39), which are double-diffused into a surface layer portion of the first semiconductor region (7, 30), and a gate electrode (38) formed on the first main surface (3) with a gate insulating film (42) interposed therebetween and facing a channel region (41) between an outer edge of the body region (39) and an outer edge of the source region (40). [Appendix 2-1]

[0173] Semiconductor device (1A to 1E), including a SiC chip (2) having a first main surface (3) and a second main surface (4), an element structure (D, 24) formed in the first main surface (3), and an electrode (19, 37, 47) formed on the second main surface (4), electrically connected to the element structure (D, 24) and including a metal layer (191) bonded to the second main surface (4), and wherein an arithmetic mean roughness (Ra) of the second main surface (4) is not less than 30 nm and a processing region (74, 76) extending in a band shape in a first direction (X) is formed in the second main surface (4), and which is formed by a plurality of laser marks (71, 72) having a predetermined shape which are regularly arranged along the first direction X. [Appendix 2-2]

[0174] A semiconductor device (1A to 1E) according to Appendix 2-1, wherein the predetermined shape of the laser marks (71, 72) includes a line shape extending along a second direction (Y) orthogonal to the first direction (X). [Appendix 2-3]

[0175] A semiconductor device (1A to 1E) according to Appendix 2-2, wherein the line shape is a straight shape or a curved shape extending along the second direction (Y). [Appendix 2-4]

[0176] A semiconductor device (1A to 1E) according to any one of Appendix 2-1 to Appendix 2-3, wherein a thickness (TL) of the SiC chip (2) is not less than 50 µm and not more than 350 µm. [Appendix 2-5]

[0177] Semiconductor device (1A to 1E) according to Annex 2-4, wherein the thickness (TL) of the SiC chip (2) is not less than 100 µm and not more than 350 µm. [Appendix 2-6]

[0178] A semiconductor device (1A to 1E) according to any one of Appendix 2-1 to Appendix 2-5, wherein the Ra of the second main surface (4) is not more than 100 nm. [Appendix 2-7]

[0179] A semiconductor device (1A to 1E) according to any one of Appendix 2-1 to Appendix 2-6, wherein the metal layer (191) is a silicide layer (191). [Appendix 2-8]

[0180] A semiconductor device (1A to 1E) according to Annex 2-7, wherein the silicide layer (191) is a nickel silicide layer (191) and the electrode (19, 37, 47) is formed of a metal including Ni. [Appendix 2-9]

[0181] A semiconductor device (1A to 1E) according to any one of Appendix 2-1 to Appendix 2-8, wherein the first main surface (3) is a silicon plane and the second main surface (4) is a carbon plane. [Appendix 2-10]

[0182] A semiconductor device (1A, 1B) according to any one of Appendix 2-1 to Appendix 2-9, wherein the element structure (D) includes a Schottky barrier diode (D) formed in the first main surface (3) and having a Schottky metal (19 / 12) forming a Schottky junction with the first main surface (3). [Appendix 2-11]

[0183] The semiconductor device (1B) according to Appendix 2-10, wherein the SiC chip (2) includes a first semiconductor region (7) of a first conductivity type formed in a surface layer portion of the first main surface (3), and a JBS (Junction Barrier Schottky) structure (23) formed by a plurality of semiconductor regions of a second conductivity type selectively formed in a Schottky junction formation region (20) in the first main surface (3). [Appendix 2-12]

[0184] A semiconductor device (1C, 1E) according to any one of Appendix 2-1 to Appendix 2-9, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a gate trench (25) formed in the first main surface (3), a gate electrode (27) embedded in the gate trench (25) with a gate insulating film (26) interposed therebetween, and a second semiconductor region (31, 45) of the first conductivity type and a third semiconductor region (28, 44) of a second conductivity type formed sequentially from the first main surface (3) in the depth direction of the gate trench (25). [Appendix 2-13]

[0185] The semiconductor device (1C) according to Appendix 2-12, wherein the SiC chip (2) includes a drain region (29) of the first conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is a source region (31). [Appendix 2-14]

[0186] A semiconductor device (1E) according to Appendix 2-12, wherein the SiC chip (2) includes a collector region (43) of the second conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is an emitter region (45). [Appendix 2-15]

[0187] A semiconductor device (1D) according to any one of Appendix 2-1 to Appendix 2-9, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a body region (39) of a second conductivity type and a source region (40) of the first conductivity type inside the body region (39), which are double-diffused into a surface layer portion of the first semiconductor region (7, 30), and a gate electrode (38) formed on the first main surface (3) with a gate insulating film (42) interposed therebetween and facing a channel region (41) between an outer edge of the body region (39) and an outer edge of the source region (40). [Appendix 3-1]

[0188] Semiconductor device (1A to 1E), including a SiC chip (2) having a first main surface (3) and a second main surface (4), an element structure (D, 24) formed in the first main surface (3), and an electrode (19, 37, 47) formed on the second main surface (4), electrically connected to the element structure (D, 24) and including a metal layer (191) bonded to the second main surface (4), and wherein an arithmetic mean roughness (Ra) of the second main surface (4) is not less than 30 nm, the second main surface (4) has a base area (73, 75) with a first color and dark areas (74, 76) with a second color which has a darker shade than the first color, the dark regions (74, 76) are selectively formed by laser markings (71, 72) in the base region (73, 75), each extending in a band-like manner along a first direction (X) and being arranged at intervals along a second direction (Y) orthogonal to the first direction (X). [Appendix 3-2]

[0189] A semiconductor device (1A to 1E) according to Appendix 3-1, wherein an aspect ratio (W / L) of a length (L) in the first direction (X) and a width (W) in the second direction (Y) of the dark regions (74, 76) is not more than 0.1. [Appendix 3-3]

[0190] Semiconductor device (1A to 1E) according to Annex 3-1 or Annex 3-2, wherein a thickness (TL) of the SiC chip (2) is not less than 50 µm and not more than 350 µm. [Appendix 3-4]

[0191] Semiconductor device (1A to 1E) according to Annex 3-3, wherein the thickness (TL) of the SiC chip (2) is not less than 100 µm and not more than 350 µm. [Appendix 3-5]

[0192] A semiconductor device (1A to 1E) according to any one of Appendix 3-1 to Appendix 3-4, wherein the Ra of the second main surface (4) is not more than 100 nm. [Appendix 3-6]

[0193] A semiconductor device (1A to 1E) according to any one of Appendix 3-1 to Appendix 3-5, wherein the metal layer (191) is a silicide layer (191). [Appendix 3-7]

[0194] A semiconductor device (1A to 1E) according to Annex 3-6, wherein the silicide layer (191) is a nickel silicide layer (191) and the electrode (19, 37, 47) is formed of a metal including Ni. [Appendix 3-8]

[0195] A semiconductor device (1A to 1E) according to any one of Appendix 3-1 to Appendix 3-7, wherein the first main surface (3) is a silicon plane and the second main surface (4) is a carbon plane. [Appendix 3-9]

[0196] A semiconductor device (1A, 1B) according to any one of Appendix 3-1 to Appendix 3-8, wherein the element structure (D) includes a Schottky barrier diode (D) formed in the first main surface (3) and having a Schottky metal (19) forming a Schottky junction with the first main surface (3). [Appendix 3-10]

[0197] The semiconductor device (1B) according to Appendix 3-9, wherein the SiC chip (2) includes a first semiconductor region (7) of a first conductivity type formed in a surface layer portion of the first main surface (3), and a JBS (Junction Barrier Schottky Structure) (23) formed by a plurality of semiconductor regions of a second conductivity type selectively formed in a Schottky junction formation region (20) in the first main surface (3). [Appendix 3-11]

[0198] A semiconductor device (1C, 1E) according to any one of Appendix 3-1 to Appendix 3-8, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a gate trench (25) formed in the first main surface (3), a gate electrode (27) embedded in the gate trench (25) with a gate insulating film (26) interposed therebetween, and a second semiconductor region (31, 45) of the first conductivity type and a third semiconductor region (28, 44) of a second conductivity type formed sequentially from the first main surface (3) in the depth direction of the gate trench (25). [Appendix 3-12]

[0199] The semiconductor device (1C) according to Appendix 3-11, wherein the SiC chip (2) includes a drain region (29) of the first conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is a source region (31). [Appendix 3-13]

[0200] A semiconductor device (1E) according to Appendix 3-11, wherein the SiC chip (2) includes a collector region (43) of the second conductivity type formed in a surface layer portion of the second main surface (4), and the second semiconductor region is an emitter region (45). [Appendix 3-14]

[0201] A semiconductor device (1D) according to any one of Appendix 3-1 to Appendix 3-8, wherein the SiC chip (2) includes a first semiconductor region (7, 30) of a first conductivity type formed in a surface layer portion of the first main surface (3), and the element structure (24) includes a body region (39) of a second conductivity type and a source region (40) of the first conductivity type inside the body region (39), which are double-diffused into a surface layer portion of the first semiconductor region (7, 30), and a gate electrode (38) formed on the first main surface (3) with a gate insulating film (42) interposed therebetween and facing a channel region (41) between an outer edge of the body region (39) and an outer edge of the source region (40). List of reference symbols 1A semiconductor device 1B Semiconductor device 1C semiconductor device 1D: Semiconductor device 1E semiconductor device 2 SiC semiconductor layer 3 First main interface 4 Second main interface 5A side surface 5B side surface 5C side surface 5D side surface 6 SiC semiconductor substrate 7 SiC epitaxial layer 8 Active area 9 Outdoor area 10 Main surface insulation layer 11A Insulating side surface 11B Insulating side surface 11C Insulating side surface 11D Insulating side surface 12 First main surface electrode 13 Passivation layer 14A side surface 14B side surface 14C side surface 14D side surface 15 Sub-pad opening 16 resin layer 17A Side resin surface 17B Lateral resin surface 17C Side resin surface 17D Side Resin Surface 18 Pad opening 19 Second main surface electrode 20 diode range 21 Protection area 22 Diode opening 23 JBS structure 24 unit cells 25 Gate Trench 26 Gate insulating film 27 Gate electrode 28 Body area 29 Drain area 30 Drift area 31 Source area 32 channel area 33 Body contact area 34 Interlayer insulating film 35 Source electrode 36 contact holes 37 Drain electrode 38 Gate electrode 39 Body area 40 Source area 41 Canal area 42 Gate insulating film 43 Collector area 44 Basic area 45 Emitter area 46 Emitter electrode 47 Collector electrode 48 SiC semiconductor wafers 49 First main wafer surface 50 Second main wafer surface 51 wafer side surface 52 First wafer corner section 53 Second wafer corner section 54 First bevelled section 55 Second bevelled section 56 Alignment flattening 57 Device formation area 58A Page 58B Page 58C Page 58D Page 59 Intended cutting line 60 First intended cutting line 61 Second intended cutting line 62 Element structure 63 Back surface electrode 64 Boundary surface 65 circular shape 66 Square shape 67 Long side 68 Short side 69 processing unit 70 processing unit 71 Laser marking 72 Laser marking 73 Basic area 74 Dark Area 75 base range 76 Dark Area 191 Silicide layer 192 First electrode layer 193 Second electrode layer QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-004565

[0001] JP 2024-001479

[0001] JP 2022-166265

[0004]

Claims

[1] A semiconductor device comprising: a SiC chip having a first main surface and a second main surface; an element structure formed in the first main surface; and an electrode formed on the second main surface, electrically connected to the element structure, and including a metal layer bonded to the second main surface; and wherein an arithmetic mean roughness (Ra) of the second main surface is not less than 30 nm and in the second main surface, laser markings are formed by mutually overlapping a plurality of processing units each having a square shape or a circular shape in plan view. [2] The semiconductor device according to claim 1, wherein a thickness of the SiC chip is not less than 50 µm and not more than 350 µm. [3] A semiconductor device according to claim 2, wherein the thickness of the SiC chip is not less than 100 µm and not more than 350 µm. [4] A semiconductor device according to any one of claims 1 to 3, wherein the arithmetic mean roughness (Ra) of the second main surface is not more than 100 nm or not more than 1000 nm. [5] The semiconductor device according to any one of claims 1 to 4, wherein each of the processing units is formed in a rectangular shape including a short side and a long side in plan view, and a length of the long side is not less than five times a length of the short side. [6] The semiconductor device according to claim 5, wherein the length of the short side of each of the processing units is not less than 0.1 mm and not more than 0.4 mm, and the length of the long side of each of the processing units is not less than 1.0 mm and not more than 4.0 mm. [7] A semiconductor device according to any one of claims 1 to 6, wherein the metal layer is a silicide layer. [8] A semiconductor device according to claim 7, wherein the silicide layer is a nickel silicide layer and the electrode is formed of a metal including Ni. [9] A semiconductor device according to any one of claims 1 to 8, wherein the first main surface is a silicon plane and the second main surface is a carbon plane. [10] A semiconductor device according to any one of claims 1 to 9, wherein the element structure includes a Schottky barrier diode formed in the first main surface and having a Schottky metal forming a Schottky junction with the first main surface. [11] The semiconductor device according to claim 10, wherein the SiC chip includes a first semiconductor region of a first conductivity type formed in a surface layer portion of the first main surface, and a JBS (Junction Barrier Schottky) structure formed by a plurality of semiconductor regions of a second conductivity type selectively formed in a Schottky junction formation region in the first main surface. [12] The semiconductor device according to any one of claims 1 to 9, wherein the SiC chip includes a first semiconductor region of a first conductivity type formed in a surface layer portion of the first main surface, and the element structure includes a gate trench formed in the first main surface, a gate electrode embedded in the gate trench with a gate insulating film interposed therebetween, and a second semiconductor region of the first conductivity type and a third semiconductor region of a second conductivity type sequentially formed from the first main surface in a depth direction of the gate trench. [13] The semiconductor device according to claim 12, wherein the SiC chip includes a drain region of the first conductivity type formed in a surface layer portion of the second main surface, and the second semiconductor region is a source region. [14] The semiconductor device according to claim 12, wherein the SiC chip includes a collector region of the second conductivity type formed in a surface layer portion of the second main surface, and the second semiconductor region is an emitter region. [15] The semiconductor device according to any one of claims 1 to 9, wherein the SiC chip includes a first semiconductor region of a first conductivity type formed in a surface layer portion of the first main surface, and the element structure includes a body region of a second conductivity type and a source region of the first conductivity type in an interior of the body region, which are double-diffused into a surface layer portion of the first semiconductor region, and a gate electrode formed on the first main surface with a gate insulating film interposed therebetween and facing a channel region between an outer edge of the body region and an outer edge of the source region.

Images