DISPLAY PANEL AND DISPLAY DEVICE

Abstract

A display panel comprising: a substrate (10), several subpixels (PX), and several data lines (DL) located in a display area (AA), and a multiplex circuit (30) located in a first frame area (B1). The several data lines (DL) connect to several subpixels (PX). The multiple multiplex circuit (30) comprises several multiplex units (31, 32, 33). At least one multiplex unit (31, 32, 33) comprises several multiplex transistors. The multiplex transistors of the multiple multiplex units (31, 32, 33) are arranged in several rows and columns. A row of multiplex transistors comprises several multiplex transistors arranged along a first direction (X), and a column of multiplex transistors comprises several multiplex transistors arranged along a second direction (Y), with the first direction (X) intersecting the second direction (Y).

Description

[0001] The present application claims priority over Chinese patent application No. 202310612612.5, filed with the Patent Office of the People's Republic of China on May 26, 2023, entitled "Display panel and display device", the contents of which are to be understood as being incorporated into this application by reference. TECHNICAL AREA

[0002] The present application relates to, but is not limited to, the field of display technology, in particular a display panel and a display device. STATE OF THE ART

[0003] Organic light-emitting diodes (OLEDs) are active light-emitting display devices that offer advantages such as self-illumination, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous development of display technology, display devices that use OLEDs as light-emitting elements and are controlled by thin-film transistors (TFTs) have become mainstream products in the current display sector. SUMMARY OF THE INVENTION

[0004] The following is an overview of the items described in detail here. This overview is not intended to limit the scope of protection afforded to the claims.

[0005] One embodiment of the present disclosure provides a display panel and a display device.

[0006] In one aspect, this embodiment represents a display panel comprising: a substrate, multiple subpixels, multiple data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. The multiple subpixels and the multiple data lines are located within the display area, with the multiple data lines connected to the multiple subpixels and configured to provide data signals to the multiple subpixels. The multiplexing circuit is located within the first frame area and comprises multiple multiplexing units. At least one of the multiple multiplexing units comprises multiple multiplexing transistors.The at least one multiplexing unit is electrically connected to a multiplexing data line, several multiplexing control lines, and several data lines, and is configured to provide the data signals transmitted by the multiplexing data line to the several data lines under the control of the multiplexing control lines. The multiplexing transistors of the multiple multiplexing units are arranged in multiple rows and columns. A row of multiplexing transistors comprises several multiplexing transistors arranged along a first direction, and a column of multiplexing transistors comprises several multiplexing transistors arranged along a second direction, with the first direction intersecting the second direction.

[0007] In some exemplary embodiments, a column of multiplex transistors comprises several multiplex transistors connected to the same multiplex control line.

[0008] In some exemplary embodiments, a column of multiplex transistors comprises several multiplex transistors connected to the same multiplex data line.

[0009] In some exemplary embodiments, the multiplex transistors of the multiplex units are arranged in three rows.

[0010] In some exemplary embodiments, the at least one multiplexing unit comprises two multiplexing transistors that are electrically connected to different multiplexing control lines and electrically connected to the same multiplexing data line; and wherein the two multiplexing transistors of the at least one multiplexing unit are arranged in the same row.

[0011] In some exemplary embodiments, the multiple multiplex units comprise at least: multiple first multiplex units, multiple second multiplex units, and multiple third multiplex units; wherein the multiplex transistors of the multiple first multiplex units are arranged in a first row, the multiplex transistors of the multiple second multiplex units are arranged in a second row, and the multiplex transistors of the multiple third multiplex units are arranged in a third row. The multiplex transistors of the first multiplex units, the second multiplex units, and the third multiplex units, which are electrically connected to the same multiplex control line, are arranged in the same column.

[0012] In some exemplary embodiments, the multiple subpixels comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color. The first multiplex units are configured to provide data signals to multiple first subpixels, the second multiplex units are configured to provide data signals to multiple second subpixels, and the third multiplex units are configured to provide data signals to multiple third subpixels.

[0013] In some exemplary embodiments, the at least one multiplexing unit comprises three multiplexing transistors that are electrically connected to different multiplexing control lines and electrically connected to the same multiplexing data line; wherein the three multiplexing transistors of the at least one multiplexing unit are arranged in the same column.

[0014] In some exemplary embodiments, the multiple subpixels comprise: first subpixels that emit light of a first color, second subpixels that emit light of a second color, and third subpixels that emit light of a third color. The three multiplex transistors of the at least one multiplexing unit are configured to provide data signals to the first subpixels, the second subpixels, and the third subpixels, respectively.

[0015] In some exemplary embodiments, the three multiplex transistors of the at least one multiplex unit are a seventh multiplex transistor, an eighth multiplex transistor, and a ninth multiplex transistor. The seventh, eighth, and ninth multiplex transistors, which are located in the same column, are arranged offset from each other in the second direction.

[0016] In some exemplary embodiments, several of the seventh multiplex transistors are arranged in a first row, several of the eighth multiplex transistors are arranged in a second row, and several of the ninth multiplex transistors are arranged in a third row, the first row, the second row, and the third row being arranged sequentially in a direction leading away from the display area.

[0017] In some exemplary embodiments, the multiplex transistors of the multiplex units are arranged in two rows.

[0018] In some exemplary embodiments, the at least one multiplexing unit comprises two multiplexing transistors, wherein the two multiplexing transistors are each electrically connected to a first multiplexing control line and a second multiplexing control line and are electrically connected to the same multiplexing data line; wherein the two multiplexing transistors of the at least one multiplexing unit are arranged in different rows and columns.

[0019] In some exemplary embodiments, the multiplex transistors in the i-th column are all electrically connected to the first multiplex control line, the multiplex transistors in the i+1-th column are electrically connected to different multiplex control lines, and the multiplex transistors in the i+2-th column are all electrically connected to the second multiplex control line, where i is an integer greater than 0.

[0020] In some exemplary embodiments, the multiple multiplex units comprise at least: multiple first multiplex units, multiple second multiplex units, and multiple third multiplex units. The multiple subpixels comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color. The first multiplex units are configured to provide data signals to multiple first subpixels, the second multiplex units are configured to provide data signals to multiple second subpixels, and the third multiplex units are configured to provide data signals to multiple third subpixels.The two multiplex transistors of the first multiplex unit are located in the i-th column and the i+1-th column, respectively; the two multiplex transistors of the second multiplex unit are located in the i-th column and the i+2-th column, respectively; and the two multiplex transistors of the third multiplex unit are located in the i+1-th column and the i+2-th column, respectively.

[0021] In some exemplary embodiments, the first frame area comprises at least: a first fan-out area and a bending area arranged sequentially along the direction leading away from the display area; wherein the multiplexing circuitry is located in the first fan-out area; wherein the first fan-out area comprises: several data output lines and several multiplexed data lines; the bending area comprises at least: several data bending connection lines. The multiplexing circuitry is electrically connected via the several data output lines to the several data lines in the display area and electrically connected to the multiplexed data lines, and the multiplexed data lines are electrically connected to the data bending connection lines.

[0022] In some exemplary embodiments, the first frame area comprises at least: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer arranged on the substrate. The multiplex data lines are arranged alternately in the first conductive layer and the second conductive layer. The data leak lines are arranged alternately in the first conductive layer and the second conductive layer.

[0023] In some exemplary embodiments, the first frame area further comprises: a fourth conductive layer located on the side of the third conductive layer facing away from the substrate; wherein the multiple data bend connection lines are located in the fourth conductive layer.

[0024] In another aspect, this embodiment provides a display device that includes the display panel described above.

[0025] In another aspect, this embodiment provides a display panel comprising: a substrate, multiple subpixels, multiple data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. The multiple subpixels and the multiple data lines are located in the display area, with the multiple data lines connected to the multiple subpixels and configured to provide data signals to the multiple subpixels. The multiplexing circuit is located in the first frame area and comprises multiple multiplexing units. At least one of the multiple multiplexing units comprises multiple multiplexing transistors.The at least one multiplexing unit is electrically connected to a multiplexing data line, multiplexing control lines, and several data lines, and is configured to provide the data signals transmitted by the multiplexing data line to the multiple data lines under the control of the multiplexing control lines, where a is an integer greater than 1 and less than or equal to 3. The multiple multiplexing transistors of the at least one multiplexing unit are located in the same row or column, or in different rows. A row of multiplexing transistors comprises multiple multiplexing transistors arranged along a first direction, and a column of multiplexing transistors comprises multiple multiplexing transistors arranged along a second direction, the first direction intersecting the second direction.

[0026] In some exemplary embodiments, a column of multiplex transistors comprises: several multiplex transistors connected to the same multiplex control line; or several multiplex transistors connected to the same multiplex data line.

[0027] Further aspects become clear when reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings serve to enhance understanding of the technical solutions of this disclosure and form part of the description. Together with the embodiments of this disclosure, they serve to illustrate the technical solutions of this disclosure and do not limit them. The shapes and sizes of one or more components in the drawings are not to scale and serve only as a schematic illustration of the content of this disclosure. Fig. Figure 1 shows a schematic representation of a display panel according to at least one embodiment of the present disclosure; Fig. Figure 2 shows a schematic top view of the structure of a display panel according to at least one embodiment of the present disclosure; Fig. Figure 3 shows a schematic partial sectional view of a display area of ​​a display panel according to at least one embodiment of the present disclosure; Fig. Figure 4 shows an equivalent circuit diagram of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. Figure 5 shows a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. Figure 6 shows a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 5; Fig. Figure 7A shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 5; Fig. Figure 7B shows a schematic top view of the first conductive layer in Fig. 7A; Fig. Figure 8A shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 5; Fig. Figure 8B shows a schematic top view of the second conductive layer in Fig. 8A; Fig. Figure 9 shows a schematic representation of the display panel after the formation of a third insulating layer in Fig. 5; Fig. Figure 10 shows a schematic top view of the third conductive layer in Fig. 5; Fig. Figure 11 shows a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. Figure 12 shows a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 11; Fig. Figure 13 shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 11; Fig. Figure 14 shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 11; Fig. Figure 15 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 11; Fig. Figure 16A shows a schematic representation of the display panel after the formation of the third conductive layer in Fig. 11; Fig. Figure 16B shows a schematic top view of the third conductive layer in Fig. 16A; Fig. Figure 17 shows a schematic representation of the display panel after the formation of the fifth insulating layer in Fig. 11; Fig. Figure 18 shows a further schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. Figure 19 shows a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 18; Fig. Figure 20A shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 18; Fig. Figure 20B shows a schematic top view of the first conductive layer in Fig. 20A; Fig. Figure 21A shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 18; Fig. Figure 21B shows a schematic top view of the second conductive layer in Fig. 21A; Fig. Figure 22 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 18; Fig. Figure 23A shows a schematic representation of the display panel after the formation of the third conductive layer in Fig. 18; Fig. Figure 23B shows a schematic top view of the third conductive layer in Fig. 23A; Fig. Figure 24 is a schematic representation of the display panel after the formation of the fifth insulating layer in Fig. 18; Fig. 25 is another equivalent circuit diagram of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. 26 is a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure; Fig. Figure 27 is a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 26; Fig. Figure 28A is a schematic representation of the display panel after the formation of the first conductive layer in Fig. 26; Fig. Figure 28B is a schematic top view of the first conductive layer in Fig. 28A; Fig. Figure 29A is a schematic representation of the display panel after the formation of the second conductive layer in Fig. 26; Fig. Figure 29B is a schematic top view of the second conductive layer in Fig. 29A; Fig. Figure 30 is a schematic representation of the display panel after the formation of the third insulating layer in Fig. 26; Fig. Figure 31 shows a schematic top view of the third conductive layer in Fig. 26; Fig. Figure 32 shows a schematic representation of a display device according to at least one embodiment of the present disclosure. EXAMPLES OF THE INVENTION

[0029] The embodiments of this disclosure are described in detail below in conjunction with the accompanying drawings. These embodiments can be implemented in various forms. Those skilled in the art in the relevant technical field can readily understand that the manner and content can be modified in various ways without deviating from the principle and scope of this disclosure. Therefore, this disclosure is not to be interpreted as being limited exclusively to the content recorded in the following embodiments. The embodiments and features in the embodiments of this disclosure can be combined arbitrarily, provided no conflicts arise.

[0030] For clarity, the drawings sometimes exaggerate the size of one or more components, the thickness of layers, or areas. Therefore, an embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings are not to scale. Furthermore, the drawings schematically depict idealized examples. An embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0031] The ordinal numbers such as "first," "second," "third," etc., in this description are provided to avoid confusion regarding the components and are not intended to limit their number. "Several" in this revelation means a quantity of two or more.

[0032] For the sake of simplicity, this description uses words and phrases indicating orientation or positional relationships, such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," etc., to illustrate the positional relationships of the components with reference to the accompanying drawings. This is solely to facilitate and simplify the description and is not intended to indicate or suggest that the device or element in question must have a particular orientation or be designed and operated in a particular orientation. Therefore, this should not be interpreted as a limitation of the present description.The positional relationships of the components change appropriately depending on the direction of description of the respective components, are therefore not limited to the words and sentences explained in the description and can be appropriately exchanged depending on the circumstances.

[0033] Unless otherwise expressly stated and defined, the terms "install," "connected," and "connect" in this description are to be understood in a broad sense. For example, it may be a permanent connection, a detachable connection, or an integral connection; it may be a mechanical connection or a joint; it may be a direct connection, an indirect connection via an intermediate element, or a connection within two elements. Those skilled in the art in this field may understand the meaning of the above terms in this disclosure according to the circumstances.

[0034] In this description, a transistor refers to a device that has at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this description, the channel region refers to the area through which the current primarily flows.

[0035] In this description, a first electrode can be a drain electrode, a second electrode can be a source electrode, or a first electrode can be a source electrode and a second electrode can be a drain electrode. The functions of "source electrode" and "drain electrode" can sometimes be reversed if transistors with opposite polarity are used or if the current direction changes during circuit operation. Therefore, in this description, "source electrode" and "drain electrode" can be used interchangeably.

[0036] In this description, "connect" encompasses the case where components are linked via an element with a specific electrical effect. "Elements with a specific electrical effect" are not subject to any particular restrictions as long as they can transmit electrical signals between connected components. Examples of "elements with a specific electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0037] In this description, "parallel" refers to a state in which the angle formed by two lines is greater than -10° and less than 10°, and thus also includes a state in which the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two lines is greater than 80° and less than 100°, and thus also includes a state in which the angle is greater than 85° and less than 95°.

[0038] “Approximately”, “about” in this revelation means that no strict limit is set and cases within the range of process and measurement errors are permitted.

[0039] In this description, "A extends along direction B" means that A can comprise a main part and a sub-part connected to the main part. The main part is a line-, line-segment-, or strip-shaped body; the main part extends along direction B; and the length of the main part along direction B is greater than the length of the sub-part along other directions. "A extends along direction B," as stated in this description, always means that the main part of A extends along direction B.

[0040] In this description, "A and B are structures on the same layer" means that A and B are formed simultaneously by the same structuring process. "Same layer" does not always mean that the thickness or height of the layers is the same in the cross-sectional view. "The orthographic projection of A contains the orthographic projection of B" means that the orthographic projection of B falls within the area of ​​the orthographic projection of A, or that the orthographic projection of A overlaps the orthographic projection of B.

[0041] With the development of display technology, increasing the screen-to-body ratio and reducing the bezel size are important areas for improvement. Current display panels typically employ multiplex circuitry (MUX) to reduce the number of data lines. This reduces the space required for data routing lines within the bezel area, thus reducing the bezel size. The multiplex circuitry typically uses a 1:6 design (i.e., a single multiplexer delivers data signals to multiple data lines under the control of six multiplex control lines), and space within the bezel of the display panel (such as the display panel for wearable products) is limited, making the layout of the multiplex circuit relatively rigid.For display products with requirements for relatively high refresh rates, conventional multiplex circuits with a 1:6 design can impair the display quality of these products.

[0042] This embodiment provides a display panel and display device that enable a multiplex circuit, meeting the high refresh rate requirements of display products, to be arranged within a display panel with limited frame space. This results in a layout design suitable for multiplex circuits with high refresh rate requirements.

[0043] This embodiment provides a display panel comprising a substrate, multiple subpixels, multiple data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. The display area contains multiple subpixels and multiple data lines. The multiple data lines are connected to the multiple subpixels and configured to provide data signals to the multiple subpixels. The multiplexing circuit is located in the first frame area and comprises multiple multiplexing units. At least one of the multiple multiplexing units comprises multiple multiplexing transistors.At least one multiplexing unit is electrically connected to a multiplexed data line, several multiplexed control lines, and several data lines, and is configured to provide the data signals transmitted by the multiplexed data lines to the several data lines by controlling the several multiplexed control lines. The multiplexing transistors of the several multiplexing units are arranged in several rows and columns. A row of multiplexing transistors comprises several multiplexing transistors arranged along a first direction, and a column of multiplexing transistors comprises several multiplexing transistors arranged along a second direction. The first direction and the second direction intersect. For example, the first direction may be perpendicular to the second direction.

[0044] In the display panel provided in this embodiment, the multiplex circuit suitable for high refresh rate requirements can be arranged within a spatially limited frame area by arranging the multiplex transistors of the multiplex circuit in an array.

[0045] In some exemplary embodiments, a column of multiplex transistors can comprise several multiplex transistors connected to the same multiplex control line. This example, by arranging several multiplex transistors connected to the same multiplex control line in a column, helps to reduce the space occupied by the multiplex circuit in the first direction.

[0046] In some exemplary embodiments, a column of multiplex transistors can comprise several multiplex transistors connected to the same multiplex data line. This example, by arranging multiple multiplex transistors connected to the same multiplex data line in a single column, helps to reduce the space occupied by the multiplex circuit in the first direction. For example, at least one multiplex unit can comprise three multiplex transistors electrically connected to different multiplex control lines and the same multiplex data line. The three multiplex transistors of the at least one multiplex unit can be arranged in the same column.

[0047] In some exemplary embodiments, the multiplex transistors of the multiplex circuit can be arranged in three rows. This embodiment is not limited to this. In other examples, the multiplex transistors of the multiplex circuit can be arranged in two or more than three rows, for example, six rows.

[0048] In some exemplary embodiments, at least one multiplex unit comprises two multiplex transistors electrically connected via different multiplex control lines and the same multiplex data line. The two multiplex transistors of the multiplex unit may be arranged in the same row. In some examples, the multiple multiplex units may comprise at least: multiple first multiplex units, multiple second multiplex units, and multiple third multiplex units. The multiplex transistors of the multiple first multiplex units may be arranged in a first row, the multiplex transistors of the multiple second multiplex units in a second row, and the multiplex transistors of the multiple third multiplex units in a third row.The multiplex transistors of the first, second, and third multiplex units, which are electrically connected to the same multiplex control line, can be arranged in the same column. For example, the gates of several multiplex transistors in a column of multiplex transistors can form an interconnected, integral structure. This arrangement in this example helps to reduce the space occupied by the multiplex circuit in the first direction.

[0049] In some exemplary embodiments, the multiple subpixels can comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color. The first multiplexing unit can be configured to provide data signals to the multiple first subpixels, the second multiplexing unit can be configured to provide data signals to the multiple second subpixels, and the third multiplexing unit can be configured to provide data signals to the multiple third subpixels. The multiplexing circuit in this example can use a 1:2 design to provide data signals to multiple subpixels, with a single multiplexing unit being able to deliver data signals to neighboring subpixels of the same color. This not only reduces the data signal load but also facilitates the fulfillment of high frame rate requirements.

[0050] The solution to this exemplary embodiment will be illustrated below using several examples.

[0051] Fig. Figure 1 shows a schematic representation of a display panel according to at least one embodiment of the present disclosure. In some examples, as in Fig. As shown in Figure 1, the display panel can comprise: a display area AA, a first frame area B1 on one side of the display area AA, and a second frame area B2 on the remaining sides of the display area AA. The first frame area B1 can be connected to the second frame area B2. For example, the first frame area B1 can form the bottom frame of the display panel, and the second frame area B2 can comprise the remaining frame area of ​​the display panel except for the bottom frame.

[0052] In some examples, such as in Fig. As shown in Figure 1, the display area AA can be a flat area comprising multiple subpixels PX that form a pixel array. These multiple subpixels PX can be configured to display dynamic images or still images. The display area AA can be referred to as the active area. In some examples, the display area AA may be circular or elliptical. However, this is not limited by this embodiment. The display area can, for example, have other shapes such as rectangular, etc. In some examples, the display panel may be flexible; thus, the display panel may be deformable, for example, rollable, bendable, foldable, or rollable.

[0053] In some examples, such as in Fig. As shown in Figure 1, the display area AA can comprise a display structure layer arranged on a substrate, or a display structure layer and a touch structure layer arranged sequentially on a substrate. For example, the display panel can integrate a touch structure, forming a touch-on-thin-film encapsulation (TFE). Touch-on-TFE structures mainly include flexible multi-layer-on-cell (FMLOC) and flexible single-layer-on-cell (FSLOC) structures. The FMLOC structure is based on the principle of mutual capacitance detection. It typically uses two metal layers to form the driver (Tx) and sensor (Rx) electrodes. The driver chip (IC) detects the mutual capacitance between the driver and sensor electrodes to implement the touch actions.The FSLOC structure is based on the operating principle of self-capacitance (or voltage) detection. It typically uses a single metal layer to form the touch electrodes. The integrated circuit detects the self-capacitance (or voltage) of the touch electrodes to implement the touch actions.

[0054] In some examples, the display structure layer can include multiple subpixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL can extend along a first direction X, and the multiple data lines DL can extend along a second direction Y. The orthographic projections of the multiple gate lines GL and the multiple data lines DL onto the substrate can intersect to form multiple subpixel areas. A subpixel PX can be located within a subpixel area. The multiple data lines DL can be electrically connected to the multiple subpixels PX and configured to provide data signals to the multiple subpixels PX. Multiple gate lines GL can be electrically connected to multiple subpixels PX and configured to provide gate driver signals to the multiple subpixels PX.The gate driver signals can include, for example, scan signals, or scan signals and light emission control signals, or scan signals, reset control signals and light emission control signals.

[0055] In some examples, such as in Fig. As shown in Figure 1, the first direction X can represent the direction of extension of the gate lines GL in the display area AA (e.g., the series direction), and the second direction Y can represent the direction of extension of the data lines DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y can intersect, for example, by being perpendicular to each other.

[0056] Fig. Figure 2 shows a schematic top view of the structure of a display panel according to at least one embodiment of the present disclosure. In some examples, as in Fig. As shown in Figure 2, a pixel unit P in the display area AA can comprise three subpixels. The three subpixels can each be a first subpixel P1, emitting light of a first color (e.g., red light), a second subpixel P2, emitting light of a second color (e.g., green light), and a third subpixel P3, emitting light of a third color (e.g., blue light). However, this is not limited by this embodiment. In some examples, a pixel unit can comprise four subpixels, each of which can be a red-emitting subpixel, a green-emitting subpixel, a blue-emitting subpixel, and a white-emitting subpixel. In other examples, a pixel unit can comprise four subpixels, each of which can be a red-emitting subpixel, a blue-emitting subpixel, and two green-emitting subpixels.

[0057] In some examples, the shape of the subpixels can be rectangular, diamond-shaped, pentagonal, or hexagonal. If a pixel unit comprises three subpixels, these three subpixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement ( They may be arranged in a -shaped pattern. If a pixel unit comprises four subpixels, these four subpixels can be arranged horizontally next to each other, vertically next to each other, or in a square pattern. However, this is not restricted by this embodiment.

[0058] In some examples, a subpixel can comprise a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit can include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T in the circuit structures mentioned above represents a thin-film transistor and C represents a capacitor. The number before T indicates the number of thin-film transistors in the circuit, and the number before C indicates the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit can be P-type or N-type transistors. Using the same transistor type in the pixel circuit can simplify the process flow, reduce the process complexity of the display panel, and increase product yield.In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0059] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of both. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor uses oxide semiconductors. Low-temperature polysilicon thin-film transistors offer advantages such as high mobility and fast charging, while oxide thin-film transistors (OTTs) offer advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors onto a single display panel, i.e.,An LTPS+Oxide (LTPO for short) display panel can utilize the advantages of both, thus enabling low-frequency control, reducing power consumption, and improving display quality.

[0060] In some examples, the light-emitting element can be a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LEDs or micro-LEDs), etc. For example, the light-emitting element can be an OLED, and under the control of its corresponding pixel circuit, the light-emitting element can emit red, green, blue, or white light, etc. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element can comprise an anode, a cathode, and an organic light-emitting layer arranged between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this is not limited by this embodiment.

[0061] Fig. Figure 3 shows a schematic partial sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. Fig. Figure 3 illustrates this schematically using the structure of a subpixel in the display area as an example. This example uses multiple transistors of the same type in the pixel circuit. For instance, the multiple transistors in the pixel circuit could each be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0062] In some examples, such as in Fig. As shown in Figure 3, the display area of ​​the display panel can comprise, in a direction perpendicular to the display panel: a substrate 10; and a circuit structure layer 12, a light emission structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15, arranged sequentially on the substrate 10. The display structure layer can comprise at least the circuit structure layer 12 and the light emission structure layer 13. The circuit structure layer 12 can comprise at least pixel circuits for multiple subpixels, wherein the pixel circuit of each subpixel can comprise multiple transistors and at least one capacitor. The light emission structure layer 13 can comprise at least light-emitting elements of the multiple subpixels.

[0063] In Fig. Figure 3 illustrates this in some examples using a thin-film transistor 21 and a capacitor 22, which are included in each subpixel. In some examples, the circuit structure layer 12 in the display area can comprise a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, arranged on the substrate 10.A first insulating layer 101 can be arranged between the semiconductor layer and the first conductive layer, a second insulating layer 102 can be arranged between the first conductive layer and the second conductive layer, a third insulating layer 103 can be arranged between the second conductive layer and the third conductive layer, a fourth insulating layer 104 and a fifth insulating layer 105 can be arranged between the third conductive layer and the fourth conductive layer, and a sixth insulating layer 106 can be arranged on the side of the fourth conductive layer facing away from the substrate 10. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be inorganic insulating layers, and the fifth insulating layer 105 and the sixth insulating layer 106 can be organic insulating layers.However, this is not limited by this embodiment. In other examples, a buffer layer can be arranged on the side of the semiconductor layer facing the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, the fourth insulating layer between the third and fourth conductive layers can be omitted, and only the fifth insulating layer provided. Alternatively, the fifth insulating layer between the third and fourth conductive layers can be omitted, and only the fourth insulating layer provided.

[0064] In some examples, such as in Fig. As shown in Figure 3, the semiconductor layer in the display area can comprise at least one active layer 210 of a thin-film transistor 21. The active layer 210 of the thin-film transistor 21 can comprise a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first conductive layer can comprise at least: a gate electrode 213 of the thin-film transistor 21 and a first electrode plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin-film transistor 21 onto the substrate 10 can overlap the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second conductive layer can comprise at least: a second electrode plate 222 of the capacitor 22.The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 onto the substrate 10 can overlap, at least partially; for example, they can coincide. The third conductive layer can comprise at least a source electrode 211 and a drain electrode 212 of the thin-film transistor 21. The third insulating layer 103 can have multiple vias in the display area (e.g., a first pixel via and a second pixel via). The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, thereby exposing at least part of the surface of the first area 2101 of the active layer 210.The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, thereby exposing at least part of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The fourth conductive layer can comprise at least one anode connection electrode 231. This anode connection electrode 231 can be electrically connected to the drain electrode 212 of the thin-film transistor 21 via the third pixel via provided in the sixth insulating layer 106.In some examples, the gate lines of the display area may be located in the first conductive layer, while the data lines and high-voltage supply lines of the display area may be located, for example, in the third conductive layer or the fourth conductive layer.

[0065] In some examples, such as in Fig. As shown in Figure 3, the light-emitting structure layer 13 can comprise a pixel definition layer 134 and several light-emitting elements. For example, each light-emitting element can comprise a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 arranged one above the other. The first electrode 131 of the light-emitting element can be an anode. The first electrode 131 can be arranged on the sixth insulating layer 106 and electrically connected to the anode connection electrode 231 via a third pixel via provided in the sixth insulating layer 106. The pixel definition layer 134 is arranged on the first electrode 131 and the second planarization layer 106. The pixel definition layer 134 can be provided with several pixel openings, one of which can expose at least a portion of the surface of a corresponding first electrode 131.At least a portion of the organic light-emitting layer 132 can be arranged within a pixel aperture and connected to the corresponding first electrode 131. The second electrode 133 can be arranged on top of the organic light-emitting layer 132 and connected to it. By activating the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 can emit light of the respective colors.

[0066] In some examples, the organic light-emitting layer 132 of a light-emitting element can comprise a light-emitting layer (EML) and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). By applying a voltage to the first electrode 131 and the second electrode 133, light can be emitted according to a desired gray level, utilizing the light-emission properties of the organic material.

[0067] In some examples, the light-emitting layers of light-emitting elements that emit light of different colors can be different. For example, a red light-emitting element comprises a red light-emitting layer, a green light-emitting element a green light-emitting layer, and a blue light-emitting element a blue light-emitting layer. To reduce process complexity and increase yield, the hole injection layer and the hole transport layer can be a single layer on one side of the light-emitting layer, while the electron injection layer and the electron transport layer can be a single layer on the other side of the light-emitting layer.In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (a vapor deposition process or an inkjet printing process), and isolation is achieved through surface area differences between the film layers or by surface treatment, etc. For example, any one or more of the corresponding hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be isolated for the adjacent subpixel. In some examples, the organic light-emitting layer can be fabricated by vapor deposition using a fine metal mask (FMM) or open mask, or by an inkjet process.

[0068] In some examples, such as in Fig. As shown in Figure 3, the encapsulation structure layer 14 can comprise a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 arranged one above the other. The first encapsulation layer 141 and the third encapsulation layer 143 can consist of inorganic materials, while the second encapsulation layer 142 can consist of organic materials. The second encapsulation layer 142 can be positioned between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that no external moisture can penetrate the light-emitting element. However, this is not limited by this embodiment. For example, the encapsulation structure layer can be a five-layer stacked structure (inorganic / organic / inorganic / organic / inorganic).

[0069] In some examples, the touch structure layer 15 can comprise multiple touch units. At least one touch unit can comprise at least one touch electrode. The orthographic projection of at least one touch electrode onto the substrate can contain the orthographic projections of multiple subpixels on the substrate. If a touch unit comprises multiple touch electrodes, these multiple touch electrodes can be spaced apart from one another, and adjacent touch electrodes can be connected to each other via connecting sections. Touch electrodes and connecting sections can be structures in the same layer. In some examples, the touch electrodes can have a rhombus shape, for example, a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. However, this is not limited by this embodiment.In some examples, the contact electrodes can have any or several of the following shapes: triangle, square, trapezoid, parallelogram, pentagon, hexagon and other polygons.

[0070] In some examples, such as in Fig. As shown in Figure 1, the first frame area B1 can comprise: a first fan-out area B11, a bending area B12, a second fan-out area B13, a first signal access area B14, and a second signal access area B15, arranged sequentially in a direction leading away from the display area AA. The first fan-out area B11 can be connected to the second frame area B2 and be located on one side of the display area AA. For example, the first fan-out area B11 can be provided with at least one first frame supply line, one second frame supply line, several display leak lines, and several touch leak lines. The first frame supply line can be configured to connect a first supply line (e.g., the high-voltage supply line) in the display area AA. The second frame supply line can be configured to connect a second supply line (e.g.,the low-voltage supply line) in the second frame area B2. The display leakage lines can include multiple data leakage lines and multiple driver leakage lines. Multiple data leakage lines can be electrically connected to multiple data lines in display area AA, for example, in a one-to-one correspondence. Multiple driver leakage lines can extend to the second frame area B2 and be connected to the gate driver circuitry in the second frame area B2 and can be configured to provide control signals to the gate driver circuitry, which may include, for example, start signals, clock signals, etc. Multiple touch leakage lines can extend from the second frame area B2 to the first fan-out area B11 and are located on the side of the multiple display leakage lines facing away from the substrate.

[0071] In some examples, such as in Fig. As shown in Figure 1, bend area B12 can be connected to the first fan-out area B11 and the second fan-out area B13 and is located on the side of the first fan-out area B11 facing away from the display area AA. Bend area B12 can be configured to bend the second fan-out area B13, the first signal access area B14, and the second signal access area B15 to the back of the display area AA. Bend area B12 can be provided with multiple bend connection lines, such as multiple data bend connection lines and multiple touch bend connection lines, etc. For example, multiple bend connection lines within bend area B12 can be located on the same layer, such as the fourth or third conductive layer.

[0072] In some examples, such as in Fig. As shown in Figure 1, the second fan-out area B13 can be located on the side of the bending area B12 facing away from the display area AA. The second fan-out area B13 can, for example, be equipped with several test circuits.

[0073] In some examples, such as in Fig. As shown in Figure 1, the first signal access area B14 can be located on the side of the second fan-out area B13 facing away from the display area AA. The first signal access area B14 can also be referred to as the driver chip placement area. The first signal access area B14 can be provided with multiple first contact pads (bumps) that can be configured for binding to at least one driver chip (IC, Integrated Circuit). The driver chip can be configured to generate the control signals required to drive the subpixels, which may include, for example, data signals.

[0074] In some examples, such as in Fig. As shown in Figure 1, the second signal access area B15 can be located on the side of the first signal access area B14 facing away from the display area AA. The second signal access area B15 can also be referred to as the circuit binding area. The second signal access area B15 can be provided with multiple second contact pads. These multiple second contact pads can be configured to be bonded to at least one printed circuit board (e.g., a flexible printed circuit board (FPC)). For example, the external printed circuit board can be configured to generate touch signals for delivery to the touch structure and to receive touch sensor signals.

[0075] In some examples, a multiplex circuit may also be provided in the first fan-out area B11. For instance, the multiplex circuit may be located near the bending area B12. The multiplex circuit may be electrically connected to the multiple data lines in the display area AA via multiple data feed lines to be configured to transmit data signals to the multiple data lines. The multiplex circuit may also be electrically connected to multiple multiplex data lines to be configured to receive data signals transmitted by a driver chip located in the first signal access area B14. The multiple multiplex data lines may be electrically connected to the data bending connection lines in the bending area. The second fan-out area may also be provided with multiple multiplex data feed lines that are electrically connected to the data bending connection lines.The multiple multiplex data lines can be electrically connected to multiple first contact pads in the first signal access area B14, which carry data signals. In some examples, the data signals provided by the driver chip can be sequentially transmitted to the data lines in the display area via the multiplex data lines, the data bend lines, the multiplex data lines, the multiplexing circuit, and the data leakage lines. The multiplexing circuit can transmit data signals carried by M multiplex data lines to N data lines, where M and N are integers and M is less than N. By providing a multiplexing circuit, the number of data signal transmission lines can be reduced, thus reducing the frame size.Furthermore, it can support situations where the driver chip has fewer data signal lines, allowing the driver chip to deliver data signals to all data lines in the display area.

[0076] Fig. Figure 4 shows an equivalent circuit diagram of a multiplex circuit according to at least one embodiment of the present disclosure. In some examples, as in Fig. As shown in Figure 4, the multiplex circuit 30 can comprise several multiplex units. A multiplex unit can be configured to deliver a data signal provided by one multiplex data line to multiple data lines (e.g., two data lines).

[0077] In some examples, such as in Fig. As shown in Figure 4, a multiplex unit can be electrically connected to two multiplex control lines (e.g., comprising a first multiplex control line 51 and a second multiplex control line 52), one multiplex data line, and multiple data lines (e.g., two data lines). Each multiplex unit can comprise two multiplex transistors. The two data lines to which a multiplex unit is connected can be electrically connected to subpixels that emit light of the same color. The way the multiplex units are connected in this example can effectively reduce the load on the data signal.

[0078] In Fig. This is illustrated in section 4 using the example of the six multiplex units of the multiplex circuit 30. Three multiplex units can form a group. Each group of multiplex units is connected in a similar way, and this is explained below using the example of a group of multiplexer units. In some examples, as in Fig. As shown in Figure 4, a group of multiplex units can comprise a first multiplex unit 31, a second multiplex unit 32 and a third multiplex unit 33.

[0079] In some examples, such as in Fig. As shown in Figure 4, the first multiplex unit 31 can comprise a first multiplex transistor T1 and a second multiplex transistor T2. The gate of the first multiplex transistor T1 is electrically connected to the first multiplex control line 51, the first electrode of the first multiplex transistor T1 is electrically connected to the first multiplex data line 41, and the second electrode of the first multiplex transistor T1 is electrically connected to the first data line 61. The first data line 61 can be electrically connected to a column of the first subpixel R1. The gate of the second multiplex transistor T2 is electrically connected to the second multiplex control line 52, the first electrode of the second multiplex transistor T2 is electrically connected to the first multiplex data line 41, and the second electrode of the second multiplex transistor T2 is electrically connected to the fourth data line 64.The fourth data line 64 can be electrically connected to a column of first subpixel R2. A column of first subpixel R1 and a column of first subpixel R2 can emit light of the same color, for example, both emitting red light.

[0080] In some examples, such as in Fig. As shown in Figure 4, the second multiplexing unit 32 can comprise a third multiplexing transistor T3 and a fourth multiplexing transistor T4. The gate of the third multiplexing transistor T3 is electrically connected to the first multiplexing control line 51, the first electrode of the third multiplexing transistor T3 is electrically connected to the second multiplexing data line 42, and the second electrode of the third multiplexing transistor T3 is electrically connected to the second data line 62. The second data line 62 can be electrically connected to a column of the second subpixel G1. The gate of the fourth multiplexing transistor T4 is electrically connected to the second multiplexing control line 52, the first electrode of the fourth multiplexing transistor T4 is electrically connected to the second multiplexing data line 42, and the second electrode of the fourth multiplexing transistor T4 is electrically connected to the fifth data line 65.The fifth data line 65 can be electrically connected to a column of second subpixel G2. A column of second subpixel G1 and a column of second subpixel G2 can emit light of the same color, for example, both emitting green light.

[0081] In some examples, such as in Fig. As shown in Figure 4, the third multiplexing unit 33 can comprise a fifth multiplexing transistor T5 and a sixth multiplexing transistor T6. The gate of the fifth multiplexing transistor T5 is electrically connected to the first multiplexing control line 51, the first electrode of the fifth multiplexing transistor T5 is electrically connected to the third multiplexing data line 43, and the second electrode of the fifth multiplexing transistor T5 is electrically connected to the third data line 63. The third data line 63 can be electrically connected to a column of the third subpixel B1. The gate of the sixth multiplexing transistor T6 is electrically connected to the second multiplexing control line 52, the first electrode of the sixth multiplexing transistor T6 is electrically connected to the third multiplexing data line 43, and the second electrode of the sixth multiplexing transistor T6 is electrically connected to the sixth data line 66.The sixth data line 66 can be electrically connected to a column of third subpixel B2. A column of third subpixel B1 and a column of third subpixel B2 can emit the same color of light, for example, both emitting blue light.

[0082] In some examples, a column of first subpixel R1, a column of second subpixel G1, a column of third subpixel B1, a column of first subpixel R2, a column of second subpixel G2 and a column of third subpixel B2 can be arranged sequentially along the first direction.

[0083] In this example, the data signals received by adjacent monochrome subpixels are controlled by the same multiplexing unit. This effectively reduces the load on the data signals and allows the corresponding data voltage difference between the same-colored subpixels in the same row of subpixels to be relatively small, thus reducing power consumption. Furthermore, the multiplexing circuit uses a 1:2 design (i.e., a design where one multiplexed data line provides data signals to two data lines), which not only effectively reduces the load on the data signals but also facilitates achieving high refresh rates.

[0084] Fig. Figure 5 shows a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure. Fig. Figure 5 illustrates this using the example of the partial planar structure of a group of multiplex units. In this example, the first connection end of the conductor track is located closer to the display area, while the second connection end is located further away from the display area.

[0085] In some examples, such as in Fig. As shown in Figure 5, the first multiplex unit 31 (comprising the first multiplex transistor T1 and the second multiplex transistor T2), the second multiplex unit 32 (comprising the third multiplex transistor T3 and the fourth multiplex transistor T4), and the third multiplex unit 33 (comprising the fifth multiplex transistor T5 and the sixth multiplex transistor T6) can be arranged sequentially along the second direction Y. For example, the third multiplex unit 33 can be located on the side of the second multiplex unit 32 facing away from the display area, and the second multiplex unit 32 can be located on the side of the first multiplex unit 31 facing away from the display area. This arrangement of the multiplex circuit in this example can save space along the first direction X.

[0086] In some examples, such as in Fig. As shown in Figure 5, multiple multiplex units comprise multiple multiplex transistors that can be arranged in an array along the first direction X and the second direction Y. For example, the multiple multiplex transistors can be arranged in three rows. A row of multiplex transistors can comprise multiple multiplex transistors arranged sequentially along the first direction X, and a column of multiplex transistors can comprise multiple multiplex transistors arranged sequentially along the second direction Y. The first multiplex transistor T1 and the second multiplex transistor T2 of the first multiplex unit 31 can be arranged sequentially along the first direction X. The first multiplex transistor T1 and the second multiplex transistor T2 can be arranged alternately in a row along the first direction X.The third multiplex transistor T3 and the fourth multiplex transistor T4 of the second multiplex unit 32 can be arranged sequentially along the first direction X. The third multiplex transistor T3 and the fourth multiplex transistor T4 can be arranged alternately in a row along the first direction X. The fifth multiplex transistor T5 and the sixth multiplex transistor T6 of the third multiplex unit 33 can be arranged sequentially along the first direction X. The fifth multiplex transistor T5 and the sixth multiplex transistor T6 can be arranged alternately in a row along the first direction X. In this example, several first multiplex units 31 can be arranged in a row, several second multiplex units 32 in a row, and several third multiplex units 33 in a row; a first multiplex unit 31, a second multiplex unit 32, and a third multiplex unit 33 can be arranged in a column.

[0087] In some examples, such as in Fig. As shown in Figure 5, the first multiplex transistor T1 of the first multiplex unit 31, the third multiplex transistor T3 of the second multiplex unit 32, and the fifth multiplex transistor T5 of the third multiplex unit 33 can be arranged in a column along the second direction Y. The second multiplex transistor T2 of the first multiplex unit 31, the fourth multiplex transistor T4 of the second multiplex unit 32, and the sixth multiplex transistor T6 of the third multiplex unit 33 can also be arranged in a column along the second direction Y.

[0088] In some examples, such as in Fig. As shown in Figure 5, the first frame region can comprise at least the following in a direction perpendicular to the display panel: a substrate, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer arranged on the substrate. A first insulating layer can be arranged between the semiconductor layer and the first conductive layer, a second insulating layer can be arranged between the first conductive layer and the second conductive layer, and a third insulating layer can be arranged between the second conductive layer and the third conductive layer.

[0089] Fig. Figure 6 is a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 5. In some examples, as in the Fig. 5 and Fig. As shown in Figure 6A, the semiconductor layer in the first frame area can include at least active layers of several multiplex transistors of several multiplex units of the multiplex circuit, such as the active layer T10 of the first multiplex transistor T1 and the active layer T20 of the second multiplex transistor T2 of the first multiplex unit 31, the active layer T30 of the third multiplex transistor T3 and the active layer T40 of the fourth multiplex transistor T4 of the second multiplex unit 32, as well as the active layer T50 of the fifth multiplex transistor T5 and the active layer T60 of the sixth multiplex transistor T6 of the third multiplex unit 33.

[0090] In some examples, such as in Fig. As shown in Figure 6, the shapes and dimensions of the orthographic projections of the active layer T10 of the first multiplex transistor and the active layer T20 of the second multiplex transistor of the first multiplex unit, the active layer T30 of the third multiplex transistor and the active layer T40 of the fourth multiplex transistor of the second multiplex unit, the active layer T50 of the fifth multiplex transistor and the active layer T60 of the sixth multiplex transistor of the third multiplex unit on the substrate can be approximately the same; for example, they can be approximately rectangular with the same dimensions. However, this is not restricted by this embodiment.

[0091] In some examples, such as in Fig. As shown in Figure 6, the active layer T10 of the first multiplex transistor and the active layer T20 of the second multiplex transistor can be aligned along a first direction X, the active layer T30 of the third multiplex transistor and the active layer T40 of the fourth multiplex transistor can be aligned along the first direction X, and the active layer T50 of the fifth multiplex transistor and the active layer T60 of the sixth multiplex transistor can be aligned along the first direction X.

[0092] In some examples, such as in Fig. As shown in Figure 6, the active layer T10 of the first multiplex transistor, the active layer T30 of the third multiplex transistor, and the active layer T50 of the fifth multiplex transistor can be arranged sequentially along the second direction Y. The active layer T10 of the first multiplex transistor has a first centerline O1, the active layer T30 of the third multiplex transistor has a third centerline O3, and the active layer T50 of the fifth multiplex transistor has a fifth centerline O5. The first centerline O1, the third centerline O3, and the fifth centerline O5 can each run parallel to the second direction Y.The third centerline O3 of the active layer T30 of the third multiplex transistor can be located on one side of the first centerline O1 of the active layer T10 of the first multiplex transistor in the first direction X, and the fifth centerline O5 of the active layer T50 of the fifth multiplex transistor can be located on one side of the third centerline O3 of the active layer T30 of the third multiplex transistor in the first direction X. In the first direction X, the distance between the third centerline O3 and the first centerline O1 can be approximately equal to the distance between the third centerline O3 and the fifth centerline O5. However, this is not restricted by this embodiment. For example, in the first direction X, the distance between the third centerline O3 and the first centerline O1 can be smaller or larger than the distance between the third centerline O3 and the fifth centerline O5.

[0093] In some examples, such as in Fig. As shown in Figure 6, the active layer T20 of the second multiplex transistor, the active layer T40 of the fourth multiplex transistor, and the active layer T60 of the sixth multiplex transistor can be arranged sequentially along the second direction Y. The active layer T20 of the second multiplex transistor can have a second centerline O2, the active layer T40 of the fourth multiplex transistor can have a fourth centerline O4, and the active layer T60 of the sixth multiplex transistor can have a sixth centerline O6. The second centerline O2, the fourth centerline O4, and the sixth centerline O6 can each be parallel to the second direction Y. The fourth centerline O4 can be located on one side of the second centerline O2 in the first direction X, and the sixth centerline O6 can be located on one side of the fourth centerline O4 in the first direction X.In the first direction X, the distance between the fourth centerline O4 and the second centerline O2 can be approximately equal to the distance between the fourth centerline O4 and the sixth centerline O6. The distance between the fourth centerline O4 and the second centerline O2 can be approximately equal to the distance between the third centerline O3 and the first centerline O1. However, this is not restricted by this embodiment.

[0094] In some examples, such as in Fig. As shown in Figure 6, in the first direction X, the distance between the fifth centerline O5 and the sixth centerline O6 can be smaller than the distance between the third centerline O3 and the fourth centerline O4, and the distance between the third centerline O3 and the fourth centerline O4 can be smaller than the distance between the first centerline O1 and the second centerline O2. However, this is not restricted by this embodiment. For example, the distances between two adjacent centerlines along the first direction X can be approximately equal.

[0095] In some examples, the active layer of each multiplex transistor can comprise a first region, a second region, and a channel region situated between the first and second regions. The orthographic projection of the channel region of the multiplex transistor's active layer onto the substrate can be overlaid by the orthographic projection of the corresponding gate onto the substrate.

[0096] Fig. Figure 7A shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 5. Fig. Figure 7B shows a schematic top view of the first conductive layer in Fig. 7A. In some examples, as in the Fig. 7A and Fig. As shown in Figure 7B, the first conductive layer in the first frame area can comprise at least: gates of several multiplex transistors of several multiplex units of the multiplex circuit (for example, comprising the gate T13 of the first multiplex transistor T1, the gate T23 of the second multiplex transistor T2, the gate T33 of the third multiplex transistor T3, the gate T43 of the fourth multiplex transistor T4, the gate T53 of the fifth multiplex transistor T5, and the gate T63 of the sixth multiplex transistor T6); several data leak lines (for example, comprising a first data leak line 251, a third data leak line 253, and a fifth data leak line 255); a first multiplex data line 41, a third multiplex data line 43, a second multiplex interconnect line 262, and a third multiplex interconnect line 263.

[0097] In some examples, such as in the Fig. 7A and Fig. As shown in Figure 7B, the gate T13 of the first multiplex transistor T1, the gate T33 of the third multiplex transistor T3, and the gate T53 of the fifth multiplex transistor T5 can all be essentially strip-shaped structures extending along the second direction Y. The gate T13 of the first multiplex transistor T1, the gate T33 of the third multiplex transistor T3, and the gate T53 of the fifth multiplex transistor T5 can form an interconnected, integral structure. The gate T23 of the second multiplex transistor T2, the gate T43 of the fourth multiplex transistor T4, and the gate T63 of the sixth multiplex transistor T6 can all be essentially strip-shaped structures extending along the second direction Y. The gate T23 of the second multiplex transistor T2, the gate T43 of the fourth multiplex transistor T4 and the gate T63 of the sixth multiplex transistor T6 can form an interconnected, integral structure.

[0098] In some examples, multiple data leakage lines may extend to one side of the display area to be electrically connected to multiple data lines within the display area. As in Fig. As shown in Figure 7B, the first data line 251, the third data line 253 and the fifth data line 255 can be arranged along the first direction X.

[0099] In some examples, such as in the Fig. 7A and Fig. As shown in Figure 7B, the first data leak line 251 can be located on the side of the active layer T10 of the first multiplex transistor T1 facing away from the active layer T30 of the third multiplex transistor T3 in the second direction Y. The third data leak line 253 can be located at least between the active layer T10 of the first multiplex transistor T1 and the active layer T20 of the second multiplex transistor T2, as well as between the active layer T30 of the third multiplex transistor T3 and the active layer T40 of the fourth multiplex transistor T4. One end of the third data leak line 253 can extend between the active layer T30 of the third multiplex transistor T3 and the active layer T50 of the fifth multiplex transistor T5, as well as near the integral structure of gate T33 of the third multiplex transistor T3 and gate T53 of the fifth multiplex transistor T5.The fifth data line 255 can be located on the side of the active layer T20 of the second multiplex transistor T2 facing away from the third data line 253. One end of the fifth data line 255 can be located between the active layer T20 of the second multiplex transistor T2 and the active layer T40 of the fourth multiplex transistor T4, as well as near the integral structure of gate T23 of the second multiplex transistor T2 and gate T43 of the fourth multiplex transistor T4.

[0100] In some examples, such as in the Fig. 7A and Fig. As shown in Figure 7B, the first multiplex data line 41 can essentially have a zigzag shape running along the second direction Y. The first multiplex data line 41 can be located on the side of the active layer T30 of the third multiplex transistor T3 and the active layer T50 of the fifth multiplex transistor T5 facing away from the third data line 253. The first connection end of the first multiplex data line 41 can be located between the active layer T10 of the first multiplex transistor T1 and the active layer T30 of the third multiplex transistor T3, as well as near the integral structure of gate T13 of the first multiplex transistor T1 and gate T33 of the third multiplex transistor T3.

[0101] In some examples, the third multiplex data line 43 can extend substantially along the second direction Y, and the first connection end of the third multiplex data line 43 can be located on one side of the active layer T60 of the sixth multiplex transistor T6 in the second direction Y.

[0102] In some examples, the third multiplex connection line 263 can extend essentially along the second direction Y. The first connection end of the third multiplex connection line 263 can be located on one side of the active layer T50 of the fifth multiplex transistor T5 in the second direction Y.

[0103] In some examples, the second multiplex connection line 262 can essentially run along the second direction Y. The second multiplex connection line 262 can be located between the active layer T50 of the fifth multiplex transistor T5 and the active layer T60 of the sixth multiplex transistor T6. The first connection end of the second multiplex connection line 262 can be located between the active layer T40 of the fourth multiplex transistor T4 and the active layer T60 of the sixth multiplex transistor T6, as well as near the integral structure of gate T43 of the fourth multiplex transistor T4 and gate T63 of the sixth multiplex transistor T6. The second multiplex connection line 262 can be adjacent to the third multiplex data line 43.

[0104] Fig. Figure 8A shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 5. Fig. Figure 8B shows a schematic top view of the second conductive layer in Fig. 8A. In some examples, as in the Fig. 8A and Fig. As shown in Figure 8B, the second conductive layer of the first frame area can include at least: several data leak lines (e.g., including the second data leak line 252, the fourth data leak line 254, and the sixth data leak line 256), a second multiplex data line 42, and a first multiplex interconnect line 261.

[0105] In some examples, the first data leak line 251, the second data leak line 252, the third data leak line 253, the fourth data leak line 254, the fifth data leak line 255, and the sixth data leak line 256 can be arranged sequentially along the first direction X. The orthographic projections of the first data leak line 251, the second data leak line 252, the third data leak line 253, the fourth data leak line 254, the fifth data leak line 255, and the sixth data leak line 256 on the substrate cannot overlap. The multiple data leak lines in this example can be arranged alternately on the first conductive layer and the second conductive layer, thereby reducing the spacing between adjacent data leak lines and thus decreasing the space occupied by the conductor tracks, which in turn contributes to narrowing the frame.

[0106] In some examples, the second data leak line 252 can essentially have a zigzag shape extending along the second direction Y. The second data leak line 252 can be located at least between the active layer T10 of the first multiplex transistor T1 and the active layer T20 of the second multiplex transistor T2. One end of the second data leak line 252 can be located between the active layer T10 of the first multiplex transistor T1 and the active layer T30 of the third multiplex transistor T3, as well as near the integral structure of gate T13 of the first multiplex transistor T1 and gate T33 of the third multiplex transistor T3. The fourth data leak line 254 can be located on one side of the active layer T20 of the second multiplex transistor T2 in the opposite direction to the second direction Y.The sixth data leak line 256 can essentially have a zigzag shape extending along the second direction Y. The sixth data leak line 256 can be located at least on one side of the fifth data leak line 255 facing away from the active layer T20 of the second transistor T2, and on one side of the active layer T40 of the fourth multiplex transistor T4 in the first direction X. One connection end of the sixth data leak line 256 can be located between the active layer T40 of the fourth multiplex transistor T4 and the active layer T60 of the sixth multiplex transistor T6, as well as near the integral structure of gate T43 of the fourth multiplex transistor T4 and gate T63 of the sixth multiplex transistor T6.

[0107] In some examples, the second multiplex data line 42 can essentially have a zigzag shape extending along the second direction Y. The second multiplex data line 42 can be located on the side of the first multiplex data line 41 facing the active layer T50 of the fifth multiplex transistor T5, and the second multiplex data line 42 can be located between the first multiplex data line 41 and the third multiplex interconnect 263. The first interconnect end of the second multiplex data line 42 can be located between the active layer T30 of the third multiplex transistor T3 and the active layer T50 of the fifth multiplex transistor T5, as well as near the integral structure of gate T33 of the third multiplex transistor T3 and gate T53 of the fifth multiplex transistor T5.

[0108] In some examples, the first multiplex connection line 261 can essentially have a zigzag shape extending along the second direction Y. The first multiplex connection line 262 can be located at least between the active layer T50 of the fifth multiplex transistor T5 and the active layer T60 of the sixth multiplex transistor T6, as well as between the active layer T30 of the third multiplex transistor T3 and the active layer T40 of the fourth multiplex transistor T4. The first multiplex connection line 261 can be located on the side of the third data line 253 facing the active layer T40 of the fourth multiplex transistor T4 and on the side of the second multiplex connection line 262 facing the active layer T50 of the fifth multiplex transistor T5.The first connection end of the first multiplex connection line 261 can be located between the active layer T20 of the second multiplex transistor T2 and the active layer T40 of the fourth multiplex transistor T4, as well as near the integral structure of the gate T23 of the second multiplex transistors T2 and the gate T43 of the fourth multiplex transistors T4.

[0109] In some examples, the first multiplex data line 41 can be connected to the first multiplex interconnect line 261 and transmit a first data signal; the second multiplex data line 42 can be connected to the second multiplex interconnect line 262 and transmit a second data signal; the third multiplex data line 43 can be connected to the third multiplex interconnect line 263 and transmit a third data signal. The first multiplex data line 41 and the first multiplex interconnect line 261 have essentially the same orientation and are located in different film layers, thus saving space occupied by the conductor tracks. The second multiplex data line 42 and the second multiplex interconnect line 262 have essentially the same orientation and are located in different film layers, which also contributes to space savings.

[0110] Fig. Figure 9 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 5. In some examples, such as in Fig. As shown in Figure 9, the third insulating layer in the first frame region can be provided with multiple vias, which may, for example, extend from the first via V1 to the twelfth via V12, from the thirteenth via V13 to the twenty-first via V21, and from the thirty-third via V33 to the thirty-ninth via V39. In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 to the twelfth via V12 can be removed, exposing part of the semiconductor layer surface. The third insulating layer and the second insulating layer within the thirteenth via V13 to the twenty-first via V21 can be removed, exposing part of the first conductive layer surface.The third insulating layer within the thirty-third via V33 to the thirty-ninth via V39 can be removed, exposing part of the surface of the second conductive layer.

[0111] Fig. Figure 10 shows a schematic top view of the third conductive layer in Fig. 5. In some examples, such as in Fig. 5 and Fig. As shown in Figure 10, the third conductive layer in the first frame area can comprise at least several connecting electrodes (e.g., comprising the first connecting electrode 301 to the sixteenth connecting electrode 316).

[0112] In some examples, the first interconnect electrode 301 can essentially be a strip-shaped structure extending along the second direction Y. The first interconnect electrode 301 can be electrically connected to the first active layer T10 of the first multiplex transistor T1 via several (e.g., four) vertically arranged first vias V1. It can also be electrically connected to the first multiplex data line 41 via two vertically arranged sixteenth vias V16. The vertical arrangement in this example refers to the arrangement along the second direction, while the horizontal arrangement refers to the arrangement along the first direction.

[0113] In some examples, the second interconnect electrode 302 can essentially have a zigzag shape extending along the second direction Y. The second interconnect electrode 302 can be electrically connected to the second region of the active layer T10 of the first multiplex transistor T1 via several (e.g., four) vertically arranged second vias V2. It can also be electrically connected to the first data line 251 via two vertically arranged thirteenth vias V13.

[0114] In some examples, the third interconnect electrode 303 can essentially be a strip-shaped structure extending along the second direction Y. The third interconnect electrode 303 can be electrically connected to the first active layer T20 of the second multiplex transistor T2 via several (e.g., four) vertically arranged third vias V3. It can also be electrically connected to the first multiplex interconnect line 261 via two vertically arranged thirty-seventh vias V37. The first multiplex interconnect line 261 can be electrically connected to the first multiplex data line 41.

[0115] In some examples, the fourth interconnect electrode 304 can essentially have a zigzag shape extending along the second direction Y. The fourth interconnect electrode 304 can be electrically connected to the second active layer T20 of the second multiplex transistor T2 via several (e.g., four) vertically arranged fourth vias V4. It can also be electrically connected to the fourth data line 254 via two vertically arranged thirty-fourth vias V34.

[0116] In some examples, the fifth interconnect electrode 305 can essentially be a strip-shaped structure extending along the second direction Y. The fifth interconnect electrode 305 can be electrically connected to the first active layer T30 of the third multiplex transistor T3 via several (e.g., four) vertically arranged fifth vias V5, and also electrically connected to the second multiplex data line 42 via two vertically arranged thirty-eighth vias V38.

[0117] In some examples, the sixth interconnect electrode 306 can essentially be a strip-shaped structure extending along the second direction Y. The sixth interconnect electrode 306 can be electrically connected to the second active layer T30 of the third multiplex transistor T3 via several (e.g., four) vertically arranged sixth vias V6, and also electrically connected to the second data line 252 via two vertically arranged thirty-sixth vias V36.

[0118] In some examples, the seventh interconnect electrode 307 can essentially be a strip-shaped structure extending along the second direction Y. The seventh interconnect electrode 307 can be electrically connected to the first region of the active layer T40 of the fourth multiplex transistor T4 via several (e.g., four) vertically arranged seventh vias V7. It can also be electrically connected to the second multiplex interconnect line 262 via two vertically arranged nineteenth vias V19. The second multiplex interconnect line 262 can be electrically connected to the second multiplex data line 42.

[0119] In some examples, the eighth interconnect electrode 308 can essentially be a strip-shaped structure extending along the second direction Y. The eighth interconnect electrode 308 can be electrically connected to the second region of the active layer T40 of the fourth multiplex transistor T4 via several (e.g., four) vertically arranged eighth vias V8. It can also be electrically connected to the fifth data line 255 via two vertically arranged seventeenth vias V17.

[0120] In some examples, the ninth interconnect electrode 309 can essentially be a strip-shaped structure extending along the second direction Y. The ninth interconnect electrode 309 can be electrically connected to the first region of the active layer T50 of the fifth multiplex transistor T5 via several (e.g., four) vertically arranged ninth vias V9. It can also be electrically connected to the third multiplex interconnect line 263 via two vertically arranged twentieth vias V20. The third multiplex interconnect line 263 can be electrically connected to the third multiplex data line 43.

[0121] In some examples, the tenth interconnect electrode 310 can essentially be a strip-shaped structure extending along the second direction Y. The tenth interconnect electrode 310 can be electrically connected to the second region of the active layer T50 of the fifth multiplex transistor T5 via several (e.g., four) vertically arranged tenth vias V10. It can also be electrically connected to the third data line 253 via two vertically arranged eighteenth vias V18.

[0122] In some examples, the eleventh interconnect electrode 311 can essentially have a strip-like structure extending along the second direction Y. The eleventh interconnect electrode 311 can be electrically connected to the first region of the active layer T60 of the sixth multiplex transistor T6 via several (e.g., four) vertically arranged eleventh vias V11 and also electrically connected to the third multiplex data line 43 via two vertically arranged twenty-first vias V21.

[0123] In some examples, the twelfth interconnect electrode 312 can essentially have a strip-like structure extending along the second direction Y. The twelfth interconnect electrode 312 can be electrically connected to the second region of the active layer T60 of the sixth multiplex transistor T6 via several (e.g., four) vertically arranged twelfth vias V12 and also electrically connected to the sixth data trace 256 via two vertically arranged thirty-ninth vias V39.

[0124] In some examples, the thirteenth connection electrode 313 can be essentially rectangular. The thirteenth connection electrode 313 can be electrically connected to the second data line 252 via two vertically arranged thirty-third vias V33. The fourteenth connection electrode 314 can be essentially rectangular. The fourteenth connection electrode 314 can be electrically connected to the third data line 253 via two vertically arranged fourteenth vias V14. The fifteenth connection electrode 315 can be essentially rectangular. The fifteenth connection electrode 315 can be electrically connected to the fifth data line 255 via two vertically arranged fifteenth vias V15. The sixteenth connection electrode 316 can be essentially rectangular.The sixteenth connecting electrode 316 can be electrically connected to the sixth data line 256 via two vertically arranged thirty-fifth vias V35.

[0125] In some examples, the first data line 251 is electrically connected to the multiplex circuit via the second connecting electrode 302, and the fourth data line 254 is electrically connected to the multiplex circuit via the fourth connecting electrode 304.The electrical connection of the thirteenth connecting electrode 313 with the second data line 252, the electrical connection of the fourteenth connecting electrode 314 with the third data line 253, the electrical connection of the fifteenth connecting electrode 315 with the fifth data line 255 and the electrical connection of the sixteenth connecting electrode 316 with the sixth data line 256 ensures the consistency of the film layer pattern of the third conductive layer and the uniformity of the vias in the third insulating layer, thereby promoting the uniformity of the resistance of the several data lines and ensuring the uniformity of signal transmission.

[0126] Fig. Figure 11 shows a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure. Fig. Figure 11 illustrates the planar structures of two groups of multiplex units and their connection to the data bending connection lines in the bending area. This will be further explained below using the example of the structure of a group of multiplex units and data bending connection lines in Fig. 11 in connection with Fig. 5 to Fig. 10 illustrated.

[0127] In some examples, such as in Fig. As shown in Figure 11, several first multiplex units 31, several second multiplex units 32, and several third multiplex units 33 can be arranged in a row along the first direction X. A column of multiplex units can comprise first multiplex units 31, second multiplex units 32, and third multiplex units 33 arranged along the second direction Y.

[0128] In some examples, such as in Fig. As shown in Figure 11, the first frame area can comprise at least the following in a direction perpendicular to the display panel: a substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged on the substrate. A fourth insulating layer and a fifth insulating layer may be arranged between the third conductive layer and the fourth conductive layer.

[0129] Fig. Figure 12 is a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 11. In some examples, as in the Fig. 11 and Fig. As shown in Figure 12, the active layers T10 of the first multiplex transistor T1 and the active layers T20 of the second multiplex transistor T2 of the first multiplex unit 31 can be arranged in a row spaced apart along the first direction X. The active layers T30 of the third multiplex transistor T3 and the active layers T40 of the fourth multiplex transistor T4 of the second multiplex unit 32 can be arranged in a row spaced apart along the first direction X. The active layers T50 of the fifth multiplex transistor T5 and the active layers T60 of the sixth multiplex transistor T6 of the third multiplex unit 33 can be arranged in a row spaced apart along the first direction X.

[0130] Fig. Figure 13 shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 11. In some examples, such as in Fig. As shown in Figure 13, the second connection end of the first multiplex data line 41 and the second connection end of the third multiplex data line 43 can be aligned in the first direction X. The second connection end of the third multiplex connection line 263 can be located on the same side as the second connection end of the third multiplex data line 43 in the opposite direction to the second direction Y. The second connection end of the second multiplex connection line 262 can be located on the same side as the third multiplex connection line 263 in the opposite direction to the second direction Y.

[0131] Fig. Figure 14 shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 11. In some examples, such as in Fig. As shown in Figure 14, the second connection end of the second multiplex data line 42 and the second connection end of the first multiplex data line 41 can be aligned in the first direction X. The second connection end of the second multiplex data line 42 can be located in the first direction X between the second connection end of the first multiplex data line 41 and the second connection end of the third multiplex data line 43. The second connection end of the first multiplex connection line 261 can be located on one side of the second connection end of the second multiplex connection line 262 in the opposite direction to the second direction Y.

[0132] Fig. Figure 15 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 11. In some examples, such as in Fig. As shown in Figure 15, the third insulating layer in the first frame area can, for example, include the first via V1 to the twelfth via V12, the thirteenth via V13 to the twenty-ninth via V29, and the thirtieth via V30 to the thirty-ninth via V39.

[0133] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 to the twelfth via V12 can be removed, exposing part of the semiconductor layer surface. The third insulating layer and the second insulating layer within the thirteenth via V13 to the twenty-ninth via V29 can be removed, exposing part of the first conductive layer surface. The third insulating layer within the thirtieth via V30 to the thirty-ninth via V39 can be removed, exposing part of the second conductive layer surface.

[0134] Fig. Figure 16A shows a schematic representation of the display panel after the formation of the third conductive layer in Fig. 11. Fig. Figure 16B shows a schematic top view of the third conductive layer in Fig. 16A. In some examples, as in the Fig. 16A and Fig. As shown in Figure 16B, the third conductive layer in the first frame area can comprise at least: several connecting electrodes (e.g., comprising the first connecting electrode 301 to the sixteenth connecting electrode 316), a first multiplex control line 51, a second multiplex control line 52, several deflection lines (e.g., the first deflection line 361, the second deflection line 362, and the third deflection line 363), several multiplex connecting electrodes (e.g., comprising the first multiplex connecting electrode 351, the second multiplex connecting electrode 352, and the third multiplex connecting electrode 353).

[0135] In some examples, the first multiplex control line 51 and the second multiplex control line 52 can be straight at least along the first direction X. The second multiplex control line 52 can be located on one side of the first multiplex control line 51 in the second direction Y. The first multiplex control line 51 can be located on the same side of the ninth connection electrode 309, the tenth connection electrode 310, the eleventh connection electrode 311, and the twelfth connection electrode 312 in the second direction Y.

[0136] In some examples, the first multiplex connection electrode 351, the second multiplex connection electrode 352, and the third multiplex connection electrode 353 can be located on one side of the second multiplex control line 52 in the second direction Y. The first multiplex connection electrode 351, the second multiplex connection electrode 352, and the third multiplex connection electrode 353 can essentially be strip-shaped structures extending along the first direction X. The second multiplex connection electrode 352 can be located on one side of the first multiplex connection electrode 351 in the second direction Y, and the third multiplex connection electrode 353 can be located on one side of the second multiplex connection electrode 352 in the second direction Y.

[0137] In some examples, the first deflection line 361, the second deflection line 362, and the third deflection line 363 can be strip-shaped structures extending along the second direction Y. The first deflection line 361, the second deflection line 362, and the third deflection line 363 can be arranged sequentially along the first direction X. The first deflection line 361, the second deflection line 362, and the third deflection line 363 can be located on one side of the third multiplex connection electrode 353 in the second direction Y.

[0138] In some examples, the first multiplex control line 51 can be electrically connected via two vertically arranged twenty-second vias V22 to the integral structure of gate T53 of the fifth multiplex transistor, gate T33 of the third multiplex transistor, and gate T13 of the first multiplex transistor. The second multiplex control line 52 can be electrically connected via two vertically arranged twenty-third vias V23 to the integral structure of gate T63 of the sixth multiplex transistor, gate T43 of the fourth multiplex transistor, and gate T23 of the second multiplex transistor.

[0139] In some examples, the first multiplex interconnect electrode 351 can be electrically connected to the first multiplex data line 41 via the twenty-fourth via V24 and can also be electrically connected to the first multiplex interconnect line 261 via two horizontally arranged thirty-first vias V31. The second multiplex interconnect electrode 352 can be electrically connected to the second multiplex data line 42 via two vertically arranged thirty-second vias V32 and can also be electrically connected to the second multiplex interconnect line 262 via two horizontally arranged twenty-fifth vias V25.The third multiplex connection electrode 353 can be electrically connected to the third multiplex connection line 263 via two horizontally arranged twenty-sixth vias V26 and can also be electrically connected to the third multiplex data line 43 via two horizontally arranged twenty-seventh vias V27.

[0140] In some examples, the first deflection line 361 can be electrically connected to the first multiplex data line 41 via several twenty-eighth vias V28 arranged in an array. The second deflection line 362 can be electrically connected to the second multiplex data line 42 via several thirtyth vias V30 arranged in an array. The third deflection line 363 can be electrically connected to the third multiplex data line 43 via several twenty-ninth vias V29 arranged in an array.

[0141] Fig. Figure 17 shows a schematic representation of the display panel after the formation of the fifth insulating layer in Fig. 11. In some examples, such as in Fig. As shown in Figure 17, the fourth and fifth insulating layers in the first frame region can be provided with multiple vias, for example, from the forty-first via 41 to the forty-third via 43. The fifth insulating layer and the fourth insulating layer within the forty-first via 41 to the forty-third via 43 can be removed, thereby exposing part of the surface of the third conductive layer.

[0142] In some examples, such as in Fig. As shown in Figure 11, the fourth conductive layer in the first frame area can comprise at least several data bend connection lines (e.g., comprising a first data bend connection line 401, a second data bend connection line 402, and a third data bend connection line 403). The multiple data bend connection lines can extend along the second direction Y and be arranged sequentially along the first direction X.The first data bend connection line 401 can be electrically connected to the first deflection line 361 via two vertically arranged forty-first vias V41, the second data bend connection line 402 can be electrically connected to the second deflection line 362 via two vertically arranged forty-second vias V42, and the third data bend connection line 403 can be electrically connected to the third deflection line 363 via two vertically arranged forty-third vias V43.

[0143] The structure and manufacturing process of the display panel of this example are described below by way of example. The “structuring process” mentioned in this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, treatments such as the application of photoresist, mask exposure, development, etching, photoresist removal, etc. For organic materials, it includes treatments such as the application of organic material, mask exposure, and development, etc. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition; application can be carried out by any one or more of spray coating, rotary coating, and inkjet printing; and etching can be carried out by any one or more of dry etching and wet etching, which is not limited in this disclosure.A "thin film" refers to a thin film produced from a material on a substrate by deposition, application, or other processes. If the "thin film" does not require any structuring process during its entire manufacturing process, it is also referred to as a "layer." If the "thin film" does require a structuring process during its entire manufacturing process, it is referred to as a "thin film" before the structuring process and as a "layer" after the structuring process. The "layer" after the structuring process contains at least one "pattern."

[0144] “A and B are arranged in the same layer” or “A and B are structures on the same layer” as stated in this disclosure means that A and B are formed simultaneously by one and the same structuring process. “A and B are structures on different layers” means that A and B are each formed by two structuring processes. The “thickness” of the film layer is the size of the film layer in a direction perpendicular to the display panel.In the exemplary embodiments of the present disclosure, “the orthographic projection of B lies within the area of ​​the orthographic projection of A” or “the orthographic projection of A contains the orthographic projection of B” means that the limits of the orthographic projection of B fall within the boundary area of ​​the orthographic projection of A or that the limits of the orthographic projection of A overlap with the limits of the orthographic projection of B.

[0145] In some examples, the manufacturing process of the display panel of this example may include the following steps. (1) Providing a substrate. In some examples, the substrate may be a rigid base substrate or a flexible base substrate. For example, the rigid base substrate may consist of, but is not limited to, one or more of glass and quartz, and the flexible base substrate may consist of, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyaryl esters, polyarylate, polyimide, polyvinyl chloride, polyethylene, or textile fibers. In some examples, the flexible base substrate may comprise a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on top of each other.The materials of the first and second flexible layers can be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic layers can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen. (2) Forming a semiconductor layer. In some examples, a semiconductor film is deposited on a substrate and this is structured by a structuring process to form a semiconductor layer arranged on the substrate. In some examples, as in Fig. 3, Fig. 6 and Fig. As shown in Figure 12, the semiconductor layer can comprise: an active layer of a thin-film transistor of a pixel circuit in a display area and an active layer of a multiplex transistor of a multiplex circuit in a first frame area. (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are successively deposited on a substrate on which the above-mentioned pattern is formed, and the first conductive film is structured by a structuring process to form a first insulating layer on the semiconductor layer and a first conductive layer on the first insulating layer, as in Fig. 3, Fig. 7A and Fig. 7B as well Fig. Figure 13 shows that in some examples, the first conductive layer can also be referred to as the first gate metal layer. The first insulating layer can also be referred to as the first gate insulating layer. (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are successively deposited on a substrate on which the above-mentioned pattern is formed. The second conductive film is structured by a structuring process to form a second insulating layer and a second conductive layer arranged on the second insulating layer, as in Fig. 3, Fig. 8A and Fig. 8B as well Fig. Figure 14 shows that in some examples, the second conductive layer can also be referred to as the second gate metal layer and the second insulating layer as the second gate insulating layer. (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on a substrate on which the above-mentioned pattern is formed. The third insulating film is structured by a structuring process to form a third insulating layer, as in Fig. 3, Fig. 9 and Fig. Figure 15 illustrates this. In some examples, the third insulating layer may have multiple vias. The third insulating layer can also be referred to as the intermediate insulating layer. (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the above-mentioned pattern is formed, and the third conductive film is structured by a structuring process to form a third conductive layer, as in Fig. 3, Fig. 10, Fig. 16A and Fig. Figure 16B shows that in some examples, the third conductive layer can also be referred to as the first source / drain metal layer. (7) Forming a fourth insulating layer and a fifth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the above-mentioned pattern is formed, and then a fifth insulating film is applied, and the fifth insulating film and the fourth insulating film are successively structured by a structuring process to form a fourth insulating layer and a fifth insulating layer, as in Fig. 3 and Fig. Figure 17 shows that in some examples, the fourth insulating layer can also be referred to as the passivation layer and the fifth insulating layer as the first planarization layer. (8) Forming a fourth conductive layer. A fourth conductive film is deposited on the substrate on which the above-mentioned pattern is formed and structured by means of a structuring process to form a fourth conductive layer arranged on the fifth insulating layer, as shown in the Fig. 3 and Fig. Figure 11 is shown. In some examples, the fourth conductive layer can also be referred to as the second source / drain metal layer.

[0146] Subsequently, a sixth insulating layer can be formed on the side of the fourth conductive layer facing away from the substrate. This completes the circuit structure layer of this embodiment on the base substrate. In some examples, after completion of the circuit structure layer of the display area, a light emission structure layer, an encapsulation structure layer, and a touch structure layer can be formed sequentially on the circuit structure layer, which will not be discussed further here.

[0147] In some examples, the first, second, third, and fourth conductive layers can be made of metallic materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of these metals, such as aluminum-neodymium alloys (AlNd) or molybdenum-niobium alloys (MoNb). These can be single-layer structures or multi-layer composite structures such as Mo / Cu / Mo, Ti / Al / Ti, etc. For example, the first and second conductive layers can use a single-layer molybdenum metal layer, and the third and fourth conductive layers can use a three-layer stacked structure of Ti / Al / Ti.The specific resistance of the conductor tracks in the third conductive layer and the fourth conductive layer can be lower than that of the conductor tracks in the first conductive layer and the second conductive layer.

[0148] In some examples, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can consist of any one or more silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and they can be single-layered, multi-layered, or composite. The fifth insulating layer 105 and the sixth insulating layer 106 can consist of organic materials such as polyimide, acrylic, or polyethylene terephthalate, etc. The semiconductor layer can consist of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene, etc. This means that the present disclosure is suitable for transistors manufactured using oxide technology, silicon technology or organic technology.

[0149] The structure and manufacturing process of the display panel in this embodiment are for illustrative purposes only. In some cases, the structure can be modified according to actual requirements, and patterning processes can be added or removed. For example, the second source / drain metal layer in the display panel can be omitted, the anode of the light-emitting element can be directly electrically connected to the drain of the thin-film transistor, and the data bend link can be located in the third conductive layer and electrically connected to the multiplex data line in the first or second conductive layer.

[0150] The manufacturing process of this example can be implemented using currently established production equipment and is highly compatible with existing manufacturing processes. The process is simple and easy to implement, and is characterized by high production efficiency, low production costs, and high yield.

[0151] The multiplex transistors in this example's multiplex circuit can be arranged in three rows, reducing the circuit's footprint along the first direction. Combined with the 1:2 design of the multiplex circuit, this allows it to meet the high refresh rate requirements of the display panel.

[0152] Fig. Figure 18 shows a further schematic partial top view of the multiplex circuit according to at least one embodiment of the present disclosure. Fig. 18 illustrates this using the example of the partial planar structure of a group of multiplex units.

[0153] In some examples, such as in Fig. As shown in Figure 18, the two multiplex transistors of each multiplex unit in a group of multiplex units can be arranged in different rows and columns.For example, the multiplex transistors in the i-th column (comprising the first multiplex transistor T1 of the first multiplex unit and the third multiplex transistor T3 of the second multiplex unit) are each electrically connected to the first multiplex control line, the multiplex transistors in the i+1-th column (comprising the fifth multiplex transistor T5 of the third multiplex unit and the second multiplex transistor T2 of the first multiplex unit) are electrically connected to different multiplex control lines, and the multiplex transistors in the i+2-th column (comprising the fourth multiplex transistor T4 of the second multiplex unit and the sixth multiplex transistor T6 of the third multiplex unit) are each electrically connected to the second multiplex control line, where i is an integer greater than 0.

[0154] In some examples, such as in Fig. As shown in Figure 18, the six multiplex transistors of a group of multiplex units can be arranged in an array along the first direction X and the second direction Y in two rows and three columns. The first row of multiplex transistors can include: a first multiplex transistor T1 of the first multiplex unit, a fifth multiplex transistor T5 of the third multiplex unit, and a fourth multiplex transistor T4 of the second multiplex unit; the first multiplex transistor T1 of the first multiplex unit, the fifth multiplex transistor T5 of the third multiplex unit, and the fourth multiplex transistor T4 of the second multiplex unit can be arranged sequentially along the first direction X.The second row of multiplex transistors can include: a third multiplex transistor T3 of the second multiplex unit, a second multiplex transistor T2 of the first multiplex unit, and a sixth multiplex transistor T6 of the third multiplex unit. The third multiplex transistor T3 of the second multiplex unit, the second multiplex transistor T2 of the first multiplex unit, and the sixth multiplex transistor T6 of the third multiplex unit can be arranged sequentially along the first direction X. The second row of multiplex transistors can be arranged on one side of the first row of multiplex transistors in the second direction Y. The arrangement of the multiplex circuit in this example can save space along the second direction Y. For example, the arrangement of the multiplex circuit in this example may be suitable for display panels with relatively narrow bottom bezels but relatively wide horizontal dimensions.

[0155] In some examples, such as in Fig. As shown in Figure 18, the i-th column of multiplex transistors can include a first multiplex transistor T1 and a third multiplex transistor T3; the i+1-th column of multiplex transistors can include a fifth multiplex transistor T5 and a second multiplex transistor T2; and the i+2-th column of multiplex transistors can include a fourth multiplex transistor T4 and a sixth multiplex transistor T6. The i-th column, the i+1-th column, and the i+2-th column of multiplex transistors can be arranged sequentially along the first direction X.

[0156] Fig. Figure 19 is a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 18. In some examples, such as in the Fig. 18 and Fig. As shown in Figure 19, the semiconductor layer in the first frame area can include at least active layers of several multiplex transistors of several multiplex units of the multiplex circuit, such as the active layer T10 of the first multiplex transistor T1 and the active layer T20 of the second multiplex transistor T2 of the first multiplex unit, the active layer T30 of the third multiplex transistor T3 and the active layer T40 of the fourth multiplex transistor T4 of the second multiplex unit, as well as the active layer T50 of the fifth multiplex transistor T5 and the active layer T60 of the sixth multiplex transistor T6 of the third multiplex unit.

[0157] In some examples, such as in Fig. As shown in Figure 19, the shapes and dimensions of the orthographic projections of the active layer T10 of the first multiplex transistor and the active layer T20 of the second multiplex transistor of the first multiplex unit, the active layer T30 of the third multiplex transistor and the active layer T40 of the fourth multiplex transistor of the second multiplex unit, as well as the active layer T50 of the fifth multiplex transistor and the active layer T60 of the sixth multiplex transistor of the third multiplex unit on the substrate can be essentially the same, for example, essentially rectangular with the same dimensions.

[0158] In some examples, such as in Fig. As shown in Figure 19, the active layer T10 of the first multiplex transistor, the active layer T50 of the fifth multiplex transistor, and the active layer T40 of the fourth multiplex transistor can be aligned along a first direction X. The active layer T30 of the third multiplex transistor, the active layer T20 of the second multiplex transistor, and the active layer T60 of the sixth multiplex transistor can be aligned along the first direction X. The active layer T10 of the first multiplex transistor and the active layer T30 of the third multiplex transistor can be arranged sequentially along the second direction Y and offset from each other in the second direction Y. The active layer T50 of the fifth multiplex transistor and the active layer T20 of the second multiplex transistor can be arranged sequentially along the second direction Y and offset from each other in the second direction Y.The active layer T40 of the fourth multiplex transistor and the active layer T60 of the sixth multiplex transistor can be arranged sequentially along the second direction Y and offset from each other in the second direction Y.

[0159] Fig. Figure 20A shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 18. Fig. 20B is a schematic top view of the first conductive layer in Fig. 20A. In some examples, as in Fig. 20A and Fig. As shown in Figure 20B, the first conductive layer in the first frame area can comprise at least: gates of several multiplex transistors of several multiplex units of the multiplex circuit (e.g., comprising the gate T13 of the first multiplex transistor T1, the gate T23 of the second multiplex transistor T2, the gate T33 of the third multiplex transistor T3, the gate T43 of the fourth multiplex transistor T4, the gate T53 of the fifth multiplex transistor T5, and the gate T63 of the sixth multiplex transistor T6); several data leak lines (e.g., comprising the second data leak line 252, the fourth data leak line 254, and the sixth data leak line 256); and a second multiplex data line 42.

[0160] In some examples, such as in the Fig. 20A and Fig. As shown in Figure 20B, the gate T13 of the first multiplex transistor T1 and the gate T33 of the third multiplex transistor T3 can form an interconnected integral structure. This integral structure of gate T13 of the first multiplex transistor T1 and gate T33 of the third multiplex transistor T3 can essentially be slot-shaped. Similarly, the gate T43 of the fourth multiplex transistor T4 and the gate T63 of the sixth multiplex transistor T6 can form an interconnected integral structure. This integral structure of gate T43 of the fourth multiplex transistor T4 and gate T63 of the sixth multiplex transistor T6 can essentially be slot-shaped.

[0161] In some examples, the second data leak line 252, the fourth data leak line 254, and the sixth data leak line 256 can have essentially zigzag shapes extending along the second direction Y. The second data leak line 252 can be located between the active layer T10 of the first multiplex transistor T1 and the active layer T50 of the fifth multiplex transistor T5. One end of the second data leak line 252 can be located between the active layer T10 of the first multiplex transistor and the active layer T30 of the third multiplex transistor. The fourth data leak line 254 can be located between the active layer T40 of the fourth multiplex transistor T4 and the active layer T50 of the fifth multiplex transistor T5.One end of the fourth data line 254 can be located between the active layer of the fifth multiplex transistor T5 and the active layer T20 of the second multiplex transistor T2. The sixth data line 256 can be located on the side of the active layer T40 of the fourth multiplex transistor T4 opposite the fourth data line 254. One end of the sixth data line 256 can be located between the active layer T40 of the fourth multiplex transistor T4 and the active layer T60 of the sixth multiplex transistor T6.

[0162] In some examples, the second multiplex data line 42 can essentially have a zigzag shape extending along the second direction Y. The first connection end of the second multiplex data line 42 can be located on one side of the active layer T30 of the third multiplex transistor in the second direction Y, and the second connection end of the second multiplex data line 42 can extend towards the bending region.

[0163] Fig. Figure 21A shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 18. Fig. Figure 21B shows a schematic top view of the second conductive layer in Fig. 21A. In some examples, as in Fig. 21A and Fig. As shown in Figure 21B, the second conductive layer in the first frame area can comprise at least: several data leak lines (e.g., comprising the first data leak line 251, the third data leak line 253, and the fifth data leak line 255), a first multiplex data line 41, a third multiplex data line 43, a first multiplex interconnect line 261, a second multiplex interconnect line 262, and a third multiplex interconnect line 263.

[0164] In some examples, such as in Fig. 21A and Fig. As shown in Figure 21B, the first data leak line 251, the second data leak line 252, the third data leak line 253, the fourth data leak line 254, the fifth data leak line 255, and the sixth data leak line 256 can be arranged sequentially along the first direction X. The orthographic projections of the first data leak line 251, the second data leak line 252, the third data leak line 253, the fourth data leak line 254, the fifth data leak line 255, and the sixth data leak line 256 on the substrate cannot overlap. The first data leak line 251, the third data leak line 253, and the fifth data leak line 255 can be located on one side of the first row of multiplex transistors in the opposite direction to the second direction Y.The multiple data leak lines in this example can be arranged alternately on the first conductive layer and the second conductive layer, thereby reducing the distance between adjacent data leak lines and thus the space occupied by the conductor tracks, which facilitates a narrowing of the frame.

[0165] In some examples, the first multiplex data line 41 can essentially have a zigzag shape extending along the second direction Y. The first multiplex data line 41 can be located on the side of the active layer T30 of the third multiplex transistor T3 facing away from the third multiplex connection line 263. The first connection end of the first multiplex data line 41 can be located on one side of the active layer T10 of the first multiplex transistor T1 in the second direction Y and adjacent to the gate T13 of the first multiplex transistor T1. The second connection end of the first multiplex data line 41 can be aligned with the second connection end of the second multiplex data line 42 in the first direction X.

[0166] In some examples, the third multiplex data line 43 can essentially have a zigzag shape extending along the second direction Y. The first connection end of the third multiplex data line 43 can be located on one side of the active layer T60 of the sixth multiplex transistor in the second direction Y and adjacent to the gate T63 of the sixth multiplex transistor. The second connection end of the third multiplex data line 43 can be aligned with the second connection end of the first multiplex data line 41 and the second connection end of the second multiplex data line 42 in the first direction X.

[0167] In some examples, the first multiplex connection line 261 can essentially have a zigzag shape extending along the second direction Y. The first connection end of the first multiplex connection line 261 can be located on one side of the active layer T20 of the second multiplex transistor in the second direction Y, and the second connection end of the first multiplex connection line 261 can be adjacent to the gate T23 of the second multiplex transistor.

[0168] In some examples, the second multiplex connection line 262 can essentially have a straight shape extending along the second direction Y. The second multiplex connection line 262 can be located between the active layer T20 of the second multiplex transistor and the gate T43 of the fourth multiplex transistor. The first connection end of the second multiplex connection line 262 can be located between the fourth data line 254 and the gate T43 of the fourth multiplex transistor, and the second connection end of the second multiplex connection line 262 can be located on one side of the second connection end of the first multiplex connection line 261 in the second direction Y.

[0169] In some examples, the third multiplex connection line 263 can essentially have a zigzag shape extending along the second direction Y. The third multiplex connection line 263 can be located between the active layer T30 of the third multiplex transistor and the gate T53 of the fifth multiplex transistor. The first connection end of the third multiplex connection line 263 can be located between the second data line 252 and the gate T53 of the fifth multiplex transistor, and the second connection end of the third multiplex connection line 263 can be located on one side of the second connection end of the second multiplex connection line 262 in the second direction Y.

[0170] Fig. Figure 22 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 18. In some examples, such as in Fig. As shown in Figure 22, the third insulating layer in the first frame area can be provided with several vias, which may include, for example: the fifty-first via V51 to the sixty-second via V62, the sixty-third via V63 to the seventy-fifth via V75 and the seventy-sixth via V76 to the ninetieth via V90.

[0171] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the fifty-first via V51 to the sixty-second via V62 can be removed to expose a portion of the semiconductor layer's surface. The third insulating layer and the second insulating layer within the sixty-third via V63 to the seventy-fifth via V75 can be removed to expose a portion of the first conductive layer's surface. The third insulating layer within the seventy-sixth via V76 to the ninetieth via V90 can be removed, exposing a portion of the second conductive layer.

[0172] Fig. Figure 23A shows a schematic representation of the display panel after the formation of the third conductive layer in Fig. 18. Fig. Figure 23B shows a schematic top view of the third conductive layer in Fig. 23A. In some examples, as in Fig. 23A and Fig. As shown in Figure 23B, the third conductive layer in the first frame area can comprise at least: several interconnecting electrodes (e.g., comprising the twenty-first interconnecting electrode 321 to the thirty-fifth interconnecting electrode 335), several multiplex interconnecting electrodes (e.g., comprising the fourth multiplex interconnecting electrode 354, the fifth multiplex interconnecting electrode 355, and the sixth multiplex interconnecting electrode 356), several deflection leads (e.g., comprising the fourth deflection lead 364, the fifth deflection lead 365, and the sixth deflection lead 366).

[0173] In some examples, the twenty-first interconnect electrode 321 can essentially be a strip-shaped structure extending along the second direction Y. The twenty-first interconnect electrode 321 can be electrically connected to the first active layer T10 of the first multiplex transistor via four vertically arranged fifty-first vias V51 and can also be electrically connected to the first multiplex data line 43 via two vertically arranged eighty-sixth vias V86.

[0174] In some examples, the twenty-second interconnect electrode 322 can essentially have a zigzag shape extending along the second direction Y. The twenty-second interconnect electrode 322 can be electrically connected to the second region of the active layer T10 of the first multiplex transistor via four vertically arranged fifty-second vias V52, and can also be electrically connected to the first data trace 251 via two vertically arranged eighty-third vias V83.

[0175] In some examples, the twenty-third interconnect electrode 323 can essentially be a strip-shaped structure extending along the second direction Y. The twenty-third interconnect electrode 323 can be electrically connected to the first active layer T50 of the fifth multiplex transistor via four vertically arranged fifty-third vias V53, and can also be electrically connected to the third multiplex interconnect 263 via two vertically arranged eighty-seventh vias V87.

[0176] In some examples, the twenty-fourth interconnect electrode 324 can have an essentially zigzag shape extending along the second direction Y. The twenty-fourth interconnect electrode 324 can be electrically connected to the second active layer T50 of the fifth multiplex transistor via four vertically arranged fifty-fourth vias V54, and can also be electrically connected to the third data trace 253 via two vertically arranged eighty-fourth vias V84.

[0177] In some examples, the twenty-fifth interconnect electrode 325 can essentially be a strip-shaped structure extending along the second direction Y. The twenty-fifth interconnect electrode 325 can be electrically connected to the first active layer T40 of the fourth multiplex transistor via four vertically arranged fifty-fifth vias V55 and can also be electrically connected to the second multiplex interconnect 262 via two vertically arranged eighty-eighth vias V88.

[0178] In some examples, the twenty-sixth interconnect electrode 326 can essentially have a zigzag shape extending along the second direction Y. The twenty-sixth interconnect electrode 326 can be electrically connected to the second active layer T40 of the fourth multiplex transistor via four vertically arranged fifty-sixth vias V56, and can also be electrically connected to the fifth data trace 255 via two vertically arranged eighty-fifth vias V85.

[0179] In some examples, the twenty-seventh interconnect electrode 327 can essentially have a zigzag shape extending along the second direction Y. The twenty-seventh interconnect electrode 327 can be electrically connected to the first active layer T30 of the third multiplex transistor via four vertically arranged fifty-seventh vias V57 and can also be electrically connected to the second data trace 252 via two vertically arranged sixty-sixth vias V66.

[0180] In some examples, the twenty-eighth interconnect electrode 328 can essentially be a strip-shaped structure extending along the second direction Y. The twenty-eighth interconnect electrode 328 can be electrically connected to the second active layer T30 of the third multiplex transistor via four vertically arranged fifty-eighth vias V58, and can also be electrically connected to the second multiplex data line 42 via two vertically arranged seventieth vias V70.

[0181] In some examples, the twenty-ninth interconnect electrode 329 can essentially have a zigzag shape extending along the second direction Y. The twenty-ninth interconnect electrode 329 can be electrically connected to the first active layer T20 of the second multiplex transistor via four vertically arranged fifty-ninth vias V59 and can also be electrically connected to the fourth data trace 254 via two vertically arranged sixty-seventh vias V67.

[0182] In some examples, the thirtieth interconnect electrode 330 can essentially be a strip-shaped structure extending along the second direction Y. The thirtieth interconnect electrode 330 can be electrically connected to the second region of the active layer T20 of the second multiplex transistor via four vertically arranged sixty-fold vias V60 and can also be electrically connected to the first multiplex interconnect line 261 via two vertically arranged eightieth-fold vias V80.

[0183] In some examples, the thirty-first interconnect electrode 331 can essentially have a zigzag shape extending along the second direction Y. The thirty-first interconnect electrode 331 can be electrically connected to the first active layer T60 of the sixth multiplex transistor via four vertically arranged sixty-first vias V61 and can also be electrically connected to the sixth data line 256 via two vertically arranged sixty-eighth vias V68.

[0184] In some examples, the thirty-second interconnect electrode 332 can essentially be a strip-shaped structure extending along the second direction Y. The thirty-second interconnect electrode 332 can be electrically connected to the second active layer T60 of the sixth multiplex transistor via four vertically arranged sixty-second vias V62, and can also be electrically connected to the third multiplex data line 43 via two vertically arranged seventy-ninth vias V79.

[0185] In some examples, the thirty-third connection electrode 333 can be electrically connected to the second data line 252 via two vertically arranged sixty-third vias V63. The thirty-fourth connection electrode 334 can be electrically connected to the fourth data line 254 via two vertically arranged sixty-fourth vias V64. The thirty-fifth connection electrode 335 can be electrically connected to the sixth data line 256 via two vertically arranged sixty-fifth vias V65. In this example, the uniformity of the openings can be ensured by the formation of the sixty-third, sixty-fourth, and sixty-fifth vias.By forming the thirty-third connecting electrode, the thirty-fourth connecting electrode, and the thirty-fifth connecting electrode, the uniformity of the resistance of the multiple data feed lines can be ensured to guarantee the consistency of the signal transmission.

[0186] In some examples, the first multiplex control line 51 and the second multiplex control line 52 can have at least straight shapes extending along the first direction X. The second multiplex control line 52 can be located on one side of the first multiplex control line 51 in the second direction Y. The first multiplex control line 51 can be located on the same side of the twenty-eighth connection electrode 328, the thirtieth connection electrode 330, and the thirty-second connection electrode 332 in the second direction Y.

[0187] In some examples, the fourth multiplex connection electrode 354, the fifth multiplex connection electrode 355, and the sixth multiplex connection electrode 356 can be located on one side of the second multiplex control line 52 in the second direction Y. The fourth multiplex connection electrode 354, the fifth multiplex connection electrode 355, and the sixth multiplex connection electrode 356 can essentially be strip-shaped structures extending along the first direction X. The fifth multiplex connection electrode 355 can be located on one side of the fourth multiplex connection electrode 354 in the second direction Y, and the sixth multiplex connection electrode 356 can be located on one side of the fifth multiplex connection electrode 355 in the second direction Y.

[0188] In some examples, the fourth deflection line 364, the fifth deflection line 365, and the sixth deflection line 366 can be strip-shaped structures extending along the second direction Y. The fourth deflection line 364, the fifth deflection line 365, and the sixth deflection line 366 can be arranged sequentially along the first direction X. The fourth deflection line 364, the fifth deflection line 365, and the sixth deflection line 366 can be located on one side of the sixth multiplex connection electrode 356 in the second direction Y.

[0189] In some examples, the first multiplex control line 51 can be electrically connected to the integral structure of gate T13 of the first multiplex transistor and gate T33 of the third multiplex transistor via three horizontally arranged sixty-ninth vias V69, and can also be electrically connected to gate T53 of the fifth multiplex transistor via two horizontally arranged seventy-first vias V71. The second multiplex control line 52 can be electrically connected to gate T23 of the second multiplex transistor via two horizontally arranged seventy-second vias V72, and can also be electrically connected to the integral structure of gate T43 of the fourth multiplex transistor and gate T63 of the sixth multiplex transistor via three horizontally arranged seventy-third vias V73.

[0190] In some examples, the fourth multiplex interconnect electrode 354 can be electrically connected to the first multiplex data line 41 via two horizontally arranged eighty-ninth vias V89 and can also be electrically connected to the first multiplex interconnect line 261 via two horizontally arranged eighty-first vias V81. The fifth multiplex interconnect electrode 355 can be electrically connected to the second multiplex data line 42 via two horizontally arranged seventy-fourth vias V74 and can also be electrically connected to the second multiplex interconnect line 262 via two horizontally arranged eighty-second vias V82.The sixth multiplex connection electrode 356 can be electrically connected to the third multiplex connection line 263 via two horizontally arranged ninetieth vias V90 and can also be electrically connected to the third multiplex data line 43 via two horizontally arranged seventy-eighth vias V78.

[0191] In some examples, the fourth deflection line 364 can be electrically connected to the first multiplex data line 41 via several array-like arranged seventy-sixth vias V76. The fifth deflection line 365 can be electrically connected to the second multiplex data line 42 via several array-like arranged seventy-fifth vias V75. The sixth deflection line 366 can be electrically connected to the third multiplex data line 43 via several array-like arranged seventy-seventh vias V77.

[0192] Fig. Figure 24 shows a schematic representation of the display panel after the formation of the fifth insulating layer in Fig. 18. In some examples, such as in Fig. As shown in Figure 24, the fourth insulating layer and the fifth insulating layer in the first frame area can be provided with multiple vias, which can, for example, include the ninety-first via V91 to the ninety-third via V93. The fifth insulating layer and the fourth insulating layer within the ninety-first via V91 to the ninety-third via V93 can be removed, thereby exposing part of the surface of the third conductive layer.

[0193] In some examples, such as in Fig. As shown in Figure 18, the fourth conductive layer in the first frame region can comprise at least several data bend connections (e.g., comprising a first data bend connection 401, a second data bend connection 402, and a third data bend connection 403). The multiple data bend connections can extend along the second direction Y and be arranged sequentially along the first direction X. The first data bend connection 401 can be electrically connected to the fourth bend connection 364 via two vertically arranged ninety-first vias V91. The second data bend connection 402 can be electrically connected to the fifth bend connection 365 via two vertically arranged ninety-second vias V92.The third data bending connection line 403 can be electrically connected to the sixth deflection line 366 via two vertically arranged ninety-third vias V93.

[0194] In this example, arranging the multiplex transistors of the multiplex circuit in two rows reduces the space occupied by the multiplex circuit in the second direction, thus compressing the space required for the multiplex circuit. The manufacturing process of the display panel in this example can be found in the descriptions of the previous embodiments, which will not be discussed in detail here.

[0195] In other examples, the multiplex transistors of the multiplex units can be arranged in a row and sequentially along the first direction, provided there is sufficient space in the first frame area.

[0196] In other examples, the multiplex transistors of the multiplexing units can be arranged in four or more rows if the dimension of the first frame area of ​​the display panel is relatively narrow in the first direction and relatively large in the second direction. For example, the multiplex transistors of the multiplexing circuit can be arranged in six rows, with the first through sixth multiplex transistors arranged sequentially along the second direction, including several first multiplex transistors in a row, several second multiplex transistors in a row, several third multiplex transistors in a row, several fourth multiplex transistors in a row, several fifth multiplex transistors in a row, and several sixth multiplex transistors in a row. However, this is not limited by this embodiment.

[0197] Fig. Figure 25 is another equivalent circuit diagram of a multiplex circuit according to at least one embodiment of the present disclosure. In some examples, as in Fig. As shown in Figure 25, the multiplex circuit 30 can comprise several multiplex units 34. A multiplex unit 34 can be configured to supply a data signal provided by a multiplex data line to multiple data lines (e.g., three data lines).

[0198] In some examples, such as in Fig. As shown in Figure 25, a multiplex unit 34 can be electrically connected to three multiplex control lines (e.g., comprising the third multiplex control line 53, the fourth multiplex control line 54, and the fifth multiplex control line 55), one multiplex data line, and multiple data lines (e.g., three data lines). Each multiplex unit 34 can comprise three multiplex transistors. The three data lines to which a multiplex unit 34 is connected can be electrically connected to subpixels that emit light of different colors. The way the multiplex units are connected in this example can effectively conserve the required data signals.

[0199] In Fig. Section 25 illustrates this using the example of four multiplex units in the multiplex circuit. The connection method for each multiplex unit is similar and is illustrated using the example of one multiplex unit. In some examples, as in Fig. As shown in Figure 25, the multiplexing unit 34 can comprise a seventh multiplex transistor T7, an eighth multiplex transistor T8, and a ninth multiplex transistor T9. The gate of the seventh multiplex transistor T7 is electrically connected to the third multiplex control line 53, the first electrode of the seventh multiplex transistor T7 is electrically connected to a multiplex data line (e.g., the fourth multiplex data line 44), and the second electrode of the seventh multiplex transistor T7 is electrically connected to the first data line. The first data line can be electrically connected to a column of the first subpixel R1.The gate of the eighth multiplex transistor T8 is electrically connected to the fourth multiplex control line 54, the first electrode of the eighth multiplex transistor T8 is electrically connected to the fourth multiplex data line 44, and the second electrode of the eighth multiplex transistor T8 is electrically connected to the second data line. The second data line can be electrically connected to a column of the second subpixel G1. The gate of the ninth multiplex transistor T9 is electrically connected to the fifth multiplex control line 55, the first electrode of the ninth multiplex transistor T9 is electrically connected to the fourth multiplex data line 44, and the second electrode of the ninth multiplex transistor T9 is electrically connected to the third data line. The third data line can be electrically connected to a column of the third subpixel B1.A column of first subpixel R1, a column of second subpixel G1, and a column of third subpixel B1 can be configured to emit light of different colors. For example, a column of first subpixel R1 can emit red light, a column of second subpixel G1 can emit green light, and a column of third subpixel B1 can emit blue light.

[0200] In this example, the data signals received by three adjacent subpixels emitting light of different colors can be controlled by one and the same multiplexing unit. The 1:3 design (i.e., a design in which one multiplexed data line supplies three data lines with data signals) can help meet the requirements for a high refresh rate.

[0201] Fig. Figure 26 shows a schematic partial top view of a multiplex circuit according to at least one embodiment of the present disclosure. Fig. Figure 26 illustrates this using the example of the palatal structure of three multiplex units. The following describes it using the example of the palatal structure of a single multiplex unit 34. In this example, the first connection end of the conductor track is located closer to the display area, and the second connection end is located farther away from the display area.

[0202] In some examples, such as in Fig. As shown in Figure 26, several multiplex units 34 can be arranged sequentially along the first direction X. The three multiplex transistors comprising each multiplex unit 34 can be arranged along the second direction Y. The multiplex transistors of the multiplex circuit in this example can be arranged in three rows. Several seventh multiplex transistors T7 can be arranged in a row, several eighth multiplex transistors T8 can be arranged in a row, and several ninth multiplex transistors T9 can be arranged in a row. A column of multiplex transistors can comprise the seventh multiplex transistor T7, the eighth multiplex transistor T8, and the ninth multiplex transistor T9, arranged sequentially in the second direction Y.

[0203] In some examples, such as in Fig. As shown in Figure 26, the first frame area can comprise at least the following in a direction perpendicular to the display panel: a substrate as well as a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer arranged on the substrate.

[0204] Fig. Figure 27 shows a schematic representation of the display panel after the formation of the semiconductor layer in Fig. 26. In some examples, such as in Fig. As shown in Figure 27, the semiconductor layer in the first frame area can include at least active layers of several multiplex transistors of several multiplex units of the multiplex circuit, such as the active layers T70 of the seventh multiplex transistors, the active layers T80 of the eighth multiplex transistors and the active layers T90 of the ninth multiplex transistors.

[0205] In some examples, the shapes and dimensions of the orthographic projections of the active layers T70 of the seventh multiplex transistors, the active layers T80 of the eighth multiplex transistors, and the active layers T90 of the ninth multiplex transistors on the substrate may be essentially the same, for example, essentially rectangular with the same dimensions.

[0206] In some examples, the active layer T70 of the seventh multiplex transistor has a seventh centerline O7, the active layer T80 of the eighth multiplex transistor has an eighth centerline O8, and the active layer T90 of the ninth multiplex transistor has a ninth centerline O9. The seventh centerline O7, the eighth centerline O8, and the ninth centerline O9 all run parallel to the second direction Y. The eighth centerline O8 of the active layer T80 of the eighth multiplex transistor can be located on one side of the ninth centerline O9 of the active layer T90 of the ninth multiplex transistor in the first direction X, and the seventh centerline O7 of the active layer T70 of the seventh multiplex transistor can be located on one side of the eighth centerline O8 of the active layer T80 of the eighth multiplex transistor in the first direction X.In the first direction X, the distance between the eighth centerline O8 and the ninth centerline O9 can be greater than the distance between the eighth centerline O8 and the seventh centerline O7. However, this is not restricted by this embodiment.

[0207] Fig. Figure 28A shows a schematic representation of the display panel after the formation of the first conductive layer in Fig. 26. Fig. Figure 28B shows a schematic top view of the first conductive layer in Fig. 28A. In some examples, as in Fig. 28A and Fig. As shown in Figure 28B, the first conductive layer in the first frame area can include at least: gates of several multiplex transistors of the multiplex circuit (for example, including the gate T73 of the seventh multiplex transistor T7, the gate T83 of the eighth multiplex transistor T8, and the gate T93 of the ninth multiplex transistor T9), several data leak lines (for example, including the first data leak line 251 and the third data leak line 253), and several conductive interconnect blocks (for example, including the first conductive interconnect block 271, the second conductive interconnect block 272, and the fourth conductive interconnect block 274).

[0208] In some examples, the gate T93 of the ninth multiplex transistor T9, the gate T83 of the eighth multiplex transistor T8 and the gate T73 of the seventh multiplex transistor T7 can be arranged sequentially along the first direction X, and their lengths in the second direction Y can gradually decrease.

[0209] In some examples, the first data leak line 251 and the third data leak line 253 may be located on one side of the active layer T70 of the seventh multiplex transistor in the opposite direction to the second direction Y. The first conductive link block 271, the second conductive link block 272, and the fourth conductive link block 274 may be located on one side of the active layer T90 of the ninth multiplex transistor in the second direction Y. The first conductive link block 271 is aligned with one end of the gate T93 of the ninth multiplex transistor in the second direction Y, and the second conductive link block 272 is aligned with one end of the gate T83 of the eighth multiplex transistor in the second direction Y. The fourth conductive link block 274 may be located between the gate T93 of the ninth multiplex transistor and the second conductive link block 272.

[0210] Fig. Figure 29A shows a schematic representation of the display panel after the formation of the second conductive layer in Fig. 26. Fig. Figure 29B shows a schematic top view of the second conductive layer in Fig. 29A. In some examples, as in Fig. 29A and Fig. As shown in Figure 29B, the second conductive layer in the first frame area can comprise at least: several data leak lines (e.g., comprising the second data leak line 252), several conductive interconnect blocks (e.g., comprising the third conductive interconnect block 273), and one multiplex data line (e.g., the fourth multiplex data line 44).

[0211] In some examples, the second data leak line 252 may be located between the first data leak line 251 and the third data leak line 253. The third conductive link block 273 may be located on one side of the gate T73 of the seventh multiplex transistor in the second direction Y and aligned with one end of the gate T73 of the seventh multiplex transistor in the second direction Y. The fourth multiplex data line 44 may be located on one side of the fourth conductive link block 274 in the second direction Y and aligned with the fourth conductive link block 274 in the second direction Y.

[0212] Fig. Figure 30 shows a schematic representation of the display panel after the formation of the third insulating layer in Fig. 26. In some examples, such as in Fig. As shown in Figure 30, the third insulating layer in the first frame area can be provided with several vias, which may include, for example: the one hundredth via V101 to the one hundred and sixth via V106, the one hundred and seventh via V107 to the one hundred and sixteenth via V116, the one hundred and twenty-first via V121 to the one hundred and twenty-fourth via V124.

[0213] In some cases, for example, the third insulating layer, the second insulating layer, and the first insulating layer within the hundredth via V101 to the hundred and sixth via V106 can be removed to expose part of the surface of the semiconductor layer; the third insulating layer and the second insulating layer within the hundred and seventh via V107 to the hundred and sixteenth via V116 can be removed to expose part of the surface of the first conductive layer; and the third insulating layer within the hundred and twenty-first via V121 to the hundred and twenty-fourth via V124 can be removed to expose part of the surface of the second conductive layer.

[0214] Fig. Figure 31 shows a schematic top view of the third conductive layer in Fig. 26. In some examples, such as in Fig. 26 and Fig. As shown in Figure 31, the third conductive layer in the first frame area can comprise at least: several interconnecting electrodes (e.g., comprising the forty-first interconnecting electrode 341 to the forty-seventh interconnecting electrode 347), a third multiplex control line 53, a fourth multiplex control line 54, and a fifth multiplex control line 55.

[0215] In some examples, the forty-first connecting electrode 341 can essentially have a zigzag shape extending along the second direction Y.The forty-first connecting electrode 341 can be connected to the first region of the active layer T70 of the seventh multiplex transistor via four vertically arranged one hundredth vias V101, and can also be connected to the first region of the active layer T80 of the eighth multiplex transistor via four vertically arranged one hundredth vias V104, and can also be connected to the first region of the active layer T90 of the ninth multiplex transistor via four vertically arranged one hundred and sixth vias V106, and can also be electrically connected to the fourth conductive connecting block 274 via two vertically arranged one hundred and eleventh vias V111, and can also be electrically connected to the fourth multiplex data line 44 via two vertically arranged one hundred and twenty-second vias V122.

[0216] In some examples, the forty-second interconnect electrode 342 can essentially be a strip-shaped structure extending along the second direction Y. The forty-second interconnect electrode 342 can be connected to the second active layer T70 of the seventh multiplex transistor via four vertically arranged 102 vias V102 and can also be electrically connected to the third data line 253 via two vertically arranged 108 vias V108.

[0217] In some examples, the forty-third interconnect electrode 343 can essentially have a zigzag shape extending along the second direction Y. The forty-third interconnect electrode 343 can be connected to the second active layer T80 of the eighth multiplex transistor via four vertically arranged one hundred-third vias V103 and can also be electrically connected to the second data trace 252 via two horizontally arranged one hundred and twenty-first vias V121.

[0218] In some examples, the forty-fourth interconnect electrode 344 can essentially have a straight shape extending along the second direction Y. The forty-fourth interconnect electrode 344 can be connected to the second active layer T90 of the ninth multiplex transistor via four vertically arranged 154 vias V105 and can also be electrically connected to the first data line 251 via two horizontally arranged 107 vias V107.

[0219] In some examples, the forty-fifth interconnect electrode 345 can generally be a strip-shaped structure extending along the second direction Y. The forty-fifth interconnect electrode 345 can be electrically connected to the gate T93 of the ninth multiplex transistor via two vertically arranged 109th vias V109 and can also be electrically connected to the first conductive interconnect block 271 via two vertically arranged 110th vias V110.

[0220] In some examples, the forty-sixth interconnect electrode 346 can essentially have a strip-shaped structure extending along the second direction Y. The forty-sixth interconnect electrode 346 can be electrically connected to the gate T83 of the eighth multiplex transistor via two vertically arranged one hundred and twelfth vias V112 and can also be electrically connected to the second conductive interconnect block 272 via two vertically arranged one hundred and thirteenth vias V113.

[0221] In some examples, the forty-seventh interconnect electrode 347 has a strip-like structure extending along the second direction Y. The forty-seventh interconnect electrode 347 can be electrically connected to the gate T73 of the seventh multiplex transistor via two vertically arranged one hundred and sixteenth vias V116 and can also be electrically connected to the third conductive interconnect block 273 via two vertically arranged one hundred and twenty-third vias V123.

[0222] In some examples, the third multiplex control line 53, the fourth multiplex control line 54, and the fifth multiplex control line 55 can have at least straight shapes extending along the first direction X. The fourth multiplex control line 54 can be located on one side of the fifth multiplex control line 55 in the second direction Y, and the third multiplex control line 53 can be located on one side of the fourth multiplex control line 54 in the second direction Y. The fifth multiplex control line 55 can be located on one side of the forty-seventh connecting electrode 347 in the second direction Y.

[0223] In some examples, the fifth multiplex control line 55 can be electrically connected to the first conductive link block 271 via two horizontally arranged 114 vias V114 to establish an electrical connection to the gate T93 of the ninth multiplex transistor. The fourth multiplex control line 54 can be electrically connected to the second conductive link block 272 via two horizontally arranged 115 vias V115 to establish an electrical connection to the gate T83 of the eighth multiplex transistor. The third multiplex control line 53 can be electrically connected to the third conductive link block 273 via two horizontally arranged 124 vias V124 to establish an electrical connection to the gate T73 of the seventh multiplex transistor.

[0224] In some examples, the fourth multiplex data line 44 can extend in the direction of the bending area and be electrically connected to the data bending connection line in the bending area.

[0225] In this example, the three multiplex transistors, electrically connected via the same multiplex data line, are arranged in a row and offset from each other in the second direction. The gates of the three multiplex transistors are connected to different multiplex control lines. This arrangement of the multiplex transistors in this example can reduce the required space in both the horizontal and vertical directions, increase space utilization, and is suitable for display panels with a relatively narrow first frame area. In combination with the 1:3 design of the multiplex circuit, the requirements for the high refresh rate of the display panel can also be met. The manufacturing process of the display panel in this example is described in the preceding embodiment and will not be discussed again here.

[0226] This embodiment further provides a display panel comprising a substrate, multiple subpixels, multiple data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. Within the display area are multiple subpixels and multiple data lines. The multiple data lines are connected to the multiple subpixels and configured to provide data signals to the multiple subpixels. The multiplexing circuit is located within the first frame area and comprises multiple multiplexing units, with at least one of the multiple multiplexing units comprising multiple multiplexing transistors.The at least one multiplexing unit is electrically connected to a multiplexing data line, multiplexing control lines, and several data lines, and is configured to provide the data signals transmitted by the multiplexing data line to the multiple data lines under the control of the multiplexing control lines, where a is an integer greater than 1 and less than or equal to 3. For example, a can be 2 or 3. The multiple multiplexing transistors of the at least one multiplexing unit are located in the same row or column, or in different rows. A row of multiplexing transistors comprises multiple multiplexing transistors arranged along a first direction, and a column of multiplexing transistors comprises multiple multiplexing transistors arranged along a second direction, the first direction intersecting the second direction.

[0227] In some examples, the multiple multiplex transistors of the at least one multiplex unit can be located in the same row, as in the example in Fig. 5. In other examples, the multiple multiplex transistors of the at least one multiplex unit can be located in the same column, as for example in the embodiment shown in Fig. 26. In other examples, the multiple multiplex transistors of the at least one multiplex unit can be located in different rows, as for example in the one shown in Fig. 18 illustrated embodiment.

[0228] In some exemplary embodiments, a column of multiplex transistors comprises: several multiplex transistors connected to the same multiplex control line; or several multiplex transistors connected to the same multiplex data line.

[0229] Regarding the relevant description of the display panel of this embodiment, reference can be made to the description of the previous embodiments, which will not be discussed again here.

[0230] Fig. Figure 32 shows a schematic representation of a display device according to at least one embodiment of the present disclosure. As in Fig.As shown in Figure 32, this embodiment provides a display device 91 with a display panel 910 from the previous embodiments. In some examples, the display panel 910 can be an OLED display panel, for example, an OLED display panel with an integrated touch structure. The display device 91 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop, a digital picture frame, or a navigation device, etc., or it can be a product or component with touch and display functions.

[0231] In some examples, the display device 91 may be a portable display device, e.g., one that can be worn on the human body in a certain way. For example, the display device 91 may be a smartwatch, a smart bracelet, etc. However, this is not limited by this embodiment.

[0232] The drawings in this disclosure relate only to the structures covered by the disclosure. For other structures, reference may be made to the usual design. Provided there is no conflict, the embodiments of the disclosure, i.e., the features in the embodiments, may be combined to obtain new embodiments. Persons skilled in the field should understand that modifications or equivalent substitutions of the technical solutions of this disclosure may be made without departing from the spirit and scope of the technical solutions of this disclosure, and all shall fall within the scope of the claims of the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CH 202310612612.5

[0001]

Claims

[1] Display panel, including: a substrate comprising a display area and a first frame area located on at least one side of the display area; multiple subpixels and multiple data lines located in the display area, wherein the multiple data lines are connected to the multiple subpixels and are configured to provide data signals to the multiple subpixels; a multiplex circuit located in the first frame area and comprising several multiplex units; wherein at least one of the several multiplex units comprises several multiplex transistors, wherein the at least one multiplex unit is electrically connected to a multiplex data line, several multiplex control lines and several data lines and is configured to provide the data signals transmitted by the multiplex data line to the several data lines under the control of the several multiplex control lines; wherein the multiplex transistors of the multiple multiplex units are arranged in multiple rows and columns, wherein a row of multiplex transistors comprises several multiplex transistors arranged along a first direction and a column of multiplex transistors comprises several multiplex transistors arranged along a second direction; wherein the first direction intersects the second direction. [2] Display panel according to claim 1, wherein a column of multiplex transistors comprises several multiplex transistors connected to the same multiplex control line. [3] Display panel according to claim 1, wherein a column of multiplex transistors comprises several multiplex transistors connected to the same multiplex data line. [4] Display panel according to one of claims 1 to 3, wherein the multiplex transistors of the multiplex units are arranged in three rows. [5] Display panel according to claim 4, wherein the at least one multiplex unit comprises two multiplex transistors which are electrically connected to different multiplex control lines and electrically connected to the same multiplex data line; and wherein the two multiplex transistors of the at least one multiplex unit are arranged in the same row. [6] Display panel according to claim 5, wherein the multiple multiplex units comprise at least: multiple first multiplex units, multiple second multiplex units and multiple third multiplex units; wherein the multiplex transistors of the multiple first multiplex units are arranged in a first row, the multiplex transistors of the multiple second multiplex units are arranged in a second row and the multiplex transistors of the multiple third multiplex units are arranged in a third row; wherein the multiplex transistors of the first multiplex units, the second multiplex units and the third multiplex units, which are electrically connected to the same multiplex control line, are arranged in the same column. [7] Display panel according to claim 6, wherein the multiple subpixels comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color; wherein the first multiplex units are configured to provide data signals to several first subpixels, and the second multiplex units are configured to provide data signals to several second subpixels, and the third multiplex units are configured to provide data signals to several third subpixels. [8] Display panel according to claim 4, wherein the at least one multiplex unit comprises three multiplex transistors which are electrically connected to different multiplex control lines and electrically connected to the same multiplex data line; wherein the three multiplex transistors of the at least one multiplex unit are arranged in the same column. [9] Display panel according to claim 8, wherein the multiple subpixels comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color; wherein the three multiplex transistors of the at least one multiplex unit are configured to provide data signals to the first subpixel, the second subpixel and the third subpixel, respectively. [10] Display panel according to claim 9, wherein the three multiplex transistors of the at least one multiplex unit are a seventh multiplex transistor, an eighth multiplex transistor and a ninth multiplex transistor; wherein the seventh multiplex transistor, the eighth multiplex transistor and the ninth multiplex transistor, which are located in the same column, are arranged offset from each other in the second direction. [11] Display panel according to claim 10, wherein several of the seventh multiplex transistors are arranged in a first row, several of the eighth multiplex transistors are arranged in a second row and several of the ninth multiplex transistors are arranged in a third row, wherein the first row, the second row and the third row are arranged sequentially along a direction leading away from the display area. [12] Display panel according to one of claims 1 to 3, wherein the multiplex transistors of the multiplex units are arranged in two rows. [13] Display panel according to claim 12, wherein the at least one multiplex unit comprises two multiplex transistors, wherein the two multiplex transistors are each electrically connected to a first multiplex control line and a second multiplex control line and are electrically connected to the same multiplex data line; wherein the two multiplex transistors of the at least one multiplex unit are arranged in different rows and columns. [14] Display panel according to claim 13, wherein the multiplex transistors in the i-th column are all electrically connected to the first multiplex control line, the multiplex transistors in the i+1-th column are electrically connected to different multiplex control lines, and the multiplex transistors in the i+2-th column are all electrically connected to the second multiplex control line, wherein i is an integer greater than 0. [15] Display panel according to claim 13 or 14, wherein the multiple multiplex units comprise at least: multiple first multiplex units, multiple second multiplex units and multiple third multiplex units; wherein the multiple subpixels comprise: first subpixels emitting light of a first color, second subpixels emitting light of a second color, and third subpixels emitting light of a third color; wherein the first multiplex units are configured to provide data signals to multiple first subpixels, the second multiplex units are configured to provide data signals to multiple second subpixels, and the third multiplex units are configured to provide data signals to multiple third subpixels; where the two multiplex transistors of the first multiplex unit are located in the i-th column and the i+1-th column respectively; the two multiplex transistors of the second multiplex unit are located in the i-th column and the i+2-th column, respectively; and the two multiplex transistors of the third multiplex unit are located in the i+1th column and the i+2th column, respectively. [16] Display panel according to any one of claims 1 to 15, wherein the first frame area comprises at least: a first fan-out area and a bending area arranged successively along the direction leading away from the display area; wherein the multiplex circuitry is located in the first fan-out area; wherein the first fan-out area comprises: several data output lines and several multiplex data lines; wherein the bending area comprises at least several data bending connection lines; wherein the multiplex circuitry is electrically connected via the several data output lines to the several data lines in the display area and is electrically connected to the multiplex data lines, and the multiplex data lines are electrically connected to the data bending connection lines. [17] Display panel according to claim 16, wherein the first frame area comprises at least: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer arranged on the substrate; wherein the multiple multiplex data lines are arranged alternately in the first conductive layer and the second conductive layer; wherein the multiple data lines are arranged alternately in the first conductive layer and the second conductive layer. [18] Display panel according to claim 17, wherein the first frame area further comprises: a fourth conductive layer located on the side of the third conductive layer facing away from the substrate; wherein the multiple data bend connection lines are located in the fourth conductive layer. [19] Display device with the display panel according to any one of claims 1 to 18. [20] Display panel, including: a substrate comprising a display area and a first frame area located on at least one side of the display area; multiple subpixels and multiple data lines located in the display area, wherein the multiple data lines are connected to the multiple subpixels and are configured to provide data signals to the multiple subpixels; a multiplex circuit located in the first frame area and comprising several multiplex units; wherein at least one of the several multiplex units comprises several multiplex transistors, wherein the at least one multiplex unit is electrically connected to a multiplex data line, a multiplex control lines and several data lines and is configured to provide, under the control of the a multiplex control lines, the data signals transmitted by the multiplex data line to the several data lines, wherein a is an integer greater than 1 and less than or equal to 3; wherein the multiplex transistors of the at least one multiplex unit are located in the same row or in the same column or in different rows; wherein a row of multiplex transistors comprises multiple multiplex transistors arranged along a first direction, a column of multiplex transistors comprises multiple multiplex transistors arranged along a second direction, the first direction intersecting the second direction. [21] Display panel according to claim 20, wherein a column of multiplex transistors comprises: several multiplex transistors connected to the same multiplex control line; or several multiplex transistors connected to the same multiplex data line.

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