HIL test procedure and system for a protective device

Abstract

The present application discloses a hardware-in-the-loop (HIL) test method and system for a protective device in the technical field of load balancing of computer platforms, and it comprises the following: creating a simulation scenario within an HIL simulation test system; determining the minimum sampling signal required for the normal operation of the protective device under test based on the installation location of the protective device under test in the simulation scenario and creating a current transformer model capable of reproducing a transient saturation scenario; switching on the protective device under test and outputting an electrical signal through the HIL simulation test system;and simulating a fault scenario in the simulation scenario after receiving correct sample values ​​from the protective device, and determining, based on the current signal calculated by the model with the transient saturation properties and the logic check of the protective device, whether the tripping result corresponds to the set value and the tripping logic. The HIL test procedure for a protective device provided in the present application reproduces the actual current under non-ideal fault conditions and thoroughly tests the operating characteristics of the power plant's relay protection device.

Description

[0001] The present application claims priority from the Chinese patent application filed with the Chinese Patent Office on September 29, 2024, under application number 202411374008.4 and invention title “HIL testing method and system for a protective device”, the entire contents of which are incorporated into the present application by reference. Technical area

[0002] The present application relates to the technical field of load balancing of computer platforms and in particular to a hardware-in-the-loop (HIL) test method and system for a protective device. Background technology

[0003] In power plant calibration tests of protective devices, the RMS-based steady-state flow and pressure calibration method is relatively mature. However, if a system fault occurs, malfunctions or failures of the protective device can still occur because the device's adjustment margins and logic checks are insufficient. This is because the simulation of the effective value chain is inadequate to reflect the actual system situation. Due to the nonlinear transition characteristics caused by the inrush current problem of the transformer core and the transition saturation problem of the current transformer, it is difficult to simulate real fault scenarios in the tripping logic of the protective device when a quantity is added to verify the protective device of conventional relay protection instruments, leading to unreliable verification results.Raising the setting thresholds of the relay protection settings can mitigate this problem to some extent. However, excessively high imbalance limits reduce sensitivity, so a device test system was developed that utilizes hardware in the lab (HIL) and accounts for the nonlinear characteristics of transient saturation. This allows for thorough testing of the associated tripping logic and setting verification of the protection device, effectively ensuring the safety and reliability of the power plant protection system.

[0004] Hardware-in-the-loop (HIL) simulation is a new testing technology that utilizes the CPU+FPGA hardware architecture to reproduce system change processes in the microsecond or even nanosecond range. The peripheral interface device can be connected to the sampling unit of the protection device, and the entire process, from fault initiation and maintenance to fault resolution, can be simulated according to a predefined program. This architecture provides a robust testing platform, but the computer-based system modeling must be accurate enough to reflect the characteristics of real-world fault transients before simulation can begin.Among the most common types of failures in power plants are motor models, which are accepted by numerous software programs. However, components such as current transformers typically use ideal transformers, and only a precise characterization of the transformer's transfer characteristics can increase the actual effectiveness of testing. The JA (Jiles-Atherton) theory, a classical ferromagnetic theory, is used to describe the magnetization properties of ferromagnetic materials. It offers a very good explanation of phenomena and is easy to calculate. It can be used to model the transient saturation of current transformers. Content of the invention

[0005] In light of the aforementioned problems, this application has been prepared.

[0006] The technical problem solved by the present application is to enable the functional measurement and in-depth testing of relay protection devices in order to ensure the safe and stable operation of the power grid.

[0007] Existing methods for verifying flow and pressure of stationary protective devices based on RMS values ​​do not reflect the actual system fault conditions, leading to malfunctions or failures of the protective devices, and the challenge is to accurately reproduce transient saturation properties through simulation and to optimize the tripping logic of the protective device.

[0008] To solve the aforementioned technical problems, the present application offers the following technical solutions: a HIL test method for a protective device, comprising: Creating a simulation scenario within a HIL simulation test system; Determining the minimum sampling signal required for the normal operation of the protective device under test based on the installation location of the protective device under test in the simulation scenario and creating a current transformer model that is capable of reproducing a transient saturation scenario; Switching on the protective device to be tested and outputting an electrical signal by the HIL simulation test system; Simulating a fault scenario in the simulation scenario after receiving correct sample values ​​from the protective device, and determining, based on the current signal calculated by the model with the transient saturation properties and the logic check of the protective device, whether the tripping result corresponds to the set value and the tripping logic. As an optional solution to the HIL test procedure for a protective device described in the present application, the current transformer model includes a TP-class current transformer and a P-class current transformer. As an optional solution to the HIL test procedure for a protective device described in the present application, the saturation properties are not taken into account for the TP class current transformer. As an optional solution to the HIL test procedure for a protective device described in the present application, a JA transient saturation model is created for the P-class current transformer. As an optional solution to the HIL test procedure for a protective device described in the present application, the creation of the JA transient saturation model includes the following: initializing the model and creating the parameters of the P-class current transformer; Calculating the differential equation of the magnetic susceptibility as an essential parameter of the JA transient saturation model; Calculating the differential equation of the excitation current; and Continuous updating of the output current of the P-class converter with saturation characteristics on the secondary side based on the changing primary current.

[0009] As an optional solution to the HIL test method for a protective device described in the present application, the parameters of the P-class current transformer include the turns ratio, the equivalent iron core cross-section, the magnetic permeability in the vacuum state, the equivalent flux linkage length of the iron core, the resistance and leakage reactance of the current transformer secondary circuit, the initial excitation current value, and the initial magnetization intensity.

[0010] As an optional solution to the HIL test procedure for a protective device described in the present application, the following is provided: Connecting the current and voltage sampling channels of the protective device under test to the hardware of the HIL simulation test system and adjusting the analog output (AO) level of the physical hardware interface card of the HIL simulation test system;

[0011] Feeding the current signal calculated in the HIL simulation test system into the current sensing port of the protection device via a signal output and amplification;

[0012] Feeding the voltage signal calculated by the ideal voltage converter model in the HIL simulation test system into the voltage sensing terminal of the protection device via a signal output and amplification;

[0013] The trigger output signal of the protective device under test is fed back to the digital input (DI) channel of the physical interface card of the HIL simulation test system.

[0014] Another objective of the present application is to provide a HIP test system for a protective device that can solve the problem of inaccurate simulation of nonlinear transient properties caused by the inrush current of the transformer core and the transient saturation properties of current transformers during the existing verification process of the protective device by creating a HIL simulation test system based on JA transient saturation theory and thoroughly testing the operating properties of the protective device under complex fault scenarios.

[0015] To solve the aforementioned technical problems, the present application offers the following technical solution: a hardware-in-the-loop (HIL) test system for a protective device, comprising: a CPU and multi-FPGA simulation test host, a host computer, a power amplifier, a protective device under test, a signal cable, a control cable, and an Ethernet cable; wherein the CPU and multi-FPGA simulation test host is designed to generate current and voltage signals in simulation scenarios and to calculate fault scenarios using simulation algorithms; wherein the host computer is connected to the CPU and multi-FPGA simulation test host via the Ethernet cable and is designed to create the fault scenarios and monitor the simulation results; wherein the power amplifier amplifies the analog signals output by the simulation host to drive the input channels of the protective device under test;wherein the signal cable connects the power amplifier to the protective device under test and transmits current and voltage signals; wherein the control cable connects the protective device under test to the simulation test host and transmits input and output signals for monitoring the operating logic of the protective device; wherein the host computer adapts the fault scenario in real time and the simulation host outputs a signal to the protective device via the power amplifier for verification purposes, provided that the signal meets the requirements.

[0016] Computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the HIL test procedure described above for a protective device are performed.

[0017] A computer-readable storage medium on which a computer program is stored, and when the processor executes the computer program, the steps of the HIL test procedure described above for a protective device are performed.

[0018] Advantageous effects of the present application: The HIL test method for a protective device provided in the present application uses a realistic simulation of the JA saturation model of the current transformer to reproduce the actual current under non-ideal fault conditions and thoroughly tests the operating characteristics of the power plant's relay protection device. Furthermore, the method of the present application is characterized by convenient wiring and reliable principles, and is therefore suitable for verifying relay protection devices based on electrical size protection principles. The semi-physical test technology is extremely versatile and safe, and can be easily promoted and applied in the field. Figures

[0019] To more clearly illustrate the technical solutions of the embodiments of the present application, the figures required for use in these embodiments are briefly presented below. Obviously, the figures described below represent some embodiments of the present application, and general technical personnel in this field can draw further figures based on these without any creative effort. Fig. Figure 1 is a schematic structural representation of a HIL simulation test system in a HIL test procedure for a protective device according to an embodiment of the present application. Fig. Figure 2 is a schematic representation of a simulation scenario to be verified in a HIL test procedure for a protective device according to an embodiment of the present application. Fig. Figure 3 is a schematic representation of three-phase fault currents on both sides of a transformer in a HIL test procedure for a protective device according to an embodiment of the present application. Fig. Figure 4 is a schematic representation of the calculated three-phase current difference and the tripping signal recordings at a "second harmonic limiting coefficient" of 0.30 in a HIL test procedure for a protective device according to an embodiment of the present application. Fig. Figure 5 is a schematic representation of the calculated three-phase current difference and the tripping signal recordings at a "second harmonic limiting coefficient" of 0.65 in a HIL test procedure for a protective device according to an embodiment of the present application. Specific embodiments

[0020] To clarify the purpose, technical solutions, and advantages of the present application, the specific embodiments of the present application are described in detail below with reference to the attached drawings of the description. The described embodiments naturally represent only a part of the present application and do not constitute the entirety of all embodiments. Based on the embodiments of the present application, all further embodiments that a person skilled in the art obtains without creative activity fall within the scope of protection of the present application.

[0021] The following description contains many specific details that serve to improve understanding of the present application. However, the present application can also be implemented in forms other than those described here. Skilled persons can make similar generalizations without infringing the meaning of the present application. Therefore, the present application is not limited to the specific embodiments described below. Example 1

[0022] Fig. 1 is an embodiment of the present application and provides a HIL test method for a protective device, comprising the following: Step 1: Create a simulation primary system within a HIL simulation test system, i.e., a simulation scenario to be verified. The components included are a generator, transformer, endless loop system, transmission line, load impedance, converter, etc.; Step 2: Determine the minimum sampling signal required for the normal operation of the protective device under test, based on the installation location of the protective device under test in the simulation scenario to be verified, and create a current transformer model capable of reproducing a transient saturation scenario. Create a JA transient saturation model for all P-class current transformers in the simulation scenario, which is to be verified using parameters such as transformation ratio, core cross-sectional area, and core size, disregarding the saturation characteristics for TP-class current transformers. Step 3: Connect the peripheral interfaces of the protective device under test, such as the current and voltage sensing channels, to the simulation primary system hardware, where the current signal is derived from the calculated value of the current transformer model in step 2) and the voltage signal can be generated via an ideal voltage transformer. Adapt the analog AIO, digital DIO, and other interface devices to their voltage levels. Step 4: Switch on the protective device under test and ensure that the simulation primary system can output continuous and stable electrical signals, with the correct sampling indicator visible on the protective device. Simulate a fault scenario in the simulation scenario to be verified and observe, based on the current signal calculated by the model with transient saturation properties and the logic check of the protective device, whether its tripping result corresponds to the set value and tripping logic. Record the corresponding process, then change the fault scenario in the simulation scenario to be verified and repeat step 4. Otherwise, the test is terminated.

[0023] The simulation primary system in step 1 has the following features: It utilizes a CPU and multi-FPGA hardware architecture, with each FPGA simulation card equipped with synchronous analog input (AI) and output (AO) channels with a maximum sampling rate of at least 1 MS / s and a voltage range of ±10 V, as well as fast digital input (DI) and digital output (DO) channels. The maximum update frequency of a single channel is at least 10 MHz and it is equipped with TTL interfaces as standard. The basic modules allow FPGA algorithm models to be created, verified, deployed, and executed as needed. These basic modules include addition, subtraction, multiplication, division, integration, differentiation, logic comparison, coordinate transformation, and PID and PLL phase synchronization modules.Circuit parameters can be adjusted online during real-time simulation without any limitations on the number of parameters or changes; power amplifiers can also be used. The structure diagram of the simulation primary system is shown in [reference]. Fig. Figure 1 shows the simulation scenario to be verified. It is a pure software model that features a human-computer interaction interface during runtime, enabling basic functions such as triggering errors and observing the model's operation.

[0024] In step 2, the TP-class current transformer in the simulation scenario to be verified is transformed into an ideal current transformer according to the turns ratio. That is, the primary current divided by the secondary current yields the output current of the model. For a P-class current transformer, the calculation is performed as follows: (1) Initializing the model and setting the parameters of the P-class current transformer, including the turns ratio N, the equivalent core cross-section A, the magnetic permeability µ0 in vacuum, µ0 = 4π× 10⁻⁷ T·m / A, the equivalent flux length 1 of the core, and the resistance R2 and leakage reactance L2 of the secondary circuit of the current transformer. Determining the initial excitation current im(k⁻¹) and the initial magnetization strength M(k⁻¹), where the k⁻¹ moment is recorded as an initial state marker for the general description of the algorithm flow. (2) Calculating the differential equation of the magnetic susceptibility as an essential parameter of the JA transient saturation model Calculating the magnetic field strength H(k)=im(k−1)⋅N / l Calculating the theoretical JA parameter - effective magnetic field strength He(k)=H(k)+αM(k−1) Calculating the theoretical JA parameter - hysteresis-free magnetization Man(k)=Ms(cothHe(k)a−aHe(k)) Calculating the theoretical JA parameter - hysteresis-free magnetic permeability dMandH(k)=Man(k)−Man(k−1)H(k)−H(k−1) Calculating the theoretical JA parameter - magnetic permeability dMdH(k)=δ⋅(1+c)(Man(k)−M(k))K⋅sign(H(k))(1+c)−α(Man(k)−M(k))+c⋅dMandH(k) in the formula M sc, K, α, and a are the five key parameters of the JA model, where Ms is the saturation magnetization of the core material; c is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; α is the domain wall coupling coefficient, which can be easily determined from the factory magnetization curve of the ferromagnetic material; Man is the magnetization assuming that the ferromagnetic material has no hysteresis effect; the direction parameter δ is calculated using the following formula: δ={0sign(H˙)×(Man−M)≤01else (3) Calculating the differential equation of the excitation current: dimdt(k)=1⋅(R2×(i1(k) / N−im(k−1))+L2⋅di1 / dt(k) / N)μ0N2A(1+dM / dH(k)+L2) (4) Continuously updating the output current of the P-class converter with saturation characteristics on the secondary side based on the changing primary current. i2(k)=i1(k) / N−im(k)

[0025] In step 3, the current and voltage sampling channels of the protective device under test are connected to the hardware of the simulation primary system and adapted to the analog AO level of the physical interface card of the simulation primary system's hardware. The current signal calculated by the converter model in the simulation primary system is fed into the current sampling port of the protective device via a signal output and amplification; the voltage signal calculated by the ideal voltage converter model in the simulation primary system is fed into the voltage sampling port of the protective device via a signal output and amplification; the trip output signal of the protective device under test is fed back to the DI channel of the physical interface card of the simulation primary system to observe and evaluate the correctness of the trip logic.

[0026] In step 4, the protective device under test is debugged and run with the simulation primary system. After observing stable signals, a fault scenario is designed according to the device under test, and the fault is triggered to verify whether the protective device under test functions correctly, whether the operating time corresponds to the protection logic, and whether the operating value corresponds to the setpoint.

[0027] Depending on requirements, multiple tests can be carried out under different scenarios. Example 2

[0028] Fig. 1 is an embodiment of the present application and provides a HIL test system for a protective device, comprising the following: a CPU and multi-FPGA simulation test host, a host computer, a power amplifier, a protective device to be tested, a signal cable and a control cable.

[0029] The system utilizes a CPU and multi-FPGA hardware architecture, with each FPGA simulation card equipped with synchronous analog input (AI) and output (AO) channels with a maximum sampling rate of at least 1 MS / s and a voltage range of ±10 V, as well as high-speed digital input (DI) and digital output (DO) channels. The maximum update frequency of a single channel is at least 10 MHz and it features TTL interfaces as standard. The basic modules allow for the creation, verification, deployment, and execution of FPGA algorithm models. These basic modules include addition, subtraction, multiplication, division, integration, differentiation, logic comparison, coordinate transformation, and PID and PLL phase synchronization modules.Circuit parameters can be adjusted online during real-time simulation without limiting the number of parameters or changes; power amplifiers can also be used.

[0030] The structure diagram of System 1 is in Fig. 1 shown. Fig. 1 is the CPU and multi-FPGA simulation test host; 2 is the host computer; 3 is the power amplifier; 4 is the protection device under test; 5 is the signal cable; 6 is the control cable; and 7 is the Ethernet cable.

[0031] During runtime, it features a human-computer interaction interface that enables basic functions such as triggering errors and observing model operation. Example 3

[0032] One embodiment of the present application differs from the two previous embodiments in that: If the described functions are implemented as software functional units and sold or used as standalone products, they can be stored on a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or a part of the technical solution is embodied in the form of a software product, wherein this computer software product, stored on a storage medium, comprises instructions, that cause a computer device (e.g., a PC, server, or network device) to run all or to perform some of the steps of the methods described in various embodiments of the present application. The storage media mentioned include various media that can store program code, such as USB flash drives, external hard drives, read-only memory (ROM), and random access memory (RAM). Magnetic disks or optical disks.

[0033] The logic and / or steps depicted in a flowchart or otherwise described herein may, for example, be considered a sequenced list of executable instructions for implementing logical functions and may be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, device, or apparatus (e.g., a computer-based system, a system with a processor, or any other system capable of receiving and executing instructions from, or in conjunction with, an instruction execution system, device, or apparatus). For the purposes of this description, "computer-readable medium" may be any device capable of containing, storing, communicating, distributing, or transporting a program for use by, or in conjunction with, an instruction execution system, device, or apparatus.

[0034] More specific examples (non-exhaustive list) of computer-readable media include: an electrical interconnect (electronic device) comprising one or more cables, a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CD-ROM). Furthermore, the computer-readable medium can even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or processing in some other suitable way if necessary, and then stored in computer memory.

[0035] It is understood that various aspects of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the embodiments described above, various steps or procedures can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. When implementing using hardware, as in another embodiment, for example, any of the following known technologies or a combination thereof can be used: discrete logic circuits with logic gates for implementing logic functions on data signals, application-specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc. Example 3

[0036] In the Fig. In an embodiment of the present application, Figures 1 to 5 provide a hardware-in-the-loop (HIL) test method for a protective device. Economic calculations and simulation experiments are used for scientific demonstration to verify the advantageous effects of the present application.

[0037] This application describes a hardware-in-the-loop (HIL) test method and system for a protective device based on JA transient saturation theory. First, a simulated primary simulation system is created within an HIL simulation test system (referred to in this document as the simulation primary system), i.e., a simulation scenario to be verified (referred to in this document as the simulation scenario to be verified). The components included are a generator, transformer, continuous loop system, transmission line, load impedance, and converter, etc., and the hardware composition of the simulation primary system is described in [reference to be added]. Fig. Figure 1 shows the simulated simulation primary system. Fig. 2 shown.

[0038] Then, the minimum sampling signal required for the normal operation of the protective device under test is determined based on the installation location of the protective device in the simulation scenario to be verified, and a current transformer model capable of reproducing a transient saturation scenario is created. For P-class current transformers, a JA transient saturation model is created using parameters such as the transformation ratio, core cross-sectional area, and core size. The TP-class current transformer is simulated as an ideal transformer. The calculation steps of the JA transient saturation model for the P-class current transformer are as follows: (1) Initializing the model and setting the parameters of the P-class current transformer, including the turns ratio N, the equivalent core cross-section A, the magnetic permeability µ0 in vacuum, µ0 = 4π×10⁻⁷ T·m / A, the equivalent flux length 1 of the core, and the resistance R2 and leakage reactance L2 of the secondary circuit of the current transformer. Determining the initial excitation current im(k⁻¹) and the initial magnetization strength M(k⁻¹), where the k⁻¹ moment is recorded as an initial state marker for the general description of the algorithm flow. (2) Calculating the differential equation of the magnetic susceptibility as an essential parameter of the JA transient saturation model Calculating the magnetic field strength H(k)=im(k−1)⋅N / l Calculating the theoretical JA parameter - effective magnetic field strength He(k)=H(k)+αM(k−1) Calculating the theoretical JA parameter - hysteresis-free magnetization Man(k)=Ms(cothHe(k)a−aHe(k)) Calculating the theoretical JA parameter - hysteresis-free magnetic permeability dMandH(k)=Man(k)−Man(k−1)H(k)−H(k−1) Calculating the theoretical JA parameter - magnetic permeability dMdH(k)=δ⋅(1+c)(Man(k)−M(k))K⋅sign(H(k))(1+c)−α(Man(k)−M(k))+c⋅dMandH(k) in the formula M s , c, K, α and a are the five key parameters of the JA model, where M swhere c is the saturation magnetization of the core material; K is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; α is the domain wall coupling coefficient, which can be easily determined from the factory magnetization curve of the ferromagnetic material; Man is the magnetization assuming that the ferromagnetic material has no hysteresis effect; the direction parameter δ is calculated using the following formula: δ={0sign(H˙)×(Man−M)≤01else (3) Calculating the differential equation of the excitation current: dimdt(k)=l⋅(R2×(i1(k) / N−im(k−1))+L2⋅di1 / dt(k) / N)μ0N2A(1+dM / dH(k)+L2) (4) Continuously updating the output current of the P-class converter with saturation characteristics on the secondary side based on the changing primary current. i2(k)=i1(k) / N−im(k)

[0039] The peripheral interfaces of the protection device under test, such as the current and voltage sampling channels, are then connected to the simulation primary system hardware. The current signal is derived from the calculated value of the converter model, and the voltage signal can be generated via an ideal voltage converter. The power amplifier in the simulation primary system compares the analog AIO signals calculated by the software with the voltage and current levels of the protection device interface under test. For example, a 0-5 V mains voltage signal output by the simulation system is converted to 0-100 V by the power amplifier, and a 0-5 V phase current signal output by the simulation system is converted to 0-1 A by the power amplifier.If the digital DIO signal differs from the signal level of the actual device, it must also be adjusted via the power amplifier before being connected to the protective device under test.

[0040] After level adjustment and wiring are complete, the protective device under test is switched on, and it is ensured that the simulation primary system can output continuous and stable electrical signals, with the correct sampling indicator displayed on the protective device. A fault scenario is then simulated in the simulation scenario to be verified. Based on the current signal calculated by the model with transient saturation characteristics and the logic check of the protective device, it is observed whether its tripping result corresponds to the set value and tripping logic. The corresponding process is recorded. Subsequently, the fault scenario in the simulation scenario to be verified is changed, and step 4 is repeated. Otherwise, the test is terminated.

[0041] This example simulates a hardware-in-the-loop (HIL) test of the transformer protection device for a 330 / 110 kV, 240 MVA, two-winding, three-phase transformer. After reviewing the manufacturer's documentation, it was determined that the transformer protection device incorporates second harmonic limiting criteria to prevent unbalanced currents such as transformer saturation and magnetizing inrush current. A comprehensive HIL test was performed. Data such as the transformer turns ratio, voltage levels, capacitance, and current transformer turns ratio from the simulation system were entered into the actual protection device, and the corresponding settings were configured. The P-class current transformer on the 330 kV side is set to 600 / 1, and the secondary load is 7 Ω. The P-class current transformer on the 110 kV side is set to 1200 / 1, and the secondary load is 7 Ω.The corresponding JA transient saturation model of the current transformer is created based on the core cross-sectional area and the equivalent magnetic flux length of the two transformers, combined with the JA parameters that describe the nonlinear core properties. The main parameters of the JA model are defined as follows: M. s = 1.8 × 106, c = 0.1, k = 300, α = 2.5 × 10-5 and a = 100. The most important settings within the transformer protection device were: “Differential start setting” is set to 0.3, “Maximum slope of differential ratio braking” is set to 0.8, “Selection of inrush current blocking function” is set to 0 (which indicates second harmonic braking) and “Second harmonic braking coefficient” is set to 0.30 or 0.65 for comparison tests.

[0042] To illustrate the advantages of the present application for verifying the setting values ​​and functional tests of the protective devices, a simulated fault outside the transformer zone is used to demonstrate the advanced nature of this method. In the simulation scenario to be verified, a three-phase short-to-earth fault occurs near the 330 kV side outside the transformer zone with a fault duration of 0.7 seconds and 0.05 seconds, respectively. The tripping output signal of the protective device and the three-phase current signals are recorded using an oscilloscope.The impedance parameters of the power supply of the simulation scenario to be verified are set so that the P-class current transformer temporarily saturates under the fault current, the adaptability of the protection device and its settings to the transient saturation signal is verified, and the correct response of the operating signals of the protection device is observed.

[0043] Fig. Figure 3 shows the three-phase current waveforms calculated using the JA transient saturation model in this simulation system. In the figure, IA, IB, and IC represent the calculated signals of the current transformer model on the 330 kV side, while Ia, Ib, and Ic represent the calculated signals of the current transformer model on the 110 kV side.

[0044] Fig. Figure 4 shows the calculation results of the three-phase differential current and the recording curve of the tripping signal with a "Secondary Harmonic Limiting Factor" of 0.30 in the transformer protection device. At this setting, the blocking logic of the protection device blocks correctly despite strong current transformer distortion and significant differential current, thus reliably preventing operation in fault scenarios outside the zone.

[0045] Fig. Figure 5 shows the calculation results of the three-phase differential current and the recording curve of the tripping signal with a "secondary harmonic limiting factor" of 0.65 in the transformer protection device. At this setting, the same transient saturation and the same differential current caused a false trip after only 0.7339 seconds.

[0046] The results show that the model, test method and system described in the present application can perform HIL simulation tests on transformer protection devices, and that compared to conventional methods for verifying protection devices, this method enables a thorough examination of fault scenarios that are difficult to reproduce using conventional means, as well as the verification of the correctness and reliability of the protection device functions and their setting values.

[0047] It should be noted that the above embodiments serve only to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the preferred embodiments, it is understood by the general technical personnel in this field that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application, and that such modifications and replacements all fall within the scope of protection of the claims of the present application.

Claims

A hardware-in-the-loop (HIL) test method for a protective device, characterized in that it comprises: creating a simulation scenario within a HIL simulation test system; determining the minimum sampling signal required for the normal operation of the protective device under test based on the installation location of the protective device under test in the simulation scenario and creating a current transformer model capable of reproducing a transient saturation scenario; switching on the protective device under test and outputting an electrical signal through the HIL simulation test system; simulating a fault scenario in the simulation scenario after receiving correct sampling values ​​from the protective device, and determining, based on the current signal calculated by the model with the transient saturation properties and the logic check of the protective device, whether the tripping result corresponds to the set value and the tripping logic. HIL test method for a protective device according to claim 1, characterized in that the current transformer model comprises a TP-class current transformer and a P-class current transformer. HIL test method for a protective device according to claim 2, characterized in that the saturation properties are not taken into account for the TP class current transformer. HIL test method for a protective device according to claim 3, characterized in that a JA transient saturation model is created for the P-class current transformer. HIL test method for a protective device according to claim 4, characterized in that the creation of the JA transient saturation model comprises: initializing the model and setting the parameters of the P-class current transformer; calculating the differential equation of the magnetic susceptibility as an essential characteristic of the JA transient saturation model; calculating the differential equation of the excitation current; and continuously updating the output current of the P-class transformer with saturation characteristics on the secondary side based on the changing primary current. HIL test method for a protective device according to claim 5, characterized in that the parameters of the P-class current transformer include the turns ratio, the equivalent iron core cross-section, the magnetic permeability in the vacuum state, the equivalent flux linkage length of the iron core, the resistance and leakage reactance of the current transformer secondary circuit, the initial excitation current value and the initial magnetization intensity. HIL test method for a protective device according to claim 6, characterized in that the following is provided: connecting the current and voltage sampling channels of the protective device under test to the hardware of the HIL simulation test system and adjusting the analog AO level of the physical hardware interface card of the HIL simulation test system; feeding the current signal calculated in the HIL simulation test system into the current sampling port of the protective device via a signal output and amplification; feeding the voltage signal calculated by the ideal voltage converter model in the HIL simulation test system into the voltage sampling port of the protective device via a signal output and amplification; feeding the trip output signal of the protective device under test back to the DI channel of the physical interface card of the HIL simulation test system. HIL simulation test system, characterized in that it comprises: a CPU and multi-FPGA simulation test host, a host computer, a power amplifier, a protective device under test, a signal cable, a control cable, and an Ethernet cable; wherein the CPU and multi-FPGA simulation test host is designed to generate current and voltage signals in simulation scenarios and to calculate fault scenarios using simulation algorithms; wherein the host computer is connected to the CPU and multi-FPGA simulation test host via the Ethernet cable and is designed to create the fault scenarios and monitor the simulation results; wherein the power amplifier amplifies the analog signals output by the simulation host to drive the input channels of the protective device under test; wherein the signal cable connects the power amplifier to the protective device under test and transmits current and voltage signals;wherein the control cable connects the protective device under test to the simulation test host and transmits input and output signals for monitoring the operating logic of the protective device; wherein the host computer adapts the fault scenario in real time and the simulation host outputs a signal that meets the requirements to the protective device via the power amplifier for verification. Computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, when the processor executes the computer program, the steps of the HIL test procedure for a protective device according to one of claims 1 to 7 are performed. A computer-readable storage medium wherein a computer program is stored, characterized in that, when the processor executes the computer program, the steps of the HIL test procedure for a protective device according to one of claims 1 to 7 are performed.

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