Display device

Abstract

Display device, comprising: a control transistor (M1, T1) comprising a first semiconductor layer (21) comprising silicon and a first gate electrode (22); a first switching transistor (M2, T3) comprising a second semiconductor layer (31, A3) comprising an oxide, and a second gate electrode (32); a first shielding layer (120) that overlaps the drive transistor (M1, T1), wherein the first shielding layer (120) is arranged between a substrate (110) and the first semiconductor layer (21); a second shielding layer (130d) that overlaps the first switching transistor (M2, T3), wherein the second shielding layer (130d) is arranged between the substrate (110) and the second semiconductor layer (31, A3); and a first capacitor (Cst), comprising a first electrode (41, Cst1) and a second electrode (43, Cst2), where: the first electrode (41, Cst1) of the first capacitor (Cst) and the first gate electrode (22) of the drive transistor (M1, T1) are formed as one body and the second electrode (43, Cst2) of the first capacitor (Cst) is located at the first gate electrode (22) of the drive transistor (M1, T1) and overlaps the first gate electrode (22) of the drive transistor (M1, T1); and the second electrode (43, Cst2) is positioned on the same layer as the second shielding layer (130d).

Description

BACKGROUND

[0001] Exemplary embodiments according to the invention generally relate to a display device. DISCUSSION OF THE BACKGROUND

[0002] Display devices, such as organic light-emitting displays, liquid crystal displays (LCDs), and the like, comprise an array substrate containing a thin-film transistor (TFT), a capacitor, and a variety of wiring. The array substrate contains intricate patterns, such as TFTs, capacitors, and wiring, and such a display device is driven by complex connections between the TFT, the capacitor, and the wiring.

[0003] As the demand for display devices with compact sizes and high resolution has increased, so too has the demand for an efficient spatial arrangement between the TFT, the capacitor and the wiring of the display device, a connection structure thereof, a drive method and an improvement in the quality of a realized image.

[0004] The above-mentioned information disclosed in this background section is provided solely for the purpose of understanding the background of the inventive concepts and may therefore contain information that does not represent the prior art. SUMMARY

[0005] Devices constructed according to exemplary implementations of the invention disclose a display device that includes a transistor with improved properties.

[0006] Additional features of the inventive concepts are set out in the following description and can partly be deduced from the description or learned from the practical implementation of the inventive concepts.

[0007] According to one or more embodiments, a display device comprises: a first thin-film transistor (TFT) (e.g., T1, discussed with reference to drawings) comprising a first semiconductor layer containing a silicon semiconductor; a second TFT (e.g., T3, discussed with reference to drawings) comprising a second semiconductor layer containing an oxide semiconductor, wherein one end of the second semiconductor layer is connected to one end of the first semiconductor layer of the first TFT and the other end of the second semiconductor layer is connected to a gate electrode of the first TFT; a first shielding layer configured to overlap the first TFT, the first shielding layer being inserted between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT, the first shielding layer being arranged between the substrate and the second TFT.

[0008] The first shielding layer and the second shielding layer can be positioned on the same layer.

[0009] The first shielding layer and the second shielding layer can be positioned on different layers.

[0010] The second shielding layer can be positioned on the same layer as the first semiconductor layer.

[0011] The second shielding layer can be positioned on the same layer as a gate electrode of the first TFT.

[0012] The display device may further include a capacitor that overlaps the first TFT, with the second shielding layer being positioned on the same layer as an electrode of the capacitor.

[0013] The display device may also include a capacitor that overlaps the second shielding layer and is positioned between the second shielding layer and the second TFT.

[0014] One electrode of the capacitor can be positioned on the same layer as one of the first semiconductor layer of the first TFT and a gate electrode of the first TFT, overlapping a channel area of ​​the first semiconductor layer.

[0015] The display device may further include at least one of the following: a first touch sensor that overlaps the first TFT; and a second touch sensor that overlaps the second shielding layer and is positioned between the second shielding layer and the substrate.

[0016] The first shielding layer can be electrically connected to a power line for applying a mains voltage.

[0017] The first shielding layer can be electrically connected to a power line for applying an initialization voltage.

[0018] The first shielding layer can be electrically connected to the first semiconductor layer.

[0019] The first shielding layer can be electrically connected to a gate electrode of the first TFT.

[0020] The second shielding layer can be electrically connected to a power line for applying an initialization voltage.

[0021] The second shielding layer can be electrically connected to the gate electrode of the second TFT.

[0022] The first TFT can be a driver transistor and the second TFT can be a switching transistor.

[0023] The first TFT can be a switching transistor and the second TFT can be a driver transistor.

[0024] According to one or more embodiments, a display device comprises: a first thin-film transistor (TFT) comprising a first semiconductor layer comprising a silicon semiconductor; a second TFT comprising a second semiconductor layer comprising an oxide semiconductor; a capacitor overlapping the first TFT; a first shielding layer overlapping the first TFT, the first shielding layer being inserted between a substrate and the first TFT; and a second shielding layer overlapping the second TFT, the second shielding layer being arranged between the substrate and the second TFT.

[0025] The same voltage can be applied to the first shielding layer and the second shielding layer.

[0026] Different voltages can be applied to the first shielding layer and the second shielding layer.

[0027] It is understood that both the preceding general description and the following detailed description are exemplary and explanatory and are intended to provide a further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the invention and are integrated into and represent part of this patent specification, illustrate embodiments of the invention and, together with the description, serve to explain the inventive concepts. Fig. 1 is a top view that schematically illustrates a display device according to an exemplary embodiment; Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D images are cross-sectional views that illustrate a pixel structure constructed according to an exemplary embodiment; Fig. 3A, Fig. 3B and Fig. 3C are cross-sectional views illustrating a pixel structure constructed according to a different embodiment; Fig. 4A, Fig. 4B and Fig. 4C are cross-sectional views illustrating a pixel structure constructed according to another embodiment; Fig. Figure 5 is a cross-sectional view illustrating a pixel structure constructed according to another embodiment; Fig. 6A, Fig. 6B and Fig. Figure 6C are cross-sectional views illustrating a pixel structure constructed according to another embodiment; Fig. 7 is an equivalent circuit diagram of pixels, illustrated in Fig. 1, according to an exemplary embodiment; Fig. 8 is a view that schematically illustrates a pixel arrangement according to an exemplary embodiment; Fig. 9 is a layout view that shows transistors and capacitors of pixels that are in Fig. 7 are illustrated schematically according to an exemplary embodiment; Fig. 10 is a cross-sectional view along the section lines II' and II-II' from Fig. 9; Fig. 11 is a layout view that shows transistors and capacitors of pixels that are in Fig. 7 are illustrated, according to another embodiment, schematically illustrated; Fig. 12 is a cross-sectional view along the section lines III-III' and IV-IV' from Fig. 11; Fig. 13 is a layout view that shows transistors and capacitors of pixels that are in Fig. 7 are illustrated, according to another embodiment, schematically illustrated; and Fig. Figure 14 is a cross-sectional view along the section lines VV' and VI-VI' from Fig. 13. DETAILED DESCRIPTION

[0029] For the sake of clarification, numerous specific details are set forth below to provide a comprehensive understanding of various embodiments or implementations of the invention. In this context, "embodiments" and "implementations" are interchangeable terms that are non-limiting examples of devices or methods that employ one or more of the inventive concepts disclosed in this document. It is understood, however, that various embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to prevent the various embodiments from becoming unnecessarily unclear. Furthermore, different embodiments may be distinct but need not be exclusive.For example, specific shapes, configurations and properties of one embodiment can be used or implemented in another embodiment without deviating from the inventive concepts.

[0030] Unless otherwise stated, the illustrated embodiments are to be understood as providing exemplary features of varying details of some ways in which the inventive concepts can be implemented in practice. Unless otherwise stated, the features, components, modules, layers, films, plates, areas and / or aspects, etc. (hereinafter referred to individually or collectively as "elements") of the various embodiments can therefore be combined, separated, exchanged and / or rearranged without departing from the inventive concepts.

[0031] The use of cross-hatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Thus, neither the presence nor the absence of cross-hatching or shading conveys a preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristic, attribute, property, etc., of the elements, unless otherwise stated. Furthermore, the size and relative dimensions of elements in the accompanying drawings may be exaggerated for the purposes of clarity and / or description. If an embodiment can be implemented differently, a specific process sequence may be carried out differently from the sequence described.For example, two processes described consecutively can be carried out essentially simultaneously or in a sequence that is the opposite of the described sequence. Furthermore, similar elements are marked with the same reference symbols.

[0032] When an element, such as a layer, is described as "on," "connected to," or "coupled to" another element or layer, the "on," "connected to," or "coupled to" state with respect to the other element or layer can be direct, or it can involve intermediate elements or layers. However, when an element or layer is described as "directly attached to," "directly connected to," or "directly coupled to" another element or layer, no intermediate elements or layers are present. For this purpose, the term "connected" can refer to a physical, electrical, and / or fluid connection, with or without intermediate elements.For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. In this context, the expression “and / or” includes any combination of one or more of the related listed elements.

[0033] Although the terms “first,” “second,” etc., may be used in this writing to describe different kinds of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without deviating from the teachings of Revelation.

[0034] Spatially relative terms, such as "below," "under," "below," "lower," "above," "over," "higher," "side" (e.g., as in "side wall"), and the like, may be used in this document for descriptive purposes and thereby describe a relationship of elements to another element(s), as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of a device in use, operation, and / or manufacture in addition to the orientation shown in the drawings. For example, if the device in the drawings is reversed, elements described as "below" or "underneath" other elements or features would then be oriented "above" the other elements or features. Accordingly, the exemplary term "below" can encompass both an orientation "above" and "under." Furthermore, the device may be oriented differently (e.g.,rotated by 90 degrees or in other orientations), and the spatial descriptions used in this text can be interpreted accordingly.

[0035] The terminology used in this document serves to describe specific embodiments and is not intended as a limitation. In this context, the singular forms "a," "an," as well as "the," "a," and "a" are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, the terms "comprises," "comprehensive," "includes," and / or "includes," when used in this description, specify the presence of indicated features, integers, steps, processes, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.It is also noted that the terms “essentially”, “approximately” and other similar terms are used in the present context as terms of approximation and not as terms of degree, and as such are used to account for inherent variations in measured, calculated and / or provided values ​​which would be recognized by the average person in the field.

[0036] Various embodiments are described in this document with reference to sectional and / or exploded views, which are schematic illustrations of idealized embodiments and / or intermediate structures. Accordingly, variations in the shapes of the illustrations are to be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments disclosed in this document should not necessarily be interpreted as being limited to the specific illustrated shapes of areas, but rather should include deviations in shapes that result, for example, from the manufacturing process. In this way, areas illustrated in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of areas of a device and are therefore not necessarily intended to be restrictive.

[0037] As is customary in this field, some exemplary embodiments are described and illustrated in the accompanying drawings with regard to functional blocks, units, and / or modules. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, and the like, which may be formed using semiconductor fabrication techniques or other manufacturing techniques. In the event that the blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform various functions discussed in this document and may optionally be controlled by firmware and / or software.It is also considered that each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Furthermore, each block, unit, and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules without deviating from the scope of the concepts according to the invention. Moreover, the blocks, units, and / or modules of some embodiments can be physically combined to form more complex blocks, units, and / or modules without deviating from the scope of the concepts according to the invention.

[0038] Unless otherwise defined, all terms used in this document (including technical and scientific terms) shall have the same meaning as generally understood by the person skilled in the art in the field of which this disclosure is a part. Terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of this patent specification and shall not be interpreted in an idealized or overly formal sense unless expressly defined so in this document.

[0039] Fig. Figure 1 is a top view schematically illustrating a display device according to an exemplary embodiment.

[0040] Pixel PX, which incorporate various display devices such as organic light-emitting devices (OLEDs), can be positioned in a first direction and a second direction within a display area DA of a substrate 110. The pixel PX can include a display device and a pixel circuit for driving the display device. Various wiring and drive circuits, i.e., a scan driver, a multiplexer (MUX), and a data driver for transmitting electrical signals to the display area DA, can be positioned within a circumferential area PA of the substrate 110.

[0041] The pixel circuitry and a driver circuitry can be implemented using a variety of thin-film transistors (TFTs) and formed on substrate 110. The TFTs can be either oxide semiconductor or silicon (Si) semiconductor, depending on the semiconductor material used to form the active layer. Appropriate TFT types that meet required criteria, such as leakage current, switching speed, drive strength, and uniformity, can be used in the pixel circuitry and the driver circuitry to improve display performance.

[0042] In the display device according to embodiments, at least two types of TFTs can be formed on the substrate 110. At least two types of TFTs include a silicon (Si) semiconductor TFT with a semiconductor layer containing a Si material, and an oxide semiconductor TFT having a semiconductor layer containing an oxide. The Si semiconductor TFT can be a low-temperature polysilicon (LTPS) TFT, an amorphous silicon (a-Si) TFT, or a polycrystalline silicon (p-Si) TFT.

[0043] Since the Si material has a relatively high electron mobility and therefore low energy consumption and excellent reliability, the Si semiconductor TFT can be applied to a driving TFT of the pixel circuit and a TFT of the driver circuit.

[0044] The oxide semiconductor material exhibits a lower turn-off current than the silicon material. Therefore, the oxide semiconductor TFT can be used in a switching TFT display, which has a short turn-on time and maintains a long turn-off time. Because the turn-off current is low and the size of the auxiliary capacitor can be reduced, the oxide semiconductor TFT is also suitable for high-resolution displays.

[0045] In the display device according to one or more embodiments, different types of TFTs, such as an oxide semiconductor TFT (hereinafter referred to as "oxide TFT") and a silicon semiconductor TFT (hereinafter referred to as "Si TFT"), can be applied to the pixel circuitry and the driver circuitry. In one or more embodiments, the oxide TFT can be an n-channel TFT, i.e., an n-channel metal oxide semiconductor (NMOS) TFT, and the Si TFT can be a p-channel or n-channel TFT, i.e., a p-channel metal oxide semiconductor (PMOS) TFT or an NMOS TFT.

[0046] In the display device according to various embodiments, different types of silicon TFTs and oxide TFTs are positioned over the same substrate so that optimal function can be provided.

[0047] Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D images are cross-sectional views that illustrate a pixel structure constructed according to an exemplary embodiment. Fig. 2A, Fig. 2B, Fig. 2C and Fig. The 2D figures illustrate embodiments in which the positions of the second shielding layers differ. The exemplary embodiments are described below based on... Fig. 2A described and in the Fig. 2B to 2D will be a redundant description of Fig. 2A omitted.

[0048] In relation to Fig. 2A, a pixel PX1 according to one embodiment can include a first transistor M1, a second transistor M2, and a capacitor Cst, which are positioned above the substrate 110. An upper surface of the substrate 110 can be connected by the first direction (see Fig. 1) and the second direction (see Fig. 1) be defined.

[0049] The first transistor M1 and the second transistor M2 can be positioned on different layers. The second transistor M2 can be positioned on an upper layer of the first transistor M1. The capacitor Cst can overlap the first transistor M1. The first transistor M1 can be a silicon TFT. The second transistor M2 can be an oxide TFT.

[0050] The first transistor M1 can include a first semiconductor layer 21, a first gate electrode 22, a first source electrode 23, and a first drain electrode 24. The second transistor M2 can include a second semiconductor layer 31, a second gate electrode 32, a second source electrode 33, and a second drain electrode 34. The capacitor Cst can include a first electrode 41 and a second electrode 43.

[0051] A first shielding layer 120 can be positioned between the first transistor M1 and the substrate 110, and a second shielding layer 130a can be positioned between the second transistor M2 and the substrate 110. The first shielding layer 120 can be positioned so that it overlaps the first transistor M1, and the second shielding layer 130a can be positioned so that it overlaps the second transistor M2.

[0052] Due to externally introduced light and variations in voltages applied to circuit devices, which can affect a semiconductor layer of a TFT, charge can be induced on substrate 110. This alters properties of the TFT, such as a threshold voltage, which can lead to afterimages and / or reduced light uniformity.

[0053] In one embodiment, each of the first and second shielding layers 120 and 130a can be positioned between the substrate 110, the first transistor M1 and the second transistor M2, and a suitable voltage is applied to each of the first and second shielding layers 120 and 130a according to a semiconductor type and a channel type of transistor, so that the first transistor M1 and the second transistor M2 are not affected by external light and an electrical potential of the substrate 110 and the transistor properties can be enhanced.

[0054] A buffer layer 10 can be positioned on the substrate 110 and the first transistor M1, the second transistor M2 and the capacitor Cst can be positioned on the buffer layer 10.

[0055] The first shielding layer 120 in an area corresponding to the first transistor M1, and the second shielding layer 130a in an area corresponding to the second transistor M2, can be positioned on the buffer layer 10.

[0056] Each of the first shielding layer 120 and the second shielding layer 130a can contain metal and can have a single-layer or multi-layer structure. For example, the first shielding layer 120 and the second shielding layer 130a can have a single-layer structure containing molybdenum (Mo). In another embodiment, the first shielding layer 120 and the second shielding layer 130a can have a three-layer structure comprising a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing Ti, positioned sequentially on the buffer layer 10.

[0057] A first insulating layer 11 can be positioned on the first shielding layer 120 and the second shielding layer 130a. The first semiconductor layer 21 of the first transistor M1 can be positioned on the first insulating layer 11. The first semiconductor layer 21 can contain polysilicon.

[0058] A second insulating layer 12 can be positioned on the first semiconductor layer 21. A first gate electrode 22 can be positioned on the second insulating layer 12. The first gate electrode 22 can function as the first electrode 41 of capacitor Cst. A third insulating layer 13 can be positioned on the first gate electrode 22. The second electrode 43 of capacitor Cst can be positioned on the third insulating layer 13. A fourth insulating layer 14 can be positioned on the second electrode 43 of capacitor Cst.

[0059] The second semiconductor layer 31 of the second transistor M2 can be positioned on the fourth insulating layer 14. The second semiconductor layer 31 can contain an oxide semiconductor. The oxide semiconductor can contain a metal oxide, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and Ti, or a mixture of metals, such as Zn, In, Ga, Sn, Ti, and oxides thereof. For example, the oxide semiconductor can be formed from a Zn oxide-based material, such as a Zn oxide, an In-Zn oxide, or a Ga-In-Zn oxide. In some embodiments, the oxide semiconductor can be an In-Ga-Zn-O (IGZO) semiconductor, in which metals, such as In and Ga, are contained in ZnO.

[0060] A fifth insulating layer 15 can be positioned on the second semiconductor layer 31. The second gate electrode 32 can be positioned on the fifth insulating layer 15. A sixth insulating layer 16 can be positioned on the second gate electrode 32.

[0061] The first source electrode 23 and the first drain electrode 24 of the first transistor M1 and the second source electrode 33 and the second drain electrode 34 of the second transistor M2 can be positioned on the sixth insulating layer 16.

[0062] A seventh insulating layer 17 can be positioned over the first transistor M1 and the second transistor M2. A conductive layer 140 can be positioned on the seventh insulating layer 17. The conductive layer 140 can be a connecting electrode for electrically connecting an electrode from the plurality of transistors and the capacitor Cst of pixel PX, including the first transistor M1 and the second transistor M2, to a pixel electrode PE. An eighth insulating layer 18 can be positioned on the conductive layer 140. The pixel electrode PE can be positioned on the eighth insulating layer 18. A ninth insulating layer 19 can be positioned at the edges of the pixel electrode PE. The pixel electrode PE can be electrically connected to the conductive layer 140.

[0063] In a Pixel PX2, which is in Fig. As illustrated in Figure 2B, the second shielding layer 130b is formed on the same layer as the first semiconductor layer 21 of the first transistor M1. The first semiconductor layer 21 and the second shielding layer 130b of the first transistor M1 can be positioned on the first insulating layer 11. The first semiconductor layer 21 can contain polysilicon.

[0064] The first shielding layer 120 can contain metal and have a single-layer or multi-layer structure. The second shielding layer 130b can be made of the same material as the first semiconductor layer 21 and can contain polysilicon. The second insulating layer 12 can be positioned on top of the first semiconductor layer 21 and the second shielding layer 130b.

[0065] In a Pixel PX3, which is in Fig. As illustrated in Figure 2C, the second shielding layer 130c is formed on the same layer as the first gate electrode 22 of the first transistor M1. The first gate electrode 22 and the second shielding layer 130c of the first transistor M1 can be positioned on the second insulating layer 12.

[0066] The first shielding layer 120 can contain metal and can have a single-layer or multi-layer structure. The second shielding layer 130c can contain the same material as that of the first gate electrode 22. The third insulating layer 13 can be positioned on the first gate electrode 22 and the second shielding layer 130c.

[0067] In a Pixel PX4, which is in Fig. As illustrated in 2D, the second shielding layer 130d is formed on the same layer as the second electrode 43 of the capacitor Cst. The second electrode 43 of the capacitor Cst and the second shielding layer 130d can be positioned on the third insulating layer 13.

[0068] The first shielding layer 120 can contain metal and can have a single-layer or multi-layer structure. The second shielding layer 130d can contain the same material as that of the second electrode 43. The fourth insulating layer 14 can be positioned on top of the second electrode 43 and the second shielding layer 130d.

[0069] Each of the first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d, which are in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. As illustrated in 2D, the conductive layers can be electrically connected to different conductive layers, allowing different voltages to be applied from the conductive layers to the first shielding layer 120 and the second shielding layers 130a, 130b, 130c, and 130d. The conductive layers can be electrodes of the circuit devices within the pixel PX or wiring for applying a signal or voltage to the pixel PX.

[0070] In one embodiment, the Fig. 2A, Fig. 2B, Fig. 2C and Fig. The 2D diagram illustrates that the first transistor, M1, is a p-channel transistor and can be the one in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. Figure 2D illustrates that the second transistor M2 is an n-channel transistor. In this case, the first shielding layer 120 can be electrically connected to a current line that is electrically connected to a positive (+) constant voltage source, or to a current line that is electrically connected to a negative (-) constant voltage source. Each of the second shielding layers 130a, 130b, 130c, and 130d can be electrically connected to the second gate electrode 32 of the second transistor M2, or to the current line that is electrically connected to the negative (-) constant voltage source.

[0071] In another embodiment, the Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D illustrated that the first transistor M1 is an n-channel transistor and can be the one in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. Figure 2D illustrates that the second transistor M2 is an n-channel transistor. In this case, the first shielding layer 120 can be electrically connected to the first gate electrode 22 or the first source electrode 23 of the first transistor M1, or to the current line that is electrically connected to the negative (-) constant voltage source. Each of the second shielding layers 130a, 130b, 130c, and 130d can be electrically connected to the second gate electrode 32 of the second transistor M2, or to the current line that is electrically connected to the negative (-) constant voltage source.

[0072] In another embodiment, the first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d, which are located in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. Those illustrated in 2D are also electrically potential-free.

[0073] If the same voltage is applied to the first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d, illustrated in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D, is applied or the first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d, illustrated in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. Since the 2D shielding layers are electrically potential-free, the first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d can be electrically connected to each other. At this point, the first shielding layer 120 and the second shielding layer 130a cannot be separate from each other, but can be formed as a single piece.

[0074] Fig. 3A, Fig. 3B and Fig. Figures 3C are cross-sectional views illustrating a pixel structure constructed according to a different embodiment. The images shown in the Fig. 3A, Fig. 3B and Fig. The pixels illustrated in 3C differ from those in Fig. 2A illustrated pixel PX1 due to a capacitor C, configured to further improve the optical characteristics of the second transistor M2, and provided below the second transistor M2. A redundant description of follows. Fig. 2A is omitted and differences from it are described.

[0075] In a Pixel PX5, which is in Fig. As illustrated in Figure 3A, a first capacitor C1 can be provided between the second transistor M2 and the second shielding layer 130a. The first capacitor C1 can include a lower electrode 181 and an upper electrode 182. The lower electrode 181 can be positioned on the first insulating layer 11, and the upper electrode 182 can be positioned on the second insulating layer 12. The lower electrode 181 can be made of the same material as the material used to form the first semiconductor layer 21 of the first transistor M1. The upper electrode 182 can be made of the same material as the material used to form the first gate electrode 22 of the first transistor M1.

[0076] The upper electrode 182 of the first capacitor C1 can be electrically connected to the second shielding layer 130a, and the lower electrode 181 of the first capacitor C1 can be electrically isolated. In another embodiment, both the upper electrode 182 and the lower electrode 181 of the first capacitor C1 can be electrically isolated.

[0077] In a Pixel PX6, which is in Fig. As illustrated in Figure 3B, a second capacitor C2 can be provided between the second transistor M2 and the second shielding layer 130a. The second capacitor C2 can include a lower electrode 183 and an upper electrode 184. The lower electrode 183 can be positioned on the first insulating layer 11, and the upper electrode 184 can be positioned on the third insulating layer 13. The lower electrode 183 can be made of the same material as the material used to form the first semiconductor layer 21 of the first transistor M1. The upper electrode 184 can be made of the same material as the material used to form the second electrode 43 of the capacitor Cst.

[0078] The upper electrode 184 of the second capacitor C2 can be electrically connected to the second shielding layer 130a, and the lower electrode 183 of the second capacitor C2 can be electrically isolated. In another embodiment, both the upper electrode 184 and the lower electrode 183 of the second capacitor C2 can be electrically isolated.

[0079] In a Pixel PX7, which is in Fig. As illustrated in Figure 3C, a third capacitor C3 can be provided between the second transistor M2 and the second shielding layer 130a. The third capacitor C3 can include a lower electrode 185 and an upper electrode 186. The lower electrode 185 can be positioned on the second insulating layer 12, and the upper electrode 186 can be positioned on the third insulating layer 13. The lower electrode 185 can be made of the same material as the first gate electrode 22 of the first transistor M1. The upper electrode 186 can be made of the same material as the second electrode 43 of capacitor Cst.

[0080] The upper electrode 186 of the third capacitor C3 can be electrically connected to the second shielding layer 130a, and the lower electrode 185 of the third capacitor C3 can be electrically isolated. In another embodiment, both the upper electrode 186 and the lower electrode 185 of the third capacitor C3 can be electrically isolated.

[0081] Fig. 4A, Fig. 4B and Fig. Figures 4C are cross-sectional views illustrating a pixel structure constructed according to an exemplary embodiment. The pixels are shown in... Fig. 4A, Fig. 4B and Fig. As illustrated in diagram 4C, a touch sensor TS is provided under the second transistor M2. A redundant description follows. Fig. 2A is omitted and differences from it are described.

[0082] In pixels PX8, PX9 and PX10, which are located in the Fig. 4A, Fig. 4B and Fig. As illustrated in Figure 4C, the touch sensor TS can be positioned below the second transistor M2. The touch sensor TS can include a first touch electrode TE1 and a second touch electrode TE2, positioned above the buffer layer 10 and spaced apart from each other. The first touch electrode TE1 and the second touch electrode TE2 can be made of the same material as the material used to form the first shielding layer 120 below the first transistor M1. Each of the first touch electrode TE1 and the second touch electrode TE2 can be a transmitting electrode and a receiving electrode, respectively.

[0083] With reference to Fig. 4A A second shielding layer 130b can be positioned on the touch sensor TS. That is, the second shielding layer 130b can be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130b can be positioned on the first insulating layer 11 and be made of the same material as the material that forms the first semiconductor layer 21 of the first transistor M1.

[0084] With reference to Fig. 4B A second shielding layer 130c can be positioned on the touch sensor TS. That is, the second shielding layer 130c can be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130c can be positioned on the second insulating layer 12 and be made of the same material as a material used to form the first gate electrode 22 of the first transistor M1.

[0085] With reference to Fig. 4C can have a second shielding layer 130d positioned on the touch sensor TS. That is, the second shielding layer 130d can be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130d can be positioned on the third insulating layer 13 and be made of the same material as the material used to form the second electrode 43 of the capacitor Cst.

[0086] Fig. Figure 5 is a cross-sectional view illustrating a pixel structure constructed according to an exemplary embodiment. In a Fig. The 5 illustrated pixels represent the touch sensor TS located above the first transistor M1. A redundant description follows. Fig. 2A is omitted and differences from it are described.

[0087] In a Pixel PX11, which is in Fig. As illustrated in Figure 5, a first contact electrode TE1 can be positioned above the fifth insulating layer 15, a sixth insulating layer 16 can be positioned above the first contact electrode TE1, and a second contact electrode TE2 can be positioned above the second insulating layer 16. Each of the first contact electrode TE1 and the second contact electrode TE2 can be a transmitting electrode and a receiving electrode, respectively.

[0088] Fig. 6A, Fig. 6B and Fig. Figures 6C are cross-sectional views illustrating a pixel structure constructed according to a different embodiment. In the Fig. 6A, Fig. 6B and Fig. 6C is a first touch sensor TS1 provided below the second transistor M2 and a second touch sensor TS2 is provided above the first transistor M1.

[0089] In relation to Fig. In pixel PX12, a first shielding layer 120 can be provided below the first transistor M1, and a second shielding layer 130b can be provided below the second transistor M2. The second touch sensor TS2 can be provided below the second shielding layer 130b. The second touch sensor TS2 includes a first touch electrode TE21 and a second touch electrode TE22, positioned above the buffer layer 10 and separated from each other, and can be located on the same layer as the first shielding layer 120. The first touch sensor TS1 can be provided above the first transistor M1. The first touch sensor TS1 can include the first touch electrode TE11 above the fifth insulating layer 15 and the second touch electrode TE12 above the sixth insulating layer 16.

[0090] In relation to Fig. In pixel PX13, the first shielding layer 120 can be located beneath the first transistor M1, and the second shielding layer 130c can be located beneath the second transistor M2. The second touch sensor TS2 can be located beneath the second shielding layer 130c. The second touch sensor TS2 can include the first touch electrode TE21 and the second touch electrode TE22, positioned above and separated from each other, and can be located on the same layer as the first shielding layer 120. The first touch sensor TS1 can be located above the first transistor M1. The first touch sensor TS1 can include the first touch electrode TE11 above the fifth insulating layer 15 and the second touch electrode TE12 above the sixth insulating layer 16.

[0091] In relation to Fig. In pixel PX14, the first shielding layer 120 can be located beneath the first transistor M1, and the second shielding layer 130d can be located beneath the second transistor M2. The second touch sensor TS2 can be located beneath the second shielding layer 130d. The second touch sensor TS2 can include the first touch electrode TE21 and the second touch electrode TE22, positioned above and separated from each other, and can be located on the same layer as the first shielding layer 120. The first touch sensor TS1 can be located above the first transistor M1. The first touch sensor TS1 can include the first touch electrode TE11 above the fifth insulating layer 15 and the second touch electrode TE12 above the sixth insulating layer 16.

[0092] Fig. Figure 7 is an equivalent circuit diagram of the one shown in Fig. 1 illustrated pixel according to an exemplary embodiment.

[0093] In relation to Fig. Figure 7 includes a Pixel PX, a display device, and a pixel circuit for controlling the display device by receiving signals from a multitude of wires. A Pixel PX with an OLED as the display device is described below as an exemplary embodiment.

[0094] In Fig. In each pixel PX, a first scanning line 131, a light-emitting control line 133, a second scanning line 151, a third scanning line 153, a data line 171, an initialization voltage line 141, and a mains voltage line 161 are provided. However, the embodiments are not limited to these. In another embodiment, at least one of the first scanning line 131, the light-emitting control line 133, the second scanning line 151, the third scanning line 153, the data line 171, the initialization voltage line 141, and the mains voltage line 161 can be shared in adjacent pixels.

[0095] In one embodiment, different types of TFTs, which are used in the Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 3A, Fig. 3B, Fig. 3C, Fig. 4A, Fig. 4B, Fig. 4C, Fig. 5, Fig. 6A, Fig. 6B and Fig. The principles illustrated in Figure 6C can be applied to optimize the performance of the pixel PX. For example, a drive transistor, T1, can be a silicon transistor, such as an NMOS silicon transistor or a PMOS silicon transistor, and switching transistors, such as T2, T3, T4, T5, T6, and T7, can be oxide transistors, such as NMOS oxide transistors, or a combination of NMOS and / or PMOS silicon transistors and NMOS oxide transistors. In another example, the drive transistor, T1, can be an NMOS oxide transistor, and the other transistors, T2, T3, T4, T5, T6, and T7, can be silicon transistors or NMOS and / or PMOS silicon and NMOS oxide transistors.

[0096] In Fig. 7 are a third transistor T3 and a fourth transistor T4 from a multitude of first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 NMOS oxide transistors and are the other transistors PMOS silicon transistors.

[0097] The signal lines include the first sampling line 131 for transmitting a first sampling signal GWP, the second sampling line 151 for transmitting a second sampling signal GWN, the third sampling line 153 for transmitting a third sampling signal GI, the light-emitting control line 133 for transmitting a light-emitting control signal EM, and the data line 171 for transmitting a data signal DATA, while intersecting with the first sampling line 131.

[0098] The mains voltage line 161 transmits an initial mains voltage ELVDD to the first transistor T1 and the initialization voltage line 141 transmits an initialization voltage VINT to initialize the first transistor T1 and the pixel electrode to the pixel PX.

[0099] The pixel circuit of the PX pixel can include a variety of transistors T1 to T7 and the capacitor Cst. The first electrodes are E11, E21, E31, E41, E51, E61 and E71, and the second electrodes are E12, E22, E32, E42, E52, E62 and E72. Fig. The seven transistors can be source electrodes (source regions) or drain electrodes (drain regions) depending on the transistor type (p-type or n-type) and / or operating conditions. The first through seventh transistors, T1, T2, T3, T4, T5, T6, and T7, can be implemented with TFTs.

[0100] The first transistor T1 includes a gate electrode G1, which is connected to the first electrode Cst1 of the capacitor Cst. The first electrode E11 is connected to the mains voltage line 161 via the fifth transistor T5, and the second electrode E12 is electrically connected to the pixel electrode of the OLED via the sixth transistor T6. The first transistor T1 acts as a driver transistor, receiving the DATA signal according to a switching operation of the second transistor T2 and supplying current to the OLED.

[0101] The second transistor T2 includes a gate electrode G2 connected to the first sampling line 131, with the first electrode E21 connected to the data line 171 and the second electrode E22 connected to the first electrode E11 of the first transistor T1. The second transistor T2 is switched on according to a second sampling signal GWP transmitted via the first sampling line 131 and performs a switching operation in which the data signal DATA, transmitted from data line 171, is transferred to the first electrode E11 of the first transistor T1.

[0102] The third transistor T3 includes a gate electrode G3, which is connected to the second scanning line 151. The first electrode E31 is connected to the second electrode E12 of the first transistor T1. The first electrode Cst1 of capacitor Cst, the second electrode E42 of the fourth transistor T4, and the second electrode E32 are connected to the gate electrode G1 of the first transistor T1. The first electrode E31 is connected to the pixel electrode of the OLED via the sixth transistor T6. The third transistor T3 is switched on according to the second scanning signal GWN, which is transmitted via the second scanning line 151, and connects the first transistor T1 to a diode.

[0103] The fourth transistor T4 includes a gate electrode G4 connected to the third sampling line 153, with its first electrode E41 connected to the initialization voltage line 141. The first electrode Cst1 of capacitor Cst, the second electrode E32 of the third transistor T3, and the second electrode E42 are connected to the gate electrode G1 of the first transistor T1. The fourth transistor T4 is switched on by a third sampling signal G1 transmitted via the third sampling line 153 and transmits the initialization voltage VINT to the gate electrode G1 of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0104] The fifth transistor T5 includes a gate electrode G5 which is connected to the light-emitting control line 133, with the first electrode E51 being connected to the mains voltage line 161 and the second electrode E52 being connected to the first electrode E11 of the first transistor T1 and the second electrode E22 of the second transistor T2.

[0105] The sixth transistor T6 includes a gate electrode G6 which is connected to the light-emitting control line 133, with the first electrode E61 connected to the second electrode E12 of the first transistor T1 and the first electrode E31 of the third transistor T3, and the second electrode E62 connected to the pixel electrode of the OLED.

[0106] The fifth transistor T5 and the sixth transistor T6 are switched on simultaneously according to the light-emitting control signal EM, which is transmitted via the light-emitting control line 133, so that a current flows through the OLED.

[0107] The seventh transistor T7 includes a gate electrode G7, which is connected to the first sampling line 131. The first electrode E71 is connected to the second electrode E62 of the sixth transistor T6 and the pixel electrode of the OLED, and the second electrode E72 is connected to the initialization voltage line 141. The seventh transistor T7 is switched on according to the third sampling signal GWP, which is transmitted via the first sampling line 131, thus initializing a voltage to the pixel electrode of the OLED.

[0108] The capacitor Cst comprises the first electrode Cst1, which is connected to the gate electrode G1 of the first transistor T1, and a second electrode Cst2, which is connected to the mains voltage line 161. The first electrode Cst1 of the capacitor Cst is connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4.

[0109] The OLED comprises the pixel electrode and a common electrode facing the pixel electrode. A second mains voltage, ELVSS, can be applied to the common electrode of the OLED. The OLED receives the current from the first transistor, T1, and emits light, thus displaying an image.

[0110] Fig. Figure 8 is a view that schematically illustrates a pixel arrangement according to an exemplary embodiment.

[0111] A pixel PX(k,p) in a k-row and a p-column, a pixel PX(k,p+1) in the k-row and a (p+1)-column, a pixel PX(k,p+2) in the k-row and a (p+2)-column, a pixel PX(k+1,p) in a (k+1)-row and a p-column, a pixel PX(k+1,p+1) in the (k+1)-row and a (p+1)-column, and a pixel PX(k+1,p+1) in the (k+1)-row and the (p+1)-column are in Fig. 8 is shown. Here, k and p are odd numbers.

[0112] In relation to Fig. 8. A pixel circuit of a pixel PX connected to a sampling line Slk in an odd row in each column, and a pixel circuit of a pixel PX connected to a sampling line Slk+1 in an even row in each column, can have a bilaterally symmetrical structure. For example, right and left arrays of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 of pixel PX(k,p) and pixel PX(k+1,p) are opposite each other, and right and left arrays of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 of pixel PX(k,p+1) and pixel PX(k+1,p+1) are opposite each other. However, the connection relationship between the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and the capacitor Cst is the same.

[0113] Furthermore, pixel circuits of a pair of pixels PX arranged in the same row in adjacent columns can exhibit bilateral symmetry. For example, the right and left arrays of the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7 of pixel PX(k,p) and pixel PX(k,p+1) are opposite each other, and the right and left arrays of the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7 of pixel PX(k+1,p+1) and pixel PX(k+1,p+2) are opposite each other. However, the connection between the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7 and the capacitor Cst is the same. A pair of pixels PX arranged in the same row in adjacent columns can share an initialization voltage line VL.

[0114] A first data line DL1 and a second data line DL2 can be separate in any column. A pair of first data lines DL1 and a pair of second data lines DL2 can be adjacent to each other between two adjacent columns. Two data lines DL1 and DL2 in any column include a first data line DL1 connected to pixel PX in an odd-numbered row and a second data line DL2 connected to pixel PX in an even-numbered row. That is, pixel PX in the odd-numbered row is connected to the first data line DL1, and pixel PX in the even-numbered row is connected to the second data line DL2.

[0115] Fig. 9 is a layout view that shows transistors and capacitors of pixels that are in Fig. Figure 7 illustrates a schematic representation of an exemplary embodiment. Fig. 10 is a cross-sectional view along the section lines II' and II-II' from Fig. 9.

[0116] In Fig. Figure 9 shows a pair of pixels PX arranged in the same row in adjacent columns. The pair of pixels PX exhibits a bilateral symmetry structure, and the positions where the pair of pixels PX is in contact with the initialization voltage line 141 are identical (overlapping). Fig. In section 9, the second shielding layer 130a is an island type in each pixel PX. This means that the second shielding layer 130a of the left pixel PX and the second shielding layer 130a of the right pixel PX are separated from each other. The left pixel PX in the diagram is described below, and this also applies to a right pixel PX.

[0117] A pixel PX of the display device according to one embodiment can include a plurality of wires extending in a first direction and a plurality of wires extending in a second direction intersecting the first direction. The first scanning line 131, the second scanning line 151, the third scanning line 153, the light-emitting control line 133, and the initialization voltage line 141 extend in the first direction. A data line (not shown) and the mains voltage line 161 extend in the second direction.

[0118] The Pixel PX can also include transistors T1, T2, T3, T4, T5, T6, and T7, and a capacitor Cst. Each of the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7 can include a semiconductor layer comprising a source region, a drain region, and a channel region between the source and drain regions, and a gate electrode insulated from the semiconductor layer at a position corresponding to the channel region.

[0119] In the present embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be silicon TFTs and p-channel transistors. The third transistor T3 and the fourth transistor T4 can be oxide TFTs and n-channel transistors.

[0120] Each of a first electrode and a second electrode of a Fig. The transistor shown in the illustration can be a source electrode (source area) or a drain electrode (drain area).

[0121] The buffer layer 10 is positioned above the substrate 110 and the first shielding layer 120 and the second shielding layer 130a are positioned on the buffer layer 10.

[0122] The substrate 110 can comprise a glass material, a ceramic material, a metal material, a plastic material, or a flexible or bendable material. The substrate 110 can have a single-layer or multi-layer structure of the materials described above, and if the substrate 110 has a multi-layer structure, it can further comprise an inorganic layer. In some embodiments, the substrate 110 can have a structure composed of organic / inorganic / organic materials.

[0123] Buffer layer 10 can contain an oxide layer, such as silicon dioxide (SiOx), and / or a nitride layer, such as silicon nitride (SiNx). Buffer layer 10 can be omitted.

[0124] The first shielding layer 120 can be positioned so that it overlaps at least the first transistor T1, and the second shielding layer 130a can be positioned so that it overlaps at least the third transistor T3 and the fourth transistor T4.

[0125] The first shielding layer 120 can be electrically connected to the mains voltage line 161, which is electrically connected to the positive (+) constant voltage source via a contact hole CH1 that perforates the first, second, third, fourth, fifth, and sixth insulating layers 11 to 16. The second shielding layer 130a can be electrically connected to the initialization voltage line 141, which is electrically connected to the negative (-) constant voltage source via a contact hole CH2 that perforates the first, second, and third insulating layers 11 to 13.

[0126] The first shielding layer 120 and the second shielding layer 130a can contain metal and have a single-layer or multi-layer structure. For example, the first shielding layer 120 and the second shielding layer 130a can have a single-layer structure containing Mo. In another embodiment, the first shielding layer 120 and the second shielding layer 130a can have a three-layer structure comprising a first layer containing Ti, a second layer containing Al, and a third layer containing Ti, positioned sequentially over the buffer layer 10.

[0127] The first insulating layer 11 can be positioned above the first shielding layer 120 and the second shielding layer 130a, and semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are positioned above the first insulating layer 11.

[0128] The first insulating layer 11 can contain an inorganic material that includes an oxide or nitride. For example, the first insulating layer 11 can contain silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0129] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be positioned on the same layer and contain the same material. For example, the semiconductor layers can contain polycrystalline silicon.

[0130] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be connected to each other and bent into various shapes. The semiconductor layer of the seventh transistor T7 can be connected to the semiconductor layer of the sixth transistor T6 in the previous row.

[0131] Each of the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can include a channel region, a source region, and a drain region on both sides of the channel region. A first doping step in the channel region and a second doping step in the source region and the drain region, where a gate electrode is used as a mask, can be performed. In one embodiment, the first doping step can be omitted.

[0132] The second insulating layer 12 can be positioned over the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the gate electrodes G1, G2, G5, G6, and G7 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be positioned over the second insulating layer 12. The first scanning line 131 and the light-emitting control line 133 can be made of the same material as a material used to form the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the first scanning line 131 and the light-emitting control line 133 can extend in the first direction.

[0133] The second insulating layer 12 can contain an inorganic material that includes an oxide or nitride. For example, the second insulating layer 12 can contain silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0134] The gate electrodes G1, G2 and G5, G6 and G7 can contain Mo, copper (Cu) and Ti and have a single-layer or multi-layer structure.

[0135] The semiconductor layer (A1, see Fig. 10) of the first transistor T1 includes the first electrode E11, the second electrode E12, and a channel region between them. The gate electrode G1 of the first transistor T1 overlaps the channel region in one plane. The semiconductor layer A1 of the first transistor T1 has a curvature, allowing the channel region to be long and thus increasing the drive area of ​​a gate voltage applied to the gate electrode G1 of the first transistor T1. Various embodiments of the shape of the semiconductor layer A1 of the first transistor T1, such as “ "-, „ "-", "S", "M", and "W" shapes are possible. The gate electrode G1 of the first transistor T1 is of an island type and overlaps the channel area of ​​the first transistor T1. The second insulating layer 12 is located between the gate electrode G1 of the first transistor T1 and the semiconductor layer A1 of the first transistor T1.

[0136] The gate electrode G1 of the first transistor T1 is electrically connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 via a connecting electrode 162. The connecting electrode 162 is provided on the sixth insulating layer 16 and can be in contact with each of the gate electrodes G1 of the first transistor T1, the second electrode E32 of the third transistor T3, and the second electrode E42 of the fourth transistor T4 via contact holes that perforate at least the sixth insulating layer 16.

[0137] A semiconductor layer of the second transistor T2 comprises a first electrode E21, a second electrode E22, and a channel region between them. The gate electrode G2 of the second transistor T2 overlaps the channel region in one plane and is formed by a section of the first scanning line 131. The first electrode E21 of the second transistor T2 is electrically connected to a data line (not shown) via a connecting electrode 163. The connecting electrode 163 can be provided on the sixth insulating layer 16 and can be in contact with the first electrode E21 of the second transistor T2 via a contact hole that perforates at least the sixth insulating layer 16. The data line can be formed above the seventh insulating layer 17 on the connecting electrode 163. The data line can be in contact with the connecting electrode 163 via a contact hole in the seventh insulating layer 17.The second electrode E22 of the second transistor T2 is connected to the first electrode E11 of the first transistor T1.

[0138] A semiconductor layer of the fifth transistor T5 comprises a first electrode E51, a second electrode E52, and a channel region between them. The gate electrode G5 of the fifth transistor T5 overlaps the channel region in the plane and is formed by a section of the light-emitting control line 133. The first electrode E51 of the fifth transistor T5 is electrically connected to the mains voltage line 161 via a contact hole that perforates at least the sixth insulating layer 16. The mains voltage line 161 may be provided above the sixth insulating layer 16. The second electrode E52 of the fifth transistor T5 is connected to the first electrode E11 of the first transistor T1.

[0139] A semiconductor layer of the sixth transistor T6 comprises a first electrode E61, a second electrode E62, and a channel region between them. The gate electrode G6 of the sixth transistor T6 overlaps the channel region in the plane and is formed by a section of the light-emitting control line 133. The first electrode E61 of the sixth transistor T6 is connected to the second electrode E12 of the first transistor T1. The first electrode E61 of the sixth transistor T6 is electrically connected to the first electrode E31 of the third transistor T3 via the connecting electrode 164. The connecting electrode 164 can be provided on the sixth insulating layer 16 and can be in contact with the first electrode E31 of the third transistor T3 via a contact hole that perforates at least the sixth insulating layer 16. The first electrode E31 of the third transistor T3 is provided on the fourth insulating layer 14.The second electrode E62 of the sixth transistor T6 is electrically connected to the pixel electrode PE of the OLED via the connecting electrode 165. The connecting electrode 165 can be provided on the sixth insulating layer 16 and can be in contact with the second electrode 62 of the sixth transistor T6 via a contact hole that perforates at least the sixth insulating layer 16.

[0140] A semiconductor layer of the seventh transistor T7 comprises a first electrode E71, a second electrode E72, and a channel region between them. The gate electrode G7 of the seventh transistor T7 overlaps the channel region in the plane and is formed by a section of the first scanning line 131. The second electrode E72 of the seventh transistor T7 is electrically connected via the connecting electrode 166 to the first electrode E41 of the fourth transistor T4 and the initialization voltage line 141. The connecting electrode 166 can be provided on the sixth insulating layer 16 and can be in contact with each of the first electrode E41 of the fourth transistor T4, the second electrode E72 of the seventh transistor T7, and the initialization voltage line 141 via contact holes that perforate at least the sixth insulating layer 16.The first electrode E71 of the seventh transistor T7 is connected to the second electrode E62 of the sixth transistor T6 in the previous row.

[0141] The third insulating layer 13 is positioned over the gate electrodes G1, G2, G5, G6, and G7 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. A second electrode Cst2 of the capacitor Cst is positioned over the third insulating layer 13. The initialization voltage line 141, which is positioned on the same layer as the upper electrode Cst2 of the capacitor Cst and is made of the same material as the material used to form the upper electrode Cst2 of the capacitor Cst, extends in the first direction.

[0142] The third insulating layer 13 can contain an inorganic material including the oxide or nitride described above. The second electrode Cst2 of the capacitor Cst can contain Mo, Cu, and Ti and can have a single-layer or multi-layer structure.

[0143] The capacitor Cst overlaps the first transistor T1. The capacitor Cst comprises a first electrode Cst1 and a second electrode Cst2. The first electrode Cst1 of the capacitor Cst is a gate electrode G1 of the first transistor T1. That is, it is understood that the first electrode Cst1 of the capacitor Cst and the gate electrode G1 of the first transistor T1 can be formed as a single body. The first electrode Cst1 of the capacitor Cst is separated from an adjacent pixel, has a rectangular shape, and is positioned on the same layer as the first scanning line 131 and the light-emitting control line 133, using the same material as the material used to form the first scanning line 131 and the light-emitting control line 133.The second electrode Cst2 of the capacitor Cst covers the entire first electrode Cst1 in a state where the third insulating layer 13 is located between the first electrode Cst1 and the second electrode Cst2, and overlaps the first electrode Cst1. In this case, the third insulating layer 13 acts as a dielectric layer of the capacitor Cst. The second electrode Cst2 of the capacitor Cst may include an opening SOP. The opening SOP is formed by removing a section of the second electrode Cst2 at a position corresponding to a contact hole for exposing a section of the first electrode Cst1 and may have a closed curve shape. The connecting electrode 162 may be connected to the first electrode Cst1 via a contact hole located in the opening SOP. The second electrode Cst2 may be connected to the mains voltage line 161 via the contact hole, which perforates at least the sixth insulating layer 16.

[0144] The transistors T3 and T4, which contain an oxide semiconductor, can be positioned above the transistors T1, T2, T5, T6 and T7, which contain a silicon semiconductor and the capacitor Cst.

[0145] A fourth insulating layer 14 is positioned above the second electrode Cst2 of the capacitor Cst. The semiconductor layer (A3, see Fig. 10) of the third transistor T3 and the semiconductor layer (A4, see Fig. The semiconductor layers A3 of the third transistor T3 and A4 of the fourth transistor T4 are positioned above the fourth insulating layer 14. The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 are located on the same layer and contain the same material. For example, the semiconductor layer may contain an oxide semiconductor.

[0146] The fourth insulating layer 14 may contain an inorganic material that includes the oxide or nitride described above.

[0147] The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can include a channel region and a source and drain region on either side of the channel region. In one example, the source and drain regions can be areas where the carrier concentration is enhanced by plasma treatment. The source and drain regions can be formed by adjusting the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the source and drain regions can be formed by increasing the carrier concentration through plasma treatment using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof within the oxide semiconductor.

[0148] The gate electrodes G3 and G4 of the third transistor T3 and the fourth transistor T4 are positioned on the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4. The fifth insulating layer 15 is positioned between the semiconductor layer A3 and the gate electrode G3 of the third transistor T3 and between the semiconductor layer A4 and the gate electrode G4 of the fourth transistor T4.

[0149] The gate electrodes G3 and G4 contain Mo, Cu and Ti and can have a single-layer or multi-layer structure.

[0150] In the drawings, the fifth insulating layer 15 is positioned over the entire surface of the substrate. However, the fifth insulating layer 15 can be an insulating pattern designed to match the gate electrodes G3 and G4. For example, the fifth insulating layer 15 can be formed with the insulating pattern using the same masking process as that used for the gate electrodes G3 and G4. The fifth insulating layer 15 can comprise an inorganic material containing the oxide or nitride described above.

[0151] A second scanning line 151 and a third scanning line 153, which are positioned on the same layer as the gate electrodes G3 and G4 of the third transistor T3 and the fourth transistor T4 using the same material, extend in the first direction.

[0152] The third transistor T3 comprises a semiconductor layer A3, which contains an oxide semiconductor, and a gate electrode G3. The semiconductor layer A3 includes a first electrode E31, a second electrode E32, and a channel region between them. The gate electrode G3 of the third transistor T3 overlaps the channel region in the plane and is formed by a section of the second scanning line 151. The first electrode E31 of the third transistor T3 is electrically connected to the first electrode E61 of the sixth transistor T6 via the connecting electrode 164. The second electrode E32 of the third transistor T3 can be connected to the gate electrode G1 of the first transistor T1 via the connecting electrode 162.

[0153] The fourth transistor T4 comprises a semiconductor layer A4, which contains an oxide semiconductor, and a gate electrode G4. The semiconductor layer A4 includes a first electrode E41, a second electrode E42, and a channel region between them. The gate electrode G4 of the fourth transistor T4 overlaps the channel region in the plane and is formed by a section of the third scanning line 153. The first electrode E41 of the fourth transistor T4 can be connected to the initialization voltage line 141 via a contact hole. The second electrode E42 of the fourth transistor T4 can be connected to the gate electrode G1 of the first transistor T1 via the connecting electrode 162 by means of a bridge.

[0154] A booster capacitor Cb can be formed in a region where the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 overlap the first scanning line 131. The booster capacitor Cb comprises a first electrode Cb1, which includes at least a section of the first scanning line 131, protrudes from the first scanning line 131, and has a predetermined area, and a second electrode Cb2, which extends from the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 and overlaps the first electrode Cb1. The second electrode Cb2 can include an oxide semiconductor. The second electrode Cb2 can be electrically connected to the gate electrode G1 of the first transistor T1 via the connecting electrode 162.The booster capacitor Cb can compensate for a recoil of the third transistor T3 and can increase a voltage of the gate electrode G1 of the first transistor T1.

[0155] A sixth insulating layer 16 can be positioned over transistors T3 and T4, which contain an oxide semiconductor, and the mains voltage line 161 and the connecting electrodes (162, 163, 164, 165 and 166) can be positioned on the sixth insulating layer 16. The sixth insulating layer 16 can contain an inorganic material that includes the oxide or nitride described above.

[0156] The mains voltage conductor 161 and the connecting electrodes 162, 163, 164, 165, and 166 can be made of materials with high conductivity, such as metal, a conductive oxide, and the like. For example, the mains voltage conductor 161 and the connecting electrodes 162, 163, 164, 165, and 166 can have a single-layer or multi-layer structure comprising Al, Cu, and Ti. In some embodiments, the mains voltage conductor 161 and the connecting electrodes 162, 163, 164, 165, and 166 can be provided with a triple layer of Ti / Al / Ti positioned consecutively.

[0157] A seventh insulating layer 17 can be positioned at the mains voltage line 161 and the connecting electrodes 162, 163, 164, 165, and 166, and a data line and a conductive layer can be positioned at the seventh insulating layer 17. The data line can extend in the second direction. The data line can be positioned to the left or right of the pixel PX. The data line can be positioned to the left or right of the first transistor T1. The data line can be a first data line DL1 or a second data line DL2. A through-hole for exposing a section of the connecting electrode 165 can be formed in the seventh insulating layer 17. The conductive layer can be in contact with the connecting electrode 165 through a contact hole.

[0158] The seventh insulating layer 17 can comprise an organic material, such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). In another embodiment, the seventh insulating layer 17 can comprise the inorganic material described above.

[0159] The data line and the conductive layer can be made of highly conductive materials, such as metal, a conductive oxide, and the like. For example, the data line and the conductive layer can have a single-layer or multi-layer structure containing Al, Cu, and Ti.

[0160] An eighth insulating layer 18 can be positioned on the data line and the conductive layer. A through-hole for exposing a section of the conductive layer can be formed in the eighth insulating layer 18.

[0161] The eighth insulating layer 18 can comprise an organic material, such as acrylic, BCB, polyimide, or HMDSO. In another embodiment, the eighth insulating layer 18 can comprise the inorganic material described above. The eighth insulating layer 18 serves as a protective layer for covering transistors T1, T2, T3, T4, T5, T6, and T7 and is configured such that an upper surface of the eighth insulating layer 18 is planarized. The eighth insulating layer 18 can have a single-layer or multi-layer structure.

[0162] The OLED can be located above the eighth insulating layer 18. The OLED can include a pixel electrode PE, a counter electrode CE facing the pixel electrode PE, and an intermediate layer IL between the pixel electrode PE and the counter electrode CE. A ninth insulating layer 19 is positioned on top of the eighth insulating layer 18 and covers edges of the pixel electrode PE. The ninth insulating layer 19 has an opening to expose a section of the pixel electrode PE, thereby defining pixels.

[0163] The pixel electrode PE of the OLED can be in contact with the conductive layer, which is electrically connected to the connecting electrode 165 via a through-hole. The pixel electrode PE can be a reflective layer comprising a reflective conductive material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and a compound thereof. In one embodiment, the pixel electrode PE can be a transparent conductive layer comprising at least one transparent conductive oxide selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In another embodiment, the pixel electrode PE can have a stacked structure of the reflective layer and the transparent conductive layer.

[0164] The ninth insulating layer 19 can contain an organic material, such as acrylic, BCB, polyimide or HMDSO.

[0165] The interlayer IL of the OLED comprises at least one emitting layer (EML) and may further comprise one or more functional layers selected from the group consisting of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The EML may be a red EML, a green EML, or a blue EML. In another embodiment, the EML may have a multilayer structure in which the red EML, the green EML, and the blue EML are stacked to emit white light, or a single-layer structure comprising a red light-emitting material, a green light-emitting material, and a blue light-emitting material.

[0166] The counter electrode CE of the OLED can be made of various conductive materials. For example, the counter electrode CE can be a semi-transparent reflective layer, including at least one selected from the group consisting of lithium (Li), calcium (Ca), fluorolithium (LiF), Al, Mg, and Ag, or a translucent metal oxide such as ITO, IZO, and ZnO, and can consist of a single layer or multiple layers.

[0167] A thin-film encapsulation layer (not shown) can be positioned on the OLED. The thin-film encapsulation layer can cover a display area DA and can extend to an outside of the display area DA. The thin-film encapsulation layer can include an inorganic encapsulation layer formed from at least one inorganic material and an organic encapsulation layer formed from at least one organic material. In some exemplary embodiments, the thin-film encapsulation layer can have a stacked structure consisting of a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0168] Furthermore, a spacer to prevent or reduce mask stamping can be positioned on the ninth insulating layer 19, and various functional layers, such as a polarization layer to reduce external light reflection, a black matrix, a color filter and / or a touchscreen layer that includes a touch electrode, can be provided on the thin-film encapsulation layer.

[0169] Fig. 11 is a layout view that shows transistors and capacitors of pixels that are in Fig. Figure 7 illustrates a schematic representation according to another embodiment. Fig. 12 is a cross-sectional view along the section lines III-III' and IV-IV' from Fig. 11.

[0170] A Pixel PX of one in the Fig. 11 and Fig. The display device shown in section 12 differs from the Pixel PX shown in the Fig. 9 and Fig. Figure 10 illustrates the display device by electrically connecting a second shielding layer 130a beneath the third transistor T3 and the fourth transistor T4 to a second scanning line 151 via a contact hole CH3 that perforates the first, second, third, fourth, and fifth insulating layers 11, 12, 13, 14, and 15. A section of the second scanning line 151 acts as a gate electrode G3 of the third transistor T3. Thus, the same voltage applied to the gate electrode G3 of the third transistor T3 is applied to the second shielding layer 130a. Fig. In section 11, the second shielding layer 130a of the left pixel PX and the second shielding layer 130a of the right pixel PX are connected as a single body. This means that the left pixel PX and the right pixel PX can share the second shielding layer 130a. Therefore, the second shielding layer 130a can be connected to the second scanning line 151 via a contact hole CH3 from either the left pixel PX or the right pixel PX.

[0171] In another embodiment, the second shielding layer 130a can be electrically connected to the third scanning line 153 via a contact hole that perforates the first, second, third, fourth, and fifth insulating layers 11, 12, 13, 14, and 15. A section of the third scanning line 153 acts as a gate electrode G4 of the fourth transistor T4. Thus, the same voltage applied to the gate electrode G4 of the fourth transistor T4 is applied to the second shielding layer 130a.

[0172] Fig. 13 is a layout view that shows transistors and capacitors of pixels that are in Fig. Figure 7 illustrates a schematic representation according to another embodiment. Fig. Figure 14 is a cross-sectional view along the section lines VV' and VI-VI' from Fig. 13.

[0173] A Pixel PX of one in the Fig. 13 and Fig. The display device illustrated in section 14 differs from the Pixel PX shown in the Fig. 9 and Fig. Figure 10 illustrates the display device by positioning a second shielding layer 130d beneath the third transistor T3 and the fourth transistor T4 on the same layer as the second electrode Cst2 of capacitor Cst and electrically connecting it to the second scanning line 151 via a contact hole CH4 that perforates the third to fifth insulating layers 13, 14, and 15. The second shielding layer 130d can be made of the same material as the material used to form the second electrode Cst2 of capacitor Cst. A section of the second scanning line 151 acts as the gate electrode G3 of the third transistor T3. Thus, the same voltage applied to the gate electrode G3 of the third transistor T3 is applied to the second shielding layer 130d. Fig. In section 13, the second shielding layer 130d of the left pixel PX and the second shielding layer 130d of the right pixel PX are connected as a single unit. This means that the left pixel PX and the right pixel PX can share the second shielding layer 130d. Therefore, the second shielding layer 130d can be connected to the second scanning line 151 via a contact hole CH4 from either the left pixel PX or the right pixel PX.

[0174] In another embodiment, the second shielding layer 130d can be positioned on the same layer as the second electrode Cst2 of the capacitor Cst and electrically connected to the third scanning line 153 via a contact hole CH4 that perforates the third to fifth insulating layers 13, 14, and 15. A section of the third scanning line 153 acts as the gate electrode G4 of the fourth transistor T4. Thus, the same voltage applied to the gate electrode G4 of the fourth transistor T4 is applied to the second shielding layer 130d.

[0175] In one embodiment, the second shielding layer can be positioned on the same layer as the semiconductor layer A1 of the first transistor T1 and electrically connected to the initialization voltage line 141 via a contact hole that perforates the second and third insulating layers 12 and 13. In another embodiment, the second shielding layer can be positioned on the same layer as the semiconductor layer A1 of the first transistor T1 and electrically connected to the second scanning line 151 or the third scanning line 153 via a contact hole that perforates the second to fifth insulating layers 12, 13, 14 and 15.

[0176] Furthermore, in another embodiment, a capacitor, as in Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D illustrated, or a touch sensor, as in Fig. 4A, Fig. 4B and Fig. Figure 4C illustrates positions with other wiring, under the second shielding layer. Of course, a touch sensor can be positioned on the first shielding layer, as shown in Figure 4C. Fig. 5 illustrates.

[0177] In one or more embodiments, at least one silicon thin-film transistor employing a silicon semiconductor with excellent reliability as a semiconductor layer and at least one oxide thin-film transistor employing an oxide semiconductor with low leakage current as a semiconductor layer are used together, so that a display device with high reliability and low power consumption can be provided.

[0178] Furthermore, in one or more embodiments, a voltage applied to a shielding layer under a transistor is controlled according to a channel type of transistor and a semiconductor type, so that optical properties of the transistor can be maintained and / or improved, and thus a high-quality image can be provided.

[0179] For the sake of simplicity, the display device according to one or more embodiments has been described as a display device that incorporates an organic light-emitting device (OLED) as the display device. However, the embodiments are not limited to this, and the display device according to one or more embodiments can be applied to various types of display devices, such as a liquid crystal display (LCD), an electrophoresis display, an inorganic EL display, and the like.

[0180] The display device according to one embodiment can be applied to a portable device, such as a tablet PC, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a gaming device, and a wristwatch. The display device is not limited to portable devices but can be used in large electronic equipment, such as a television (TV) or an external billboard, a personal computer (PC), a notebook, a vehicle navigation unit, and small and medium-sized electronic equipment, such as a camera. Embodiments are not limited to those described above but can be used in other electronic devices without departing from the concept of the present disclosure.

[0181] According to one or more embodiments, a display device may include a transistor that has improved properties, thereby preventing or reducing image quality losses that may be caused by the use of different types of transistors.

Claims

[1] Display device comprising: a control transistor (M1, T1) comprising a first semiconductor layer (21) comprising silicon and a first gate electrode (22); a first switching transistor (M2, T3) comprising a second semiconductor layer (31, A3) comprising an oxide, and a second gate electrode (32); a first shielding layer (120) that overlaps the drive transistor (M1, T1), wherein the first shielding layer (120) is arranged between a substrate (110) and the first semiconductor layer (21); a second shielding layer (130d) that overlaps the first switching transistor (M2, T3), wherein the second shielding layer (130d) is arranged between the substrate (110) and the second semiconductor layer (31, A3); and a first capacitor (Cst), comprising a first electrode (41, Cst1) and a second electrode (43, Cst2), where: the first electrode (41, Cst1) of the first capacitor (Cst) and the first gate electrode (22) of the drive transistor (M1, T1) are formed as one body and the second electrode (43, Cst2) of the first capacitor (Cst) is located at the first gate electrode (22) of the drive transistor (M1, T1) and overlaps the first gate electrode (22) of the drive transistor (M1, T1); and the second electrode (43, Cst2) is positioned on the same layer as the second shielding layer (130d). [2] Display device according to claim 1, wherein one end of the second semiconductor layer (31, A3) is connected to one end of the first semiconductor layer (21) of the control transistor (M1, T1) and the other end of the second semiconductor layer (31, A3) is connected to the first gate electrode (22) of the control transistor (M1, T1). [3] Display device according to claim 1, wherein the second electrode (43, Cst2) and the second shielding layer (130d) comprise the same material. [4] Display device according to claim 1, wherein the second shielding layer (130d) is electrically connected to the second gate electrode (32). [5] Display device according to claim 1, further comprising a second switching transistor (T4) comprising a third semiconductor layer comprising an oxide and a third gate electrode (G4), wherein an equal voltage is applied to the third gate electrode (G4) and the second shielding layer (130d). [6] Display device according to claim 1, further comprising a second capacitor (Cb) and comprising a lower electrode (Cb1) and an upper electrode (Cb2) overlapping the lower electrode (Cb1), wherein the lower electrode (Cb1) of the second capacitor (Cb) is positioned on the same layer as the first gate electrode of the drive transistor (M1, T1) and the upper electrode (Cb2) of the second capacitor (Cb) is positioned on the same layer as the second semiconductor layer (31, A3) of the first switching transistor (M2, T3). [7] Display device according to claim 6, wherein the upper electrode (Cb2) of the second capacitor (Cb) and the second semiconductor layer (31, A3) comprise the same material. [8] Display device according to claim 6, wherein the second shielding layer (130d) is arranged between the lower electrode (Cb1) and the upper electrode (Cb2) of the second capacitor (Cb). [9] Display device according to claim 1, further comprising a current line (161) that overlaps the first shielding layer (120). [10] Display device comprising: a substrate (110); a first insulating layer (11) on the substrate (110); a control transistor (M1, T1) comprising a first gate electrode (22) and a first semiconductor layer (21); a first capacitor (Cst) overlapping the drive transistor (M1, T1) and comprising a first electrode (41, Cst1) and a second electrode (43, Cst2), wherein the first electrode (41, Cst1) is the first gate electrode (22) and the second electrode (43, Cst2) overlaps the first electrode (41, Cst1); a switching transistor comprising a second gate electrode (32) and a second semiconductor layer (31, A3), wherein the second gate electrode (32) is arranged over the first gate electrode (22) of the drive transistor (M1, T1); a second insulating layer (12) arranged between the first gate electrode (22) and the first semiconductor layer (21); a third insulating layer (13) arranged between the first electrode (41, Cst1) and the second electrode (43, Cst2); a fourth insulating layer (14) arranged on the second electrode (43, Cst2), wherein the fourth insulating layer (14) is arranged between the first gate electrode (22) and the second gate electrode (32); a fifth insulating layer (15) arranged between the second gate electrode (32) and the second semiconductor layer (31, A3); a first shielding layer (120) that overlaps the drive transistor (M1, T1), wherein the first shielding layer (120) is arranged between the substrate (110) and the first semiconductor layer (21); a second shielding layer (130d) that overlaps the first switching transistor (M2, T3), wherein the second shielding layer (130d) is arranged between the third insulating layer (13) and the second semiconductor layer (31, A3); a first connecting electrode at the second gate electrode (32), which is connected to the first semiconductor layer (21) and the second semiconductor layer (31, A3); and a second connecting electrode at the second gate electrode (32) which is connected to the first gate electrode (22) and the second semiconductor layer (31, A3). [11] Display device according to claim 10, further comprising a second switching transistor (T4) comprising a third semiconductor layer comprising an oxide and a third gate electrode (G4), wherein the second semiconductor layer (31, A3) and the third semiconductor layer are a body. [12] Display device according to claim 10, further comprising a second capacitor (Cb) comprising a lower electrode (Cb1) and an upper electrode (Cb2) overlapping the lower electrode (Cb1) of the second capacitor (Cb), wherein the lower electrode (Cb1) of the second capacitor (Cb) is positioned on the same layer as the first gate electrode and the upper electrode (Cb2) of the second capacitor (Cb) is positioned on the same layer as the second semiconductor layer (31, A3). [13] Display device according to claim 12, wherein the upper electrode (Cb2) of the second capacitor (Cb) and the second semiconductor layer (31, A3) comprise the same material. [14] Display device according to claim 10, further comprising a current line (161) that overlaps the first shielding layer (120). [15] Display device according to claim 10, wherein the second shielding layer (130d) is electrically connected to the second gate electrode (32). [16] Display device according to claim 12, wherein the second shielding layer (130d) is arranged between the lower electrode (Cb1) and the upper electrode (Cb2) of the second capacitor (Cb). [17] Display device comprising a first pixel and a second pixel in a display area, each of the first pixel and the second pixel comprising the following: a control transistor (M1, T1) comprising a first semiconductor layer (21) comprising silicon and a first gate electrode (22); a first switching transistor (M2, T3) comprising a second semiconductor layer (31, A3) comprising an oxide, and a second gate electrode (32); a first shielding layer (120) that overlaps the drive transistor (M1, T1), wherein the first shielding layer (120) is arranged between a substrate (110) and the first semiconductor layer (21); and a second shielding layer (130d) that overlaps the first switching transistor (M2, T3), wherein the second shielding layer (130d) is arranged between the substrate (110) and the second semiconductor layer (31, A3), where: the first shielding layer (120) of the first pixel and the first shielding layer (120) of the second pixel are spaced apart from each other adjacent to the first pixel; and the second shielding layer (130d) of the first pixel and the second shielding layer (130d) of the second pixel are one body. [18] Display device according to claim 17, further comprising a current line that overlaps first shielding layers (120) and second shielding layers (130d) of the first pixel and the second pixel. [19] Display device according to claim 17, wherein each of the first pixel and the second pixel further comprises a capacitor (Cst) overlapping the drive transistor (M1, T1). [20] Display device according to claim 19, wherein the capacitor (Cst) comprises a first electrode (41, Cst1) and a second electrode (43, Cst2), wherein the second electrode (43, Cst2) is positioned on the same layer as the second shielding layer (130d).

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