Display device

Abstract

Display device, comprising: a substrate (110) that includes a display area (DA) in which a display element is arranged; a first thin-film transistor (T1) located in the display area (DA) and comprising a first semiconductor layer (AS1) containing silicon and a first control electrode (G1) isolated from the first semiconductor layer (AS1); a first intermediate insulating layer (114) covering the first control electrode (G1); a second thin-film transistor (T4) arranged on the first intermediate insulating layer (114) and comprising a second semiconductor layer (AO4) which includes an oxide semiconductor and a second control electrode (G4) which is insulated from the second semiconductor layer (AO4); a second intermediate insulating layer (116) covering the second control electrode (G4); a node connection line (166) which is arranged on the second intermediate insulating layer (116) and is connected to the first control electrode (G1) via a first contact hole (CNT1); a first planarization layer (118) covering the node connection line (166); and a shielding electrode (173) which is arranged on the first planarization layer (118) to overlap the node connection line (166).

Description

BACKGROUND 1. Area

[0001] The present invention relates to a display device and in particular a display device which is controlled by using a thin-film transistor comprising a silicon semiconductor layer and a thin-film transistor comprising an oxide semiconductor layer. 2. Description of the related prior art

[0002] Display devices typically include a display element and a driver circuit to control an electrical signal applied to the display element. The driver circuit includes a thin-film transistor (TFT), a storage capacitor, and a variety of wires.

[0003] To precisely control whether a display element emits light, or to precisely control the degree of light emission, the number of thin-film transistors electrically connected to a display element has increased. Accordingly, active research is being conducted regarding the high integration level and power consumption of display devices. SUMMARY

[0004] One or more embodiments include a display device driven by a thin-film transistor incorporating a silicon semiconductor and a thin-film transistor incorporating an oxide semiconductor, in order to reduce the power consumption of the display device while enabling a high level of integration.

[0005] However, the above task is exemplary and the scope of the present disclosure is not limited to it.

[0006] Additional aspects are partly set out in the following description and partly become apparent from the description or can be learned by implementing the present embodiments of the disclosure.

[0007] According to an embodiment of the present invention, a display device comprises a substrate comprising a display area in which a display element is arranged, a first thin-film transistor arranged in the display area comprising a first semiconductor layer comprising silicon and a first control electrode insulated from the first semiconductor layer, a first intermediate insulating layer covering the first control electrode, a second thin-film transistor arranged on the first intermediate insulating layer comprising a second semiconductor layer comprising an oxide semiconductor and a second control electrode insulated from the second semiconductor layer, a second intermediate insulating layer covering the second control electrode, and a node connection line arranged on the second intermediate insulating layer and connected to the first control electrode via a first contact hole.a first planarization layer covering the node connection line, and a shielding electrode positioned on the first planarization layer to overlap the node connection line.

[0008] According to an embodiment of the present invention, a display device comprises a substrate containing a display area in which a display element is arranged, a first thin-film transistor arranged in the display area and comprising a silicon semiconductor layer and a first control electrode insulated from the silicon semiconductor layer, a first intermediate insulating layer covering the first control electrode, a second thin-film transistor arranged on the first intermediate insulating layer and comprising an oxide semiconductor layer and a second control electrode insulated from the oxide semiconductor layer, and a booster capacitor comprising a lower electrode and an upper electrode. The lower and upper electrodes are arranged on a first layer, and the upper electrode and the oxide semiconductor layer are arranged on a second layer, which is distinct from the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing and other aspects, features and advantages of certain embodiments of the disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which the following applies: Fig. 1 is a schematic view of a display device according to one embodiment; Fig. Figure 2 is a schematic view of a display device according to one embodiment; Fig. Figure 3 is an equivalent circuit diagram of a pixel included in a display device according to embodiments; Fig. Figure 4 is a layout representation showing the positions of a multitude of thin-film transistors and a storage capacitor arranged in a pixel; Fig. 5A is an excerpt view of some of the in Fig. 4 illustrated elements; Fig. Figure 5B is an extract layout representation of some components of a display device according to one embodiment; Fig. 5C is an extract layout representation of some components of a display device according to one embodiment; Fig. Figure 6 is a schematic cross-sectional view of Fig. 4 along line I-I'; Fig. Figure 7 is a schematic cross-sectional view of Fig. 4 along line II-II'; Fig. 8 is a cross-sectional view of a display device according to one embodiment; and Fig. Figure 9 is a cross-sectional view of a display device according to one embodiment. DETAILED DESCRIPTION

[0010] Extensive reference is now made to embodiments, examples of which are illustrated in the accompanying drawings, where the same reference numerals refer to the same elements. In this respect, the present embodiments may have various forms and should not be interpreted as limiting the descriptions set forth in this document. Accordingly, the embodiments are merely described below by reference to the figures to clarify aspects of the present description. In this context, the expression "and / or" includes any and all combinations of one or more of the associated listed elements. Throughout the disclosure, the expression "at least one of a, b, or c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0011] The embodiments are described in more detail below with reference to the accompanying drawings. Components that are identical or correspond to each other are given the same reference numeral, regardless of the figure number, and any repeated description thereof is omitted.

[0012] It is understood that, although the terms "first," "second," etc., may be used in this document to describe different components, these components should not be restricted by these terms. These terms are used only to distinguish one component from another.

[0013] Singular expressions, unless otherwise defined in the context, include plural expressions.

[0014] In the following embodiments, it is further understood that the terms “comprise” and / or “have”, as used in this document, specify the presence of the aforementioned features or components, but do not exclude the presence or addition of one or more other features or components.

[0015] In the following embodiments, it is understood that when a section, such as a layer, area or element, is described as being “on” or “over” another section, it may be directly on or over the other section, or there may be an intermediate section.

[0016] Furthermore, for the sake of clarity, the sizes of elements may be enlarged or reduced in the drawings. In other words, since the sizes and thicknesses of components are arbitrarily illustrated in the drawings for the sake of simplicity, the following embodiments are not limited to them.

[0017] If an embodiment can be implemented in a different way, a predetermined process sequence may differ from one described. For example, two processes described sequentially may be carried out essentially simultaneously or in the opposite order to the described sequence.

[0018] In the following embodiments, when a layer, region, or element is described as "connected," this can be interpreted such that the layer, region, or element may be connected not directly, but also indirectly through other components in between. For example, when a layer, region, element, or the like is described as electrically connected, the layer, region, element, or the like may not be directly electrically connected, but may also be connected indirectly through another layer, region, element, or the like in between.

[0019] Fig. 1 and Fig. Figure 2 shows schematic views of a display device according to embodiments.

[0020] A substrate 110 can be divided into a display area DA, which displays an image, and a circumferential area PA, which is arranged around the display area DA.

[0021] The substrate 110 can comprise various materials, such as glass, metal, or plastic. According to one embodiment, the substrate 110 can comprise a flexible material. A flexible material refers to a substrate that can be easily bent, curved, folded, or rolled. The substrate 110 formed from a flexible material, as described above, can comprise ultrathin glass, metal, or plastic.

[0022] Within the display area DA of substrate 110, pixels PX, containing various display elements such as organic light-emitting diodes (OLEDs), can be arranged. A large number of pixels PX are contained within and can be arranged in various configurations, such as a stripe arrangement, a PenTile arrangement, a mosaic arrangement, or similar configurations, to create an image.

[0023] In a top view, the display area DA can have a rectangular shape, as shown in Fig. 1 illustrates, or a circular shape, as in Fig. Figure 2 illustrates the following. According to another embodiment, the display area DA can have a polygonal shape, such as a triangle, a pentagon, a hexagon, or the like, or an oval shape, an irregular shape, or the like.

[0024] The peripheral area PA of substrate 110 is arranged around the display area DA and can be an area where no image is displayed. Within the peripheral area PA, there can be contact points on which various lines, a printed circuit board, or a chip of an integrated driver circuit (driver IC) are mounted, which transmits an electrical signal to the display area DA.

[0025] For the sake of simplicity, a display device incorporating an organic light-emitting diode (OLED) as a display element is described below. However, the embodiments could be applied to various types of display devices, such as liquid crystal displays, electrophoretic displays, inorganic electroluminescent (EL) displays, or the like.

[0026] Fig. Figure 3 is an equivalent circuit diagram of a pixel included in a display device according to embodiments.

[0027] With reference to Fig. 3 comprises a pixel PX, signal lines SL1, SL2, SLp, SLn, 133 and 171, a plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 connected to the signal lines SL1, SL2, SLp, SLn, 133 and 171, a storage capacitor Cst, a booster capacitor Cbt, an initialization voltage line VIL, a drive voltage line 165 and an organic light-emitting diode OLED as a display element. In some embodiments, at least one of the signal lines SL1, SL2, SLp, SLn, 133 and 171 and the initialization voltage line VIL and / or the drive voltage line 165 can be shared between adjacent pixels PX.

[0028] The thin-film transistors can include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensating thin-film transistor T3, a first initializing thin-film transistor T4, a control-operating thin-film transistor T5, an emission-controlling thin-film transistor T6 and a second initializing thin-film transistor T7.

[0029] Some of the many thin-film transistors T1, T2, T3, T4, T5, T6 and T7 can be an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) and the others can be a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (PMOS).

[0030] For example, as in Fig. As illustrated in Figure 3, the compensating thin-film transistor T3 and the first initializing thin-film transistor T4 can be an NMOS from the multitude of thin-film transistors T1, T2, T3, T4, T5, T6 and T7, and the others can be a PMOS.

[0031] According to another embodiment, the compensating thin-film transistor T3, the first initializing thin-film transistor T4, and the second initializing thin-film transistor T7 can be NMOS transistors from the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and the others can be PMOS transistors. Alternatively, only one of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be NMOS transistors, and the others can be PMOS transistors. Alternatively, all of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be NMOS transistors.

[0032] The signal lines SL1, SL2, SLp, SLn, 133 and 171 can include a first sampling line SL1, which transmits a first sampling signal Sn, a second sampling line SL2, which transmits a second sampling signal Sn', a previous sampling line SLp, which transmits a previous sampling signal Sn-1 to the first initializing thin-film transistor T4, an emission control line 133, which transmits an emission control signal En to the operating control thin-film transistor T5 and the emission control thin-film transistor T6, a next sampling line SLn, which transmits a next sampling signal Sn+1 to the second initializing thin-film transistor T7, and a data line 171, which crosses the first sampling line SL1 and transmits a data signal Dm.

[0033] The drive voltage line 165 transmits a drive voltage ELVDD to the driving thin-film transistor T1 and the initialization voltage line VIL transmits an initialization voltage Vint, which initializes the driving thin-film transistor T1 and a pixel electrode.

[0034] Each of the thin-film transistors T1 to T7 can include a control electrode, a first electrode, and a second electrode. The control electrode can be a gate electrode. Additionally, one of the first and second electrodes can be a source electrode, and the other can be a drain electrode.

[0035] A control electrode of the control thin-film transistor T1 is connected to the storage capacitor Cst, a first control electrode of the control thin-film transistor T1 is electrically connected to the drive voltage line 165 via the operating control thin-film transistor T5, and a second control electrode of the control thin-film transistor T1 is electrically connected to a pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The control thin-film transistor T1 receives the data signal Dm according to a switching operation of the switching thin-film transistor T2 in order to generate a drive current I. OLED to be supplied via the organic light-emitting diode (OLED).

[0036] A switching control electrode of the switching thin-film transistor T2 is connected to the first sampling line SL1, a switching first electrode of the switching thin-film transistor T2 is connected to the data line 171, and a switching second electrode of the switching thin-film transistor T2 is connected to the driving first electrode of the driving thin-film transistor T1 and, via the operating control thin-film transistor T5, to the drive voltage line 165. The switching thin-film transistor T2 is switched on according to the first sampling signal Sn, which is received via the first sampling line SL1, in order to perform a switching operation of transmitting the data signal Dm, which is transmitted to the data line DL, to the driving first electrode of the driving thin-film transistor T1.

[0037] A compensating control electrode of the compensating thin-film transistor T3 is connected to the second scanning line SL2. A compensating second electrode of the compensating thin-film transistor T3 is connected to the driving second electrode of the driving thin-film transistor T1 and is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission-controlling thin-film transistor T6. A compensating first electrode of the compensating thin-film transistor T3 is connected via a node connection line 166 to a first electrode CE1 of the storage capacitor Cst and the driving control electrode of the driving thin-film transistor T1. Additionally, the compensating first electrode is connected to a first initializing second electrode of the first initializing thin-film transistor T4.

[0038] The compensating thin-film transistor T3 is switched on according to the second sampling signal Sn', which is received via the second sampling line SL2, in order to electrically connect the driving control electrode of the driving thin-film transistor T1 with the driving second electrode of it, thereby connecting the driving thin-film transistor T1 by means of a diode.

[0039] A first initializing control electrode of the first initializing thin-film transistor T4 is connected to the previous sampling line SLp. A first initializing first electrode of the first initializing thin-film transistor T4 is connected to a second initializing first electrode of the second initializing thin-film transistor T7 and the initialization voltage line VIL. The first initializing second electrode of the first initializing thin-film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensating first electrode of the compensating thin-film transistor T3, and the driving control electrode of the driving thin-film transistor T1.The first initializing thin-film transistor T4 is switched on according to the previous signal Sn-1, which is received via the previous sampling line SLp, in order to perform an initialization process of transmitting an initialization voltage Vint to the driving control electrode of the driving thin-film transistor T1 in order to initialize a voltage of the driving control electrode of the driving thin-film transistor T1.

[0040] A control electrode of the control thin-film transistor T5 is connected to the emission control line 133, a control first electrode of the control thin-film transistor T5 is connected to the control voltage line 165, and a control second electrode of the control thin-film transistor T5 is connected to the control first electrode of the control thin-film transistor T1 and the switching second electrode of the switching thin-film transistor T2.

[0041] An emission-controlling electrode of the emission-controlling thin-film transistor T6 is connected to the emission-controlling line 133, and an emission-controlling first electrode of the emission-controlling thin-film transistor T6 is connected to the driving second electrode of the driving thin-film transistor T1 and the compensating second electrode of the compensating thin-film transistor T3, and an emission-controlling second electrode of the emission-controlling thin-film transistor T6 is electrically connected to the second initializing second electrode of the second initializing thin-film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0042] The operating-controlling thin-film transistor T5 and the emission-controlling thin-film transistor T6 are switched on simultaneously according to the emission-controlling signal En, which is received via the emission-controlling line 133, so that the drive voltage ELVDD is transferred to the organic light-emitting diode OLED and thus a drive current I OLED through the organic light-emitting diode (OLED).

[0043] A second initializing control electrode of the second initializing thin-film transistor T7 is connected to the next sampling line SLn, and the second initializing second electrode of the second initializing thin-film transistor T7 is connected to the emission-controlling second electrode of the emission-controlling thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initializing first electrode of the second initializing thin-film transistor T7 is connected to the first initializing first electrode of the first initializing thin-film transistor T4 and the initialization voltage line VIL. The second initializing thin-film transistor T7 is switched on according to the next sampling signal Sn+1, which is received via the next sampling line SLn, to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0044] The second initializing thin-film transistor T7 can be connected to the next sampling line SLn, as shown in Fig. Figure 3 illustrates this. According to another embodiment, the second initializing thin-film transistor T7 can be connected to the emission control line 133 to be driven according to the emission control signal En. The positions of the first electrodes and the second electrodes are shown in Figure 3. Fig. 2 can be exchanged according to the type of transistor (p-type or n-type).

[0045] The storage capacitor Cst comprises a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst is connected to the driving electrode of the driving thin-film transistor T1, and the second electrode CE2 of the storage capacitor Cst is connected to the drive voltage line 165. The storage capacitor Cst can store a voltage corresponding to the difference between the voltage of the driving electrode of the driving thin-film transistor T1 and the drive voltage ELVDD.

[0046] The booster capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be connected to the switching control electrode of the switching thin-film transistor T2 and the first sampling line SL1, and the fourth electrode CE4 can be connected to the compensating first electrode of the compensating thin-film transistor T3 and the node connection line 166. The booster capacitor Cbt can raise the voltage of the first node N1 when the first sampling signal Sn, which is fed to the first sampling line SL1, is switched off. When the voltage of the first node N1 is raised as described above, a black level can be clearly expressed.

[0047] The first node N1 can be an area in which the driving control electrode of the driving thin-film transistor T1, the first electrode of the compensating thin-film transistor T3, the second electrode of the first initializing thin-film transistor T4 and the fourth electrode CE4 of the booster capacitor Cbt are connected.

[0048] A detailed operation of each pixel PX according to one embodiment is as follows.

[0049] During an initialization period, in which the previous sampling signal Sn-1 is supplied via the previous sampling line SLp, the first initializing thin-film transistor T4 is switched on according to the previous sampling signal Sn-1 and the driving thin-film transistor T1 is initialized by the initialization voltage Vint supplied via the initialization voltage line VIL.

[0050] During a data programming period, in which the first sampling signal Sn and the second sampling signal Sn' are supplied via the first sampling line SL1 and the second sampling line SL2, the switching thin-film transistor T2 and the compensating thin-film transistor T3 are switched on in response to the first sampling signal Sn and the second sampling signal Sn'. The driving thin-film transistor T1 is connected to the switched-on compensating thin-film transistor T3 via a diode and is forward-biased.

[0051] Then a compensation voltage (Dm + Vth, Vth has a (-) value), which is a result of subtracting a threshold voltage Vth of the driving thin-film transistor T1 based on the data signal Dm supplied via data line 171, is applied to the driving control electrode of the driving thin-film transistor T1.

[0052] The control voltage ELVDD and the compensation voltage (Dm+Vth) are applied to opposite electrodes of the storage capacitor Cst and a charge corresponding to a voltage difference between the opposite electrodes of the storage capacitor Cst is stored in the storage capacitor Cst.

[0053] During an emission period, the operating-controlling thin-film transistor T5 and the emission-controlling thin-film transistor T6 are switched on according to an emission-controlling signal En supplied by the emission-controlling line 133. The control current I OLED is generated according to a voltage difference between a voltage of the driving control electrode of the driving thin-film transistor T1 and the drive voltage ELVDD, and the drive current I OLED The current flows through the organic light-emitting diode OLD and the emission-controlling thin-film transistor T6.

[0054] In the present embodiment, at least one of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 includes a semiconductor layer containing an oxide (i.e., an oxide semiconductor layer), and the others include a semiconductor layer containing silicon (i.e., a silicon semiconductor layer).

[0055] Specifically, a driving thin-film transistor that directly affects the brightness of a display device is configured to include a semiconductor layer formed from polycrystalline silicon, which has high reliability, and a high-resolution display device can be implemented in this way.

[0056] An oxide semiconductor exhibits high carrier mobility and low leakage current, meaning that the voltage drop across it is not significant even over a relatively long drive period. This means that even during low-frequency drive operation, changes in image color due to voltage drop are minimal, allowing for low-frequency control.

[0057] If the oxide semiconductor has a low leakage current, at least one of the compensating thin-film transistor T3 and the first initializing thin-film transistor T4, which are connected to the driving control electrode of the driving thin-film transistor T1, can incorporate an oxide semiconductor in order to prevent a leakage current that can flow to the driving control electrode and at the same time reduce power consumption.

[0058] Fig. Figure 4 is a layout representation of the positions of a plurality of thin-film transistors and a storage capacitor arranged in a pixel circuit of a display device, according to one embodiment. Fig. 5A and Fig. 5C are excerpt views from some of the in Fig. 4 illustrated elements. Fig. Figure 5B is an extract layout representation of some components of a display device according to one embodiment. Fig. Figure 6 is a schematic cross-sectional view along line II' from Fig. 4'. Fig. Figure 7 is a schematic cross-sectional view along line II-II' from Fig. 4'.

[0059] First, with reference to the Fig. 4 and Fig. 5A The pixel circuit of the display device according to one embodiment comprises the first scanning line SL1, the second scanning line SL2, the previous scanning line SLp, the next scanning line SLn, the emission control line 133, and the initialization voltage line VIL, extending in a first direction, and the data line 171 and the drive voltage line 165, extending in a second direction that intersects the first direction. The initialization voltage line VIL may include a first initialization voltage line 125 and a second initialization voltage line 145.

[0060] Furthermore, the pixel circuit can include the driving thin-film transistor T1, the switching thin-film transistor T2, the compensating thin-film transistor T3, the first initializing thin-film transistor T4, the operating-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6, the second initializing thin-film transistor T7, the storage capacitor Cst and the booster capacitor Cbt.

[0061] According to one embodiment, the driving thin-film transistor T1, the switching thin-film transistor T2, the operation-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6 and the second initializing thin-film transistor T7 can be a thin-film transistor with a silicon semiconductor (e.g. silicon or polycrystalline silicon).

[0062] Furthermore, the compensating thin-film transistor T3 and the first initializing thin-film transistor T4 can be a thin-film transistor containing an oxide semiconductor.

[0063] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operating-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6, and the second initializing thin-film transistor T7 are arranged on the same layer and contain the same material. For example, the semiconductor layers can contain polycrystalline silicon.

[0064] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operating-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6 and the second initializing thin-film transistor T7 can be arranged on the buffer layer 111 (see Fig. 6), which is arranged on substrate 110.

[0065] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operating-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6 and the second initializing thin-film transistor T7 can be interconnected and can be bent into different shapes.

[0066] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operating-controlling thin-film transistor T5, the emission-controlling thin-film transistor T6, and the second initializing thin-film transistor T7 can each include a channel region and a source and a drain region on two opposite sides of the channel region. For example, the source and drain regions can be doped with impurities, and the impurities can be N-type or P-type. The source and drain regions can each correspond to a first electrode and a second electrode. The source and drain regions can be interchanged according to the characteristics of a transistor. Subsequently, the terms "source region" and "drain region" are used instead of a first electrode or a second electrode.

[0067] The driving thin-film transistor T1 includes a driving semiconductor layer AS1 and the driving control electrode G1. The driving semiconductor layer AS1 includes a driving channel region A1, a driving source region S1, and a driving drain region D1 on two opposite sides of the driving channel region A1. The driving semiconductor layer AS1 has a curved shape, such that the driving channel region A1 is longer than the other channel regions A2 to A7. For example, if the driving semiconductor layer AS1 has a shape including multiple bends, such as an omega shape or an "S", a long channel length can be provided in a relatively small space.If the driving channel region A1 has a relatively long length, the drive area of ​​a gate voltage applied to the driving control electrode G1 is extended, thereby finely controlling the gradation of light emitted by the organic light-emitting diode (OLED) and improving the display quality. In some embodiments, the driving semiconductor layer AS1 can be provided in a linear form instead of a curved one. The driving control electrode G1 can be of an island type and includes a first gate insulating layer 112 (see figure 112) to isolate the driving channel region A1. Fig. 6) to overlap in between.

[0068] The storage capacitor Cst can be arranged to overlap the driving thin-film transistor T1. The storage capacitor Cst includes the first electrode CE1 and the second electrode CE2. The driving control electrode G1 can function not only as the control electrode of the driving thin-film transistor T1, but also as the first electrode CE1 of the storage capacitor Cst. That is, the driving control electrode G1 and the first electrode CE1 can be considered a single unit. The second electrode CE2 of the storage capacitor Cst is provided to connect the first electrode CE1 with a second gate insulating layer 113 (see Fig. 6) to overlap in between. In this case, the second gate insulating layer 113 can function as a dielectric layer of the storage capacitor Cst.

[0069] The second electrode CE2 can include a memory opening section SOP. The memory opening section SOP is formed by removing a section of the second electrode CE2 and can have a closed shape. The node connection line 166 can be connected to the first electrode CE1 via a first contact hole CNT1 located in the memory opening section SOP. The second electrode CE2 can be connected to the drive voltage line 165 via a seventh contact hole CNT7. The second electrode CE2 can extend in the first direction to transmit the drive voltage ELVDD in the first direction. Accordingly, a plurality of drive voltage lines 165 and a plurality of second electrodes CE2 can form a network structure in the display area DA.

[0070] The switching thin-film transistor T2 comprises a switching semiconductor layer and the switching control electrode G2. The switching semiconductor layer includes a switching channel region A2, a switching source region S2, and a switching drain region D2 on two sides of the switching channel region A2. The switching source region S2 is connected to data line 171 via a contact hole and a connecting electrode, and the switching drain region D2 is connected to the driving source region S1. The switching control electrode G2 is included as a section of the first sampling line SL1.

[0071] The control-controlled thin-film transistor T5 comprises a control-controlled semiconductor layer and the control-controlled electrode G5. The control-controlled semiconductor layer includes a control-controlled channel region A5, a control-controlled source region S5, and a control-controlled drain region D5 on two sides of the control-controlled channel region A5. The control-controlled source region S5 is connected to the drive voltage line 165 via an eighth contact hole CNT8, and the control-controlled drain region D5 can be connected to the control-controlled source region S1. The control-controlled electrode G5 is included as a section of the emission control line 133.

[0072] The emission-controlling thin-film transistor T6 comprises an emission-controlling semiconductor layer and the emission-controlling electrode G6. The emission-controlling semiconductor layer includes an emission-controlling channel region A6, an emission-controlling source region S6, and an emission-controlling drain region D6 on two sides of the emission-controlling channel region A6. The emission-controlling source region S6 is connected to the driving drain region D1, and the emission-controlling drain region D6 can be connected to a first connection electrode 167 via a sixth contact hole CNT6. The first connection electrode 167 can be connected to a pixel electrode 310 via an upper connection electrode 177, which is arranged in a different layer from the first connection electrode 167 (see Fig. 7) the organic light-emitting diode (OLED). The emission control electrode G6 is included as a section of the emission control line 133.

[0073] The second initializing thin-film transistor T7 includes a second initializing semiconductor layer and the first initializing control electrode G7. The second initializing semiconductor layer includes a second initializing channel region A7, a second initializing source region S7, and a second initializing drain region D7 on two sides of the second initializing channel region A7. The second initializing source region S7 can be connected to the first initializing voltage line 125, which is located in the same layer as the second initializing semiconductor layer, and the second initializing drain region D7 can be connected to the emission-controlling drain region D6. The second initializing control electrode G7 is included as a section of the next sampling line SLn.

[0074] A first intermediate insulating layer 114 (see Fig. 6) is arranged on the thin-film transistors T1, T2, T5, T6 and T7, which contain a silicon semiconductor, and the thin-film transistors T3 and T4, which contain an oxide semiconductor, may be arranged on the first intermediate insulating layer 114.

[0075] The semiconductor layers of the compensating thin-film transistor T3 and the first initializing thin-film transistor T4 can be arranged on the same layer and contain the same material. For example, the semiconductor layers can contain an oxide semiconductor.

[0076] The semiconductor layers can include a channel region and a source region and drain region on either side of the channel region. For example, the source region and drain region can be areas with a carrier concentration that is increased by plasma processing. The source region and drain region can each correspond to a first electrode and a second electrode, respectively. Subsequently, the terms "source region" and "drain region" are used instead of "first electrode" or "second electrode."

[0077] The compensating thin-film transistor T3 includes a compensating semiconductor layer AO3, which contains an oxide semiconductor, and the compensating control electrode G3. The compensating semiconductor layer AO3 includes a compensating channel region A3, a compensating source region S3, and a compensating drain region D3 on two sides of the compensating channel region A3. The compensating source region S3 can be connected to the driving control electrode G1 via the node connection line 166 by means of a bridge. One end of the node connection line 166 can be connected to the compensating source region S3 via a second contact hole CNT2, and the other end of the node connection line 166 can be connected to the driving control electrode G1 via the first contact hole CNT1.Furthermore, the compensating source region S3 can be connected to the first initializing drain region D4, which is located in the same layer. The compensating drain region D3 can be connected via a second connection electrode 168 to the driving semiconductor layer AS1 of the driving thin-film transistor T1 and the emission-controlling semiconductor layer of the emission-controlling thin-film transistor T6. The compensating control electrode G3 is included as a section of the second scanning line SL2.

[0078] The first initializing thin-film transistor T4 comprises a first initializing semiconductor layer AO4, which includes an oxide semiconductor, and the first initializing control electrode G4. The first initializing semiconductor layer AO4 includes a first initializing channel region A4, a first initializing source region S4, and a first initializing drain region D4 on two sides of the first initializing channel region A4. The first initializing source region S4 can be connected to the second initializing voltage line 145 via a ninth contact hole CNT9, and the first initializing drain region D4 can be connected to the driving control electrode G1 via a bridge connected to the node link line 166. The first initializing control electrode G4 is included as a section of the previous sampling line SLp.

[0079] A third gate insulating layer 115 (see Fig. 6) is connected between the compensating semiconductor layer AO3 and the compensating control electrode G3 and between the first initializing semiconductor layer AO4 and the first initializing control electrode G4 to correspond to the respective channel areas.

[0080] The third electrode, CE3, which is an electrode of the booster capacitor Cbt, is included as a section of the first scanning line SL1 to be connected to the switching control electrode G2. The fourth electrode, CE4, of the booster capacitor Cbt is arranged to overlap the third electrode, CE3, and may include an oxide semiconductor. The fourth electrode, CE4, may be located on the same layer as the compensating semiconductor layer AO3 of the compensating thin-film transistor T3 and the first initializing semiconductor layer of the first initializing thin-film transistor T4, thus forming a region between the compensating semiconductor layer AO3 and the first initializing semiconductor layer AO4. Alternatively, the fourth electrode, CE4, may extend from the first initializing semiconductor layer AO4.

[0081] The second intermediate insulating layer 116 (see Fig. 6) can be arranged on the compensating thin-film transistor T3 and the first initializing thin-film transistor T4, which contain the oxide semiconductor, and the drive voltage line 165, the node connection line 166 and the first and second connection electrodes 167 and 168 can be arranged on the second intermediate insulating layer 116.

[0082] In the present embodiment, a first planarization layer 118 (see Fig. 6) be arranged to cover the control voltage line 165, and the data line 171 and a shielding electrode 173 can be arranged on the first planarization layer 118.

[0083] The shielding electrode 173 can be positioned above the node connection line 166. If the shielding electrode 173 is not positioned above the node connection line 166, the node connection line 166 can have a coupling capacitance with the data line 171 and / or the pixel electrode 310 of the display element (see Fig. 6) or the like, which are arranged across the node connection line 166. Accordingly, the thin-film transistors connected to the node connection line 166 can be influenced by the coupling capacitance.

[0084] According to the present embodiment, the shielding electrode 173 can be arranged above the node connection line 166, and a constant voltage can be applied to the shielding electrode 173 to minimize the influence due to coupling capacitance. In some embodiments, the shielding electrode 173 can be connected to the control voltage line 165 via a third contact hole CNT3. Accordingly, a control voltage ELVDD can be applied to the shielding electrode 173.

[0085] In some embodiments, the shielding electrode 173 can be configured to completely cover the node connection line 166. In some embodiments, the shielding electrode 173 can be arranged to overlap at least a section of the driving thin-film transistor T1, the compensating thin-film transistor T3, and / or the first initializing thin-film transistor T4.

[0086] Furthermore, the control voltage line 165 can be used in some embodiments, such as in Fig. Figure 5A illustrates that the control voltage line 165 is arranged to at least partially overlap data line 171. Furthermore, a section of the control voltage line 165 can be located between data line 171 and the node connection line 166. Because the control voltage line 165 is arranged to overlap data line 171 and is located below data line 171, it prevents components located below or adjacent to data line 171 from being affected by a data signal from data line 171.

[0087] In some embodiments, the control voltage line 165, as shown in Fig. Figure 5B illustrates how the control voltage line 165 should be arranged so as not to overlap the data line 171. Even if the control voltage line 165 does not overlap the data line 171, because the control voltage line 165 is arranged in a top view between the data line 171 and the node connection line 166, it is possible to prevent a data signal from influencing the node connection line 166 laterally. Furthermore, because the shielding electrode 173 is arranged on an upper surface of the node connection line 166, it is possible to prevent a data signal from influencing the node connection line 166 from above.

[0088] According to one embodiment, the first scanning line SL1, the next scanning line SLn and the emission-controlling line 133 can be included in the same layer as the controlling control electrode G1 and can be made of the same material as the controlling control electrode G1.

[0089] According to one embodiment, some of the lines can be comprised as two conductive lines arranged in different layers. For example, the second scanning line SL2 can comprise a lower scanning line 143 and an upper scanning line 153 arranged in different layers. The lower scanning line 143 can be in the same layer as the second electrode CE2 of the storage capacitor Cst and comprise the same material, and the upper scanning line 153 can be arranged on the third gate insulating layer 115 (see Fig. 6) The lower scanning line 143 can be arranged to at least partially overlap the upper scanning line 153. Since the lower scanning line 143 and the upper scanning line 153 correspond to a section of the compensating control electrode of the compensating thin-film transistor T3, the compensating thin-film transistor T3 can have a dual-gate structure incorporating two control electrodes G3a and G3b (see Fig. 7), which are arranged in the upper and lower sections of the semiconductor layer, respectively. For example, the two control electrodes G3a and G3b correspond to the lower scanning line 143 and the upper scanning line 153, respectively.

[0090] Additionally, the previous sampling line SLp can include a lower previous sampling line 141 and an upper previous sampling line 151, which are arranged on different layers. The lower previous sampling line 141 can be located in the same layer as the second electrode CE2 of the storage capacitor Cst and may be made of the same material, while the upper previous sampling line 151 can be located on the third gate insulating layer 115 (see Fig. 6) The lower previous sampling line 141 can be arranged to at least partially overlap the upper previous sampling line 151. Since the lower previous sampling line 141 and the upper previous sampling line 151 correspond to a section of the first initializing control electrode G4 of the first initializing thin-film transistor T4, the first initializing thin-film transistor T4 can have a dual-gate structure incorporating two control electrodes G4a and G4b (see Fig. 6), which are arranged in the upper and lower sections of the semiconductor layer, respectively. For example, the two control electrodes G4a and G4b correspond to the lower previous scanning line 141 and the upper previous scanning line 151.

[0091] With reference to Fig. 5C can extend the lower preceding sampling line 141 to correspond to the first initializing thin-film transistor T4. The preceding section can also be considered a second lower control electrode G4a (see Fig. 6) of the first initializing thin-film transistor T4. The foregoing section is arranged to completely cover a channel region of the first initializing semiconductor layer AO4 beneath the first initializing semiconductor layer AO4, and thus light that can be applied from below the substrate 110 can be blocked by the foregoing section.

[0092] Similarly, the lower scanning line 143 can protrude to correspond to the compensating thin-film transistor T3. The preceding section can be considered a first lower control electrode G3a (see Fig. 7) of the compensating thin-film transistor T3. As described above, the compensating semiconductor layer AO3 can be stably controlled because the compensating thin-film transistor T3 includes a first upper control electrode G3b and a first lower control electrode G3a, to which an identical signal is applied. Furthermore, the preceding section is arranged to completely cover a channel region of the compensating semiconductor layer AO3 beneath the compensating thin-film transistor T3, thus blocking light that can be applied from below the substrate 110.

[0093] The initialization voltage line VIL can include the first initialization voltage line 125 and the second initialization voltage line 145, which are located on different layers. The first initialization voltage line 125 can be located on the same layer as the semiconductor layer of the driving thin-film transistor T1 and be made of the same material, and the second initialization voltage line 145 can be located on the same layer as the second electrode CE2 of the storage capacitor Cst and be made of the same material.

[0094] The structure of a display device according to one embodiment is described in detail below with reference to the Fig. 6 and Fig. 7 described according to a stacking order. In the Fig. 6 and Fig. Figure 7 mainly illustrates the structures of the driving thin-film transistor T1, the compensating thin-film transistor T3, the first initializing thin-film transistor T4, the emission-controlling thin-film transistor T6, the storage capacitor Cst and the booster capacitor Cbt, and some components may be omitted.

[0095] With reference to the Fig. 6 and Fig. According to one embodiment, the display device comprises the substrate 110, a first thin-film transistor (e.g., the driving thin-film transistor T1) comprising a silicon semiconductor, a second thin-film transistor (e.g., the first initializing thin-film transistor T4) comprising an oxide semiconductor, the node connection line 166, which connects a first control electrode of the first thin-film transistor to a second semiconductor layer of the second thin-film transistor, and the shielding electrode 173, which is arranged to overlap the node connection line 166. The shielding electrode 173 can be connected to the drive voltage line 165 via a contact hole (e.g., a third contact hole CNT3). The first thin-film transistor can be the driving thin-film transistor T1, and the second thin-film transistor can be the first initializing thin-film transistor T4.The second thin-film transistor can also be the compensating thin-film transistor T3, which has a semiconductor layer containing an oxide semiconductor. The semiconductor layer of thin-film transistor T3 can be connected to the control electrode G1 of the controlling thin-film transistor T1 via the node connection line 166.

[0096] Furthermore, the display device can also include various insulating layers, such as the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 115, the first intermediate insulating layer 114, the second intermediate insulating layer 116, the first planarizing layer 118 and a second planarizing layer 119.

[0097] The substrate 110 can comprise a glass material, a ceramic material, a metal material, or a flexible or bendable material. If the substrate 110 is flexible or bendable, it can comprise a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 110 can comprise a single-layer or multi-layer structure of the material described above and can further comprise an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 110 can have an organic / inorganic / organic material structure.

[0098] The buffer layer 111 can perform a function of increasing the smoothness of an upper surface of the substrate 110 and the buffer layer 111 can be an oxide layer, such as silicon dioxide (SiOx), and / or a nitride layer, such as silicon nitride (SiN). x ) or silicon oxynitride (SiON).

[0099] A barrier layer (not shown) may also be included between the substrate 110 and the buffer layer 111. The barrier layer can prevent or minimize the penetration of impurities from the substrate 110 into a silicon semiconductor layer. The barrier layer may contain an inorganic material, such as an oxide or a nitride, and / or an organic material, and may have a single-layer or multi-layer structure containing an inorganic and an organic material.

[0100] The controlling semiconductor layer AS1 and an emission-controlling semiconductor layer AS6, which are semiconductor layers containing a silicon semiconductor, can be arranged on the buffer layer 111.

[0101] The driving semiconductor layer AS1 can include the driving source region S1 and the driving drain region D1, which are doped with impurities to exhibit conductivity and are spaced apart from each other, and the driving channel region A1, which is located between the driving source region S1 and the driving drain region D1. The driving source region S1 and the driving drain region D1 can each correspond to the first and second electrodes of the driving thin-film transistor T1, and the positions of the driving source region S1 and the driving drain region D1 can be interchanged.

[0102] The emission-controlling semiconductor layer AS6 can include the emission-controlling source region S6 and the emission-controlling drain region D6, which are doped with impurities to exhibit conductivity and are arranged at a distance from each other, and the emission-controlling channel region A6, which is located between the emission-controlling source region S6 and the emission-controlling drain region D6. The emission-controlling source region S6 and the emission-controlling drain region D6 can each correspond to the first and second electrodes of the emission-controlling thin-film transistor T6, and the positions of the emission-controlling source region S6 and the emission-controlling drain region D6 can be interchanged.

[0103] The control electrode G1 is arranged on the control semiconductor layer AS1, and the emission control electrode G6 is arranged on the emission control semiconductor layer AS6. The first gate insulating layer 112 can be arranged between the control semiconductor layer AS1 and the control electrode G1, and between the emission control semiconductor layer AS6 and the emission control electrode G6.

[0104] The first gate insulating layer 112 can contain an inorganic material that includes oxide or nitride. For example, the first gate insulating layer 112 can contain at least one of silicon dioxide (SiO2) or silicon nitride (SiN2). xThe control electrode G1 is arranged to overlap the control channel area A1 and may contain a single layer or multiple layers, including at least one of molybdenum (Mo), copper (Cu), and titanium (Ti). The control electrode G1 is arranged to overlap the control channel area A1 and may contain a single layer or multiple layers, including at least one of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0105] The storage capacitor Cst can be arranged on the semiconductor layer of the driving thin-film transistor T1. The storage capacitor Cst comprises the first electrode CE1 and the second electrode CE2. The second gate insulating layer 113 can be arranged between the first electrode CE1 and the second electrode CE2. The driving control electrode G1 can function not only as the control electrode of the driving thin-film transistor T1, but also as the first electrode CE1 of the storage capacitor Cst. That is, the driving control electrode G1 and the first electrode CE1 can be considered a single unit.

[0106] The second gate insulating layer 113 can contain an inorganic material that includes oxide or nitride. For example, the second gate insulating layer 113 can contain at least one of silicon dioxide (SiO2) or silicon nitride (SiN). x), silicon oxynitride (SiON), aluminium oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and zinc oxide (ZnO2).

[0107] The second electrode CE2 is positioned on the second gate insulating layer 113 to overlap the first electrode CE1. The second electrode CE2 may include a storage opening section SOP. The storage opening section SOP is formed by removing a portion of the second electrode CE2 and may have a closed shape. The first contact hole CNT1, defined in the second gate insulating layer 113, may be located within the storage opening section SOP. The driving control electrode G1 and the node connection line 166 may be connected via the first contact hole CNT1. The second electrode CE2 may contain at least one of molybdenum (Mo), copper (Cu), and titanium (Ti) and may comprise a single layer or multiple layers.

[0108] The first intermediate insulating layer 114 can be arranged on the second electrode CE2. The first intermediate insulating layer 114 can contain an inorganic material that includes oxide or nitride. For example, the first intermediate insulating layer 114 can contain at least one of silicon dioxide (SiO2) or silicon nitride (SiN2). x ), silicon oxynitride (SiON), aluminium oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and zinc oxide (ZnO2).

[0109] The compensating semiconductor layer AO3 and the first initializing semiconductor layer AO4, which includes an oxide semiconductor, can be arranged on the first intermediate insulating layer 114. The compensating semiconductor layer AO3 can include the compensating source region S3 and the compensating drain region D3, which are conductive and spaced apart from each other, and the compensating channel region A3 between the compensating source region S3 and the compensating drain region D3.

[0110] The first initializing semiconductor layer AO4 can include the first initializing source region S4 and the first initializing drain region D4, which are conductive and spaced apart from each other, and the first initializing channel region A4 between the first initializing source region S4 and the first initializing drain region D4.

[0111] The compensating semiconductor layer AO3 and the first initializing semiconductor layer AO4 can contain a Zn oxide-based material and can, for example, include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like. In some embodiments, the compensating semiconductor layer AO3 and the first initializing semiconductor layer AO4 can contain In-Ga-Zn-O(IGZO), In-Sn-Zn-O(ITZO), or In-Ga-Sn-Zn-O(IGTZO) semiconductors containing metals such as In, Ga, and tin (Sn) in ZnO.

[0112] The compensating source region S3, the compensating drain region D3, the first initializing source region S4, and the first initializing drain region D4 can be configured to exhibit conductivity by adjusting the carrier concentration in an oxide semiconductor. For example, the compensating source region S3, the compensating drain region D3, the first initializing source region S4, and the first initializing drain region D4 can be formed by increasing the carrier concentration of an oxide semiconductor, by performing plasma processing on the oxide semiconductor, by using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0113] The first lower control electrode G3a can be located below the compensating semiconductor layer AO3, and the first upper control electrode G3b can be located on top of the compensating semiconductor layer AO3. This means that the compensating thin-film transistor T3 can incorporate a dual control electrode. As described above, the compensating semiconductor layer AO3 can be stably controlled because the compensating thin-film transistor T3 incorporates the first upper control electrode G3b and the first lower control electrode G3a, each receiving an identical signal. Furthermore, light that can be applied from below the substrate 110 can be blocked by using the first lower control electrode G3a.

[0114] The second lower control electrode G4a can be located below the first initializing semiconductor layer AO4, and a second upper control electrode G4b can be located on top of the first initializing semiconductor layer AO4. This means that the first initializing thin-film transistor T4 can incorporate a dual control electrode. As described above, the first initializing semiconductor layer AO4 can be stably controlled because the first initializing thin-film transistor T4 incorporates the second upper control electrode G4b and the second lower control electrode G4a, each receiving the same signal. Furthermore, light that can be applied from below the substrate 110 can be blocked by using the second lower control electrode G4a.

[0115] The first intermediate insulating layer 114 can be arranged between the first lower control electrode G3a and the compensating semiconductor layer AO3, and between the second lower control electrode G4a and the first initializing semiconductor layer AO4. The first lower control electrode G3a and the second lower control electrode G4a can be arranged on the same layer (e.g., the second gate insulating layer 113) as the second electrode CE2 of the storage capacitor Cst and can be made of the same material.

[0116] The third gate insulating layer 115 can be arranged between the compensating semiconductor layer AO3 and the first upper control electrode G3b, and between the first initializing semiconductor layer AO4 and the second upper control electrode G4b. The first upper control electrode G3b is arranged to overlap the compensating channel region A3 and is insulated from the compensating semiconductor layer AO3 by the third gate insulating layer 115. The second upper control electrode G4b is arranged to overlap the first initializing channel region A4 and is insulated from the first initializing semiconductor layer AO4 by the third gate insulating layer 115.

[0117] The third gate insulating layer 115 can be formed by the same masking process as the first upper control electrode G3b and the second upper control electrode G4b. In this case, the third gate insulating layer 115 can be formed in the same shape as the first upper control electrode G3b and the second upper control electrode G4b.

[0118] The third gate insulating layer 115 can contain an inorganic material that includes an oxide or a nitride. For example, the third gate insulating layer 115 can contain at least one of silicon dioxide (SiO2) or silicon nitride (SiN2). xThe first upper control electrode G3b and the second upper control electrode G4b can be arranged on the third gate insulating layer 115 and can contain at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may comprise a single layer or multiple layers.

[0119] The booster capacitor Cbt includes the third electrode CE3 and the fourth electrode CE4. The third electrode CE3 and the driving control electrode G1 can be located on the same layer (e.g., the first gate insulating layer 112). The fourth electrode CE4 can extend from the first initializing semiconductor layer 4 or the compensating semiconductor layer AO3. This means that the fourth electrode CE4 can contain an oxide semiconductor and be located on the first intermediate insulating layer 114. The second gate insulating layer 113 and the first intermediate insulating layer 114 can be located between the third electrode CE3 and the fourth electrode CE4, and the second gate insulating layer 113 and the first intermediate insulating layer 114 can function as a dielectric layer of the booster capacitor Cbt.

[0120] The fourth electrode CE4 of the booster capacitor Cbt can be connected to the node connection line 166 to be electrically connected to the driving control electrode G1. Accordingly, a black gradient can be clearly indicated when the booster capacitor Cbt increases a voltage of the first node N1 (see Fig. 3) when the first sampling signal Sn, which is fed to the first sampling line SL1, is switched off.

[0121] The second intermediate insulating layer 116 covers thin-film transistors containing an oxide semiconductor, such as the compensating thin-film transistor T3, the first initializing thin-film transistor T4, or the like. The second intermediate insulating layer 116 can be arranged on the first upper control electrode G3b and the second upper control electrode G4b, and the drive voltage line 165, the node connection line 166, and the first and second connection electrodes 167 and 168 can be arranged on the second intermediate insulating layer 116.

[0122] The second intermediate insulating layer 116 can contain an inorganic material that includes oxide or nitride. For example, the second intermediate insulating layer 116 can contain at least one of silicon dioxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminium oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and zinc oxide (ZnO2).

[0123] The control voltage line 165, the node connection line 166, and the first and second connection electrodes 167 and 168 can comprise a highly conductive material, such as metal or conductive oxide. For example, the control voltage line 165, the node connection line 166, and the first and second connection electrodes 167 and 168 can comprise a single layer or multiple layers containing at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the control voltage line 165, the node connection line 166, and the first and second connection electrodes 167 and 168 can comprise a triple layer containing Ti, Al, and Ti (Ti / Al / Ti) arranged sequentially.

[0124] One end of the node connection line 166 can be connected to the driving control electrode G1 via the first contact hole CNT1. The first contact hole CNT1 can extend through the second intermediate insulating layer 116, the first intermediate insulating layer 114, and the second gate insulating layer 113, thus exposing the driving control electrode G1. Since a section of the node connection line 166 is inserted into the first contact hole CNT1, the node connection line 166 can be electrically connected to the driving control electrode G1.

[0125] Meanwhile, the first contact hole CNT1 can be located away from the edges of the storage opening section SOP in the storage opening section SOP of the second electrode CE2, and accordingly, the node connecting line 166, which is inserted into the first contact hole CNT1, can be electrically isolated from the second electrode CE2.

[0126] The other end of the node connection line 166 can be connected via the second contact hole CNT2 to an oxide semiconductor layer, for example the fourth electrode CE4 of the booster capacitor Cbt or the first initializing semiconductor layer AO4. The second contact hole CNT2 can pass through the second intermediate insulating layer 116 to align with the oxide semiconductor layer of the first initializing thin-film transistor T4.

[0127] With reference to Fig. 7. The first junction electrode 167 can be connected to the emission-controlling semiconductor layer AS6 via the sixth contact hole CNT6. The sixth contact hole CNT6 can extend through the second intermediate insulating layer 116, the first intermediate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112, exposing a section of the emission-controlling semiconductor layer AS6. Since a section of the first junction electrode 167 is inserted into the sixth contact hole CNT6, the first junction electrode 167 can be electrically connected to the emission-controlling semiconductor layer AS6. The first junction electrode 167 can be connected to the pixel electrode 310 to transmit a signal applied via the emission-controlling thin-film transistor T6 to the pixel electrode 310.

[0128] One end of the second connecting electrode 168 can be connected to the emission-controlling semiconductor layer AS6 via a fourth contact hole CNT4. The other end of the second connecting electrode 168 can be connected to the compensating semiconductor layer AO3 via a fifth contact hole CNT5.

[0129] The first planarization layer 118 is located on the node connection line 166, the drive voltage line 165, and the first and second connection electrodes 167 and 168. The first planarization layer 118 can comprise an organic material, such as acrylic, benzocyclobutene (BCB), PI, or hexamethyldisiloxane (HMDSO). Alternatively, the first planarization layer 118 can comprise an inorganic material. The first planarization layer 118 acts as a protective layer covering the thin-film transistors T1 to T7, and an upper portion of the first planarization layer 118 is planarized. The first planarization layer 118 can comprise a single layer or multiple layers.

[0130] The data line 171, the shielding electrode 173, and the upper connecting electrode 177 can be arranged on the first planarization layer 118. The data line 171 can partially overlap the drive voltage line 165. A section R1 of the drive voltage line 165 can be located, in a top view, between the data line 171 and the node connecting line 166. For example, section R1 of the drive voltage line 165 can overlap a region between the data line 171 and the node connecting line 166. Accordingly, the drive voltage line 165 can reduce coupling in a horizontal direction between the node connecting line 166 and the data line 171.

[0131] The shielding electrode 173 can be positioned above the node connection line 166 to overlap it. Accordingly, the shielding electrode 173 can reduce coupling in a vertical direction between the node connection line 166 and the data line 171.

[0132] The upper connecting electrode 177 can be connected to the first connecting electrode 167 via a contact hole defined in the first planarization layer 118. The data line 171, the shielding electrode 173, and the upper connecting electrode 177 can contain a conductive material, such as Al, Cu, and Ti, and can comprise a single layer or multiple layers.

[0133] The organic light-emitting diode OLED, which includes the pixel electrode 310, an opposing electrode 330 and an intermediate layer 320, which is arranged between them and includes an emission layer, can be located on the second planarization layer 119.

[0134] The pixel electrode 310 can be connected to the upper connecting electrode 177 via a contact hole defined in the second planarization layer 119 and can be connected to the emission-controlling drain region D6 of the emission-controlling thin-film transistor T6 via the upper connecting electrode 177 and the first connecting electrode 167.

[0135] A pixel-defining layer 120 can be arranged on the second planarization layer 119. The pixel-defining layer 120 has an opening corresponding to each subpixel and is an opening that exposes a central section of at least the pixel electrode 310, thereby defining a pixel. Furthermore, the pixel-defining layer 120 can increase the distance between an edge of the pixel electrode 310 and the opposite electrode 330 above the pixel electrode 310 to prevent arcing or the like at the edge of the pixel electrode 310. The pixel-defining layer 120 can contain an organic material, such as PI or HMDSO.

[0136] The interlayer 320 of the organic light-emitting diode (OLED) can comprise a low molecular weight material or a polymer. If the interlayer 320 comprises a low molecular weight material, it can have a structure in which a hole injection layer (HIL), hole transport layer (HTL), emission layer (EML), electron transport layer (ETL), electron injection layer (EIL), or the like are stacked in a single or complex structure, and can include various organic materials, including copper phthalocyanine (CuPc), N,N-di(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), Tris-8-hydroxyquinoline aluminum (Alq3), or the like. The layers described above can be formed using a vacuum deposition process.

[0137] If the intermediate layer 320 contains a polymer material, it can typically have a structure comprising a high-temperature layer (HTL) and an electron microlayer (EML). The HTL can contain poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML can contain a polymer material such as a poly(p-phenylenevinylene)-based (PPV-based) or a polyfluoro-based material. The intermediate layer 320 can be formed, for example, using a screen printing process, an inkjet printing process, or a laser-induced thermal imaging (LITI) process.

[0138] The intermediate layer 320 is not limited to this and can also have other different structures. The intermediate layer 320 can include a layer formed as a single body with respect to a plurality of pixel electrodes 310, or it can include a layer patterned to correspond to the plurality of pixel electrodes 310.

[0139] The opposite electrode 330 can be formed in one piece with respect to a plurality of organic light-emitting diodes to correspond to a plurality of pixel electrodes 310.

[0140] Since the organic light-emitting diode (OLED) is likely to be damaged by external moisture or oxygen, a thin-film encapsulation layer (not shown) or an encapsulation substrate (not shown) can be arranged on the OLED to cover and protect it. The thin-film encapsulation layer (not shown) can cover and extend over the display area DA. The thin-film encapsulation layer can include an inorganic encapsulation layer containing at least one inorganic material and an organic encapsulation layer containing at least one organic material. In some embodiments, the thin-film encapsulation layer can have a structure in which a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer are stacked.The encapsulation substrate (not shown) can be arranged to face the substrate 110 and can be attached to the substrate 110 in the circumferential area PA (see .) using an encapsulation element, such as a sealant or frit. Fig. 1) be bound.

[0141] Furthermore, a spacer may be included on the pixel-defining layer 120 to prevent damage from masking, and various functional layers, such as a polarizing layer, a black matrix, a color filter and / or a touchscreen layer which includes a touch electrode to reduce light reflection from the outside, may be provided on the thin-film encapsulation layer.

[0142] Fig. Figure 8 is a schematic cross-sectional view of a display device according to one embodiment. Fig. 8 denote the same reference symbols as those from Fig. There are 6 identical elements, therefore a redundant description of them is omitted.

[0143] With reference to Fig. According to one embodiment, the display device comprises the substrate 110, a first thin-film transistor (e.g., the driving thin-film transistor T1) comprising a silicon semiconductor, a second thin-film transistor (e.g., the first initializing thin-film transistor T4) comprising an oxide semiconductor, the node connection line 166, which connects a first control electrode of the first thin-film transistor to a second semiconductor layer of the second thin-film transistor, and the shielding electrode 173, which is arranged to overlap the node connection line 166. The shielding electrode 173 can be connected to the drive voltage line 165 via a contact hole. The first thin-film transistor can be the driving thin-film transistor T1, and the second thin-film transistor can be the first initializing thin-film transistor T4.The second thin-film transistor can also be the compensating thin-film transistor T3, which has a semiconductor layer containing an oxide semiconductor. The semiconductor layer of thin-film transistor T3 can be connected to the control electrode G1 of the controlling thin-film transistor T1 via the node connection line 166.

[0144] In the present embodiment, a data line 161 can be arranged on the same layer (e.g., the second intermediate insulating layer 116) as the drive voltage line 165 and the node connection line 166. In this case, the drive voltage line 165 can be positioned between the data line 161 and the node connection line 166, spaced apart from each other. Since the drive voltage line 165, to which a constant voltage is applied, is located between the data line 161 and the node connection line 166, coupling effects that may occur between the data line 161 and the node connection line 166 can be minimized.

[0145] Furthermore, in the present embodiment, since the shielding electrode 173 is arranged above the node connection line 166, coupling effects occurring between the node connection line 166 and the pixel electrode 310 or the like can be minimized.

[0146] Meanwhile, in the present embodiment, the first initializing thin-film transistor T4 can have an upper gate structure that includes the first initializing control electrode G4, which is arranged on the third gate insulating layer 115.

[0147] Fig. Figure 9 is a schematic cross-sectional view of a display device according to one embodiment. Fig. 9 denote the same reference symbols as those from Fig. There are 6 identical elements, therefore a redundant description of them is omitted.

[0148] With reference to Fig.According to one embodiment, the display device comprises the substrate 110, a first thin-film transistor (e.g., the driving thin-film transistor T1) comprising a silicon semiconductor, a second thin-film transistor (e.g., the first initializing thin-film transistor T4) comprising an oxide semiconductor, the node connection line 166, which connects a first control electrode of the first thin-film transistor to a second semiconductor layer of the second thin-film transistor, and the shielding electrode 173, which is arranged to overlap the node connection line 166. The shielding electrode 173 can be connected to the drive voltage line 165 via a contact hole. The first thin-film transistor can be the driving thin-film transistor T1, and the second thin-film transistor can be the first initializing thin-film transistor T4.The second thin-film transistor can also be the compensating thin-film transistor T3, which has a semiconductor layer containing an oxide semiconductor. The semiconductor layer of thin-film transistor T3 can be connected to the control electrode G1 of the controlling thin-film transistor T1 via the node connection line 166.

[0149] According to the present embodiment, a data line can comprise a lower data line 161' and an upper data line 171' arranged on different layers. The lower data line 161' can be arranged on the same layer (e.g., the second intermediate insulating layer 116) as the node connection line 166. The upper data line 171' can be arranged on the same layer (e.g., the first planarization layer 118) as the shielding electrode 173. The upper data line 171' can be connected to the lower data line 161' via a contact hole.

[0150] In the present embodiment, the control voltage line 165 can be arranged to be spaced apart from each of the lower data line 161' and the node connection line 166 between the lower data line 161' and the node connection line 166. Since the control voltage line 165, to which a constant voltage is applied, is arranged between the lower data line 161' and the node connection line 166, coupling effects that can occur between the lower data line 161' and the node connection line 166 can be minimized.

[0151] Furthermore, in the present embodiment, since the shielding electrode 173 is arranged above the node connection line 166, coupling effects occurring between the node connection line 166 and the upper data line 171' and / or the pixel electrode 310 or the like can be minimized.

[0152] According to one embodiment as described above, a drive circuit that drives a display device is configured to include a first thin-film transistor incorporating a silicon semiconductor and a second thin-film transistor incorporating an oxide semiconductor, and accordingly a display device with high resolution and low power consumption can be provided.

[0153] Furthermore, effects caused by coupling capacitance can be minimized because the shielding electrode overlaps the node connection line that is connected to the first thin-film transistor.

[0154] Furthermore, a clear black gradation can be achieved due to the booster capacitor.

[0155] It is understood that the embodiments described in this document are to be considered descriptive only and not as limitations. Descriptions of features or aspects within each embodiment should typically be considered as being available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it is understood by the person skilled in the art that various modifications to the shape and details therein may be made without deviating from the scope as defined in the following claims.

Claims

[1] Display device comprising: a substrate (110) that includes a display area (DA) in which a display element is arranged; a first thin-film transistor (T1) located in the display area (DA) and comprising a first semiconductor layer (AS1) containing silicon and a first control electrode (G1) isolated from the first semiconductor layer (AS1); a first intermediate insulating layer (114) covering the first control electrode (G1); a second thin-film transistor (T4) arranged on the first intermediate insulating layer (114) and comprising a second semiconductor layer (AO4) which includes an oxide semiconductor and a second control electrode (G4) which is insulated from the second semiconductor layer (AO4); a second intermediate insulating layer (116) covering the second control electrode (G4); a node connection line (166) which is arranged on the second intermediate insulating layer (116) and is connected to the first control electrode (G1) via a first contact hole (CNT1); a first planarization layer (118) covering the node connection line (166); and a shielding electrode (173) which is arranged on the first planarization layer (118) to overlap the node connection line (166). [2] Display device according to claim 1, wherein the node connection line (166) is connected to the second semiconductor layer (AO4) via a second contact hole (CNT2). [3] Display device according to claim 1, further comprising: a control voltage line (165) which is arranged on the second intermediate insulating layer (116) on which the node connection line (166) is arranged, wherein the shielding electrode (173) is connected to the control voltage line (165) via a third contact hole (CNT3). [4] Display device according to claim 1, further comprising: a control voltage line (165) arranged on the second intermediate insulating layer (116) on which the node connection line (166) is arranged; and a data line (171) which is arranged on the first planarization layer (118) on which the shielding electrode (173) is arranged, where the control voltage line (165) overlaps at least partially the data line (171). [5] Display device according to claim 4, wherein a section of the control voltage line (165) overlaps an area between the data line (171) and the shielding electrode (173) in a top view. [6] Display device according to claim 1, further comprising: a control voltage line (165) arranged on the second intermediate insulating layer (116) on which the node connection line (166) is arranged; and a data line (171) which is arranged on the first planarization layer (118) on which the shielding electrode (173) is arranged, and wherein the control voltage line (165) overlaps an area between the data line (171) and the shielding electrode (173) in a top view. [7] Display device according to claim 1, further comprising a booster capacitor (Cbt) comprising a lower electrode (CE3) arranged on a first gate insulating layer (112) and an upper electrode (CE4) arranged on the first intermediate insulating layer (114). [8] Display device according to claim 7, wherein the upper electrode (CE4) is part of the second semiconductor layer (AO4). [9] Display device according to claim 1, wherein the second thin-film transistor (T4) further comprises a third control electrode (G4a) arranged below the second semiconductor layer (AO4) to overlap the second semiconductor layer (AO4). [10] Display device according to claim 9, further comprising: a storage capacitor (Cst) comprising the first control electrode (G1) as a first electrode (CE1) and a second electrode (CE2) arranged above the first control electrode (G1), wherein the third control electrode (G4a) and the second electrode (CE2) of the storage capacitor (Cst) are arranged on a second gate insulating layer (113). [11] Display device according to claim 1, further comprising a data line (161) and a control voltage line (165) arranged on the second intermediate insulating layer (116) on which the node connection line (166) is arranged, wherein the control voltage line (165) is arranged between the data line (161) and the node connection line (166). [12] Display device according to claim 1, further comprising: a lower data line located on the second intermediate insulating layer, on which the node connection line is located; and an upper data line that is located on the first planarization layer and is connected to the lower data line via a contact hole. [13] Display device according to claim 12, further comprising a control voltage line located on the second intermediate insulating layer, on which the node connection line is located, the control voltage line is arranged between the lower data line and the node connection line. [14] Display device according to claim 1, further comprising a second planarization layer (119) covering the shielding electrode (173), wherein the display element comprises an organic light-emitting diode (OLED) arranged on the second planarization layer (119). [15] Display device comprising: a substrate (110) comprising a display area (DA) in which a display element is arranged; a first thin-film transistor (T1) arranged in the display area (DA) comprising a silicon semiconductor layer (AS1) and a first control electrode (G1) separated from the silicon semiconductor layer (AS1); a first intermediate insulating layer (114) covering the first control electrode; a second thin-film transistor (T4) located on the first intermediate insulating layer and comprising an oxide semiconductor layer (AO4) and a second control electrode, which is insulated from the oxide semiconductor layer; and a booster capacitor (Cbt) comprising a lower electrode and an upper electrode, wherein the lower electrode and the first control electrode are arranged on a first layer and the upper electrode and the oxide semiconductor layer are arranged on a second layer which is different from the first layer. [16] Display device according to claim 15, wherein the upper electrode is part of the oxide semiconductor layer. [17] Display device according to claim 15, further comprising: a node connection line (166) that connects the first control electrode to the oxide semiconductor layer; and a shielding electrode (173) which is arranged over the node connection line to overlap the node connection line. [18] Display device according to claim 17, further comprising a control voltage line (165) which is electrically connected to the shielding electrode, wherein the control voltage line and the node connection line are arranged on a third layer which covers the second thin-film transistor. [19] Display device according to claim 17, further comprising: a control voltage line (165) arranged on a third layer on which the node connection line is arranged; and a data line (171) which is arranged on a fourth layer on which the shielding electrode is arranged, where the control voltage line overlaps at least partially the data line. [20] Display device according to claim 19, wherein a section of the control voltage line overlaps an area between the data line and the shielding electrode in a top view.

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