Passivated contact structure and solar cell encompassing this, cell arrangement and photovoltaic system

Abstract

Passivated contact structure of a solar cell, comprising the passivated contact structure: a silicon substrate; a first passivated contact area arranged on the silicon substrate, and a second passivated contact area arranged on the first passivated contact area; wherein: the first passivated contact area comprises a first doped layer, a first passivation layer and a second doped layer; the second passivated contact area comprises a second passivation layer and a third doped layer; the first doped layer, the first passivation layer, the second doped layer, the second passivation layer, and the third doped layer are arranged sequentially on the silicon substrate; and the second passivated contact area includes an opening for connecting a conductive layer of the solar cell to the first passivated contact area, where the first passivation layer is an oxide layer comprising a silicon oxide layer or a combination of an oxide layer comprising a silicon oxide layer and a silicon carbide layer or an amorphous silicon layer, the second passivation layer is an amorphous silicon layer or a combination of an amorphous silicon layer and an oxide layer or a silicon carbide layer, and The thickness of the second passivation layer is greater than the thickness of the first passivation layer.

Description

TECHNICAL AREA

[0001] The disclosure relates to the technical field of solar cells, and in particular to a passivated contact structure and a solar cell comprising therein, a cell arrangement and a photovoltaic system. BACKGROUND

[0002] Electricity generated by solar cells is a sustainable, clean energy source. Through the photovoltaic effect of a semiconductor p-n junction, sunlight can be converted into electrical energy. The conversion efficiency is a key indicator of solar cell performance. In an interdigitated back-contact (IBC) cell, a positive / negative electrode is located on the back of the cell, meaning the front side is not shielded by a metal gate line. This completely eliminates the optical loss caused by the metal gate line shielding. Furthermore, the electrode width can be greater than in a conventional electrode, reducing series resistance loss and significantly improving the conversion efficiency.Since the front side is designed without electrodes, the product also has a more appealing appearance and is suitable for a wide variety of application scenarios.

[0003] In conventional IBC technology, an n-region and a p-region must be formed alternately. However, high recombination can occur due to direct contact between the n-region and the p-region, leading to a decrease in parallel resistance and conversion efficiency. In some technologies, a silicon substrate is exposed or a gap is provided between the n-region and the p-region for insulation. However, the insulation effect is poor. Furthermore, since the doping concentration of the p-region and any gap (an empty region or a gap between the n-region and the p-region) is relatively low, the passivation effect is poor, and the surface is susceptible to contamination. Additionally, in an IBC passivated contact cell, an electrode is printed directly in the p-region or the n-region.Therefore, during a subsequent sintering process, burn-through can easily occur, leading to direct contact between the electrode and the silicon substrate. As a result, recombination increases and the conversion efficiency decreases.

[0004] In a conventional passivated IBC cell with doped polysilicon, the doped polysilicon is isolated from a silicon substrate by means of a tunnel layer, forming a passivated contact structure in a stacked configuration of doped polysilicon – tunnel layer (an insulating layer) – silicon substrate. The thickness of the tunnel layer has a very significant influence on the tunnel resistance. To achieve a desired resistance, the thickness of the tunnel layer must be sufficiently small. However, to achieve a desired passivation effect, the thickness of the tunnel layer must be sufficiently large. Therefore, the thickness range of the tunnel layer must be tightly controlled. During production, the accuracy of the tunnel layer thickness is difficult to control. Consequently, mass production is not currently feasible. Furthermore, requirements for a thermal process in a subsequent production step are also imposed.Therefore, the conversion efficiency of the cell is limited. SUMMARY

[0005] The invention relates to a passivated contact structure according to claim 1. Further embodiments of the invention are defined in the dependent claims. Embodiments of the disclosure aim to provide a passivated contact structure for a solar cell to solve problems caused by the poor insulation effect of a conventional conductive layer, the increased recombination, and the reduced conversion efficiency resulting from direct contact with a silicon substrate.

[0006] The embodiments of the disclosure are implemented as follows. A passivated contact structure of a solar cell comprises: a first passivated contact area arranged on a silicon substrate, and a second passivated contact area arranged on top of the first passivated contact area.

[0007] The second passivated contact area includes an opening for connecting a conductive layer to the first passivated contact area.

[0008] The first passivated contact area comprises a first doped layer, a first passivation layer and a second doped layer, and the second passivated contact area comprises a second passivation layer and a third doped layer.

[0009] Furthermore, the first passivation layer is a porous structure that includes a hole area, and the first doped layer and / or the second doped layer are / are located in the hole area.

[0010] Furthermore, the second doped layer and the third doped layer have opposite doping polarities.

[0011] Furthermore, the first doped layer and the second doped layer have the same doping polarity.

[0012] Furthermore, the pore size of the porous structure is less than 20 µm.

[0013] Furthermore, the pore size of the porous structure is less than 10 µm.

[0014] Furthermore, the pore size of the porous structure is less than 1000 nm. A hole is designed as a nanoscale hole with a pore size of less than 1000 nm, and a surface hole density can be up to 10 6 -10 8 / cm 2 It can be understood that the arrangement of a hole at the nanoscale with a pore size of less than 1000 nm greatly reduces the total contact area between the second doped layer and the silicon substrate, thereby not only reducing resistance but also significantly reducing recombination.

[0015] Furthermore, a non-hole region of the porous structure includes a dopant that has the same doping type as the first doped layer and / or the second doped layer.

[0016] Furthermore, part of the hole area of ​​the porous structure includes the first doped layer and / or the second doped layer.

[0017] Furthermore, the ratio of the area of ​​the hole region of the porous structure to the total area of ​​the porous structure is less than 20%.

[0018] According to the invention, the thickness of the second passivation layer is greater than the thickness of the first passivation layer.

[0019] Furthermore, the thickness of the first passivation layer is in the range of 0.5-10 nm.

[0020] Furthermore, the thickness of the first passivation layer is in the range of 0.8-2 nm.

[0021] Furthermore, the thickness of the second passivation layer is in the range of 5-150 nm.

[0022] According to the invention, the first passivation layer is an oxide layer comprising a silicon oxide layer or a combination of an oxide layer comprising a silicon oxide layer and a silicon carbide layer or an amorphous silicon layer.

[0023] According to the invention, the second passivation layer is an amorphous silicon layer or a combination of an amorphous silicon layer and an oxide layer or a silicon carbide layer. Furthermore, the oxide layer comprises one or more silicon oxide layers and aluminum oxide layers.

[0024] Furthermore, the silicon carbide layer in the first passivation layer and / or the second passivation layer comprises a hydrogenated silicon carbide layer.

[0025] Furthermore, the doping concentration of the first doped layer lies between the doping concentration of the silicon substrate and the doping concentration of the second doped layer.

[0026] Furthermore, the junction depth of the first doped layer is less than 1.5 µm.

[0027] Furthermore, the first doped layer is a monocrystalline silicon-doped layer doped with a group III or group V element.

[0028] Furthermore, the second doped layer and / or the third doped layer comprise a polysilicon-doped layer, a silicon carbide-doped layer or an amorphous silicon-doped layer.

[0029] Furthermore, the silicon carbide-doped layer in the second doped layer or the third doped layer comprises at least one silicon carbide-doped film, each having a different specific refractive index.

[0030] Furthermore, the refractive indices of the silicon carbide-doped films decrease from the silicon substrate outwards.

[0031] Furthermore, the silicon carbide-doped layer in the second doped layer and / or the third doped layer comprises a hydrogenated silicon carbide-doped layer, wherein the conductivity of the hydrogenated silicon carbide-doped layer is greater than 0.01 S·cm and the thickness of the hydrogenated silicon carbide-doped layer is greater than 10 nm.

[0032] The invention further relates to a solar cell according to claim 13. The solar cell comprises: a silicon substrate; a first doped region and a second doped region, spaced apart on a back side of the silicon substrate and having opposite polarities; a first dielectric layer, arranged on one front side of the silicon substrate; a second dielectric layer, arranged between the first doped region and the second doped region; and a first conductive layer and a second conductive layer, arranged in the first doped region and the second doped region respectively.

[0033] The first doped area and / or the second doped area utilize the passivated contact structure described above. Further embodiments of the invention are defined in the dependent claims.

[0034] Furthermore, one of the first doped region and the second doped region uses the passivated contact structure described above, and the other of the first doped region and the second doped region is arranged on a fourth doped layer in the silicon substrate.

[0035] Furthermore, the fourth doped layer is a monocrystalline silicon-doped layer doped with a group III or group V element.

[0036] Furthermore, a third passivation layer and a fifth doped layer are arranged sequentially on the fourth doped layer.

[0037] Furthermore, spaced grooves are provided on the back of the silicon substrate, and the first doped area and the second doped area are arranged alternately in the grooves.

[0038] Furthermore, spaced grooves are provided on the back side of the silicon substrate, with one groove being located in one of the grooves and the other located outside the grooves.

[0039] Furthermore, a trench is planned between the first endowed area and the second endowed area.

[0040] Furthermore, the first doped area and the second doped area are arranged in a portion of areas inside and outside the grooves.

[0041] Furthermore, the first dielectric layer and the second dielectric layer are each an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer, or a combination thereof.

[0042] Furthermore, the first dielectric layer and / or the second dielectric layer comprise the aluminum oxide layer and the silicon carbide layer or the silicon oxide layer and the silicon carbide layer; and The thickness of the first dielectric layer is greater than 50 nm and the thickness of the second dielectric layer is greater than 25 nm.

[0043] Furthermore, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer is less than 40 nm, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the silicon carbide layer in the first dielectric layer and / or in the second dielectric layer is greater than 10 nm.

[0044] Furthermore, the silicon carbide layer in the first dielectric layer and / or in the second dielectric layer comprises at least one silicon carbide film.

[0045] Furthermore, the refractive indices of the silicon carbide-doped films decrease from the silicon substrate outwards.

[0046] Furthermore, a magnesium fluoride layer is arranged outside the first dielectric layer and / or the second dielectric layer.

[0047] Furthermore, the first conductive layer and the second conductive layer are transparent conductive TCO films and / or metal electrodes.

[0048] Furthermore, the metal electrodes each comprise a silver electrode, a copper electrode, an aluminum electrode, a tinned copper electrode, or a silver-coated copper electrode.

[0049] Furthermore, the copper electrode is galvanized copper produced using an electroplating process, or the copper electrode produced by physical vapor deposition.

[0050] Furthermore, an electric field layer or a floating junction is arranged between the front of the silicon substrate and the second dielectric layer.

[0051] Furthermore, one of the first doped region and the second doped region is a P-type doped region and the other of the first doped region and the second doped region is an N-type doped region, and the thickness of a first passivation layer in the P-type doped region is greater than the thickness of a first passivation layer in the N-type doped region.

[0052] Furthermore, one of the first doped region and the second doped region is a P-type doped region and the other of the first doped region and the second doped region is an N-type doped region, and a hole density of a first passivation layer in the P-type doped region is greater than a hole density of a first passivation layer in the N-type doped region.

[0053] An alternative embodiment of the disclosure aims to provide a solar cell. The solar cell comprises: a silicon substrate; the passivated contact structure described above, arranged on a back side of the silicon substrate; a third dielectric layer, arranged on the passivated contact structure; a sixth doped layer and a fourth dielectric layer, arranged sequentially on one front side of the silicon substrate; and a third conductive layer and a fourth conductive layer, electrically connected to the passivated contact structure and the sixth doped layer respectively.

[0054] The passivated contact structure and the sixth doped layer have opposite polarities.

[0055] The invention further aims to provide a cell arrangement. The cell arrangement comprises one of the solar cells described above.

[0056] The invention further aims to provide a photovoltaic system. The photovoltaic system comprises the cell arrangement described above.

[0057] An alternative embodiment of the disclosure aims to provide a cell arrangement. The cell arrangement comprises a different type of solar cell described above.

[0058] An alternative embodiment of the disclosure aims to provide a photovoltaic system. The photovoltaic system comprises a different cell arrangement than those described above.

[0059] According to the passivated contact structure of the solar cell provided in the present disclosed embodiment, an opening is arranged in the second passivated contact area, and the conductive layer penetrates the opening to connect with the first passivated contact area, thus locating the conductive layer within the first passivated contact area. Therefore, the second passivated contact area surrounding the conductive layer can form an insulating barrier for the conductive layer, thereby creating insulation between an emitter and the conductive layer located on a back-field array in the cell, fabricated using the passivated contact structure. In this way, the insulation effect is enhanced, and the recombination of a space charge region is reduced.If no opening is provided in advance, the conductive layer can be printed directly onto the second passivated contact area for sintering, so that the conductive layer penetrates the second passivated contact area and thus comes into contact with the second doped layer of the first passivated contact area. In the prior art, the second doped layer and the passivation layer are easily burned through when the conductive layer is printed onto the second doped layer for sintering, resulting in the conductive layer coming into direct contact with the silicon substrate, which leads to increased recombination and a reduced conversion efficiency. The embodiments of the disclosure solve the above problems. In addition, the second passivated contact area blocks contaminants, reducing the possibility of surface contamination.Furthermore, the opening provided in the second passivated contact area can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus increasing the accuracy of the conductive layer fabrication. As a Fermi level of the first doped layer is altered, the solid concentration of transition metal increases, thereby improving the gettering of impurities. A Fermi level of the third doped layer is altered, increasing an interfacial defect, allowing heterogeneous nucleation sites to form on the interfacial defect and thus enhancing the gettering effect of impurities. In this way, an additional impurity getter effect is achieved. Hydrogen contained in the second and third doped layers can diffuse inwards during a high-temperature process, further enhancing hydrogen passivation.Therefore, the poor insulation effect of a conventional conductive layer and the increased recombination and reduced conversion efficiency caused by direct contact with a silicon substrate are solved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic structure diagram of a passivated contact structure of a solar cell according to an embodiment of the disclosure. Fig. 2 to Fig. Figure 11 shows schematic structure diagrams of a solar cell during various implementations according to an embodiment of the disclosure. Fig. Figure 12 shows a schematic structure diagram of a solar cell according to another embodiment of the disclosure. DETAILED DESCRIPTION

[0060] To make the tasks, technical solutions, and advantages of the disclosure clearer and more understandable, the disclosure is described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are used only to illustrate the disclosure and are not intended to limit it.

[0061] In the disclosure, unless expressly stated or defined otherwise, terms such as "assemble," "attach," "connect," "connection," and "fasten" should be understood in a broad sense. For example, the connection may be a permanent connection, a detachable connection, or an integral connection; or the connection may be a mechanical connection or an electrical connection; or the connection may be a direct connection, an indirect connection via an intermediate piece, or an internal connection between two components. A person skilled in the art may understand specific meanings of the foregoing terms in the disclosure according to certain situations. The term "and / or" used in this description includes any and all combinations of one or more related listed elements.

[0062] According to the disclosure, an opening is arranged in a second passivated contact region, and a conductive layer penetrates the opening to connect with a first passivated contact region, such that the conductive layer is located within the first passivated contact region. Therefore, a second passivated contact region surrounding the conductive layer can form an insulating shield for the conductive layer, thereby creating insulation between an emitter and the conductive layer located on the back field of a cell fabricated using the passivated contact structure. In this way, the insulation effect is enhanced, and the recombination of a space charge region is reduced.If no opening is provided in advance, the conductive layer can be printed directly onto the second passivated contact area for sintering, so that the conductive layer penetrates the second passivated contact area and thus comes into contact with the second doped layer of the first passivated contact area. In the prior art, the second doped layer and the passivation layer are easily burned through when the conductive layer is printed onto the second doped layer for sintering, resulting in the conductive layer coming into direct contact with the silicon substrate, which leads to increased recombination and a reduced conversion efficiency. The embodiments of the disclosure solve the above problems. In addition, the second passivated contact area blocks contaminants, reducing the possibility of surface contamination.Furthermore, the opening provided in the second passivated contact area can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus increasing the accuracy of the conductive layer fabrication. As a Fermi level of the first doped layer is altered, the solid concentration of transition metal increases, thereby improving the gettering of impurities. A Fermi level of the third doped layer is altered, increasing an interfacial defect, allowing heterogeneous nucleation sites to form on the interfacial defect and thus enhancing the gettering effect of impurities. In this way, an additional impurity getter effect is achieved. Hydrogen contained in the second and third doped layers can diffuse inwards during a high-temperature process, further enhancing hydrogen passivation.Therefore, the poor insulation effect of a conventional conductive layer and the increased recombination and reduced conversion efficiency caused by direct contact with a silicon substrate are solved. Example 1

[0063] One embodiment of the disclosure provides a passivated contact structure for a solar cell. For the sake of simplicity, only parts relating to this embodiment of the disclosure are shown. With reference to Fig. 1, comprises the passivated contact structure of the solar cell provided in this embodiment of the disclosure: a first passivated contact area 11 arranged on a silicon substrate 10, and a second passivated contact area 12 arranged on the first passivated contact area 11.

[0064] The second passivated contact area 12 includes an opening 13 through which a conductive layer can penetrate to be connected to the first passivated contact area 11.

[0065] The first passivated contact area 11 comprises a first doped layer 111, a first passivation layer 112 and a second doped layer 113, and the second passivated contact area 12 comprises a second passivation layer 121 and a third doped layer 122.

[0066] In one embodiment of the disclosure, the silicon substrate 10 has a front face that faces the sun during normal operation and a back face opposite the front face. The front face is a light-receiving surface. The back face is opposite the front face and is located on a different side of the silicon substrate 10. That is, the front and back faces are located on different and opposite sides of the silicon substrate 10. In this embodiment, the silicon substrate 10 is a monocrystalline silicon wafer of type N. It can be understood that in other embodiments, the silicon substrate 10 may also be a silicon wafer of a different type, such as a polysilicon wafer, a quasi-monocrystalline silicon wafer, or the like. The silicon substrate 10 may also be of type P.The silicon substrate 10 can be designed according to the actual usage requirements, which are not specifically limited here.

[0067] In one embodiment of the disclosure, with reference to Fig. 1. The passivated contact structure comprises the first doped layer 111, the first passivation layer 112, the second doped layer 113, the second passivation layer 121, and the third doped layer 122, arranged sequentially on the silicon substrate 10. The through-hole 13 is located on the second passivation layer 121 and the third doped layer 122, allowing the conductive layer to penetrate the hole 13 and connect to the second doped layer 113. It should be noted that, as in Fig. As shown in Figure 1, the opening 13 is located in the middle of the second passivation layer 121 and the third doped layer 122. Therefore, when the conductive layer penetrates the opening 13 to connect with the second doped layer 113, the second passivation layer 121 and the third doped layer 122 surrounding the conductive layer can form an insulating barrier for the conductive layer. Therefore, as shown in Fig. 2 to Fig. Figure 11 shows that in a cell fabricated using the passivated contact structure in this embodiment, the second passivated contact area 12 surrounding the conductive layer provides insulation between an emitter in the cell and the conductive layer located on the back side, thus reducing the load in a space charge region. Furthermore, the second passivated contact area 12 also blocks contaminants, reducing the possibility of surface contamination. Additionally, the opening 13 provided in the second passivated contact area 12 can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus enabling more accurate fabrication of the conductive layer.

[0068] In one embodiment of the disclosure, the first passivation layer 112 is preferably an oxide layer, a silicon carbide layer, an amorphous silicon layer, or a combination thereof. In some examples of the disclosure, the first passivation layer 112 may comprise a single material such as an oxide layer, a variety of materials such as a combination of an oxide layer and an amorphous silicon layer, or a single material such as a combination of several amorphous silicon layers, each having a different refractive index. Furthermore, the first passivation layer 112 may also be a silicon oxynitride layer, a silicon nitride layer, or the like. It can be understood that the specific structure of the first passivation layer 112 includes, but is not limited to, those mentioned above.The first passivation layer 112 can be designed according to the actual application requirements, which is not specifically limited here. Furthermore, the thickness of the first passivation layer 112 is in the range of 0.5–10 nm. In a preferred embodiment of the disclosure, the thickness of the first passivation layer 112 is in the range of 0.8–2 nm. The thickness of the first passivation layer 112 can be the same as that of a tunnel layer in the prior art or greater than that of a conventional tunnel layer. The thickness can be designed according to the actual application requirements, which is not specifically limited here.

[0069] In a preferred embodiment of the disclosure, the first passivation layer 112 particularly comprises the oxide layer and the silicon carbide layer. The oxide layer and the silicon carbide layer are arranged sequentially outwards from the silicon substrate 10. The oxide layer is in contact with the first doped layer 111, which is located on the inside, and the silicon carbide layer is in contact with the second doped layer 113, which is located on the outside. Furthermore, the oxide layer preferably comprises one or more silicon oxide layers and aluminum oxide layers. Therefore, the first passivation layer 112 can also be a combination of the silicon oxide layer and the aluminum oxide layer within the oxide layer. The silicon carbide layer in the first passivation layer 112 comprises a hydrogenated silicon carbide layer.Hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate 10 via a diffusion mechanism and a thermal effect, such that an unsaturated bond (dangling bond) is formed to neutralize defects in the silicon substrate 10. Therefore, the weakening of unsaturated bonds (dangling bonds) in a forbidden band increases the probability that a carrier will penetrate through the first passivation layer 112 into the second doped layer 113.

[0070] Furthermore, in one embodiment of the disclosure, as in Fig. Figure 1 shows the first passivation layer 112 as having a porous structure comprising the first doped layer 111 and / or the second doped layer 113 in a porous region. In this case, the first passivation layer 112 is a porous structure. The porous structure can be produced by additional chemical corrosion, dry etching, thermal diffusion, or the like. The porous structure is designed according to the actual application requirements, which are not specifically limited here. It should be noted that the porous structure is shown in a top view of the first passivation layer 112. A cross-sectional view of the first passivation layer 112 shows a multi-channel structure. The porous structure has holes extending through the first passivation layer 112.The porous structure also exhibits grooves / depressions that do not extend through the first passivation layer 112 on a surface of the first passivation layer 112. A pore size of the porous structure is less than 20 µm. In particular, the average pore size of the holes is less than 20 µm, or the pore sizes of 90% of all holes are smaller than 20 µm. Furthermore, the pore size of the porous structure is less than 10 µm. Additionally, the pore size of the porous structure is less than 1000 nm. A hole is designed as a nanoscale hole with a pore size of less than 1000 nm, and a surface hole density can be up to 10. 6 -10 8 / cm 2It can be understood that the arrangement of a hole at the nanoscale with a pore size of less than 1000 nm greatly reduces the total contact area between the second doped layer and the silicon substrate, thereby not only reducing resistance but also significantly decreasing recombination. The ratio of the area of ​​the hole region of the porous structure to the total area of ​​the porous structure is less than 20%. That is, the holes are sparsely distributed on the first passivation layer 112.

[0071] In one embodiment of the disclosure, the hole region of the porous structure comprises the first doped layer 111 and / or the second doped layer 113. That is, the hole region can be filled with the first doped layer 111 or the second doped layer 113 alone, or it can be filled with a mixture of the first doped layer 111 and the second doped layer 113. It should be noted that in an actual manufacturing and preparation process, part of the hole region of the porous structure may comprise the first doped layer 111 and / or the second doped layer 113, and other parts not filled with the first doped layer 111 and / or the second doped layer 113 may be gap regions.It should also be noted that, in addition to the first doped layer 111 and / or the second doped layer 113 filling the hole region, impurities (such as hydrogen, oxygen, and various metallic elements) that are formed in a thermal process (solar cell manufacturing can involve a variety of high-temperature processes according to different processes) or generated during segregation may be present in the hole region. Since the first passivation layer 112 is designed as a porous structure and the hole region contains the first doped layer 111 and / or the second doped layer 113, a conductive channel is formed in the hole region of the first passivation layer 112, thus creating the desired resistance of the first passivation layer 112.In this way, the thickness of the first passivation layer 112 has a lesser influence on the resistance, and the control requirements for the thickness of the first passivation layer 112 are reduced. Thus, compared to the prior art, more methods for producing the first passivation layer 112 are applicable. In the porous structure, the second doped layer 113 is connected to the silicon substrate 10 via the doped hole region and the first doped layer 111, further reducing the overall resistance of the manufactured cell and improving its conversion efficiency.

[0072] Furthermore, in one embodiment of the disclosure, a non-hole region of the porous structure contains a dopant having the same doping type as the first doped layer 111 and / or the second doped layer 113. For example, if the first doped layer 111 and the second doped layer 113 are N-type doped layers (such as a phosphorus-doped layer), the non-hole region of the first passivation layer 112 contains a diffused N-type dopant.

[0073] In one embodiment of the disclosure, the first doped layer 111 is located between the silicon substrate 10 and the first passivation layer 112. The first doped layer 111 can be a doped layer formed directly on the silicon substrate 10 by ion implantation or the like. In this case, the first doped layer 111 is located on the silicon substrate 10. Accordingly, the first passivation layer 112 is produced on the first doped layer 111. The first doped layer 111 can also be a doped layer formed on the silicon substrate 10 after a doping source has penetrated directly into the first passivation layer 112 or the holes in the porous structure during the production of the second doped layer 113. In this case, the first doped layer 111 is located in the silicon substrate 10.Accordingly, the first passivation layer 112 is produced directly on the silicon substrate 10. Therefore, during the production of the second doped layer 113, the first passivation layer is thermally diffused into the silicon substrate 10, so that a portion of the silicon substrate 10 is converted into the first doped layer 111 by diffusion. The doping concentration of the first doped layer 111 lies between that of the silicon substrate 10 and that of the second doped layer 113. In a preferred embodiment of the disclosure, the first doped layer 111 and the second doped layer 113 have the same doping polarity. For example, if the second doped layer 113 is an N-type doped layer, the first doped layer 111 is correspondingly preferably an N-type doped layer.It should be noted that the doping polarities of the first doped layer 111 and the second doped layer 113 may differ from the doping polarity of the silicon substrate 10. For example, in this embodiment, the silicon substrate 10 is a monocrystalline N-type silicon, and the first doped layer 111 and the second doped layer 113 may be P-type doped layers.

[0074] Preferably, the material of the first doped layer 111 is identical to that of the silicon substrate 10. That is, if the silicon substrate 10 is a monocrystalline silicon wafer, the first doped layer 111 is also preferably a monocrystalline silicon wafer. The first doped layer 111 is a monocrystalline silicon-doped layer doped with a group III or group V element. If the second doped layer 113 is the N-type doped layer, the first doped layer 111 is a monocrystalline silicon-doped layer doped with group V elements such as nitrogen, phosphorus, and arsenic. If the second doped layer 113 is the P-type doped layer, the first doped layer 111 is a monocrystalline silicon-doped layer doped with group III elements such as boron, aluminum, and gallium.It can be understood that if the silicon substrate 10 is formed as silicon wafers of other types, the first doped layer 111 can also be formed accordingly as doped silicon wafers of other types, doped with a group III or group V element.

[0075] Furthermore, in one embodiment of the disclosure, the first doped layer 111 is present in a discrete or continuous distribution. The first doped layer can be arranged completely continuously between the silicon substrate 10 and the first passivation layer 112, or it can be locally discretely distributed near each hole region of the first passivation layer 112. The distribution of the first doped layer 111 can be controlled using a doping method. The amount of doping increases over a doping time, so that the first doped layer 111 becomes more continuous until the first doped layer 111, which completely covers the silicon substrate 10, is formed. Furthermore, the junction depth of the first doped layer 111 is less than 1.5 µm.The first doped layer 111 is positioned between the silicon substrate 10 and the first passivation layer 112 to form an electric separation field capable of increasing surface electron holes, thus enhancing the field passivation effect. As the Fermi level of the first doped layer 111 is altered, the solid concentration of the transition metal increases, thereby enhancing impurity gettering and achieving an additional impurity getter effect.

[0076] In one embodiment of the disclosure, the second doped layer 113 comprises a polysilicon-doped layer, a silicon carbide-doped layer, or an amorphous silicon-doped layer. The silicon carbide-doped layer in the second doped layer 113 comprises at least one silicon carbide-doped film, each having a specific refractive index. The refractive indices of the silicon carbide-doped films decrease outwards from the silicon substrate 10. It should be noted that the thicknesses and refractive indices of the silicon carbide-doped films can be designed according to the actual application requirements, provided that the refractive indices decrease outwards from the silicon substrate 10, which is not specifically limited here.Since silicon carbide has a large optical band gap and a low absorption coefficient, parasitic absorption can be reduced and a short-circuit current density can be effectively increased. Furthermore, the silicon carbide-doped layer in the second doped layer 113 comprises a hydrogenated silicon carbide-doped layer. The conductivity of the hydrogenated silicon carbide-doped layer is greater than 0.01 S·cm and its thickness is greater than 10 nm. Accordingly, the conductivity and thickness can also be adjusted to other values, provided that a conductivity requirement of the second doped layer 113 can be met by controlling the conductivity and thickness of the hydrogenated silicon carbide-doped layer, which is not specifically limited here.It should be noted that the first doped layer 111 and the second doped layer 113 can be made of the same material or different materials. For example, the first doped layer 111 and the second doped layer 113 can both contain doped polysilicon. Alternatively, the first doped layer 111 can contain doped monocrystalline silicon and the second doped layer 113 can contain doped silicon carbide. The first and second doped layers can be designed according to the actual application requirements, which are not specifically limited here.

[0077] In one embodiment of the disclosure, the details of the second passivation layer 121 are described in the above description of the first passivation layer 112. That is, the second passivation layer 121 is an oxide layer, a silicon carbide layer, an amorphous silicon layer, or a combination thereof. In particular, the second passivation layer 121 preferably comprises the oxide layer and the silicon carbide layer. The oxide layer and the silicon carbide layer are arranged sequentially outward from the silicon substrate 10. The oxide layer is in contact with the second doped layer 113, which is located inside, and the silicon carbide layer is in contact with the third doped layer 122, which is located outside. The silicon carbide layer in the second passivation layer 121 comprises a hydrogenated silicon carbide layer. It should be noted that the second passivation layer 121 is not the porous structure described above.It should also be noted that the film layer structures in the first passivation layer 112 and the second passivation layer 121 can be designed to be the same or different. Therefore, the first passivation layer 112 and / or the second passivation layer 121 may be one or a combination of several oxide layers, silicon carbide layers, and amorphous silicon layers. For example, both the first passivation layer 112 and the second passivation layer 121 may include both the oxide layer and the silicon carbide layer. In another example, the first passivation layer 112 may include both the oxide layer and the silicon carbide layer, and the second passivation layer 121 may include both the aluminum oxide layer and the silicon carbide layer.The first passivation layer 112 and the second passivation layer 121 can each be designed according to the actual application requirements, which are not specifically limited here. Furthermore, in this embodiment, the thickness of the second passivation layer 121 is in the range of 5–150 nm and is preferably greater than the thickness of the first passivation layer 112. The second passivation layer 121 can also contain a dopant with the same doping type as the second doped layer 113 and / or the third doped layer 122.

[0078] In one embodiment of the disclosure, reference is made to the above description of the second doped layer 113 with regard to the details of the third doped layer 122; that is, the third doped layer 122 comprises a polysilicon-doped layer, a silicon carbide-doped layer, or an amorphous silicon-doped layer. The silicon carbide-doped layer in the third doped layer 122 comprises at least one silicon carbide-doped film, each having a different refractive index. The refractive indices of the silicon carbide-doped films decrease from the silicon substrate 10 outwards. The silicon carbide-doped layer in the third doped layer 122 comprises a hydrogenated silicon carbide-doped layer. The conductivity of the hydrogenated silicon carbide-doped layer is greater than 0.01 S·cm, and the thickness of the hydrogenated silicon carbide-doped layer is greater than 10 nm.Hydrogen contained in the second doped layer 113 and the third doped layer 122 can diffuse inwards during a high-temperature process, thus enhancing hydrogen passivation. It should be noted that the second doped layer 113 and the third doped layer 122 can be of the same material or of different materials. Therefore, the second doped layer 113 and / or the third doped layer 122 comprise the polysilicon-doped layer, the silicon carbide-doped layer, or an amorphous silicon-doped layer. Preferably, the second doped layer 113 and the third doped layer 122 have opposite doping polarities. A Fermi level of the third doped layer 122 is altered, increasing interfacial defects so that heterogeneous nucleation sites can form on the interfacial defect to enhance the impurity getter effect.In this way, an additional contamination getter effect is achieved.

[0079] In this embodiment, an opening is arranged in the second passivated contact region, and the conductive layer penetrates the opening to connect with the first passivated contact region, thus locating the conductive layer within the first passivated contact region. Therefore, the second passivated contact region surrounding the conductive layer can form an insulating shield for the conductive layer, thereby creating insulation between an emitter and the conductive layer located on the backside of the cell, fabricated using the passivated contact structure. In this way, the insulation effect is enhanced, and the recombination of a space charge region is reduced.If no opening is provided in advance, the conductive layer can be printed directly onto the second passivated contact area for sintering, allowing the conductive layer to penetrate the second passivated contact area and thus come into contact with the second doped layer of the first passivated contact area. In the prior art, the second doped layer and the passivation layer are easily burned through when the conductive layer is printed onto the second doped layer for sintering, resulting in the conductive layer coming into direct contact with the silicon substrate, which leads to increased recombination and a reduced conversion efficiency. The embodiments of the disclosure solve the above problems. Furthermore, the second passivated contact area blocks contaminants, reducing the potential for surface contamination.Furthermore, the opening provided in the second passivated contact area can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus increasing the accuracy of the conductive layer fabrication. Since a Fermi level of the first doped layer is altered, the solid concentration of transition metal increases, thereby improving the gettering of impurities. A Fermi level of the third doped layer is altered, increasing an interfacial defect, allowing heterogeneous nucleation sites to form on the interfacial defect and thus enhancing the gettering effect of impurities. In this way, an additional impurity getter effect is achieved. Hydrogen contained in the second and third doped layers can diffuse inwards during a high-temperature process, further enhancing hydrogen passivation.Therefore, the poor insulation effect of a conventional conductive layer and the increased recombination and reduced conversion efficiency caused by direct contact with a silicon substrate are solved. Example 2

[0080] A second embodiment of the disclosure provides a solar cell. To simplify the description, only parts relating to this embodiment of the disclosure are shown. With reference to Fig. 2 to Fig. 11 includes the solar cell provided in this embodiment of the disclosure: a silicon substrate 10; a first doped region 20 and a second doped region 30, spaced apart on a back side of the silicon substrate 10 and having opposite polarities; a first dielectric layer 40, arranged on a front side of the silicon substrate 10; a second dielectric layer 50, arranged between the first doped region 20 and the second doped region 30; and a first conductive layer 60 and a second conductive layer 70, arranged in the first doped region 20 and the second doped region 30 respectively.

[0081] The first doped area 20 and / or the second doped area 30 use the passivated contact structure described in the embodiments above.

[0082] Therefore, in one embodiment of the disclosure, both the first doped region 20 and the second doped region 30 of the solar cell can both use the passivated contact structure described in the embodiments above, as shown in Fig. 2, Fig. 5 and Fig. Figure 8 shows that since the first doped region 20 and the second doped region 30 have opposite polarities, a first doped layer and a second doped layer in the first doped region 20, and a first doped layer, a second doped layer, and a third doped layer in the second doped region 30 also have opposite polarities. For example, if the first doped layer and the second doped layer in the first doped region 20 are P-type doped layers and the third doped layer is a P-type doped layer, then the first doped layer and the second doped layer in the second doped region 30 are N-type doped layers with opposite polarities, and the third doped region is a P-type doped region with opposite polarity. In this case, the first doped region 20 is a P-type doped region and the second doped region 30 is an N-type doped region.Of course, the first doped region 20 can also be the N-type doped region, and the second doped region 30 can also be the P-type doped region. Therefore, if one of the first doped region 20 and the second doped region 30 is the P-type doped region, then the other of the first and second doped regions is the N-type doped region.

[0083] Alternatively, one of the first doped region 20 and the second doped region 30 in the solar cell uses the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region uses a conventional structure (such as a conventional passivated contact structure or a conventional diffusion structure). In a preferred embodiment of this embodiment, the other is a fourth doped layer located on the back side of the silicon substrate 10. That is, the other uses the conventional diffusion structure, as described in Fig. 3, Fig. 6, Fig. 9 and Fig. Figure 11 shows that, optionally, the other party can also use the conventional passivated contact structure. The passivated contact structure comprises a tunnel layer and a doped region. It should be noted that the fourth doped layer is also a monocrystalline silicon-doped layer doped with a group III or group V element. For a specific structure of the third doped layer, reference is made to the description of the first doped layer in the embodiments above. It should further be noted that, since the first doped region 20 and the second doped region 30 have opposite polarities, and the first and second doped layers have the same doped polarity, the first and fourth doped layers are doped with elements of different groups.That is, if the first doped layer is doped with a group III element, the fourth doped layer is doped with a group V element. If the first doped layer is doped with a group V element, the fourth doped layer is doped with a group III element.

[0084] In another preferred embodiment of this embodiment, a third passivation layer and a fifth doped layer are arranged sequentially on the fourth doped layer, as shown in Fig. 4, Fig. 7 and Fig. Figure 10 shows that the fourth doped layer, the third passivation layer, and the fifth doped layer form a doped region structure that is essentially similar to the first passivated contact region in the embodiments described above. The third passivation layer is also a porous structure. For a specific structure of the third passivation layer, reference is made to the first passivation layer in the embodiments described above. In this embodiment, the fourth doped layer and the fifth doped layer have the same doping polarity.Since the first doped region 20 and the second doped region 30 have opposite polarities, if the first and second doped layers are N-type doped layers and the third doped layer is P-type doped layer, then the fourth and fifth doped layers will accordingly be P-type doped layers with opposite polarities. Therefore, the above embodiments are also used for the fabrication of the fourth doped layer, the third passivation layer, and the fifth doped layer. The third passivation layer, which has a porous structure, is first fabricated on the silicon substrate 10. Then, the fifth doped layer is fabricated on top of the third passivation layer.During the fabrication of the fifth doped layer, a doping source penetrates directly into the third passivation layer or into holes in the porous structure to form the fourth doped layer in the silicon substrate 10. Since the second passivation layer and the third doped layer have a similar structure and doping polarity to the third passivation layer and the fifth doped layer, they can be fabricated synchronously using the same procedure. However, it is important to note that during the fabrication of the second passivation layer by deposition, additional chemical corrosion, dry etching, or thermal diffusion is not required to create the porous structure.Since the deposition time of the second passivation layer is longer than the deposition time of the third passivation layer, the thickness of the second passivation layer is greater than the thickness of the third passivation layer.

[0085] If the first doped region 20 and the second doped region 30 both use the passivated contact structure described in the embodiments above, the material and thickness selected for each layer structure in the first doped region 20 can be the same as, or different from, those selected for each layer structure in the second doped region 30. For example, if a first passivation layer in the first doped region 20 is specifically selected as a silicon oxide layer and a silicon carbide layer, a first passivation layer in the second doped region 30 can be selected to be identical to the first passivation layer in the first doped region 20, or it can be selected as a material that differs from the first passivation layer in the first doped region 20, such as...an aluminum oxide layer and a silicon carbide layer.

[0086] The thickness of the first passivation layer in the first doped region 20 can be the same or different from the thickness of the first passivation layer in the second doped region 30. Preferably, regardless of whether the material of the first passivation layer in the first doped region 20 is the same as the material of the first passivation layer in the second doped region 30, the thickness of the first passivation layer belonging to the first doped layer doped with the group III element is greater, and the thickness of the first passivation layer belonging to the first doped layer doped with the group V element is smaller. That is, the thickness of the first passivation layer in the P-type doped region is greater than the thickness of the first passivation layer in the N-type doped region.One main reason is that the P-type doped region requires a process such as boron doping and a higher temperature, and necessitates a thicker first passivation layer due to the numerous heat treatment processes required. In this embodiment, the material and thickness of each layer structure in the first doped region 20 and in the second doped region 30 are designed according to the actual application requirements, which are not specifically limited here.

[0087] Furthermore, in a preferred embodiment of the disclosure, the hole density of the first passivation layer in the P-type doped region is greater than the hole density of the first passivation layer in the N-type doped region. Hole density denotes the number of holes per unit area. That is, for the same unit area, the first passivation layer in the P-type doped region has more holes than the first passivation layer in the N-type doped region. A primary reason for this is that the conductivity of the P-type doped region is relatively poor, and the thickness of the first passivation layer in the P-type doped region is relatively large. Therefore, more holes are required to improve the conductivity.

[0088] It should be noted that if one of the first doped region 20 and the second doped region 30 is a doped region structure containing the fourth doped layer, the third passivation layer, and the fifth doped layer, reference can also be made to the embodiments described above. The material and thickness of the first passivation layer in the passivated contact structure may be the same as or different from those of the third passivation layer in the doped region structure.For example, if the passivated contact structure is the P-type doped region and the doped region structure is the N-type doped region, preferably the thickness of the first passivation layer in the passivated contact structure is greater than the thickness of the third passivation layer in the doped region structure, and a hole density of the first passivation layer in the passivated contact structure is greater than a hole density of the third passivation layer in the doped region structure.

[0089] In one embodiment of the disclosure, the first dielectric layer 40 and the second dielectric layer 50 are each an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer, or a combination thereof. The first dielectric layer 40 and the second dielectric layer 50 achieve a passivation effect. The first dielectric layer 40 and the second dielectric layer 50 are each configured as a structure with at least one layer. The refractive indices of the first dielectric layer and the second dielectric layer decrease from the silicon substrate 10 outwards, such that a film layer near the silicon substrate 10 achieves the passivation effect, and a film layer farther from the silicon substrate 10 achieves an antireflection effect, thereby enhancing the antireflection effect.In this way, the silicon substrate 10 absorbs and utilizes light more effectively, and the short-circuit current density is increased. Each film layer in the first dielectric layer 40 and in the second dielectric layer 50, which has a different structure, can comprise a variety of films, each with a different refractive index. As described above, the film layers are arranged such that the refractive indices of the film layers decrease outwards from the silicon substrate 10. For example, the silicon oxide layer in the first dielectric layer 40 can comprise a variety of silicon oxide films with refractive indices that decrease outwards from the silicon substrate 10.

[0090] It should be noted that the first dielectric layer 40 and the second dielectric layer 50 can have the same or different structural arrangements. The film layer structures in the first dielectric layer 40 and in the second dielectric layer 50 can be designed according to the actual application requirements, which are not specifically limited here. Preferably, the first dielectric layer 40 and the second dielectric layer 50 are identical, so that the first dielectric layer 40 and the second dielectric layer 50 can be produced on the front and back sides of the silicon substrate 10, respectively, using the same process.

[0091] In a preferred embodiment of the disclosure, the first dielectric layer 40 and / or the second dielectric layer 50 comprise a double-layer structure of an aluminum oxide layer and a silicon carbide layer, or a double-layer structure of a silicon oxide layer and a silicon carbide layer. In this case, the total thickness of the first dielectric layer 40 is greater than 50 nm, and the total thickness of the second dielectric layer 50 is greater than 25 nm. It can be understood that the specific structural arrangements of the first dielectric layer 40 and the second dielectric layer 50 include, but are not limited to, the specific examples listed above.

[0092] Furthermore, in one embodiment of the disclosure, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer 40 is less than 40 nm. The thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer 50 is less than 25 nm. The thickness of the silicon carbide layer in the first dielectric layer 40 and / or in the second dielectric layer 50 is greater than 10 nm. The silicon carbide layer in the first dielectric layer 40 and / or in the second dielectric layer 50 can not only provide a hydrogen passivation effect but also reduce parasitic light absorption due to a large optical band gap and a small absorption coefficient.

[0093] It should be noted that the multilayer structure in this embodiment corresponds to the disclosed arrangement sequence from the silicon substrate 10 outwards. For example, if the first dielectric layer 40 above contains the aluminum oxide layer and the silicon carbide layer, the aluminum oxide layer is arranged close to the silicon substrate 10 and the silicon carbide layer is located close to the outer surface. It should also be noted that in the drawings Fig. 2 to Fig. Figure 11 shows only the first dielectric layer 40 and the second dielectric layer 50 as double-layer structures. However, it can be understood that the first dielectric layer 40 and the second dielectric layer 50 may also contain other numbers of layers. Corresponding specific structures can be designed according to actual needs and are not entirely limited to the drawings. It should also be noted that each drawing of the disclosure is used only to describe the specific structural distribution in the solar cell, but does not correspond to an actual size of each structure. The drawings do not fully correspond to specific actual sizes in this embodiment, and the actual size of each structure must correspond to certain parameters provided in this embodiment.

[0094] Furthermore, the silicon carbide layer in the first dielectric layer 40 and / or in the second dielectric layer 50 comprises at least one silicon carbide film. The refractive indices of the silicon carbide films decrease outwards from the silicon substrate 10. Optionally, the refractive index of each material can generally be chosen as follows: the refractive index of monocrystalline silicon is 3.88, the refractive index of amorphous silicon is in the range of 3.5–4.2, the refractive index of polysilicon is 3.93, the refractive index of silicon carbide is in the range of 2–3.88, the refractive index of silicon nitride is in the range of 1.9–3.88, the refractive index of silicon oxynitride is in the range of 1.45–3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63.It can be understood that the refractive indices of the above materials can also be adjusted to other values ​​according to the actual usage requirements, which are not specifically limited here.

[0095] Furthermore, in one embodiment of the disclosure, a magnesium fluoride layer is arranged outside the first dielectric layer 40 and / or the second dielectric layer 50. That is, in addition to one or a combination of several of the aluminum oxide layer, the silicon nitride layer, the silicon oxynitride layer, the silicon carbide layer, the amorphous silicon layer, and the silicon oxide layer selected for the first dielectric layer 40 and the second dielectric layer 50, a magnesium fluoride layer can be arranged outside the first dielectric layer 40 and / or the second dielectric layer 50. The magnesium fluoride layer must have a very low refractive index. Generally, the refractive index is set to 1.4. The magnesium fluoride layer has an optical effect that improves antireflection.

[0096] Furthermore, in one embodiment of the disclosure, an electric field layer or a floating junction is arranged between the front face of the silicon substrate 10 and the first dielectric layer 40. In particular, the electric field layer is produced on the silicon substrate 10 by phosphorus diffusion, or the floating junction is produced by boron diffusion. The electric field layer or the floating junction is used as a front-face electric field of the solar cell.

[0097] In one embodiment of the disclosure, the first conductive layer 60 and / or the second conductive layer 70 are a TCO-transparent conductive film and / or a metal electrode. The metal electrode comprises a silver electrode, a copper electrode, an aluminum electrode, a tinned copper electrode, or a silver-coated copper electrode. Furthermore, the copper electrode is electroplated copper produced using an electroplating process or a copper electrode produced by physical vapor deposition. A nickel electrode, a chromium electrode, a titanium electrode, or a tungsten electrode is used as a seed layer or a protective layer of the electroplated copper. It should be noted that the first conductive layer 60 and the second conductive layer 70 can select the same electrode or different electrodes.For example, the first conductive layer 60 and the second conductive layer 70 both choose the aluminum electrode, or the first conductive layer 60 chooses the silver electrode and the second conductive layer 70 chooses the aluminum electrode.

[0098] Furthermore, in one embodiment of the disclosure, a texturing process is carried out before the first dielectric layer 40 is produced on the front surface of the silicon substrate 10. A shape formed on the front surface includes, but is not limited to, an alkali-polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape intermediate between the aforementioned shapes. The surface shape formed on the front surface of the silicon substrate 10 helps to reduce the reflection of sunlight on the front surface, thereby improving the conversion efficiency of the solar cell.

[0099] Furthermore, in one embodiment of the disclosure, the second dielectric layer 50 can cover only a region between the first doped region 20 and the second doped region 30 on the silicon substrate 10, or extend to cover the first doped region 20 and / or the second doped region 30. If the second dielectric layer 50 covers only the region between the first doped region 20 and the second doped region 30 on the silicon substrate 10, the first conductive layer 60 covers an entire back side of the first doped region 20 for electrical connection, and the second conductive layer 70 covers an entire back side of the second doped region 30 for electrical connection.If the second dielectric layer 50 extends to cover the first doped region 20 and / or the second doped region 30, the first conductive layer 60 covers a back side of any remaining part not covered by the second dielectric layer 50 in the first doped region 20 to establish an electrical connection, and the second conductive layer 70 covers a back side of any remaining part not covered by the second dielectric layer 50 in the second doped region 30 to establish an electrical connection.When the second dielectric layer 50 covers the entire back surface, the first conductive layer 60 penetrates the second dielectric layer 50 through perforations or the like to be electrically connected to the first doped region 20, and the second conductive layer 70 penetrates the second dielectric layer 50 through perforations or the like to be electrically connected to the second doped region 30. The conductive polarities of the first conductive layer 60 and the second conductive layer 70 are determined according to the polarities of the first doped region 20 and the second doped region 30, which are not specifically limited here.

[0100] In one embodiment of the disclosure, with reference to Fig. 2, Fig. 3 and Fig. In Figure 4, the first doped region 20 and the second doped region 30 are arranged alternately on the back side of the silicon substrate 10. To prevent undesirable phenomena, such as electrical leakage, caused by an unobstructed connection between the first doped region 20 and the second doped region 30, a trench is provided between them. The trench separates the first doped region 20 from the second doped region 30. Accordingly, the second dielectric layer 50 covers the trench. It should be noted that the surface of the trench in contact with the silicon substrate 10 may also have a rough textured structure.The rough texture structure is typically created by texturing and includes, but is not limited to, an alkali-polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape intermediate between the above. An irregular hemispherical texture can be created by acid texturing, a pyramidal texture can be created by alkaline texturing, or the pyramidal texture can first be created by alkaline texturing and then smoothed on one side of the pyramidal texture by acid texturing.In this way, the surface shape formed at the trench on the back of the silicon substrate 10 helps the silicon substrate 10 to absorb and reuse light more effectively, and the short-circuit current density is increased, thereby improving the conversion efficiency of the solar cell.

[0101] In another embodiment of the disclosure, with reference to Fig. 5, Fig. 6 and Fig. 7, spaced-apart grooves are provided on the back side of the silicon substrate 10. The first doped region 20 and the second doped region 30 are arranged alternately in the grooves. The grooves can be formed by laser ablation or by using a combination of a mask (e.g., a hard mask, a silicon oxide mask, a silicon nitride mask, or a photoresist mask) and wet / dry etching. By means of the spaced-apart grooves on the back side of the silicon substrate 10, a protrusion is generally formed between two adjacent grooves of the silicon substrate 10. Therefore, the blocking between the first doped region 20 and the second doped region 30, which are arranged in the grooves, can be achieved by the protrusion structure between the grooves of the silicon substrate 10.Optionally, a trench can also be arranged between the first doped region 20 and the second doped region 30. In this case, a trench can be provided in the projection structure or the groove, so that double insulation between the first doped region 20 and the second doped region 30 can be achieved by the projection structure between the grooves of the silicon substrate 10 and the trench structure.

[0102] The first doped region 20 and the second doped region 30 have at least the passivated contact structure described in the embodiments above. It should be noted that the passivation layer in the passivated contact structure can cover only the bottom wall of the grooves or extend to cover the side walls of the grooves. Preferably, the passivation layer covers both the bottom wall and the side walls of the groove. In this case, the first doped layer is accordingly arranged on the bottom wall and the side walls of the groove. Therefore, the charge carriers generated on the silicon substrate 10 are readily separated and selectively collected in the corresponding second doped layer using the passivation layer on the side walls of the groove. In this way, multidimensional charge carrier capture in the bottom wall and the side walls of the groove can be achieved.It should be noted that the first doped area 20 and the second doped area 30 may each be arranged in sub-areas in the corresponding grooves.

[0103] Furthermore, in one embodiment of the disclosure, the groove has a circular arc shape, a trapezoidal shape, or a square shape. The groove is preferably configured as a circular arc or a trapezoid. When the groove is configured as a circular arc or a trapezoid, the inner walls of the groove can reflect light more effectively, and the surface area of ​​the passivation layer of the passivated contact structure, which is in contact with the first doped layer, can be further increased. Naturally, if the groove is configured as a square shape, the actual production process is much simpler. It should also be noted that the grooves can have the same shape or different shapes.For example, the groove of the first doped area 20 and the groove of the second doped area 30 are designed as square shapes, or the groove of the first doped area 20 is designed as a square shape, and the groove of the second doped area 30 is designed as a circular arc shape, or similar. Thus, the shapes of the grooves can be designed according to the actual application requirements, which are not specifically limited here. Furthermore, the width and depth of each groove can be the same or different and can be designed according to the actual application requirements, which are not specifically limited here.

[0104] Furthermore, in one embodiment of the disclosure, the total thickness of the first doped region 20 and / or the total thickness of the second doped region 30 can be greater than, less than, or equal to the depth of the groove. If the total thickness of the first doped region 20 and / or the total thickness of the second doped region 30 is less than or equal to the depth of the groove, the first doped region 20 and / or the second doped region 30 do not extend beyond the groove. Therefore, the blocking of the first doped region 20 and / or the second doped region 30 is directly achieved by the projection structure between the grooves. If the total thickness of the first doped region 20 and / or the total thickness of the second doped region 30 is greater than the depth of the groove, the first doped region 20 and / or the second doped region 30 can extend to projection areas between the grooves.This means, for example, that the first doped area 20 can extend over a partial or total area between the grooves, but does not come into contact with the adjacent second doped area 30.

[0105] Furthermore, in one embodiment of the disclosure, the back side of the silicon substrate 10 has a rough textured structure in the protruding areas between the grooves. The rough textured structure is typically formed by texturing and includes, but is not limited to, an alkali-polished surface, a mechanically polished surface, a random pyramidal shape, an inverted pyramidal shape, a spherical cap shape, a V-shaped groove, and a shape intermediate between the aforementioned shapes. An irregular hemispherical texture can be formed by acid texturing, a pyramidal texture can be formed by alkaline texturing, or the pyramidal texture can first be formed by alkaline texturing, and then smoothing is performed on one top side of a pyramidal texture by acid texturing.It can be understood that the rough texture structure can also be arranged on the entire back side of the silicon substrate 10.

[0106] In yet another embodiment of the disclosure, with reference to Fig. 8 to Fig. Figure 11 shows grooves spaced apart on the back side of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 is located in one of the grooves, and the other of the first and second doped regions is located outside the groove. To achieve blockage between the first doped region 20 and the second doped region 30, a trench can be provided between them. The first doped region 20 is separated from the second doped region 30 by the trench, as shown in Figure 11. Fig. 8, Fig. 9 and Fig. 10 shown. The first doped region 20 and the second doped region 30 can also be arranged in partial areas inside and outside the grooves, such that the silicon substrate 10 inside and outside the grooves, which is not covered by the first doped region 20 and the second doped region 30, realizes the separation of the first doped region 20 from the second doped region 30, as shown in Fig. Figure 11 shows that the non-contact between the first doped area 20 and the second doped area 30 can also be achieved by adjusting the groove depth. Further specific descriptions of the groove and the first doped area 20 and the second doped area 30, located inside and outside the groove, are provided in the descriptions above and are not repeated here.

[0107] Therefore, in one embodiment of the disclosure, the first doped region 20 and the second doped region 30 can both be arranged on the back side of the silicon substrate 10, or can both be arranged on the grooves spaced apart on the silicon substrate 10, or can be arranged inside and outside the grooves spaced apart on the silicon substrate 10, respectively. The first doped region 20 and the second doped region 30 comprise at least the passivated contact structure described in the embodiments above and include a diffusion structure comprising the fourth doped layer, the doped region structure comprising the fourth doped layer, the third passivation layer, and the fifth doped layer, or a conventional passivated contact structure comprising a tunnel layer and a doped region. Thus, the manufactured solar cell can be as follows.

[0108] Cell I: The first doped region 20 and the second doped region 30 are both located on the back side of the silicon substrate 10. The first doped region 20 and the second doped region 30 have the passivated contact structure described in the embodiments above. A groove is provided between the first doped region 20 and the second doped region 30.

[0109] Cell II: The first doped region 20 and the second doped region 30 are both located on the back side of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the diffusion structure comprising the fourth doped layer. A groove is provided between the first doped region 20 and the second doped region 30.

[0110] Cell III: The first doped region 20 and the second doped region 30 are both located on the back side of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the doped region structure comprising the fourth doped layer, the third passivation layer, and the fifth doped layer. A groove is provided between the first doped region 20 and the second doped region 30.

[0111] Cell IV: The first doped region 20 and the second doped region 30 are both located on the back side of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the conventional passivated contact structure comprising the tunnel layer and the doped region. A trench is provided between the first doped region 20 and the second doped region 30.

[0112] Cell V: The first doped region 20 and the second doped region 30 are arranged alternately in the grooves of the silicon substrate 10. Both the first doped region 20 and the second doped region 30 have the passivated contact structure described in the embodiments above.

[0113] Cell VI: The first doped region 20 and the second doped region 30 are arranged alternately in the grooves of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the diffusion structure comprising the fourth doped layer.

[0114] Cell VII: The first doped region 20 and the second doped region 30 are arranged alternately in the grooves of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the doped region structure comprising the fourth doped layer, the third passivation layer, and the fifth doped layer.

[0115] Cell VIII: The first doped region 20 and the second doped region 30 are arranged alternately in the grooves of the silicon substrate 10. One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the conventional passivated contact structure comprising the tunnel layer and the doped region.

[0116] Cell IX: The first doped area 20 is arranged in the groove and the second doped area 30 is arranged on the projection. Both the first doped area 20 and the second doped area 30 have the passivated contact structure described in the embodiments above. A groove may be provided between the first doped area 20 and the second doped area 30.

[0117] Cell X: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the diffusion structure comprising the fourth doped layer. The passivated contact structure is arranged on the projection, and the diffusion structure is arranged in the groove. A trench may be provided between the first doped region 20 and the second doped region 30.

[0118] Cell XI: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the diffusion structure comprising the fourth doped layer. The passivated contact structure is arranged in the groove, and the diffusion structure is arranged on the projection. A trench may be provided between the first doped region 20 and the second doped region 30.

[0119] Cell XII: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the doped region structure comprising the fourth doped layer, the third passivation layer, and the fifth doped layer. The passivated contact structure is arranged on the projection, and the doped region structure is arranged in the groove. A trench may be provided between the first doped region 20 and the second doped region 30.

[0120] Cell XIII: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the doped region structure comprising the fourth doped layer, the third passivation layer, and the fifth doped layer. The passivated contact structure is arranged in the groove, and the doped region structure is arranged on the projection. A trench may be provided between the first doped region 20 and the second doped region 30.

[0121] Cell XIV: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the conventional passivated contact structure comprising the tunnel layer and the doped region. The passivated contact structure is arranged on the projection, and the conventional passivated contact structure is arranged in the groove. A trench may be provided between the first doped region 20 and the second doped region 30.

[0122] Cell XV: One of the first doped region 20 and the second doped region 30 has the passivated contact structure described in the embodiments above, and the other of the first doped region and the second doped region has the conventional passivated contact structure comprising the tunnel layer and the doped region. The passivated contact structure is arranged in the groove, and the conventional passivated contact structure is arranged on the projection. A trench may be provided between the first doped region 20 and the second doped region 30.

[0123] In this embodiment, an opening is provided in the second passivated contact region, and the conductive layer penetrates this opening to connect with the first passivated contact region, thus locating the conductive layer within the first passivated contact region. Therefore, the second passivated contact region surrounding the conductive layer can form an insulating shield for the conductive layer, thereby creating insulation between an emitter and the conductive layer located on a back-side array within the cell, fabricated using the passivated contact structure. In this way, the insulation effect is enhanced, and the recombination of a space charge region is reduced.If no opening is provided in advance, the conductive layer can be printed directly onto the second passivated contact area for sintering, allowing the conductive layer to penetrate the second passivated contact area and thus come into contact with the second doped layer of the first passivated contact area. In the prior art, the second doped layer and the passivation layer are easily burned through when the conductive layer is printed onto the second doped layer for sintering, resulting in the conductive layer coming into direct contact with the silicon substrate, which leads to increased recombination and a reduced conversion efficiency. The embodiments of the disclosure solve the above problems. Furthermore, the second passivated contact area blocks contaminants, reducing the potential for surface contamination.Furthermore, the opening provided in the second passivated contact area can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus increasing the accuracy of the conductive layer fabrication. Since a Fermi level of the first doped layer is altered, the solid concentration of transition metal increases, thereby improving the gettering of impurities. A Fermi level of the third doped layer is altered, increasing an interfacial defect, allowing heterogeneous nucleation sites to form on the interfacial defect and thus enhancing the gettering effect of impurities. In this way, an additional impurity getter effect is achieved. Hydrogen contained in the second and third doped layers can diffuse inwards during a high-temperature process, further enhancing hydrogen passivation.Therefore, the poor insulation effect of a conventional conductive layer and the increased recombination and reduced conversion efficiency caused by direct contact with a silicon substrate are solved. Example 3

[0124] A third embodiment of the disclosure provides a solar cell. To simplify the description, only parts relating to this embodiment of the disclosure are shown. With reference to Fig. 12 includes the solar cell provided in this embodiment of the disclosure: a silicon substrate 10; the passivated contact structure 1 described in the above embodiments, arranged on a back side of the silicon substrate 10; a third dielectric layer 80, arranged on the passivated contact structure 1; a sixth doped layer 90 and a fourth dielectric layer 100, arranged sequentially on a front face of the silicon substrate 10; and a third conductive layer 110 and a fourth conductive layer 120, electrically connected to the passivated contact structure 1 and the sixth doped layer 90 respectively.

[0125] The passivated contact structure 1 and the sixth doped layer 90 have opposite polarities.

[0126] The sixth doped layer 90 is a monocrystalline silicon-doped layer doped with a group III or group V element. For details of the sixth doped layer, reference is made to the description of the first doped layer in the passivated contact structure 1 in the embodiments above. It should be noted that, since the doped area structure and the sixth doped layer 90 have opposite polarities, the first doped layer and the sixth doped layer 90 are each doped with an element of a different group. That is, if the first doped layer is doped with a group III element, the sixth doped layer 90 is doped with a group V element. If the first doped layer is doped with a group V element, the sixth doped layer 90 is doped with a group III element.

[0127] In one embodiment of the disclosure, the third dielectric layer 80 and the fourth dielectric layer 100 are each one or a combination of a plurality of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer. The third dielectric layer 80 and the fourth dielectric layer 100 achieve a passivation effect. The third dielectric layer 80 and the fourth dielectric layer 100 are each configured as a structure with at least one layer. The refractive indices of the third dielectric layer and the fourth dielectric layer decrease from the silicon substrate 10 outwards, such that a film layer near the silicon substrate 10 achieves the passivation effect and a film layer farther from the silicon substrate 10 achieves an antireflection effect, thereby enhancing the antireflection effect.In this way, the silicon substrate 10 absorbs and utilizes light more effectively, and the short-circuit current density is increased. Each film layer in the third dielectric layer 80 and in the fourth dielectric layer 100, which has a different structure, can comprise a variety of films, each with a different refractive index. As described above, the film layers are arranged such that the refractive indices of the film layers decrease outwards from the silicon substrate 10. For example, the silicon oxide layer in the third dielectric layer 80 can comprise a variety of silicon oxide films with refractive indices that decrease outwards from the silicon substrate 10.

[0128] It should be noted that the third dielectric layer 80 and the fourth dielectric layer 100 can have the same or different structural arrangements. The film layer structures in the third dielectric layer 80 and in the fourth dielectric layer 100 can be designed according to the actual application requirements, which are not specifically limited here. Preferably, the third dielectric layer 80 and the fourth dielectric layer 100 are identical, so that the fourth dielectric layer 100 and the third dielectric layer 80 can be produced on the front and back sides of the silicon substrate 10, respectively, using the same process.

[0129] In a preferred embodiment of the disclosure, the third dielectric layer 80 and / or the fourth dielectric layer 100 comprise a bilayer structure of an aluminum oxide layer and a silicon carbide layer, or a bilayer structure of a silicon oxide layer and a silicon carbide layer. The total thickness of the third dielectric layer 80 is greater than 25 nm, and the total thickness of the fourth dielectric layer 100 is greater than 50 nm. It can be understood that the specific structural arrangements of the third dielectric layer 80 and the fourth dielectric layer 100 include, but are not limited to, the specific examples listed above.

[0130] Furthermore, in one embodiment of the disclosure, the thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer 80 is less than 25 nm. The thickness of the aluminum oxide layer or the silicon oxide layer in the fourth dielectric layer 100 is less than 40 nm. The thickness of the silicon carbide layer in the third dielectric layer 80 and / or in the fourth dielectric layer 100 is greater than 10 nm. The silicon carbide layer in the third dielectric layer 80 and / or in the fourth dielectric layer 100 can not only provide a hydrogen passivation effect but also reduce parasitic light absorption due to a large optical band gap and a small absorption coefficient.

[0131] It should be noted that the multilayer structure in this embodiment corresponds to the disclosed arrangement sequence from the silicon substrate 10 outwards. For example, if the third dielectric layer 80 above contains the aluminum oxide layer and the silicon carbide layer, the aluminum oxide layer is located close to the silicon substrate 10 and the silicon carbide layer is located near the outer surface. It should also be noted that in the drawings Fig.Figure 12 shows only the third dielectric layer 80 and the fourth dielectric layer 100 as double-layer structures. However, it can be understood that the third dielectric layer 80 and the fourth dielectric layer 100 may also contain other numbers of layers. Corresponding specific structures can be designed according to actual needs and are not entirely limited to the drawings. It should also be noted that each drawing in the disclosure is used merely to describe the specific structural distribution in the solar cell, but does not correspond to an actual size of each structure. The drawings do not fully correspond to specific actual sizes in this embodiment, and the actual size of each structure must correspond to certain parameters provided in this embodiment.

[0132] Furthermore, the silicon carbide layer in the third dielectric layer 80 and / or the fourth dielectric layer 100 comprises at least one silicon carbide film, each having a specific refractive index. The refractive indices of the silicon carbide films decrease outwards from the silicon substrate 10. Optionally, the refractive index of each material can generally be chosen as follows: the refractive index of monocrystalline silicon is 3.88, the refractive index of amorphous silicon is in the range of 3.5–4.2, the refractive index of polysilicon is 3.93, the refractive index of silicon carbide is in the range of 2–3.88, the refractive index of silicon nitride is in the range of 1.9–3.88, the refractive index of silicon oxynitride is in the range of 1.45–3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63.It can be understood that the refractive indices of the above materials can also be adjusted to other values ​​according to the actual usage requirements, which are not specifically limited herein.

[0133] Furthermore, in one embodiment of the disclosure, a magnesium fluoride layer is arranged outside the third dielectric layer 80 and / or the fourth dielectric layer 100. That is, in addition to one or a combination of several of the aluminum oxide layer, the silicon nitride layer, the silicon oxynitride layer, the silicon carbide layer, the amorphous silicon layer, and the silicon oxide layer selected for the third dielectric layer 80 and the fourth dielectric layer 100, a magnesium fluoride layer can be arranged outside the third dielectric layer 80 and / or the fourth dielectric layer 100. The magnesium fluoride layer must have a very low refractive index. Generally, the refractive index is set to 1.4. The magnesium fluoride layer has an optical effect that improves antireflection.

[0134] In one embodiment of the disclosure, the third conductive layer 110 and / or the fourth conductive layer 120 are a TCO-transparent conductive film and / or a metal electrode. The metal electrode comprises a silver electrode, a copper electrode, an aluminum electrode, a tinned copper electrode, or a silver-coated copper electrode. Furthermore, the copper electrode is electroplated copper produced using an electroplating process or a copper electrode produced by physical vapor deposition. A nickel electrode, a chromium electrode, a titanium electrode, or a tungsten electrode is used as a seed layer or a protective layer of the electroplated copper. It should be noted that the third conductive layer 110 and the fourth conductive layer 120 can be of the same material or different materials.For example, the third conductive layer 110 and the fourth conductive layer 120 both select the aluminum electrode, or the third conductive layer 110 selects the silver electrode and the fourth conductive layer 120 selects the aluminum electrode. Furthermore, the third conductive layer 110 penetrates the third dielectric layer 80 through perforations or the like to be electrically connected to the passivated contact structure 1. The third conductive layer 110 penetrates the fourth dielectric layer 100 through perforations or the like to be electrically connected to the sixth doped layer 90. The conductive polarities of the third conductive layer 110 and the fourth conductive layer 120 are determined according to the polarities of the passivated contact structure 1 and the sixth doped layer 90, which are not specifically limited here.

[0135] Furthermore, in one embodiment of the disclosure, a texturing process is carried out before the fourth dielectric layer 100 is produced on the front surface of the silicon substrate 10. A shape formed on the front surface is not limited to an alkali-polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape intermediate between the above. The surface shape formed on the front surface of the silicon substrate 10 helps to reduce the reflection of sunlight on the front surface, thereby improving the conversion efficiency of the solar cell.

[0136] In this embodiment, an opening is provided in the second passivated contact region, and the conductive layer penetrates this opening to connect with the first passivated contact region, thus locating the conductive layer within the first passivated contact region. Therefore, the second passivated contact region surrounding the conductive layer can form an insulating shield for the conductive layer, thereby creating insulation between an emitter and the conductive layer located on a back-field array within the cell, fabricated using the passivated contact structure. In this way, the insulation effect is enhanced, and the recombination of a space charge region is reduced.If no opening is provided in advance, the conductive layer can be printed directly onto the second passivated contact area for sintering, allowing the conductive layer to penetrate the second passivated contact area and thus come into contact with the second doped layer of the first passivated contact area. In the prior art, the second doped layer and the passivation layer are easily burned through when the conductive layer is printed onto the second doped layer for sintering, resulting in the conductive layer coming into direct contact with the silicon substrate, which leads to increased recombination and a reduced conversion efficiency. The embodiments of the disclosure solve the above problems. Furthermore, the second passivated contact area blocks contaminants, reducing the potential for surface contamination.Furthermore, the opening provided in the second passivated contact area can be used as an alignment reference during the subsequent fabrication of the conductive layer, thus increasing the accuracy of the conductive layer fabrication. Since a Fermi level of the first doped layer is altered, the solid concentration of transition metal increases, thereby improving the gettering of impurities. A Fermi level of the third doped layer is altered, increasing an interfacial defect, allowing heterogeneous nucleation sites to form on the interfacial defect and thus enhancing the gettering effect of impurities. In this way, an additional impurity getter effect is achieved. Hydrogen contained in the second and third doped layers can diffuse inwards during a high-temperature process, further enhancing hydrogen passivation.Therefore, the poor insulation effect of a conventional conductive layer and the increased recombination and reduced conversion efficiency caused by direct contact with a silicon substrate are solved. Example 4

[0137] A fourth embodiment of the disclosure further provides a cell arrangement. The cell arrangement comprises the solar cell described in Example 2. Example 5

[0138] A fifth embodiment of the disclosure further provides a photovoltaic system. The photovoltaic system comprises the cell arrangement described in Example 4. Example 6

[0139] A sixth embodiment of the disclosure further provides a cell arrangement. The cell arrangement comprises the solar cell described in Example 3. Example 7

[0140] A seventh embodiment of the disclosure further provides a photovoltaic system. The photovoltaic system comprises the cell arrangement described in Example 6.

[0141] The foregoing descriptions are merely preferred embodiments of the disclosure and are not intended to limit the disclosure. Any modification, equivalent replacement, or improvement made in accordance with the spirit and principles of the disclosure falls within the scope of protection afforded by the disclosure.

[0142] The disclosure also includes the objects of the following embodiments: Embodiment 1: A passivated contact structure of a solar cell, the passivated contact structure comprising: a silicon substrate; a first passivated contact area arranged on the silicon substrate, and a second passivated contact area arranged on the first passivated contact area; wherein: the first passivated contact area comprises a first doped layer, a first passivation layer, and a second doped layer; the second passivated contact area comprises a second passivation layer and a third doped layer; the first doped layer, the first passivation layer, the second doped layer, the second passivation layer, and the third doped layer are arranged sequentially on the silicon substrate; and the second passivated contact area comprises an opening for connecting a conductive layer of the solar cell to the first passivated contact area. Embodiment 2: The passivated contact structure according to embodiment 1, wherein the first passivation layer is a porous structure comprising a hole area, and the first doped layer and / or the second doped layer are arranged in the hole area. Embodiment 3: The passivated contact structure according to embodiment 1, wherein the second doped layer and the third doped layer have opposite doping polarities. Embodiment 4: The passivated contact structure according to embodiment 1, wherein the first doped layer and the second doped layer have the same doping polarity. Embodiment 5: The passivated contact structure according to embodiment 2, wherein a pore size of the porous structure is less than 20 µm. Embodiment 6: The passivated contact structure according to embodiment 2, wherein part of the hole area of ​​the porous structure comprises the first doped layer and / or the second doped layer. Embodiment 7: The passivated contact structure according to embodiment 2, wherein the ratio of an area of ​​the hole region of the porous structure to a total area of ​​the porous structure is less than 20%. Embodiment 8: The passivated contact structure according to embodiment 1, wherein the thickness of the second passivation layer is greater than the thickness of the first passivation layer. Embodiment 9: The passivated contact structure according to embodiment 1, wherein the thickness of the first passivation layer is in the range of 0.5-10 nm. Embodiment 10: The passivated contact structure according to embodiment 1, wherein the thickness of the second passivation layer is in a range of 5-150 nm. Embodiment 11: The passivated contact structure according to embodiment 1, wherein the first passivation layer and / or the second passivation layer is an oxide layer, a silicon carbide layer, an amorphous silicon layer or a combination thereof. Embodiment 12: The passivated contact structure according to embodiment 11, wherein the oxide layer comprises one or more silicon oxide layers and aluminum oxide layers. Embodiment 13: The passivated contact structure according to embodiment 1, wherein a doping concentration of the first doped layer lies between a doping concentration of the silicon substrate and a doping concentration of the second doped layer. Embodiment 14: The passivated contact structure according to embodiment 1, wherein the second doped layer and / or the third doped layer comprises a polysilicon-doped layer, a silicon carbide-doped layer or an amorphous silicon-doped layer. Embodiment 15: The passivated contact structure according to embodiment 14, wherein the silicon carbide-doped layer in the second doped layer or the third doped layer comprises at least one silicon carbide-doped film; and refractive indices of silicon carbide-doped films decrease from the silicon substrate outwards. Embodiment 16: The passivated contact structure according to embodiment 14, wherein the silicon carbide-doped layer in the second doped layer and / or in the third doped layer comprises a hydrogenated silicon carbide-doped layer, and a conductivity of the hydrogenated silicon carbide-doped layer is greater than 0.01 S·cm; and a thickness of the hydrogenated silicon carbide-doped layer is greater than 10 nm. Embodiment 17: A solar cell comprising: a silicon substrate; a first doped region and a second doped region, spaced apart on a back side of the silicon substrate and having opposite polarities; a first dielectric layer, arranged on a front side of the silicon substrate; a second dielectric layer, arranged between the first doped region and the second doped region; and a first conductive layer and a second conductive layer, arranged in the first doped region and the second doped region respectively; wherein the first doped region and / or the second doped region uses the passivated contact structure according to any one of embodiments 1 to 16. Embodiment 18: The solar cell according to embodiment 17, wherein one of the first doped area and the second doped area uses the passivated contact structure and the other of the first doped area and the second doped area is a fourth doped layer arranged on the silicon substrate. Embodiment 19: The solar cell according to embodiment 18, wherein a third passivation layer and a fifth doped layer are arranged sequentially on the fourth doped layer. Embodiment 20: The solar cell according to embodiment 17, wherein spaced grooves are provided on the back side of the silicon substrate and the first doped area and the second doped area are arranged alternately in the grooves. Embodiment 21: The solar cell according to embodiment 17, wherein spaced grooves are provided on the back side of the silicon substrate; one groove is arranged in one of the grooves between the first doped area and the second doped area, and the other groove is arranged outside the grooves between the first doped area and the second doped area. Embodiment 22: The solar cell according to embodiment 17, 20 or 21, wherein a trench is provided between the first doped area and the second doped area. Embodiment 23: The solar cell according to embodiment 21, wherein the first doped area and the second doped area are arranged in a subset of areas inside and outside the grooves. Embodiment 24: The solar cell according to embodiment 17, wherein the first dielectric layer and the second dielectric layer are each an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer or a combination thereof. Embodiment 25: The solar cell according to embodiment 24, wherein the first dielectric layer and / or the second dielectric layer comprises the aluminum oxide layer and the silicon carbide layer or the silicon oxide layer and the silicon carbide layer; and the thickness of the first dielectric layer is greater than 50 nm and the thickness of the second dielectric layer is greater than 25 nm. Embodiment 26: The solar cell according to embodiment 25, wherein the thickness of the aluminium oxide layer or the silicon oxide layer in the first dielectric layer is less than 40 nm, the thickness of the aluminium oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm and the thickness of the silicon carbide layer in the first dielectric layer and / or in the second dielectric layer is greater than 10 nm. Embodiment 27: The solar cell according to embodiment 24 or 25, wherein the silicon carbide layer in the first dielectric layer and / or in the second dielectric layer comprises at least one silicon carbide film; and refractive indices of silicon carbide films decrease from the silicon substrate outwards. Embodiment 28: The solar cell according to embodiment 24, wherein a magnesium fluoride layer is arranged outside the first dielectric layer and / or the second dielectric layer. Embodiment 29: The solar cell according to embodiment 17, wherein the first conductive layer and the second conductive layer are transparent conductive films of transparent conductive oxide layer (TCO) and / or metal electrodes. Embodiment 30: The solar cell according to embodiment 29, wherein the metal electrodes each comprise a silver electrode, a copper electrode, an aluminum electrode, a tinned copper electrode or a silver-coated copper electrode. Embodiment 31: The solar cell according to embodiment 17, wherein an electric field layer or a floating junction is arranged between the front of the silicon substrate and the second dielectric layer. Embodiment 32: The solar cell according to embodiment 17, wherein one of the first doped region and the second doped region is a P-type doped region and the other of the first doped region and the second doped region is an N-type doped region; and a thickness of a first passivation layer in the P-type doped region is greater than a thickness of a first passivation layer in the N-type doped region. Embodiment 33: The solar cell according to embodiment 17, wherein one of the first doped region and the second doped region is a P-type doped region and the other of the first doped region and the second doped region is an N-type doped region, and a hole density of a first passivation layer in the P-type doped region is greater than a hole density of a first passivation layer in the N-type doped region. Embodiment 34: A solar cell comprising: a silicon substrate; the passivated contact structure according to one of embodiments 1 to 16, arranged on a back side of the silicon substrate; a third dielectric layer, arranged on the passivated contact structure; a sixth doped layer and a fourth dielectric layer, arranged sequentially on a front side of the silicon substrate; and a third conductive layer and a fourth conductive layer, electrically connected to the passivated contact structure and the sixth doped layer respectively; wherein the passivated contact structure and the sixth doped layer have opposite polarities. Embodiment 35: A cell arrangement comprising the solar cell according to one of embodiments 17 to 33. Embodiment 36: A photovoltaic system comprising the cell arrangement according to embodiment 35.

Claims

[1] Passivated contact structure of a solar cell, comprising the passivated contact structure: a silicon substrate; a first passivated contact area arranged on the silicon substrate, and a second passivated contact area arranged on the first passivated contact area; wherein: the first passivated contact area comprises a first doped layer, a first passivation layer and a second doped layer; the second passivated contact area comprises a second passivation layer and a third doped layer; the first doped layer, the first passivation layer, the second doped layer, the second passivation layer, and the third doped layer are arranged sequentially on the silicon substrate; and the second passivated contact area includes an opening for connecting a conductive layer of the solar cell to the first passivated contact area, where the first passivation layer is an oxide layer comprising a silicon oxide layer or a combination of an oxide layer comprising a silicon oxide layer and a silicon carbide layer or an amorphous silicon layer, the second passivation layer is an amorphous silicon layer or a combination of an amorphous silicon layer and an oxide layer or a silicon carbide layer, and The thickness of the second passivation layer is greater than the thickness of the first passivation layer. [2] Passivated contact structure according to claim 1, wherein a conductive layer penetrates the opening to be connected to the second doped layer. [3] Passivated contact structure according to claim 2, wherein each of the first doped layer and the second doped layer is an N-type doped layer. [4] Passivated contact structure according to claim 1, wherein the first doped layer is part of the silicon substrate. [5] Passivated contact structure according to claim 1, wherein the second doped layer is an N-type doped polysilicon. [6] Passivated contact structure according to claim 1, wherein the third doped layer contains hydrogen. [7] Passivated contact structure according to claim 1, wherein the thickness of the first passivation layer is in the range of 0.5-10 nm. [8] Passivated contact structure according to claim 1, wherein a conductive channel is formed in the first passivation layer. [9] Passivated contact structure according to claim 1, wherein the first passivation layer contains a diffused N-type dopant. [10] Passivated contact structure according to claim 1, wherein the thickness of the second passivation layer is in the range of 5-150 nm. [11] Passivated contact structure according to claim 1, wherein the third doped layer comprises an amorphous silicon-doped layer. [12] Passivated contact structure according to claim 1, wherein the second passivation layer is in contact with the second doped layer and the third doped layer. [13] Solar cell, comprising: a silicon substrate; a first doped region and a second doped region, spaced apart on a back side of the silicon substrate and having opposite polarities; a first dielectric layer, arranged on one front side of the silicon substrate; a second dielectric layer, arranged between the first doped region and the second doped region; and a first conductive layer and a second conductive layer, arranged in the first doped region and the second doped region respectively; where the first doped area and / or the second doped area use the passivated contact structure according to any one of claims 1 to 12. [14] Solar cell according to claim 13, wherein the first conductive layer and the second conductive layer are transparent conductive films of transparent conductive oxide layer (TCO) and / or metal electrodes. [15] Solar cell according to claim 13, wherein the second doped layer is a P-type doped layer. [16] Solar cell according to claim 13, wherein one of the first doped region and the second doped region is arranged in one of the grooves and the other of the first doped region and the second doped region is arranged outside the grooves. [17] Solar cell according to claim 16, wherein the first doped area is arranged outside the grooves. [18] Solar cell according to claim 13, wherein the second doped region comprises a third passivation layer and a fifth doped layer. [19] Solar cell according to claim 15, wherein the first doped region is an N-type doped region and the thickness of the third passivation layer is greater than the thickness of the first passivation layer. [20] Solar cell according to claim 18, wherein the third passivation layer comprises a P-type dopant and the first passivation layer comprises an N-type dopant. [21] Solar cell according to claim 18, wherein the thickness of the second passivation layer is greater than the thickness of the third passivation layer. [22] Solar cell according to claim 18, wherein the third passivation layer comprises an amorphous silicon layer. [23] Cell arrangement comprising the solar cell according to any one of claims 13 to 22. [24] Photovoltaic system comprising the cell arrangement according to claim 23.

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