Device with a signal amplifier integrated into a semiconductor chip

Abstract

Device (1, 1') with a signal amplifier (2, 2') integrated into a semiconductor chip, the signal amplifier having an amplifier input (E) for an input signal and an amplifier output (A) for an output signal, the signal amplifier (2, 2') having at least two amplifier stages (6, 6', 7, 7', 8, 9) connected in series between the amplifier input (E) and the amplifier output (A) and a feedback network arranged between the amplifier input (E) and the amplifier output (A), and with an error detection circuit (3) integrated into the semiconductor chip for detecting a faulty modulation of the output signal caused by a fault in the circuitry of the integrated circuit, the error detection circuit having a comparator (16),which is designed to compare a comparator input signal applied to a comparator input (17) of the comparator (16) with a predetermined tolerance value or tolerance range, characterized in that a comparator input (17) of the comparator (16) is connected to a node (14, 14') of the signal amplifier (2, 2') arranged between two amplifier stages (6, 6', 7, 7', 8, 9), and that the signal amplifier (2, 2') is designed such that a signal can be output at the node (14, 14') which is more strongly modulated than the input signal.

Description

[0001] The invention relates to a device with a signal amplifier integrated into a semiconductor chip, which has an amplifier input for an input signal and an amplifier output for an output signal, wherein the signal amplifier has at least two amplifier stages connected in series between the amplifier input and the amplifier output and a feedback network arranged between the amplifier input and the amplifier output, with an error detection circuit integrated into the semiconductor chip for detecting a faulty control of the output signal caused by a fault in the circuitry of the integrated circuit, wherein the error detection circuit has a comparator which is configured to compare a comparator input signal applied to a comparator input of the comparator with a predetermined tolerance value or a tolerance range.

[0002] Sensor technology is becoming increasingly important in the field of automotive engineering. Particularly when sensors are used in safety-related applications, very high demands are placed not only on the accuracy but also on the reliability of the sensor signals. According to the state of the art, the reliability of the systems is increased through redundant design, including systemic plausibility checks.

[0003] As an alternative to redundancy, relevant signal paths in the systems are monitored or designed to be robust against known sources of interference and effects by means of compensating architectures.

[0004] Especially in the field of electronic circuit architecture combined with physical sensors, many approaches are known that lead to extremely robust systems. A generic example of this is the temperature compensation of the circuit and sensor, which is inherent in modern sensor systems. Other effects, such as electromagnetic compatibility (EMC), are also sometimes compensated for with satisfactory results.

[0005] A prerequisite for good and reliable compensation is a precise understanding of the mechanisms by which the disturbances are introduced into the sensor system.

[0006] Less well-defined mechanisms of action include, in particular, errors caused by the failure or malfunction of components involved in the overall system's operation. In this case, disturbance compensation fails, and reliability is only guaranteed by diagnostic systems that continuously monitor the system's operation. A faulty output signal is no longer prevented in this case, but it is at least detected and can be signaled to a higher system instance.

[0007] In the case of monolithically integrated sensor systems or integrated circuits (ICs) in general, the potentially fault-causing system components also include the external circuitry, including the input peripherals of an evaluation unit to which the data or sensor signals are transmitted.

[0008] In many applications, the output signals are present as differential or absolute output voltages. An output amplifier drives the external load, which consists of resistive, capacitive, and inductive components, and is sometimes also parasitic.

[0009] If the described failures result in a change in the load, this can lead to an overload of the output amplifier and voltage deviations.

[0010] While large deviations from the internally specified setpoint, for example caused by short circuits, can be detected very easily due to the size of the deviation, smaller deviations of only a few mV, which arise from a moderately increased load current, can only be detected with significantly increased effort.

[0011] A device of the type mentioned above is known in practice, comprising a first signal amplifier integrated into a semiconductor chip, which has several amplifier stages. The first signal amplifier has an amplifier input for a variable input signal and an amplifier output for an output signal. An error detection circuit is integrated into the semiconductor chip, comprising a second signal amplifier identical in construction to the first signal amplifier, whose amplifier input is connected to the amplifier input of the first signal amplifier. The error detection circuit also has a differential amplifier, whose non-inverting input is connected to the amplifier output of the first signal amplifier and whose inverting input is connected to the amplifier output of the second signal amplifier.To detect deviations in the output signals of the signal amplifiers that lie outside a predetermined tolerance range, the output of the differential amplifier is connected to the input of a comparator. If smaller deviations are to be detected, the error detection circuit must have a correspondingly high accuracy. A further disadvantage is that the second signal amplifier requires a considerable amount of circuitry.

[0012] The object of the invention is therefore to provide a device of the type mentioned above, whose fault detection circuit enables a simple and cost-effective design, but can nevertheless detect faulty circuit states of the integrated circuit that cause only small deviations of the output signal from a target output signal.

[0013] This problem is solved by the features of claim 1. These provide, in a device of the type mentioned at the outset, that a comparator input of the comparator is connected to a node of the signal amplifier arranged between two amplifier stages, and that the signal amplifier is designed such that a signal can be output at the node which is more strongly modulated than the input signal.

[0014] An advantage of the device according to the invention is that the first amplifier stage of the multi-stage amplifier can typically have a high gain factor of greater than 1000, while the last amplifier stage, also referred to as the output stage, is more focused on driving capability than on high signal amplification or a high gain factor. This allows deviation signals in the volt range to occur at the nodes between the amplifier stages if the output signal deviates, for example, in the millivolt range. Thus, deviations in the output signal caused by a faulty circuit in the semiconductor chip can be easily detected using a simple comparator whose thresholds are tuned to the normal range of the signal applied at the node.As a result, the comparator's threshold values, which define the tolerance value or tolerance range that triggers error detection, can also be designed with a generous accuracy in the range of a few tens of millivolts, which is easier to implement in the circuit design. The error in the integrated circuit's wiring can, in particular, involve connecting an insufficient load impedance to the amplifier output.

[0015] In a preferred embodiment of the invention, the comparator is designed as a window comparator. The detection circuit thereby enables a two-sided verification of the signal applied to the comparator input.

[0016] This allows the detection circuit to identify errors even more reliably in certain applications.

[0017] A further development of the invention provides that the comparator comprises at least one comparator element having an inverting and a non-inverting comparator element input, that one of these comparator element inputs is connected to the comparator input and the other comparator element input is connected to a limit switch by means of which a limit signal can be applied to the latter comparator element input, and that the limit switch has a device for dynamically adapting the limit signal to the temperature and / or the amplitude of the input signal. The detection circuit thus enables even more reliable fault detection.

[0018] In an advantageous embodiment of the invention, the fault detection circuit includes a low-pass filter. This enables the fault detection circuit to operate more reliably in the event of EMC interference and rapid load changes.

[0019] In the simplest case, the amplifier is designed as a two-stage circuit, and the node connected to the comparator input of the window comparator is located between the first and second amplifier stages. In this configuration, the output of the first amplifier stage is connected to the input of the second amplifier stage and the input of the detection circuit.

[0020] In a preferred embodiment of the invention, the low-pass filter has a low-pass input connected to the node and a low-pass output connected to the comparator input. The comparator output can then serve as the output of the detection circuit. Using a low-pass filter before the comparator limits the input bandwidth and thus reduces the sensitivity of the detection circuit. Rapid load changes, particularly capacitive ones, temporarily cause a strong drive signal at the nodes between the amplifier stages. The detection circuit might then temporarily respond to this. In this case, the low-pass filter prevents the detection circuit from being triggered.

[0021] In a further development of the invention, the low-pass filter is implemented as a first-order RC filter.

[0022] It is advantageous if the window comparator design includes two comparator elements and a digital gate of type NAND or AND, where the output of the digital gate forms the output of the window comparator. The two comparator elements serve to define the upper and lower limits for triggering the detection circuit. The upper and lower thresholds for the window comparator are specified via the respective reference inputs of the comparator elements. If the upper threshold is exceeded by the low-pass filtered signal at the node, the corresponding comparator output switches from logic ONE to NULL. If the lower threshold is undershot by the low-pass filtered signal at the node, the corresponding comparator output switches from logic ONE to NULL. The inputs of the digital gate are connected to the outputs of the two comparator elements.Depending on the definition, exceeding or falling below the corresponding threshold, which corresponds to an error, can then be encoded into a digital output state of ONE or NULL. A NAND or AND gate is particularly suitable for this purpose.

[0023] In an advantageous embodiment of the invention, the signal amplifier has more than two amplifier stages. In this case, the node connected to the comparator input is arranged between the penultimate and the last amplifier stage.

[0024] Further details, features and advantages of the present invention will become apparent from the following description of exemplary embodiments with reference to the drawing.

[0025] It shows: Fig. 1 a device comprising a four-stage signal amplifier designed as a voltage signal amplifier and a fault detection circuit, which are integrated into a semiconductor chip, Fig. 2 a circuit diagram of the fault detection circuit and Fig. 3. An embodiment of a device with a two-stage signal amplifier designed as a voltage signal amplifier.

[0026] The Fig. Figure 1 shows a block diagram of a first embodiment of a device designated in its entirety by 1, which comprises a signal amplifier 2 integrated into a semiconductor chip with an amplifier input E for applying a variable input signal, an amplifier output A for outputting an output signal, and an error detection circuit 3 for detecting a faulty modulation of the output signal caused by a fault in the circuitry of the integrated circuit. Between the amplifier input E and the amplifier output A, the signal amplifier 2 has a feedback network comprising a first feedback impedance 4 and a second feedback impedance 5 connected in series with it.

[0027] The signal amplifier 2 has four amplifier stages 6, 7, 8, 9 connected in series, each with an input and an output 10, 11, 12, 13. The amplifier input E is connected via the first feedback impedance 4 to the input of the first amplifier stage 6. The output 10 of the first amplifier stage 6 is connected to the input of the second amplifier stage 7. The output 11 of the second amplifier stage 7 is connected to the input of a third amplifier stage 8, whose output 12 is connected via a node 14 to the input of a fourth amplifier stage 9. The output 13 of the fourth amplifier stage 9 is connected to the amplifier output A of the signal amplifier 2 and, via the second feedback impedance 5, to the input of the first amplifier stage 6. The node 14 is connected to a signal tap S of the fault detection circuit 3.

[0028] As in Fig. As can be seen in Figure 2, the error detection circuit 3 has a low-pass filter 15 and a comparator 16, which is designed as a window comparator. The low-pass filter 15 includes a resistor R. TP and a capacity C TP . A comparator input 17 of the comparator 16 is used for threshold monitoring via the resistor R. TP with the signal tap S of the fault detection circuit 3 and via the capacitance C TPwith a connection for a reference potential. The comparator 16 comprises two comparator elements 18 and 19 designed as operational amplifiers and a NAND gate 20. A first comparator element 18 has a first, inverting comparator element input, which is connected to the comparator input 17 of the window comparator 16 and to a non-inverting comparator element input of a second comparator element 19. A non-inverting comparator element input O of the first comparator element 18 is connected to an upper threshold encoder (not shown in detail in the drawing), and an inverting comparator element input U of the second operational amplifier 19 is connected to a lower threshold encoder (not shown in detail in the drawing). The upper and lower thresholds define a tolerance range within which the voltage at comparator input 17 may lie during fault-free operation of the signal amplifier 2.

[0029] If the potential at comparator input 17 is higher than the upper threshold, a first voltage corresponding to the logical value zero is present at the output of the first comparator element 18. If the potential at comparator input 17 is lower than the upper threshold, a second voltage corresponding to the logical value one is present at the output of the first comparator element 18.

[0030] Similarly, the second voltage (logic ONE) is present at the output of the second comparator element 19 when the potential at the comparator input 17 is higher than that of the lower threshold. When the potential at the comparator input 17 is lower than that of the lower threshold, the first voltage, corresponding to the logic value ZERO, is present at the output of the second comparator element 19.

[0031] The output of the first comparator element 18 is connected to a first input of the NAND gate 20, and the output of the second operational amplifier 19 is connected to a second input of the NAND gate 20. The output F of the NAND gate 20 forms the output of the fault detection circuit 3. During operation of the device 1, a signal is output at output F indicating whether the potential at the comparator input 17 is within the tolerance range defined by the lower and upper threshold values.

[0032] If the potential at comparator input 17 exceeds the potential at comparator element input O, or falls below the potential at comparator element input U, the signal at output F switches from logic zero to one. If the potential at comparator input 17 is within the tolerance range defined by the potentials at comparator element inputs O and U, output F is logic zero.

[0033] Fig. Figure 3 shows a second embodiment of a device 1' according to the invention, which has a two-stage signal amplifier 2' with an amplifier input E and an amplifier output A. In this embodiment, the amplifier input E is connected via a first feedback impedance 4' to an inverting input of a first amplifier stage 6' and via a second feedback impedance 5' to the output A of the signal amplifier 2'. A non-inverting input of the first amplifier stage 6' is connected to a reference potential Ref.

[0034] Output 10 of the first amplifier stage 6 is connected to node 14' and to an inverting input of a second amplifier stage 7'. An inverting input of the second amplifier stage 6' is connected to the reference potential Ref.

[0035] Output 11 of the second amplifier stage 7 is connected to amplifier output A of signal amplifier 1 and, via the second feedback impedance 5', to the inverting input of the first amplifier stage 6'. The feedback network formed by feedback impedances 4' and 5' generates the feedback factor R1 / (R1+R2) and configures the arrangement as an inverting amplifier.

[0036] Node 14' is connected to the signal tap S of the in Fig. 2 is connected to the fault detection circuit 3 shown. This corresponds to the fault detection circuit 3 of the one shown in Fig. The first embodiment is shown in Figure 1. The description of the first embodiment applies accordingly to the second embodiment.

[0037] It should also be mentioned that the device according to the invention can also be built using bipolar or BiCMOS circuit technology. In some cases, the comparators are then implemented as current comparators rather than voltage comparators.

Claims

[1] Device (1, 1') with a signal amplifier (2, 2') integrated into a semiconductor chip, the signal amplifier having an amplifier input (E) for an input signal and an amplifier output (A) for an output signal, the signal amplifier (2, 2') having at least two amplifier stages (6, 6', 7, 7', 8, 9) connected in series between the amplifier input (E) and the amplifier output (A) and a feedback network arranged between the amplifier input (E) and the amplifier output (A), and with a fault detection circuit (3) integrated into the semiconductor chip for detecting a faulty modulation of the output signal caused by a fault in the circuitry of the integrated circuit, the fault detection circuit having a comparator (16),which is designed to compare a comparator input signal applied to a comparator input (17) of the comparator (16) with a predetermined tolerance value or tolerance range, characterized by , that a comparator input (17) of the comparator (16) is connected to a node (14, 14') of the signal amplifier (2, 2') arranged between two amplifier stages (6, 6', 7, 7', 8, 9), and that the signal amplifier (2, 2') is designed such that a signal can be output at the node (14, 14') which is more strongly modulated than the input signal. [2] Device (1, 1') according to claim 1, characterized by , that the comparator (16) is designed as a window comparator. [3] Device (1, 1') according to claim 1 or 2, characterized by, that the comparator (16) comprises at least one comparator element (18, 19) having an inverting and a non-inverting comparator element input, that one of these comparator element inputs is connected to the comparator input (17) and the other comparator element input is connected to a limit switch by means of which a limit signal can be applied to the latter comparator element input, and that the limit switch has a device for dynamically adapting the limit signal to the temperature and / or the amplitude of the input signal. [4] Device (1, 1') according to any one of claims 1 to 3, characterized by , that the fault detection circuit has a low-pass filter (15). [5] Device (1, 1') according to claim 4, characterized by, that the low-pass filter (15) has a low-pass input connected to the node (14, 14') and a low-pass output connected to the comparator input (17), and that the output of the comparator (16) preferably forms the output (F) of the detection circuit. [6] Device (1, 1') according to claim 4 or 5, characterized by , that the low-pass filter (15) is implemented as a first-order RC filter. [7] Device (1, 1') according to any one of claims 2 to 6, characterized by , that the comparator (16) designed as a window comparator has two comparator elements (18, 19) and a digital gate, preferably of type AND or NAND, and that the output of the digital gate forms the output of the window comparator (16). [8] Device (1, 1') according to any one of claims 1 to 7, characterized by, that the signal amplifier (2) has more than two amplifier stages (6, 6', 7, 7', 8, 9), and that the node (14, 14') connected to the comparator input (17) is located between the penultimate and the last amplifier stage (8, 9).

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