SOP8L power device package structure and preparation method thereof

Abstract

The scheme discloses a SOP8L power device packaging structure and a preparation method thereof. The packaging structure comprises the following steps: a reverse cutting structure is designed for a lead frame, so that the carrier frame is located at the top area of the package after packaging is completed; a top insulating heat dissipation structure is arranged on the carrier frame and the back surface of the semiconductor chip at the top of the package; a whole drain pad is formed by a plurality of pins at the bottom of the package, and a through hole is arranged on the drain pad; a target pin connected to the gate of the semiconductor chip is a composite structure comprising a gull wing structure and a straight insertion structure; and the top insulating heat dissipation structure, the drain pad and the pin area of the package are not packaged. The packaging structure does not need to use compressible thermal bonding materials, realizes stable and predictable low-thermal-resistance heat dissipation through the top insulating heat dissipation structure, and cooperates the reverse cutting frame and the riveting pad to improve the mechanical reliability of the package.

Description

Technical Field

[0001] This solution relates to the field of semiconductor device packaging technology, and in particular to an SOP8L power device packaging structure and its fabrication method. Background Technology

[0002] In existing power device packaging, to balance heat dissipation and electrical insulation, some solutions use compressible insulating and thermally conductive interface materials as thermal bonding layers. However, such solutions typically rely on the elastic deformation of the material to achieve interface bonding, which can easily lead to performance degradation, thickness changes, or interface aging under long-term thermal cycling, mechanical loads, and vibration environments, making it difficult to meet the requirements of high-reliability applications.

[0003] Furthermore, in small surface mount packages such as SOP8L, traditional bottom heat dissipation paths are inadequate in terms of insulation withstand voltage, soldering reliability, and mechanical stability. Summary of the Invention

[0004] This solution aims to at least address the technical problems existing in the prior art. To this end, the first aspect of this invention proposes an SOP8L power device packaging structure, the packaging structure comprising: a carrier frame, a semiconductor chip disposed on the carrier frame, a lead frame, bonding wires, and a package encapsulating the semiconductor chip and a portion of the carrier frame, wherein: The lead frame adopts a reverse-cut structure design, so that the carrier frame is located in the top area of ​​the package after packaging, while the pin area for PCB soldering is located in the bottom of the package. A top insulating heat dissipation structure is provided on the carrier frame located at the top of the package and on the back of the semiconductor chip. The bottom of the package is provided with an integral drain pad formed by multiple pin connections, and the drain pad is provided with through holes; The target pin connected to the Gate terminal of the semiconductor chip is a composite structure including a gull-wing structure and a through-hole structure; The package does not encapsulate the top insulating heat dissipation structure, the drain pad, and the pin area.

[0005] Optionally, the top insulating heat dissipation structure is an integrally formed solid structure that is solidified together with the lead frame and the package body during the packaging process to form a whole.

[0006] Optionally, the top insulating heat dissipation structure is made of a material with high thermal conductivity and high insulation strength, and the outer surface of the top insulating heat dissipation structure is in direct contact with the external heat sink.

[0007] Optionally, the material of the top insulating heat dissipation structure is one or more of the following: alumina, aluminum nitride, and glass ceramic.

[0008] Optionally, the bottom of the package is provided with an integral drain pad formed by multiple pin connections, and the drain pad is provided with through holes.

[0009] Optionally, the through hole is used to absorb and contain molten solder during the reflow soldering process; the solidified solder forms a "rivet"-like mechanical interlocking structure within the through hole.

[0010] Optionally, the gull-wing structure of the target pin is a gull-wing surface mount pin used to provide the main electrical connection; the through-hole structure extends downward into the PCB through-hole to provide additional mechanical anchoring and electrical connection.

[0011] Optionally, the lead frame includes: the carrier frame located in the central region; a plurality of pin segments distributed around the carrier frame; and at least one multi-pin connection area for forming the Drain pad.

[0012] A second aspect of this invention provides a method for fabricating an SOP8L power device package structure, the method comprising: The lead frame is formed by reverse cutting, so that the carrier frame is located in the top area of ​​the package after packaging, while the pin area for PCB soldering is located in the bottom of the package. The back side of the semiconductor chip is fixed to the surface of the carrier frame with solder or conductive adhesive, and the source, gate or other electrodes of the semiconductor chip are facing the pin area of ​​the lead frame. The electrodes of the semiconductor chip are electrically connected to the corresponding lead frame pins using bonding wires; wherein the target pin corresponding to the gate of the semiconductor chip is a composite structure including gull-wing structure and through-hole structure; A top insulating heat dissipation structure is pre-placed or formed in the top region corresponding to the back of the carrier frame and the semiconductor chip. The semiconductor chip, the lead frame, and the bonding wires are molded and packaged to form a package encapsulating the semiconductor chip and a portion of the carrier frame; wherein the top insulating heat dissipation structure is at least partially exposed on the outer surface of the package. Connect the pins PIN5 to PIN8 of the pin area to form an integral drain pad, and form multiple through holes on the drain pad; The lead frame is trimmed and the pins are shaped to form an external dimension that conforms to the SOP8L standard, thus obtaining the SOP8L power device package structure.

[0013] Optionally, after obtaining the SOP8L power device package structure, the following is also included: Electrical performance tests, insulation withstand voltage tests, and reliability verifications were performed on the power devices in the packaged structure.

[0014] The embodiments of the present invention have the following beneficial effects: The SOP8L power device package structure provided in this embodiment of the invention includes: a carrier frame, a semiconductor chip disposed on the carrier frame, a lead frame, bonding wires, and a package body encapsulating the semiconductor chip and a portion of the carrier frame. The lead frame employs a reverse-cut structure design, such that the carrier frame is located at the top region of the package body after packaging, while the pin area for PCB soldering is located at the bottom of the package body. A top insulating heat dissipation structure is provided on the carrier frame and the back of the semiconductor chip located at the top of the package body. A multi-pin-connected integral drain pad is provided at the bottom of the package body, and the drain pad has through-holes. The target pin connected to the gate of the semiconductor chip is a composite structure including gull-wing and through-hole structures. The package body does not encapsulate the top insulating heat dissipation structure, the drain pad, or the pin area. This package structure eliminates the need for compressible thermal bonding materials, avoiding reliability issues caused by compression degradation. Stable and predictable low thermal resistance heat dissipation is achieved through the solid-state top insulating heat dissipation structure. The reverse-cut frame and riveted pads work together to improve the mechanical reliability of the package, making it suitable for high power density, small size SOP8L power device packages. Attached Figure Description

[0015] Figure 1 This is a side cross-sectional view of an SOP8L power device package structure provided in an embodiment of the present invention; Figure 2 This is a top view of an SOP8L power device package structure provided in an embodiment of the present invention; Figure 3 This is a detailed schematic diagram of the PIN4 composite pin structure provided in an embodiment of the present invention; Figure 4 A flowchart illustrating the steps of a method for fabricating an SOP8L power device package structure according to an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present solution, and not all embodiments. Based on the embodiments of the present solution, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present solution.

[0017] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0018] The purpose of this invention is to provide a high-reliability SOP8L power device package structure that achieves low thermal resistance, high insulation withstand voltage, and high mechanical reliability through structural design without using compressible thermal bonding materials, making it suitable for automotive electronics and industrial power applications.

[0019] Figure 1 This is a side cross-sectional view of an SOP8L power device package structure provided in an embodiment of the present invention.

[0020] like Figure 1 As shown, the packaging structure includes: a carrier frame 1, a semiconductor chip 3 disposed on the carrier frame 1, a lead frame 2, bonding wires 4, and a package 5 encapsulating the semiconductor chip 3 and a portion of the carrier frame 1, wherein: The lead frame 2 adopts a reverse-cut structure design, so that the carrier frame 1 is located in the top area of ​​the package body 5 after the packaging is completed, while the pin area for PCB soldering is located at the bottom of the package body 5. A top insulating heat dissipation structure 6 is provided on the back of the carrier frame 1 located at the top of the package 5 and the semiconductor chip 3. The bottom of the package 5 is provided with an integral drain pad 7 formed by multiple pin connections, and the drain pad 7 is provided with through holes 8; The target pin connected to the 3Gate terminal of the semiconductor chip is a composite structure including a gull-wing structure 9 and a through-hole structure 10; The package 5 does not encapsulate the top insulating heat dissipation structure 6, the drain pad 7, and the pin area.

[0021] In this embodiment of the invention, the lead frame 2 adopts a reverse-cut structure design, so that the carrier frame is located in the top area of ​​the package body 5 after the packaging is completed, thereby forming an inverted package shape and providing a structural basis for top heat dissipation.

[0022] A top insulating heat dissipation structure 6 is provided on the carrier frame 1 and the back of the chip located on top of the package 5. The top insulating heat dissipation structure 6 mainly undertakes the functions of heat conduction and electrical isolation. It is not used as an interface bonding material between the carrier frame 1 and the package 5. Under device assembly and working load conditions, it is a low deformation structure and does not have compressible characteristics for buffering mechanical stress.

[0023] The heat dissipation path of the semiconductor device is: semiconductor chip 3 → carrier frame 1 → top solid-state insulating heat dissipation structure 6 → external heat sink. The heat dissipation path is a continuous structural heat conduction path.

[0024] With this design, the heat from the top of the chip can be directly conducted to the external heat sink through the top heat dissipation structure 6, achieving efficient heat dissipation while ensuring high insulation strength and mechanical stability.

[0025] The bottom of the package 5 is provided with an integral drain pad 7 formed by multiple pins. The drain pad 7 is provided with through holes 8, which form a solder riveting structure after reflow soldering to enhance shear resistance and vibration resistance.

[0026] The Gate pin adopts a composite structure combining a gull-wing structure 9 and a through-hole structure 10. The through-hole structure 10 is inserted into the PCB through-hole to provide additional mechanical anchoring for the Gate pin and prevent the pin from lifting or breaking.

[0027] As an optional embodiment, the top insulating heat dissipation structure 6 is a solid-state structure that is integrally formed and solidifies together with the lead frame 2 and the package body 5 during the packaging process to form a whole.

[0028] The top insulating heat dissipation structure 6 is a one-piece solid structure. During the packaging process, the top insulating heat dissipation structure 6 is integrally molded or co-cured with the carrier frame 1 and the package body 5 to form an integral structure, which provides a heat dissipation path from the chip to the outside of the package body 5 and achieves electrical isolation. This structure does not serve as an interface bonding material between the carrier frame 1 and the package body 5, and does not have compressible properties for buffering mechanical stress.

[0029] The thickness of the top heat dissipation structure 6 can be 0.2–1 mm, and the specific thickness can be designed according to the power level.

[0030] As an optional embodiment, the top insulating heat dissipation structure 6 is made of a material with high thermal conductivity and high insulation strength, and the outer surface of the top insulating heat dissipation structure 6 is in direct contact with the external heat sink. The thermal conductivity of the top insulating heat dissipation structure 6 is greater than 4 W / m·K, and the withstand voltage is greater than 3 kV AC.

[0031] As an optional embodiment, the material of the top insulating heat dissipation structure 6 is one or more of the following: alumina, aluminum nitride, and glass ceramic.

[0032] In this embodiment of the invention, the top insulating heat dissipation structure 6 may be made of aluminum nitride, aluminum oxide or glass ceramic materials, or a composite material of the three.

[0033] As an optional embodiment, the bottom of the package 5 is provided with an integral drain pad 7 formed by multiple pin connections, and the drain pad 7 is provided with through holes 8.

[0034] As an optional embodiment, the through hole 8 is used to absorb and contain molten solder during the reflow soldering process; the solidified solder forms a "rivet"-like mechanical interlocking structure within the through hole 8.

[0035] Figure 2 This is a top view of an SOP8L power device package structure provided in an embodiment of the present invention.

[0036] like Figure 2 As shown, the bottom of the package 5 is provided with an integral drain pad 7 formed by the connection of PIN5–PIN8 pins. Several through holes 8 are formed on the drain pad 7.

[0037] During reflow soldering, molten solder can partially flow into the holes, forming a riveted structure.

[0038] The functions of this riveting structure include: 1. absorbing excess solder to prevent bridging and short circuits; 2. forming a mechanical interlock to enhance the shear and vibration resistance of the package within the PCB plane; 3. improving the long-term reliability of the pads and the PCB, especially under thermal cycling and vibration conditions.

[0039] The copper thickness of the Drain pad is approximately 100–200 µm, and the diameter of the through hole 8 is 0.5–1.5 mm.

[0040] This design not only ensures reliable electrical connections at the bottom of the package, but also significantly improves mechanical strength.

[0041] As an optional embodiment, the gull-wing structure 9 of the target pin is a gull-wing surface mount pin used to provide the main electrical connection; the through-hole structure 10 extends downward into the PCB through-hole to provide additional mechanical anchoring and electrical connection.

[0042] As an optional embodiment, the target pins include, but are not limited to, riveted bonding structures, widened through-hole structures, and dual-pin structures.

[0043] Reference Figure 2 The PIN4 (Gate) pin adopts a composite structure combining a gull-wing structure 9 and a through-hole structure 10.

[0044] Figure 3 This is a detailed schematic diagram of the PIN4 composite pin structure provided in an embodiment of the present invention.

[0045] like Figure 3 As shown, the gull-wing structure 9 is used for surface mount technology (SMT) and provides the main electrical connection; the through-hole structure 10 extends into the PCB via and provides additional mechanical anchoring and electrical connection.

[0046] This design can prevent the base of the Gate pin from breaking or falling off the pad under high-temperature thermal cycling or vibration environments, thereby ensuring the functional reliability of the power device.

[0047] The length of the gull-wing structure is approximately 1.0–1.5 mm, and the length of the straight-insertion structure is approximately 0.8–1.2 mm.

[0048] These parameters can be adjusted according to specific power device and packaging requirements, but the core technology remains unchanged.

[0049] As an optional embodiment, the lead frame 2 includes: the carrier frame located in the central region; a plurality of pin segments distributed around the carrier frame; and at least one multi-pin connection area for forming the Drain pad 7.

[0050] The carrier frame of this solution is located at the top via a reverse-cut frame, achieving structural heat dissipation. The top solid-state insulated heat dissipation structure 6 provides a high thermal conductivity and high insulation top heat dissipation path. The integral drain pad 7 at the bottom of the package forms a riveting structure through holes, improving PCB soldering reliability. The gate pins adopt a gull-wing + through-hole composite structure to ensure stable electrical connection under high temperature and vibration conditions. This solution does not rely on compressible thermal bonding materials and achieves a unified high reliability in thermal, electrical, and mechanical aspects through structural innovation.

[0051] In summary, the SOP8L power device package structure provided by this embodiment of the invention includes: a carrier frame, a semiconductor chip disposed on the carrier frame, a lead frame, bonding wires, and a package body encapsulating the semiconductor chip and a portion of the carrier frame. Specifically: the lead frame adopts a reverse-cut structure design, so that the carrier frame is located in the top region of the package body after packaging, while the pin area for PCB soldering is located at the bottom of the package body; a top insulating heat dissipation structure is provided on the carrier frame and the back of the semiconductor chip located at the top of the package body; a multi-pin-connected integral drain pad is provided at the bottom of the package body, and the drain pad has through holes; the target pin connected to the gate of the semiconductor chip is a composite structure including gull-wing and through-hole structures; the package body does not encapsulate the top insulating heat dissipation structure, the drain pad, and the pin area. This package structure eliminates the need for compressible thermal bonding materials, avoiding reliability issues caused by compression performance degradation; and achieves stable and predictable low thermal resistance heat dissipation through the solid-state top insulating heat dissipation structure. The reverse-cut frame and riveted pads work together to improve the mechanical reliability of the package, making it suitable for high power density, small size SOP8L power device packages.

[0052] Figure 4 A flowchart illustrating the steps of a method for fabricating an SOP8L power device package structure according to an embodiment of the present invention.

[0053] like Figure 4 As shown, the method includes: Step 101: The lead frame is formed by reverse cutting so that the carrier frame is located in the top area of ​​the package after packaging, while the pin area for PCB soldering is located in the bottom of the package.

[0054] The SOP8L lead frame is fabricated using copper or copper alloy materials, and a reverse-cut carrier frame is formed through stamping or etching processes. This reverse-cut structure positions the carrier frame at the top of the package after encapsulation, while the pin area for PCB soldering is located at the bottom of the package.

[0055] The lead frame includes: a carrier frame located in the central region; multiple pin segments distributed around the carrier frame; and at least one multi-pin connection area for forming an integral drain pad.

[0056] Step 102: Fix the back side of the semiconductor chip to the surface of the carrier frame using solder or conductive adhesive, and make the source, gate or other electrodes of the semiconductor chip face the pin area of ​​the lead frame.

[0057] The carrier frame is the frame part for packaging and attaching the chip. The carrier frame is used to hold the chip and also has electrical connection functions.

[0058] The back side of the semiconductor chip is fixed to the surface of the carrier frame using solder or conductive adhesive, with the source, gate, or other electrodes of the semiconductor chip facing the lead frame pin area to provide connection conditions for subsequent bonding.

[0059] Step 103: Connect the electrodes of the semiconductor chip to the corresponding lead frame pins using bonding wires; wherein the target pin corresponding to the Gate electrode of the semiconductor chip is a composite structure including gull-wing structure and through-hole structure.

[0060] Gold, copper, or alloy bonding wires are used to electrically connect the electrodes of a semiconductor chip to the corresponding lead frame pins.

[0061] Among them, the pins corresponding to the Gate pole are pre-formed into a gull-wing and through-hole composite structure, with the through-hole portion extending downward to provide a structural basis for subsequent insertion into PCB through-holes.

[0062] Step 104: Pre-place or form a top insulating heat dissipation structure in the top area corresponding to the back of the carrier frame and the semiconductor chip.

[0063] A top insulating heat dissipation structure is pre-placed or formed in the top area corresponding to the back of the carrier frame and the semiconductor chip.

[0064] The top insulating heat dissipation structure is a solid insulating thermally conductive structure that can be made of aluminum nitride, aluminum oxide, glass ceramics or their composite materials, and has high thermal conductivity and high dielectric strength.

[0065] The top insulating heat dissipation structure is cured together with the lead frame and package body during the encapsulation process to form a stable structural heat dissipation channel, rather than being used as a flexible or compressible interface bonding material.

[0066] Step 105: Moldulate and package the semiconductor chip, the lead frame, and the bonding wire to form a package encapsulating the semiconductor chip and a portion of the carrier frame; wherein the top insulating heat dissipation structure is at least partially exposed on the outer surface of the package.

[0067] Epoxy molding compound is used to mold and encapsulate the lead frame, semiconductor chip and bonding wire, so that the package encapsulates all the semiconductor chip and part of the carrier frame.

[0068] During the molding process, the top insulating heat dissipation structure is at least partially exposed on the outer surface of the package body, forming a top heat dissipation area that can directly contact the external heat sink.

[0069] Step 106: Connect the PIN5 to PIN8 pins of the pin area to form an integral Drain pad, and form multiple through holes on the Drain pad.

[0070] During the lead frame design phase or subsequent processing, pins PIN5 to PIN8 are connected to form an integral drain pad, and multiple through holes are formed on the drain pad.

[0071] The holes are used to absorb solder during reflow soldering and form a riveting structure to improve the reliability of the mechanical connection between the package and the PCB.

[0072] Step 107: Trim the lead frame and shape the pins to make each pin conform to the SOP8L standard dimensions.

[0073] After the molding and packaging are completed, the lead frame is trimmed and the pins are shaped to make each pin conform to the SOP8L standard dimensions.

[0074] The Gate pins form a composite structure combining gull-wing and through-hole designs, with the through-hole portion having sufficient length to be inserted into a PCB via.

[0075] As an optional embodiment, after obtaining the SOP8L power device package structure, the following is also included: Electrical performance tests, insulation withstand voltage tests, and reliability verifications were performed on the power devices in the packaged structure.

[0076] In this embodiment of the invention, the packaged power device is subjected to electrical performance testing, insulation withstand voltage testing, and reliability verification, including but not limited to thermal cycling testing, vibration testing, and shear force testing.

[0077] Tests have verified that the prepared SOP8L power device package structure is superior to traditional package structures in terms of heat dissipation, electrical insulation, and mechanical reliability.

[0078] In summary, the method for fabricating the SOP8L power device package structure provided by this invention includes: forming a lead frame using a reverse cutting process, such that the carrier frame is located in the top region of the package after packaging, while the pin region for PCB soldering is located in the bottom region of the package; fixing the back side of the semiconductor chip to the surface of the carrier frame using solder or conductive adhesive, and making the source, gate, or other electrodes of the semiconductor chip face the pin region of the lead frame; electrically connecting the electrodes of the semiconductor chip to the corresponding lead frame pins using bonding wires; wherein the target pin corresponding to the gate of the semiconductor chip is a composite structure including a gull-wing structure and a through-hole structure; pre-placing or forming a top insulating heat dissipation structure in the top region corresponding to the back side of the carrier frame and the semiconductor chip; molding and packaging the semiconductor chip, the lead frame, and the bonding wires to form a package encapsulating the semiconductor chip and a portion of the carrier frame; wherein the top insulating heat dissipation structure is at least partially exposed on the outer surface of the package; connecting the PIN5 to PIN8 pins of the pin region to form an integral drain pad, and in the drain... Multiple through holes are formed on the pads; the lead frame is trimmed, and the pins are shaped to conform to the SOP8L standard dimensions, resulting in an SOP8L power device package structure. This solution eliminates the need for compressible or interface-type thermal bonding materials, enables a structural heat dissipation path on the top of the chip, and significantly improves the package structure's resistance to shear, vibration, and thermal fatigue, making it suitable for the packaging and manufacturing of high-power-density power semiconductor devices.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0081] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. An SOP8L power device package structure, characterized in that, The packaging structure includes: a carrier frame, a semiconductor chip disposed on the carrier frame, a lead frame, bonding wires, and a package encapsulating the semiconductor chip and a portion of the carrier frame, wherein: The lead frame adopts a reverse-cut structure design, so that the carrier frame is located in the top area of ​​the package after packaging, while the pin area for PCB soldering is located in the bottom of the package. A top insulating heat dissipation structure is provided on the carrier frame located at the top of the package and on the back of the semiconductor chip. The bottom of the package is provided with an integral drain pad formed by multiple pin connections, and the drain pad is provided with through holes; The target pin connected to the Gate terminal of the semiconductor chip is a composite structure including a gull-wing structure and a through-hole structure; The package does not encapsulate the top insulating heat dissipation structure, the drain pad, and the pin area.

2. The packaging structure according to claim 1, characterized in that, The top insulating heat dissipation structure is a one-piece solid structure that is solidified together with the lead frame and the package body during the packaging process to form a whole.

3. The packaging structure according to claim 1, characterized in that, The top insulating heat dissipation structure is made of a material with high thermal conductivity and high insulation strength, and the outer surface of the top insulating heat dissipation structure is in direct contact with the external heat sink.

4. The packaging structure according to claim 1, characterized in that, The material of the top insulating heat dissipation structure is one or more of the following: alumina, aluminum nitride, and glass ceramic.

5. The packaging structure according to claim 1, characterized in that, The bottom of the package has an integral drain pad formed by multiple pin connections, and the drain pad has through holes.

6. The packaging structure according to claim 1, characterized in that, The through-hole is used to absorb and contain molten solder during the reflow soldering process; the solidified solder forms a "rivet"-like mechanical interlocking structure within the through-hole.

7. The packaging structure according to claim 1, characterized in that, The target pin has a gull-wing structure, which is a gull-wing surface mount pin used to provide the main electrical connection; the through-hole structure extends downward and is inserted into the PCB through-hole to provide additional mechanical anchoring and electrical connection.

8. The packaging structure according to claim 1, characterized in that, The lead frame includes: the carrier frame located in the central region; a plurality of pin segments distributed around the carrier frame; and at least one multi-pin connection area for forming the Drain pad.

9. A method for fabricating an SOP8L power device package structure, characterized in that, The method includes: The lead frame is formed by reverse cutting, so that the carrier frame is located in the top area of ​​the package after packaging, while the pin area for PCB soldering is located in the bottom of the package. The back side of the semiconductor chip is fixed to the surface of the carrier frame with solder or conductive adhesive, and the source, gate or other electrodes of the semiconductor chip are facing the pin area of ​​the lead frame. The electrodes of the semiconductor chip are electrically connected to the corresponding lead frame pins using bonding wires; wherein the target pin corresponding to the gate of the semiconductor chip is a composite structure including gull-wing structure and through-hole structure; A top insulating heat dissipation structure is pre-placed or formed in the top region corresponding to the back of the carrier frame and the semiconductor chip. The semiconductor chip, the lead frame, and the bonding wires are molded and packaged to form a package encapsulating the semiconductor chip and a portion of the carrier frame; wherein the top insulating heat dissipation structure is at least partially exposed on the outer surface of the package. Connect the pins PIN5 to PIN8 of the pin area to form an integral drain pad, and form multiple through holes on the drain pad; The lead frame is trimmed and the pins are shaped to form an external dimension that conforms to the SOP8L standard, thus obtaining the SOP8L power device package structure.

10. The method according to claim 9, characterized in that, After obtaining the SOP8L power device package structure, the following is also included: Electrical performance tests, insulation withstand voltage tests, and reliability verifications were performed on the power devices in the packaged structure.

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