solar cell

Abstract

Solar cell, characterized in that it comprises the following: a silicon substrate with a first conductivity type; wherein the back side of the silicon substrate is provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, a second crystalline conductive layer and a first passivation layer, which are arranged in stacked positions; the first tunnel layer has a large number of first notches; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, wherein the density of the second notches is greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a first conductivity type; a back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; an emitter located on the front of the silicon substrate and having a second conductivity type; a second passivation layer that lies on the emitter; a front electrode that passes through the second passivation layer and is in contact with the emitter.

Description

TECHNICAL AREA

[0001] The present utility model belongs to the technical field of solar energy and relates to a solar cell. STATE OF THE ART

[0002] In the prior art, the back surface of a solar cell uses a tunnel oxide layer and a doped polysilicon layer to form a passivation contact. For example, CN115863452A discloses a solar cell and a manufacturing process, as well as a photovoltaic module. The solar cell comprises a silicon substrate; wherein a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer, and a first passivation layer are stacked on the silicon substrate, wherein both the first oxide layer and the second oxide layer have through-holes, the density of through-holes in the first oxide layer being greater than the density of through-holes in the second oxide layer; wherein the first electrode is electrically connected to the polysilicon layer through the first passivation layer, or the first electrode is connected through the first passivation layer.The polysilicon layer and the second oxide layer are sequentially electrically connected to the semiconductor layer; wherein the silicon substrate comprises a base region and an emitter; wherein the side of the emitter facing away from the base region is provided with a second passivation layer; wherein a second electrode is electrically connected to the emitter through the second passivation layer. The patent uses the vias of different oxide layers to increase the density of the resonant state and improve the probability of resonant tunneling, but it is still pore tunneling, not contact transmission, and the through-hole density of the primary oxide layer near the surface of the silicon substrate is greater than the through-hole density of the secondary oxide layer, which is not conducive to the passivation of the silicon substrate interface.and the distance between the first oxide layer and the secondary oxide layer in the quantum well structure must be very small (i.e., the thickness of the semiconductor layer is less than 3 nm) to achieve the effect of resonance tunneling, which can easily lead to excessive diffusion of the dopant from the polysilicon layer to the silicon substrate. CN118299432A discloses a solar cell backside structure and its fabrication method relating to the technical field of photovoltaics and comprising a monocrystalline silicon substrate, a stacked polycrystalline silicon passivation layer structure, wherein the metal electrode body is located on the side of the stacked polycrystalline silicon passivation layer facing away from the monocrystalline silicon substrate.Two different types of silver particles, type I and type II, are deposited from the side of the metal electrode body facing the polysilicon passivation layer. The type II silver particles penetrate the second tunnel oxide layer and come into contact with the first doped polysilicon layer. The charge carrier transfer efficiency at the tunnel layer interface of the aforementioned cell structure is low, which hinders improvements in battery efficiency.

[0003] Therefore, it is an urgent technical problem to be solved how the charge carrier transfer efficiency at the interface of the tunnel layer in the cell structure can be improved, thereby improving the efficiency of the solar cell. DISCLOSURE OF THE USE PATTERN

[0004] Due to the shortcomings of the prior art, the purpose of the utility model is to provide a solar cell. In the solar cell structure provided by the utility model, both the first tunnel layer and the second tunnel layer are provided with notches, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate, and wherein the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer. The density of the second notches is greater than the density of the first notches.The design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves charge carrier transfer efficiency, thereby improving the solar cell's efficiency.

[0005] To achieve this purpose, the utility model adopts the following technical solutions: In a first aspect, the utility model provides a solar cell comprising the following: a silicon substrate with a first conductivity type; wherein the back side of the silicon substrate is provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, a second crystalline conductive layer and a first passivation layer, which are arranged in stacked positions; the first tunnel layer has a large number of first notches; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, the density of the second notches being greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a first conductivity type; a back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; an emitter located on the front of the silicon substrate and having a second conductivity type; a second passivation layer that lies on the emitter; a front electrode that passes through the second passivation layer and is in contact with the emitter.

[0006] In the solar cell structure provided by the utility model, both the first and second tunnel layers are provided with notches. The first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate. Furthermore, the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer. The density of the second notches is greater than the density of the first notches. This design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves the cell's charge carrier transfer efficiency, thereby improving the solar cell's overall efficiency.

[0007] Preferably the density of the first notches is 5×10 5 -5×10 10 cm -2 .

[0008] Preferably, the density of the second notches is 1×10 8 -1×10 13 cm -2 Preferably, the width of the first notches and / or the width of the second notches is less than 200 nm.

[0009] Preferably, both the first crystalline conductive layer and the second crystalline conductive layer contain a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer is in contact with the silicon substrate.

[0010] Preferably, the thickness of the first tunnel layer is designated as d1 and the thickness of the second tunnel layer as d2, where d2≤d1.

[0011] Preferably, the range of values ​​for d1 is: 1nm≤d1≤10nm.

[0012] Preferably, the range of values ​​for d2 is: 1nm≤d2≤10nm.

[0013] Preferably, the range of values ​​for d1 is: 2nm≤d1≤5nm.

[0014] Preferably, the range of values ​​for d2 is: 2nm≤d2≤5nm.

[0015] Preferably, the first crystalline conductive layer and the second crystalline conductive layer each independently comprise a polysilicon layer or a silicon carbide layer.

[0016] Preferably, the thickness of the first crystalline conductive layer is designated as d3 and the thickness of the second crystalline conductive layer is designated as d4, where d3 < d4.

[0017] Preferably the ratio of d3 and d4 is 1:10 to 7:10.

[0018] Preferably, the range of values ​​for d3 is 10-50 nm.

[0019] Preferably, the value range of d4 is 20-90 nm.

[0020] Preferably, the first passivation layer comprises at least one silicon oxide nitride layer, one silicon nitride layer and one silicon oxide layer.

[0021] Preferably, a first antireflection layer is provided on the first passivation layer.

[0022] Preferably, the first antireflection layer comprises a hydrogenated silicon nitride layer and / or a silicon oxide nitride layer.

[0023] Preferably, the first passivation layer is a silicon oxide nitride passivation layer.

[0024] Preferably, the first antireflection layer comprises a hydrogenated silicon nitride layer and a silicon oxide nitride layer stacked on top of each other in the direction away from the back of the silicon substrate.

[0025] Preferably, the emitter is located on the inside or outside of the front face of the silicon substrate.

[0026] Preferably, the second passivation layer comprises at least one of the aluminium oxide layer, the silicon oxide layer and the silicon nitride layer.

[0027] Preferably, a second antireflection layer is provided on the second passivation layer.

[0028] Preferably, the second antireflection layer comprises at least one of the silicon nitride layer, the silicon oxide nitride layer, the silicon oxide layer and the magnesium fluoride layer.

[0029] Preferably, the first tunnel layer and / or the second tunnel layer independently comprise at least one of the silicon oxide layer, the aluminum oxide layer, the silicon nitride layer and the silicon oxide nitride layer.

[0030] In a second aspect, the utility model provides a solar cell comprising the following: a silicon substrate with a first conductivity type; wherein the back side of the silicon substrate is provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, a second crystalline conductive layer and a first passivation layer, which are arranged in stacked positions; the first tunnel layer has a large number of first notches; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, the density of the second notches being greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a second conductivity type; a back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; a front surface field located on the front of the silicon substrate and exhibiting a first conductivity type; a second passivation layer located on the front surface field; a front electrode that passes through the second passivation layer and is in contact with the front surface field.

[0031] In the solar cell structure provided by the utility model, the silicon substrate has a first conductivity type, wherein the first crystalline conductive layer and the second crystalline conductive layer have a second conductivity type, the front surface of the silicon substrate being a front surface field of the same conductivity type as the silicon substrate, the first crystalline conductive layer and the second crystalline conductive layer being designated as emitter layers on the back side of the silicon substrate, the density of first notches in the first tunnel layer being greater than the density of second notches in the second tunnel layer. This structure can effectively suppress excessive diffusion of the dopant into the silicon substrate and reduce charge carrier recombination near the PN junction on the back side, resulting in a relatively high open-circuit voltage.

[0032] In a third aspect, the utility model provides a solar cell comprising the following: a silicon substrate with a first conductivity type or a second conductivity type; wherein the back side of the silicon substrate is provided with a plurality of areas of the first conductivity type and a plurality of areas of the second conductivity type, wherein the plurality of areas of the first conductivity type and the plurality of areas of the second conductivity type are spaced apart from each other along the horizontal direction of the back side of the silicon substrate; wherein the areas of the first conductivity type are provided with a first tunnel layer which has a plurality of first notches; wherein a first crystalline conductive layer, a second tunnel layer and a second crystalline conductive layer are stacked successively on the first tunnel layer; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, the density of the second notches being greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a first conductivity type.

[0033] In the solar cell structure provided by the utility model, both the first and second tunnel layers are provided with notches, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate, and wherein the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer, while the density of the second notches is greater than the density of the first notches. This design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves the cell's charge carrier transfer efficiency, thereby improving the solar cell's efficiency.

[0034] Preferably, the solar cell further comprises a backside passivation layer arranged on the areas of the second conductivity type and the areas of the first conductivity type.

[0035] Preferably, a first electrode is provided on the backside passivation layer in the areas of the first conductivity type, wherein the first electrode is in contact with at least the second crystalline conductive layer through the backside passivation layer.

[0036] Preferably, a second electrode is provided on the backside passivation layer in the areas of the second conductivity type, wherein the second electrode penetrates through the backside passivation layer into the silicon substrate, and wherein the second electrode has a contact of the second conductivity type within the silicon substrate.

[0037] Preferably the second electrode is an aluminum electrode, wherein the contact of the second conductivity type is an aluminum-silicon alloy contact.

[0038] Preferably, the front side of the silicon substrate is provided with a doped passivation layer, wherein a frontal passivation layer and / or a frontal antireflection layer are arranged on the doped passivation layer in a direction away from the silicon substrate.

[0039] The numerical range described in this utility model includes not only the point values ​​mentioned above, but also any point values ​​between these ranges, which are not merely examples. Due to space limitations and for the sake of conciseness, this utility model will not exhaustively list all the specific point values ​​contained within this range.

[0040] Compared to the prior art, the utility model has the following advantageous effects: In the solar cell structure provided by the utility model, both the first and second tunnel layers are provided with notches, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate, and wherein the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer. This design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves the charge carrier transfer efficiency within the cell, thereby enhancing the solar cell's efficiency. ILLUSTRATION OF THE USE SAMPLE Fig. Figure 1 shows a schematic structural representation of the solar cell, which is provided by embodiment 1 in the utility model. Fig. Figure 2 shows a TEM scan diagram of the back side of the solar cell provided by embodiment 1 in the utility model. Fig. Figure 3 shows a schematic structural representation of a part of the solar cell, which is provided by embodiment 3 in the utility model. Fig. Figure 4 shows a schematic representation of a first tunnel layer in the solar cell, which is provided by embodiments 1, 2, 3 in the utility model. Fig. Figure 5 shows a schematic representation of a second tunnel layer in the solar cell, which is provided by embodiments 1, 2, 3 in the utility model. Fig. Figure 6 shows a schematic structural representation of the solar cell, which is provided by embodiment 4 in the utility model. Fig. Figure 7 shows a schematic structural representation of the solar cell, which is provided by embodiment 5 in the utility model.

[0041] Reference symbol list: 100 n-type silicon wafer; 101 first tunnel layer; 102 first crystalline conductive layer; 103 second tunnel layer; 104 second crystalline conductive layer; 105 first passivation layer; 106 hydrogenated silicon nitride layer; 107 silicon oxide nitride layer; 108 back electrode; 109 p-type emitter; 110 second passivation layer; 111 second antireflection layer; 112 front electrode; 113 first notch; 114 second notch; 102A first crystalline conductive layer in the n-region; 102B first crystalline conductive layer in the p-region; 103A second tunnel layer in the n-region; 103B second tunnel layer in the p-region; 104A second crystalline conductive layer in the n-region; 104B Second crystalline conductive layer in the p-region; 105' Backside passivation layer; 106' Backside hydrogenated silicon nitride layer; 107' Backside silicon oxide nitride; 109' Doped passivation layer; 110' Frontal passivation layer; 111' Frontal antireflection layer;115 metallic negative electrode; 116 metallic positive electrode; 600 p-type silicon wafer; 601 first tunnel oxide layer; 602a first n-phosphorus-doped polysilicon layer; 602b second n-phosphorus-doped polysilicon layer; 603 second tunnel oxide layer; 604 interface passivation layer; 605 hydrogenated silicon nitride film; 606 silicon oxide nitride film; 607 second electrode; 608 first electrode; 609 boron-doped layer; 610 front passivation layer; 611 front reflection layer; 612 p-type contact. SPECIFIC EXECUTION FORMS

[0042] It is understood that in the description of the utility model, the orientation or position relationship indicated by the terms "center," "longitudinal," "horizontal," "top," "bottom," "front," "back," "left," "right," "vertical," "horizontal," "above," "below," "inside," "outside," etc., is based solely on the orientation or position relationship shown in the accompanying drawing to facilitate and simplify the description of the utility model, and not to indicate or imply that the device or element referred to must have, be constructed, and operate in a specific orientation, and therefore cannot be understood as a limitation of the utility model. Furthermore, the terms "first," "second," etc., are used here to refer to the user in a specific way.These terms are used for descriptive purposes only and cannot be interpreted as indicating relative importance or implicitly specifying the number of technical features listed. Thus, features such as "first," "second," etc., can either explicitly or implicitly encompass one or more of these features. In the description of the utility model, "several" means two or more unless otherwise specified.

[0043] It should be noted that, in the description of the utility model, the terms "adjustment," "connection," and "connecting" should be understood in the broadest sense, unless expressly specified and limited otherwise. For example, it may be a permanent connection, a detachable connection, or an integrated connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection via an intermediate element, and it may be an internal connection between two elements. The specific meaning of the aforementioned terms in the utility model can be understood by a person skilled in the art based on the specific situation.

[0044] The technical solution of the utility model is further explained below in conjunction with the drawings and based on the specific embodiments.

[0045] In a specific embodiment, the utility model provides a solar cell whose structural schematic representation and backside TEM scan representation are shown in the Fig. 1 and Fig. 2 are shown, where the solar cell comprises the following: a silicon substrate with a first conductivity type (for example, it could be an n-type silicon wafer 100); a first tunnel layer 101, wherein the first tunnel layer 101 is located on the back side of the silicon substrate, wherein the first tunnel layer 101 has a plurality of first notches; a first crystalline conductive layer 102, wherein the first crystalline conductive layer 102 is provided on the first tunnel layer 101 and has a first conductivity type, wherein the first crystalline conductive layer 102 extends into at least one of the first notches and is in contact with the silicon substrate; a second tunnel layer 103, wherein the second tunnel layer 103 is provided on the first crystalline conductive layer 102, wherein the second tunnel layer 103 has a plurality of second notches, wherein the density of the second notches is greater than the density of the first notches; a second crystalline conductive layer 104, wherein the second crystalline conductive layer 104 is provided on the second tunnel layer 103 and has a first conductivity type, wherein the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one of the second notches, such that the second crystalline conductive layer 104 is in contact with the first crystalline conductive layer 102; a first passivation layer 105, wherein the first passivation layer 105 is provided on the second crystalline conductive layer 104; a back electrode 108, wherein the back electrode 108 passes through the first passivation layer 105 and is in contact with at least the second crystalline conductive layer 104; an emitter located on the front of the silicon substrate and having a second conductivity type (for example, a p-doped emitter 109); a second passivation layer 110, wherein the second passivation layer 110 is located on the emitter; a front electrode 112, wherein the front electrode 112 passes through the second passivation layer 110 and is in contact with the emitter.

[0046] In the solar cell structure provided by the utility model, both the first tunnel layer 101 and the second tunnel layer 103 are provided with notches, wherein the first crystalline conductive layer 102 extends into at least one of the first notches and is in contact with the silicon substrate, and wherein the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extends into at least one of the second notches, such that the second crystalline conductive layer 104 is in contact with the first crystalline conductive layer 102. The density of the second notches is greater than the density of the first notches. This design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves the cell's charge carrier transfer efficiency, thereby improving the solar cell's efficiency.

[0047] In the utility model, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 achieve direct contact through the notches on the second tunnel layer 103, thereby reducing the grain boundary density of the polysilicon and minimizing charge carrier scattering and connection losses. The second tunnel layer 103 acts as a buffer layer to dampen the diffusion of the dopants in the polysilicon layer. This achieves the graded doping distribution of the low doping concentration in the first crystalline conductive layer 102 and the high doping concentration in the second crystalline conductive layer 104, while simultaneously reducing the carrier transmission blocking effect of the second tunnel layer 103.

[0048] It should be noted that there are two conductivity types of semiconductors: N-type and P-type. In N-type semiconductors, the majority carriers are electrons and the minority carriers are holes, and their conductivity is primarily achieved through electron movement. In P-type semiconductors, the majority carriers are holes and the minority carriers are electrons, and hole movement dominates conduction. To facilitate research, the utility model defines one N-type or P-type semiconductor as the "first conductivity type," and the remaining type as the "second conductivity type." For example, if the first conductivity type is N-type and the second conductivity type is P-type, then the silicon substrate is N-type silicon, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are N-type semiconductors, and the emitter is P-type. The same applies in the following.

[0049] It should be noted that "notch density" refers to the number of notches per unit area, e.g., the number of notches per square centimeter. It is essentially an indicator for the quantitative description of the density of the notch distribution in the layer structure. The same applies in the following.

[0050] It should be noted that when the back electrode 108 penetrates the second tunnel layer 103, the notches of the second tunnel layer 103 refer to a different position than the penetration of the back electrode 108.

[0051] It should be noted that in the utility model the first crystalline conductive layer 102, the second crystalline conductive layer 104, the first tunnel layer 101 and the second tunnel layer 103 may be arranged substantially over the entire back side of the silicon substrate or may be arranged over part of the back side of the silicon substrate, e.g. similar Fig. 6, Fig. 7 or other sub-constructions also fall within the scope of protection of the utility model.

[0052] To avoid interference with carrier transfer, surface passivation of the first tunnel layer 101 plays a crucial role in the utility model, while simultaneously requiring higher conductivity in the second crystalline conductive layer 104. Therefore, the density of second notches in the second tunnel layer 103 is greater than the density of first notches in the first tunnel layer 101; that is, the density of the second tunnel layer 103 is lower than that of the first tunnel layer 101. Consequently, the second tunnel layer 103, with its high density of second notches, can reduce losses during charge carrier transfer. At the same time, the second notches increase the diffusion channel for highly concentrated phosphorus dopants in the second crystalline conductive layer 104, reduce phosphorus enrichment on the surface of the second tunnel layer 103, and improve the doping concentration distribution.

[0053] In the utility model, the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one of the second notches, such that the second crystalline conductive layer 104 is in contact with the first crystalline conductive layer 102. The following scenarios are possible: The first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend together into the same second notch; The first crystalline conductive layer 102 and the second crystalline conductive layer 104 each extend into different second notches; Part of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend together into the same second notch, and other parts extend into different second notches.

[0054] Furthermore, the density of the first notches is 5×10 5 -5×10 10 cm-2 , for example 5× 10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2 or the like, preferably 5×10 6 -5×10 8 cm -2 .

[0055] If the density of the first notches in the utility model is less than 5×10 5 cm -2 If the density of the first notches is greater than 5 × 10⁻⁶, the junction resistance is too high, the charge carrier transfer efficiency is low, and the passivation effect does not change significantly; 10 cm -2 If this occurs, the recombination loss of the interface carriers is too large and the passivation effect is reduced.

[0056] Furthermore, the density of the second notches is 1×10 8 -1×10 13 cm 2 , for example 1× 10 8 cm -2 , 1×10 9 cm -2, 1×10 10 cm -2 , 1×10 11 cm -2 , 1×10 12 cm -2 or 1×10 13 cm -2 etc., preferably 1x10 9 -1×10 11 cm -2 .

[0057] If the density of the second notches in the utility model is less than 1×10 8 cm -2 If the density of the second notches is greater than 1 × 10 13 cm -2 is, it is insufficient to buffer the diffusion of a high concentration of dopants in the second crystalline conductive layer 104, which leads to excessive diffusion of the dopants in the silicon substrate, resulting in excessive recomposit loss of the interface carriers and a reduced passivation effect.

[0058] Furthermore, the width of the first notches is 1-100 nm and can be, for example, 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm or the like.

[0059] It should be noted that in the first tunnel layer 101, due to the not completely equal widths of the several notches, the selection of the width parameters of the several notches must be limited to the conditions that the above-mentioned range of notch density is met, in order to avoid the inclusion of technical features that cannot be achieved.

[0060] Furthermore, the width of the second notches is 1-200 nm and can be, for example, 1 nm, 2 nm, 10 nm, 15 nm, 30 nm, 50 nm, 100 nm, 150 nm or 200 nm etc., preferably 5-100 nm.

[0061] It should be noted that in the second tunnel layer 103, due to the not completely equal widths of the multiple notches, the selection of the width parameters of the multiple notches must be limited to the conditions that the above-mentioned range of notch density is met, in order to avoid the inclusion of technical features that cannot be achieved.

[0062] Furthermore, the first notches and the second notches can be produced using the following methods: A first tunnel layer 101, a first amorphous conductive layer, a second tunnel layer 103, and a second amorphous conductive layer are successively deposited on the back side of the silicon substrate. Subsequently, heat treatment is performed to crystallize the first and second amorphous conductive layers to form the first crystalline conductive layer 102 and the second crystalline conductive layer 104. Simultaneously, the first and second tunnel layers form a multitude of notches. The amorphous conductive layer may comprise amorphous silicon, and the first crystalline conductive layer 102 and the second crystalline conductive layer 104, formed after heat treatment for crystallization, may comprise polycrystalline silicon.

[0063] Furthermore, excess hydrogen gas is supplied during the deposition of the second tunnel layer 103, so that the hydrogen in the second tunnel layer 103 is released in a subsequent process, thereby creating further notches in the second tunnel layer 103.

[0064] Furthermore, by adjusting the temperature and atmosphere of the heat treatment, the crystallization of the first and second amorphous conductive layers is controlled such that the density of the first notches is lower than the density of the second notches. For example, the heat treatment temperature is 800–1200°C, such as 800°C, 850°C, 950°C, 1050°C, 1100°C, 1150°C, or 1200°C, and so on.

[0065] Following the heat treatment, a cooling treatment step is carried out, and furthermore, a type of rapid cooling or gradient cooling is applied. This is intended to create 103 additional second notches in the second tunnel layer.

[0066] Furthermore, the process for forming a large number of notches includes a plasma etching process, a wet etching process, or a laser etching process.

[0067] Furthermore, the first crystalline conductive layer and the second crystalline conductive layer are produced by an in-situ doping process to control the doping concentration distribution of the first crystalline conductive layer and the second crystalline conductive layer, and can be produced in the same chamber, thus simplifying the manufacturing process.

[0068] Preferably, both the first crystalline conductive layer 102 and the second crystalline conductive layer 104 contain a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer 104 is in contact with the silicon substrate.

[0069] In the utility model, at least one crystal grain in the second crystalline conductive layer 104 penetrates at least one of the second notches and extends into at least one of the first notches, that is, there are complete crystal grains between the notches between the upper and lower tunnel layers, and there are no grain boundaries between the notches of the upper and lower tunnel layers along the direction of the silicon substrate thickness (e.g., inducing vertical growth of crystal grains or a high-temperature treatment to shift the grain boundaries, and the crystal grains of the first crystalline conductive layer and the second crystalline conductive layer engulf each other to form crystal grains that are larger than the thickness of the first crystalline conductive layer), which can reduce the grain boundary density and further improve the charge carrier transfer efficiency.

[0070] Furthermore, the thickness of the first tunnel layer is referred to as d1 and the thickness of the second tunnel layer as d2, where d2≤d1.

[0071] In the utility model, d2≤d1, which avoids excessive suppression of the diffusion of the doping element of the second crystalline conductive layer 104 during the annealing process and reduces the blockage of charge carrier transfer.

[0072] Furthermore, the range of values ​​for d1 is 1nm≤d1≤10nm, d1 can be, for example, 1 nm, 3 nm, 5 nm, 7 nm, 9 nm or 10 nm etc.

[0073] If d1 in the utility model is less than 1 nm, the interface passivation effect is poor; if d1 is greater than 10 nm, there is a serious hindrance of charge carrier transfer and the efficiency is significantly reduced.

[0074] Furthermore, the range of values ​​for d2 is 1nm≤d2≤10nm; d2 can be, for example, 1 nm, 3 nm, 5 nm, 7 nm, 9 nm or 10 nm, etc.

[0075] If d2 in the utility model is less than 1 nm, the interface passivation effect is poor; if d2 is greater than 10 nm, there is a serious hindrance of charge carrier transfer and the efficiency is significantly reduced.

[0076] Furthermore, the range of values ​​for d1 is: 2nm <d1≤5nm.

[0077] Furthermore, the range of values ​​for d1 is: 2.5nm <d1≤5nm.

[0078] Even slight variations in the tunnel layer thickness significantly affect the junction resistance. Generally, the tunnel layer thickness must be less than 2 nm. However, an excessively thin tunnel layer leads to poor passivation. In the utility model, the thickness of the first tunnel layer 101 is greater than 2 nm, and a thickness greater than 2.5 nm is also permissible. This considerably improves the surface passivation effect and reduces the internal expansion effect of the first crystalline conductive layer 102 on the silicon substrate. Since the first crystalline conductive layer 102 is in local contact with the silicon substrate via the notches, the charge carrier transfer channel is simultaneously increased, effectively suppressing the problem of increased junction resistance due to a thick tunnel layer.

[0079] Furthermore, the range of values ​​for d2 is: 2nm≤d2≤5nm.

[0080] Furthermore, the range of values ​​for d2 is: 2.5 nm≤d2≤5nm.

[0081] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 each independently have a polysilicon layer or a silicon carbide layer.

[0082] Furthermore, the polysilicon layer and / or the silicon carbide layer are each doped with first conductivity type.

[0083] Furthermore, the doping elements in the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are phosphorus elements.

[0084] Furthermore, the doping concentration of the doping element in the first crystalline conductive layer 102 is lower than the doping concentration of the doping element in the second crystalline conductive layer 104.

[0085] In the utility model, the doping concentration of the dopant in the first crystalline conductive layer 102 is lower than the doping concentration of the dopant in the second crystalline conductive layer 104. This is advantageous for maintaining a higher doping concentration in the second crystalline conductive layer 104 and improving carrier transfer efficiency. A lower doping concentration in the first crystalline conductive layer 102 helps to prevent excessive diffusion of phosphorus dopants into the silicon substrate. Furthermore, the density of the first notches in the first tunneling layer 101 is lower than the density of the notches in the second tunneling layer 103. This further reduces the doping concentration between the first crystalline conductive layer 102 and the silicon substrate and decreases interfacial charge carrier recombination.The second crystalline conductive layer 104 requires a high concentration of phosphorus doping, and when the phosphorus-doped elements in the second crystalline conductive layer 104 expand inwards, they readily accumulate on the surface of the second tunnel layer 103, introducing undesirable band bending. If the notch density in the second tunnel layer 103 is greater than the notch density in the first tunnel layer 101, the charge carrier transfer loss is reduced, and the highly concentrated phosphorus-doped element diffusion channel of the second crystalline conductive layer 104 is increased, thereby improving the doping concentration distribution of the first crystalline conductive layer 102 and the second crystalline conductive layer 104.

[0086] Furthermore, the doping concentration of the phosphorus element in the first crystalline conductive layer is 102 1×1018 cm -3 -5×10 20 cm -3 , for example 1×10 18 cm -3 , 5 ×10 18 cm -3 , 1×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 or 5×10 20 cm -3 etc., and the doping concentration of the phosphorus element in the second crystalline conductive layer 104 is 3×10 19 cm -3 -1×10 22 cm -3 , for example 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 5×10 20 cm -3 , 1×10 21 cm -3 or 1×10 22 cm -3 etc.

[0087] Furthermore, the deposition processes of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are each independent vapor deposition processes.

[0088] Furthermore, the thickness of the first crystalline conductive layer 102 is referred to as d3 and the thickness of the second crystalline conductive layer 104 as d4, where d3 < d4.

[0089] Furthermore, the ratio of d3 and d4 is 1:10 to 7:10, for example 1:10, 2:10, 3:10, 4:10, 5:10, 6:10 or 7:10 etc.

[0090] In the utility model, the ratio of d3 and d4 is limited to 1:10 to 7:10, which is advantageous for the concentration gradient diffusion of the doping elements in the second crystalline conductive layer 104, thereby forming high and low transitions, reducing the diffusion of impurities in the silicon substrate and improving the passivation effect.

[0091] Furthermore, the range of values ​​for d3 is 10-50 nm, for example it can be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm etc., preferably 15-40 nm.

[0092] If the thickness of the first crystalline conductive layer 102 in the utility model is greater than 50 nm, this is not conducive to the gradient diffusion of the doping element in the second crystalline conductive layer 104; if the thickness of the first crystalline conductive layer 102 is less than 10 nm, the buffering effect is not good, leading to excessive diffusion of the doping element into the silicon substrate.

[0093] Furthermore, the range of values ​​for d4 is 20-90 nm, for example it can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm etc., preferably 30-80 nm.

[0094] Furthermore, the first passivation layer 105 has at least one silicon oxide nitride passivation layer, one silicon nitride layer and one silicon oxide layer.

[0095] Furthermore, a first antireflection layer is provided on the first passivation layer 105.

[0096] In the utility model, the first anti-reflective layer has a passivation effect.

[0097] Furthermore, the first antireflection layer comprises a hydrogenated silicon nitride layer 106 and / or a silicon oxide nitride layer.

[0098] Furthermore, the first passivation layer is a silicon oxide nitride passivation layer.

[0099] In the utility model, the silicon oxide nitride passivation layer has a fixed positive charge, and due to the presence of oxygen atoms, the electrical properties of the first passivation layer 105 can be adjusted to reduce the density of the n-type surface states and charge carrier recombination.

[0100] Furthermore, the first antireflection layer comprises a hydrogenated silicon nitride layer 106 and a silicon oxide nitride layer 107, which are stacked one after the other.

[0101] In the utility model, hydrogen diffuses in the hydrogenated silicon nitride layer 106 into the first passivation layer 105 and the silicon substrate through heat treatment, which is advantageous for passivating surface defects.

[0102] Furthermore, the manufacturing processes for the first passivation layer 105 and the first antireflection layer are vapor deposition processes.

[0103] Furthermore, the thickness of the first passivation layer 105 is less than 10 nm and can be, for example, 8 nm, 6 nm, 4 nm or 2 nm or the like.

[0104] In the utility model, the thickness of the first passivation layer 105 is less than 10 nm, which is advantageous for the diffusion of hydrogen atoms in the first antireflection layer and further improves the passivation effect.

[0105] Furthermore, the thickness of the hydrogenated silicon nitride layer is 106 30-70 nm, for example it can be 30 nm, 40 nm, 50 nm, 60 nm or 70 nm etc.

[0106] If the thickness of the hydrogenated silicon nitride layer 106 in the utility model is less than 30 nm, the passivation effect is poor; if the thickness of the hydrogenated silicon nitride layer 106 is greater than 70 nm, the optical properties deteriorate.

[0107] Furthermore, the thickness of the silicon oxide nitride layer is 107 20-60 nm, for example it can be 20 nm, 30 nm, 40 nm, 50 nm or 60 nm etc.

[0108] If the thickness of the silicon oxide nitride layer 107 in the utility model is less than 20 nm, the passivation effect is poor; if the thickness of the silicon oxide nitride layer 107 is greater than 60 nm, the optical properties deteriorate.

[0109] Furthermore, the emitter is located on the inside or outside of the front of the silicon substrate.

[0110] In the utility model, the emitter is formed by diffusion of an n-doper or a p-doper into the front face of the silicon substrate, where the p-doper can be, for example, a boron doper.

[0111] Furthermore, the manufacturing process of the emitter includes a thermal diffusion or ion implantation process.

[0112] Furthermore, the second passivation layer 110 comprises at least one of the aluminium oxide layer, the silicon oxide layer and the silicon nitride layer.

[0113] In the utility model, the aluminum oxide layer has a solid negative charge with high density and has a good passivation effect on the p-type surface.

[0114] Furthermore, a second antireflection layer 111 is provided on the second passivation layer 110.

[0115] Furthermore, the second antireflection layer 111 comprises at least one of the silicon nitride layer, the silicon oxide nitride layer, the silicon oxide layer and the magnesium fluoride layer.

[0116] Furthermore, the manufacturing processes for the second passivation layer 110 and the second antireflection layer 111 are vapor deposition processes.

[0117] Furthermore, the first tunnel layer 101 and the second tunnel layer 103 independently comprise at least one of the silicon oxide layer, the silicon nitride layer, the silicon oxynitride layer and the aluminum oxide layer.

[0118] In the utility model, the silicon oxide layer is advantageous for the selective tunneling of charge carriers.

[0119] Furthermore, the manufacturing processes of the first tunnel layer 101 and the second tunnel layer 103 each independently include the thermal oxidation process, the chemical oxidation process or the vapor deposition process.

[0120] Furthermore, the back electrode 108 includes any of the silver electrodes, aluminum electrodes, copper electrodes, nickel electrodes, platinum electrodes, gold electrodes or palladium electrodes.

[0121] Furthermore, the frontal electrode 112 comprises any of the silver electrodes, aluminum electrodes, copper electrodes, nickel electrodes, platinum electrodes, gold electrodes, palladium electrodes or silver-aluminium electrodes, preferably silver-aluminium electrodes.

[0122] In a further specific embodiment, the utility model provides a solar cell which differs from the solar cell described above in that the silicon substrate has a first conductivity type, wherein the first crystalline conductive layer and the second crystalline conductive layer have a second conductivity type, and wherein the front of the silicon substrate is a front surface field of the same conductivity type as the silicon substrate.

[0123] In the solar cell structure provided by the utility model, the first and second crystalline conductive layers are arranged as emitter layers on the back side of the silicon substrate, with the density of the first notches in the first tunnel layer being greater than the density of the second notches in the second tunnel layer. This structure can effectively suppress excessive diffusion of the dopant into the silicon substrate and reduce charge carrier recombination near the pn junction on the back side, resulting in a relatively high open-circuit voltage.

[0124] In a specific embodiment, the utility model provides a solar cell, the structural schematic representation of which is shown in the Fig. 7 is shown, where the solar cell comprises the following: a silicon substrate with a first conductivity type or second conductivity type (for example, it could be a p-doped silicon wafer 600); wherein the back side of the silicon substrate is provided with a plurality of areas of the first conductivity type and a plurality of areas of the second conductivity type, wherein the plurality of areas of the first conductivity type and the plurality of areas of the second conductivity type are spaced apart from each other along the horizontal direction of the back side of the silicon substrate; wherein the areas of the first conductivity type are provided with a first tunnel layer (e.g. a first tunnel oxide layer 601) which has a plurality of first notches; a first crystalline conductive layer (for example, a first n-type phosphor-doped polysilicon layer 602a.), wherein the first crystalline conductive layer is provided on the first tunnel layer and has a first conductivity type, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; a second tunnel layer (for example, a second tunnel oxide layer 602a.), wherein the second tunnel layer is provided on the first crystalline conductive layer, wherein the second tunnel layer has a plurality of second notches, wherein the density of the second notches is greater than the density of the first notches; and a second crystalline conductive layer (for example, a second n-type phosphor-doped polysilicon layer 602b), wherein the second crystalline conductive layer is provided on the second tunnel layer and has a first conductivity type, wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer.

[0125] In the solar cell structure provided by the utility model, both the first and second tunnel layers are provided with notches, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate, and wherein the first crystalline conductive layer and / or the second crystalline conductive layer extends into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer. This design not only effectively reduces charge carrier recombination in the solar cell and improves the cell's passivation effect, but also increases the charge carrier transfer channel and improves the charge carrier transfer efficiency at the interface of the first tunnel layer in the cell structure, thereby improving the solar cell's efficiency.

[0126] Furthermore, the solar cell also includes a backside passivation layer (namely an interface passivation layer 604) which is arranged on the areas of the second conductivity type and the areas of the first conductivity type.

[0127] Furthermore, the solar cell also includes a backside antireflection layer, wherein the backside antireflection layer is arranged on the backside passivation layer.

[0128] Furthermore, a first electrode 608 is provided on the backside passivation layer in the areas of the first conductivity type, wherein the first electrode 608 is in contact with at least the second crystalline conductive layer through the backside passivation layer.

[0129] It should be noted that “at least in contact with the second crystalline conductive layer” means that the first electrode 608 can be in contact with the second crystalline conductive layer or can be in contact with the first crystalline conductive layer.

[0130] Furthermore, a second electrode 607 is provided on the backside passivation layer in the areas of the second conductivity type, wherein the second electrode 607 enters the silicon substrate through the backside passivation layer, wherein the second electrode 607 has a contact of the second conductivity type within the silicon substrate.

[0131] Furthermore, the first electrode 608 comprises any of the silver electrodes, aluminum electrodes, copper electrodes, nickel electrodes, platinum electrodes, gold electrodes or palladium electrodes.

[0132] Furthermore, the second electrode 607 is an aluminum electrode, with the contact of the second conductivity type being an aluminum-silicon alloy contact.

[0133] Furthermore, the backside antireflection layer comprises a hydrogenated silicon nitride film 605 and a silicon oxide nitride film 606, which are stacked in one direction away from the silicon substrate.

[0134] Furthermore, the front side of the silicon substrate is provided with a doped passivation layer (for example, it may be a boron-doped layer 609) on which a frontal passivation layer (i.e., a front passivation layer 610) and / or a front antireflection layer (i.e., a front reflection layer 611) are stacked in the direction away from the silicon substrate.

[0135] In the utility model, the doping type of the doped passivation layer can be n-type or p-type, which is advantageous to reduce the support recombination of the silicon substrate on this surface.

[0136] Furthermore, a front passivation layer 610 and a front reflection layer 611 are stacked successively on the doped passivation layer in the direction away from the silicon substrate.

[0137] Furthermore, the silicon substrate is an n-type silicon wafer or a p-type silicon wafer. Example 1

[0138] This embodiment provides a solar cell, the schematic structure of which is shown in Fig. 1 is shown and comprises an n-type silicon wafer 100, the front side of which (i.e.the light-receiving surface) in a direction away from the n-type silicon wafer 100 is stacked successively with a p-type emitter 109, a second passivation layer 110 and a second antireflection layer 111; the back side of which, in a direction away from the n-type silicon wafer 100, is stacked successively with a first tunnel layer 101, a first crystalline conductive layer 102, a second tunnel layer 103, a second crystalline conductive layer 104, a first passivation layer 105 and a second antireflection layer; wherein the first tunnel layer 101 is a silicon oxide layer with a thickness d1 of 3 nm; wherein the second tunnel layer 103 is a silicon oxide layer with a thickness d2 of 2 nm; wherein the first crystalline conductive layer 102 is an n-type phosphor-doped polysilicon layer with a thickness d3 of 30 nm and a doping concentration of 5×10. 19 cm -3; wherein the second crystalline conductive layer 104 is an n-type phosphorus-doped polysilicon layer with a thickness d4 of 50 nm and a doping concentration of 5 × 10 20 cm -3 and a d3 to d4 ratio of 6:10; wherein the second passivation layer 110 is an aluminum oxide layer 5 nm thick, wherein the first passivation layer 105 is a silicon oxide nitride layer 5 nm thick, wherein the second antireflection layer 111 is a silicon nitride layer 70 nm thick, wherein the first antireflection layer comprises a hydrogenated silicon nitride layer 106 50 nm thick and a silicon oxide nitride layer 107 40 nm thick stacked sequentially; wherein the p-type emitter 109 is equipped with the boron element at a doping concentration of 3 × 10 20 cm -3 endowed.

[0139] With reference to Fig. 2 It is evident that the first tunnel layer 101 has a plurality of first notches, wherein the second tunnel layer 103 has a plurality of second notches, the density of the second notches being greater than the density of the first notches, as shown in the red circle segment, wherein the first crystalline conductive layer 102 extends into at least one of the first notches and is in contact with the n-type silicon wafer 100, wherein the second crystalline conductive layer 104 extends into at least one of the second notches, such that the second crystalline conductive layer 104 is in contact with the first crystalline conductive layer 10102; wherein the first notches have a density of 5×10 5 -5×10 10 cm -2 (alternatively, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5× 10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2etc.) has a density of 1×10 8 -1×10 13 cm -2 (alternatively, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1 × 10 10 cm -2 , 1 × 10 11 cm -2 , 1 × 10 12 cm -2 or 1 × 10 13 cm -2 etc.) has; wherein the width of the first notches is 1 to 50 nm and the width of the second notches is 1 to 200 nm.

[0140] A back electrode 108 is provided on the second antireflection layer, wherein the back electrode 108 is in contact with the first crystalline conductive layer 102 through the first antireflection layer, the first passivation layer 105, the second crystalline conductive layer 104 and the second tunnel layer 103; wherein the back electrode 108 is an Ag electrode.

[0141] A front electrode 112 is provided on the second antireflection layer 111, wherein the front electrode 112 is in contact with the p-type emitter 109 of the n-type silicon wafer 100 through the second antireflection layer 111 and the second passivation layer 110; wherein the front electrode 112 is a silver-aluminum electrode that is in contact with the p-type emitter 109 to generate a p + to form a -doped area.

[0142] The emitter is located on the surface of the front of the silicon substrate. Example 2

[0143] This embodiment differs from embodiment 1 in that the first crystalline conductive layer is a p-type boron-doped polysilicon layer and the second crystalline conductive layer is also a p-type boron-doped polysilicon layer, wherein the p-type emitter is replaced by an n-type phosphorus-doped front surface field.

[0144] The rest of the structure remains as in embodiment 1. Example 3

[0145] The difference between this embodiment and embodiment 1 is that the thickness d1 of the first tunnel layer is 3 nm and the thickness d2 of the second tunnel layer is 2.2 nm and d2 < d1; wherein the density of the second notches is greater than the density of the first notches, while the density of the first notches is 5×10 5 -5×10 10 cm -2 and the density of the second notches 1×10 8 -1×10 13 cm -2 amounts.

[0146] The second crystalline conductive layer comprises a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, such that the second crystalline conductive layer is in contact with the n-type silicon wafer.

[0147] The remaining structure and parameters remain as in example 1.

[0148] Fig. Figure 3 shows a schematic representation of part of the structure of the solar cell provided by this embodiment, wherein 100 is an n-type silicon wafer, 101 is a first tunnel layer, 102 is a first crystalline conductive layer, 103 is a second tunnel layer, 104 is a second crystalline conductive layer, 113 is a first notch, and 114 is a second notch. At the second notch 114, the crystal grains of the second crystalline conductive layer 104 penetrate the second notch and extend into the first notches of the first tunnel layer 101. That is, complete grains (such as crystal grains induced by vertical growth) are located between the notches of the upper and lower tunnel layers, thereby reducing the grain boundary density and further improving the charge carrier transfer efficiency. The arrows indicate the direction of charge carrier flow at the first notches.

[0149] Fig. 4 and Fig. Figure 5 shows schematic representations of the first tunnel layer and the second tunnel layer in the solar cells provided by embodiment 1, embodiment 2, and embodiment 3. A comparison shows that the first tunnel layer is denser than the second tunnel layer; that is, the density of the notches in the second tunnel layer is greater than the density of the notches in the first tunnel layer. Example 4

[0150] The exemplary embodiment provides a solar cell, the structural schematic representation of which is shown in the Fig. 6 is shown, where the solar cell comprises the following: N-type silicon wafer 100, wherein the back side of the N-type silicon wafer 100 is provided with a first tunnel layer 101 having a thickness of 3 nm, wherein the material is silicon oxide, wherein the first tunnel layer 101 has a plurality of first notches, wherein the density of the first notches is 5×105 -5×10 10 cm -2 is (alternatively, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5× 10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5 × 10 10 cm -2 etc.); wherein the first tunnel layer 101 is provided with a plurality of n-type regions and a plurality of p-type regions, wherein the plurality of n-type regions and the plurality of p-type regions are spaced apart from each other along the horizontal direction of the back side of the n-type silicon wafer 100, wherein a separation region is provided between adjacent n-type regions and p-type regions, The n-type region comprises a first crystalline conductive layer 102A in the n-region, a second tunnel layer 103A in the n-region and a second crystalline conductive layer 104A in the n-region, which are stacked in one direction away from the first tunnel layer 101, wherein the p-type region comprises a first crystalline conductive layer 102B in the p-region, a second layer 103B in the p-region and a second crystalline conductive layer 104B in the p-region, which are stacked in one direction away from the first tunnel layer 101; wherein the thickness of the first crystalline conductive layer 102A in the n-region and the first crystalline conductive layer 102B in the p-region is both 30 nm, wherein the first crystalline conductive layer 102A in the n-region is an n-type phosphorus-doped polysilicon layer, and wherein the first crystalline conductive layer in the p-region 102B is a p-type boron-doped polysilicon layer;wherein the thickness of the second tunnel layer 103A in the n-region and the second tunnel layer 103B in the p-region are both 2 nm and the materials are both silicon oxide; wherein the thickness of the second crystalline conductive layer 104A in the n-region and the second crystalline conductive layer 104B in the p-region are each 50 nm, wherein the second crystalline conductive layer 104A in the n-region is an n-type phosphorus-doped polysilicon layer and the second crystalline conductive layer 104B in the p-region is a p-type boron-doped polysilicon layer; wherein the second tunnel layer 103A in the n-region and the second tunnel layer 103B in the p-region each have a plurality of second notches, wherein the density of the notches is each 1 × 10; 8 -1×10 13 cm -2 is (alternatively, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1× 10 10 cm -2 , 1 × 10 11 cm -2 , 1 × 1012 cm -2 or 1 × 10 13 cm -2 etc.); a backside passivation layer 105', which is provided on the outer surface of the n-type region, the p-type region and the separation region, and has a thickness of 5 nm and consists of silicon oxynitride; a backside antireflection layer provided on the outer surface of the backside passivation layer 105' and comprising a backside hydrogenation silicon nitride layer 106' with a thickness of 50 nm and a backside silicon oxide nitride layer 107' with a thickness of 40 nm, stacked sequentially; a doped passivation layer 109' arranged on the surface of the front face of the n-type silicon wafer 100, wherein the dopant is boron and the doping concentration is 3 × 10 20 cm -3is. wherein a frontal passivation layer 110' with a thickness of 5 nm and a frontal antireflection layer 111' with a thickness of 70 nm are stacked successively on the doped passivation layer 109', wherein the frontal antireflection layer 111' is a silicon nitride layer; a metallic negative electrode 115, which is arranged in the n-type region and is in contact with the first crystalline conductive layer 102A in the n-region through the antireflection layer on the back, the passivation layer on the back 105', the second crystalline conductive layer 104A in the n-region and the second tunnel layer 103A in the n-region and is made of silver; a metallic positive electrode 116, which is arranged in the p-type region and is in contact with the first crystalline conductive layer 102B in the p-region and is made of silver through the antireflection layer on the back, the passivation layer on the back 105', the second crystalline conductive layer 104B in the p-region and the second tunnel layer 103B in the p-region; Example 6

[0151] The exemplary embodiment provides a solar cell, the structural schematic representation of which is shown in the Fig. 7 is shown, where the solar cell comprises the following: N-type silicon wafer 600, wherein the back side of the P-type silicon wafer 600 is provided with a plurality of n-type regions and a plurality of p-type regions, wherein the plurality of n-type regions and the plurality of p-type regions are spaced apart from each other along the horizontal direction of the back side of the P-type silicon wafer 600; wherein the n-type regions are provided with a first tunneling layer, wherein the first tunneling layer is a first tunneling oxide layer 601 with a plurality of first notches and with a thickness of 3 nm, wherein the material is silicon oxide, wherein the density of the first notches is 5×10 5 -5×10 10 cm -2 is (alternatively, the density can be 5×10 5 cm -2 , 5×10 6 cm -2 , 5×10 7 cm -2 , 5×10 8 cm -2 , 5×10 9 cm -2 or 5×10 10 cm -2 etc.); and a first crystalline conductive layer, wherein the first crystalline conductive layer is a first n-type phosphorus-doped polysilicon layer 602a with a thickness of 30 nm, arranged on the first tunnel oxide layer 601 and having a doping concentration of 5× 10 19 cm -3 exhibits, wherein the first n-type phosphor-doped polysilicon layer 602a extends into at least one of the first notches and is in contact with the P-type silicon wafer 600; and a second tunnel layer, wherein the second tunnel layer is a second tunnel oxide layer 603 and is arranged on the first n-type phosphor-doped polysilicon layer 602a, wherein the material is silicon oxide and is provided with a thickness of 2 nm and with a plurality of second notches, wherein the density of the second notches is greater than the density of the first notches, wherein the density of the second notches is 1×10 8 -1×10 13 cm -2is (alternatively, the density can be 1×10 8 cm -2 , 1×10 9 cm -2 , 1 × 10 10 cm -2 , 1 × 10 11 cm -2 , 1 × 10 12 cm -2 or 1 × 10 13 cm -2 etc.); and a second crystalline conductive layer, wherein the second crystalline conductive layer is a second n-type phosphoro-doped polysilicon layer 602b with a thickness of 50 nm and is arranged on the first tunnel oxide layer 603, wherein the second n-type phosphoro-doped polysilicon layer 602b extends into at least one of the second notches, such that the second n-type phosphoro-doped polysilicon layer 602b is in contact with the first n-type phosphoro-doped polysilicon layer 602a.

[0152] The fabrication process for the p-type and n-type regions comprises: First, a complete first tunnel layer, a first n-type phosphor-doped polysilicon layer, a second tunnel layer, and a second n-type phosphor-doped polysilicon layer are successively deposited on the back side of the p-type silicon wafer; Then, the functional layer deposited on the back side of the p-type silicon wafer is partially removed using a laser or mask etching process, creating a plurality of spaced openings on the functional layer, and the plurality of openings exposes the p-type silicon wafer to form a p-type region, and the region of the aforementioned functional layer that remains outside the opening is an n-type region.

[0153] The solar cell further comprises a backside passivation layer, wherein the backside passivation layer is an interface passivation layer 604 arranged on the n-type region and the p-type region, wherein the interface passivation layer 604 is a silicon oxide nitride with a thickness of 5 nm.

[0154] The solar cell further comprises a backside antireflection layer, wherein the backside antireflection layer is an interface antireflection layer provided on the interface passivation layer 604, the interface passivation layer comprising a hydrogenated silicon nitride film 605 with a thickness of 50 nm and a silicon oxide nitride film 606 with a thickness of 40 nm, which are stacked successively.

[0155] The first electrode 608 is provided on the interfacial antireflection layer located in the n-type region, wherein the first electrode 608 passes through the interfacial antireflection layer and the interfacial passivation layer 604 and is in contact with at least the second n-type phosphor-doped polysilicon layer 602b, wherein the first electrode 608 is an Ag electrode.

[0156] A second electrode 607 is provided on the interface antireflection layer in the p-type region, wherein the second electrode 607 enters the p-type silicon wafer 600 through the interface antireflection layer and the interface passivation layer 604 (the opening through the interface antireflection layer and the interface passivation layer 604 can be a laser aperture or an aperture formed by sintering and penetration of aluminum paste), wherein the second electrode 607 forms a p-type contact 612 in the p-type silicon wafer 600, wherein the second electrode 607 is an aluminum electrode, and the p-type contact 612 is an aluminum-silicon alloy contact that is sintered through an aluminum electrode to form a p-type silicon wafer 600 and reacts with the p-type silicon wafer 600 to form a p+ layer of to form an Al-Si alloy in order to achieve an ohmic contact.

[0157] The front face of the P-type silicon wafer 600 is provided with a doped passivation layer, which is a boron-doped layer 609 with a doping concentration of 3×10 20 cm -3 is, wherein a front passivation layer 610 and a front reflection layer 611 are stacked successively on the boron-doped layer 609 along the direction away from the P-type silicon wafer, wherein the front passivation layer 610 is an aluminum oxide layer with a thickness of 5 nm and the front antireflection layer 611 is a silicon nitride layer with a thickness of 70 nm.

[0158] In this embodiment, the p-type region is not provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, and a second crystalline conductive layer, but instead directly forms a backside passivation layer and a backside antireflection layer. The aluminum electrode is directly sintered to achieve an ohmic contact, thus reducing the insulation process steps and offering advantages for industrial manufacturing. Furthermore, the cost of the aluminum electrode is lower, and the p-type region is more efficient. + The layer of the Al-Si alloy forms an ohmic contact, thereby improving the efficiency of charge carrier transfer.

[0159] The applicant states that the above is only one specific embodiment of the utility model, but the scope of protection of the utility model is not limited to it, and the person skilled in the art should understand that any modifications or replacements readily conceivable within the technical scope of the disclosure of the utility model fall within the scope of protection and disclosure of the utility model, which are readily conceivable to any person skilled in the art. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 115863452A

[0002] CN 118299432A

[0002]

Claims

[1] Solar cell, characterized by that it includes the following: a silicon substrate with a first conductivity type; wherein the back side of the silicon substrate is provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, a second crystalline conductive layer and a first passivation layer, which are arranged in stacked positions; the first tunnel layer has a large number of first notches; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, wherein the density of the second notches is greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a first conductivity type; a back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; an emitter located on the front of the silicon substrate and having a second conductivity type; a second passivation layer that lies on the emitter; a front electrode that passes through the second passivation layer and is in contact with the emitter. [2] Solar cell according to claim 1, characterized bythat the density of the first notches is 5×10 5 -5×10 10 cm -2 is; where the density of the second notches is 1×10 8 -1×10 13 cm -2 amounts. [3] Solar cell according to claim 1 or 2, characterized by that the width of the first notches and / or the width of the second notches is less than 200 nm. [4] Solar cell according to any one of the preceding claims, characterized by , that both the first crystalline conductive layer and the second crystalline conductive layer contain a plurality of crystal grains; wherein at least one of the crystal grains penetrates at least one of the second notches and extends into at least one of the first notches, so that the second crystalline conductive layer is in contact with the silicon substrate. [5] Solar cell according to any one of the preceding claims, characterized by, that the thickness of the first tunnel layer is designated as d1 and the thickness of the second tunnel layer as d2, where d2≤d1. [6] Solar cell according to claim 5, characterized by , that the range of values ​​for d1 is: 1 nm≤d1≤10 nm; where the range of values ​​for d2 is: 1 nm≤d2≤10 nm. [7] Solar cell according to claim 6, characterized by , that the range of values ​​for d1 is: 2 nm <d1≤5 nm; wobei der Wertebereich von d2 beträgt: 2 nm≤d2≤5 nm. [8] Solar cell according to any one of the preceding claims, characterized by that the first crystalline conductive layer and / or the second crystalline conductive layer each independently have a polysilicon layer or a silicon carbide layer. [9] Solar cell according to any one of the preceding claims, characterized by , that the thickness of the first crystalline conductive layer is designated as d3 and the thickness of the second crystalline conductive layer is designated as d4, where d3 < d4. [10] Solar cell according to claim 9, characterized by , that the ratio of d3 and d4 is 1:10~7:

10. [11] Solar cell according to claim 9, characterized by , that the range of values ​​for d3 is 10-50 nm; where the range of values ​​for d4 is 20-90 nm. [12] Solar cell according to any one of the preceding claims, characterized by , that the first passivation layer comprises at least one of the silicon oxide nitride layer, the silicon nitride layer and the silicon oxide layer; wherein a first antireflection layer is provided on the first passivation layer; wherein the first antireflection layer comprises a hydrogenated silicon nitride layer and / or a silicon oxide nitride layer. [13] Solar cell according to claim 12, characterized by, wherein the first passivation layer comprises a silicon oxide nitride passivation layer; wherein the first antireflection layer comprises a hydrogenated silicon nitride layer and a silicon oxide nitride layer stacked on top of each other in the direction away from the back of the silicon substrate. [14] Solar cell according to any one of the preceding claims, characterized by that the emitter is located on the inside or outside of the front face of the silicon substrate. [15] Solar cell according to any one of the preceding claims, characterized by , that the second passivation layer comprises at least one of the aluminium oxide layer, the silicon oxide layer and the silicon nitride layer; wherein a second antireflection layer is provided on the second passivation layer; wherein the second antireflection layer comprises at least one of the silicon nitride layer, the silicon oxide nitride layer, the silicon oxide layer and the magnesium fluoride layer. [16] Solar cell according to any one of the preceding claims, characterized by that the first tunnel layer and / or the second tunnel layer independently comprise at least one of the silicon oxide layer, the aluminum oxide layer, the silicon nitride layer and the silicon oxide nitride layer. [17] Solar cell, characterized by that it includes the following: a silicon substrate with a first conductivity type; wherein the back side of the silicon substrate is provided with a first tunnel layer, a first crystalline conductive layer, a second tunnel layer, a second crystalline conductive layer and a first passivation layer, which are arranged in stacked positions; the first tunnel layer has a large number of first notches; wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, the density of the second notches being greater than the density of the first notches; wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer; wherein the first crystalline conductive layer and the second crystalline conductive layer each have a second conductivity type; a back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; a front surface field located on the front of the silicon substrate and exhibiting a first conductivity type; a second passivation layer located on the front surface field; a front electrode that passes through the second passivation layer and is in contact with the front surface field. [18] Solar cell, characterized by that it includes the following: a silicon substrate with a first conductivity type or a second conductivity type; wherein the back side of the silicon substrate is provided with a plurality of areas of the first conductivity type and a plurality of areas of the second conductivity type, wherein the plurality of areas of the first conductivity type and the plurality of areas of the second conductivity type are spaced apart from each other along the horizontal direction of the back side of the silicon substrate; wherein the areas of the first conductivity type are provided with a first tunnel layer which has a plurality of first notches; wherein a first crystalline conductive layer, a second tunnel layer and a second crystalline conductive layer are stacked successively on the first tunnel layer; wherein the first crystalline conductive layer has a first conductivity type, wherein the first crystalline conductive layer extends into at least one of the first notches and is in contact with the silicon substrate; wherein the second tunnel layer has a plurality of second notches, the density of the second notches being greater than the density of the first notches; wherein the second crystalline conductive layer has a first conductivity type, wherein the first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer. [19] Solar cell according to claim 18, characterized by , that the solar cell further has a backside passivation layer arranged on the areas of the second conductivity type and the areas of the first conductivity type. [20] Solar cell according to claim 19, characterized by , that a first electrode is provided on the backside passivation layer in the areas of the first conductivity type, wherein the first electrode is in contact with at least the second crystalline conductive layer through the backside passivation layer; wherein a second electrode is provided on the backside passivation layer in the areas of the second conductivity type, wherein the second electrode passes through the backside passivation layer into the silicon substrate, and wherein the second electrode has a contact of the second conductivity type within the silicon substrate. [21] Solar cell according to claim 20, characterized by , that the second electrode is an aluminum electrode, wherein the contact of the second conductivity type is an aluminum-silicon alloy contact. [22] Solar cell according to one of claims 18 to 21, characterized by , that the front side of the silicon substrate is provided with a doped passivation layer, wherein a frontal passivation layer and / or a frontal antireflection layer are arranged on the doped passivation layer in a direction away from the silicon substrate.

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