A gate-all-around charge plasma-based dual-material gate stack nanowire field-effect transistor

Abstract

A gate-all-around charge plasma-based dual-material gate stack nanowire field-effect transistor, consisting of: an undoped intrinsic silicon nanowire body whose thickness is smaller than the Debye length; a source electrode and a drain electrode generated in the undoped intrinsic silicon nanowire body by means of a charge plasma, wherein the source electrode and the drain electrode have metal contacts with a work function that is less than the sum of the electron affinity of silicon and half the band gap of silicon, and wherein the source electrode and the drain electrode are configured to generate an electron charge plasma in the source and drain regions of the silicon nanowire body; a gate structure surrounding the undoped intrinsic silicon nanowire body, wherein the gate structure comprises a dual-material gate containing a first gate metal material and a second gate metal material arranged along a length of the silicon nanowire body, and wherein the first gate metal material has a first work function and the second gate metal material has a second work function, the difference between the first and second work functions being 0.5 electron volts; and a gate dielectric layer arranged between the gate structure and the silicon nanowire body, wherein the gate dielectric layer comprises a gate stack structure containing a silicon dioxide layer and a layer of dielectric material with a high dielectric constant; the transistor is configured to provide improved analog performance with reduced short-channel effects and operates without chemical doping in the source and drain regions.

Description

AREA OF INVENTION

[0001] The present disclosure relates to a gate-all-around charge plasma-based dual-material gate-stack nanowire field-effect transistor (FET). In particular, the invention relates to a gate-all-around (GAA) charge plasma-based, doped-free dual-material gate-nanowire FET, the structure of which additionally has a gate-stack function and in which the source and drain are realized by a charge plasma concept through a suitable selection of the work functions for the source and drain electrodes. BACKGROUND OF THE INVENTION

[0002] Gate-all-around (GAA) silicon nanowire MOSFETs (NWFETs) offer superior electrostatic control, higher packing density, and insensitivity to short-channel effects (SCEs), thus enabling continuous miniaturization of the devices. However, conventional GAA NWFETs exhibit high series resistance, which arises from sharp transitions between highly doped source / drain regions and partially doped channels.

[0003] Junctionless (JL) NWFETs eliminate physical junctions by using uniformly highly doped source, channel, and drain regions. Despite reduced series resistance, JL devices exhibit low drain current (ID) and low transconductance (gm) due to reduced charge carrier mobility at high doping concentrations. Furthermore, JL NWFETs show increased sensitivity to random doping fluctuations (RDFs) caused by the high doping requirements.

[0004] Charge plasma-based, doping-free FETs overcome these limitations by eliminating chemical doping through appropriate selection of the work function for the source and drain electrodes. Compared to JL devices, this approach offers lower thermal overhead, higher drain current, lower short-channel effects, and improved insensitivity to variations in the radial distribution function (RDF).

[0005] Two-material gate structures (DM) offer improved drain current, higher transconductance, and reduced short-channel effects (SCEs) compared to single-material gate structures (SMG). Gate-stacked configurations (GS), which integrate a high-k dielectric layer deposited on a silicon dioxide layer, overcome the scaling limitations of SiO₂ caused by the quantum tunneling effect. 2 - Gate dielectrics below 2 nanometers. High-k dielectric spacers further improve the performance of JL-FETs.

[0006] In light of the foregoing, the present invention aims to integrate gate-stack and dual-material-gate architectures with high-k spacers into charge plasma-based doping-free NWFETs, thereby creating improved device configurations (CP-DM and CP-GS-DM) with superior analog performance characteristics. SUMMARY OF THE INVENTION

[0007] The present invention relates to a gate-all-around charge plasma-based dual-material gate stack nanowire field-effect transistor designed for improved analog performance. The transistor utilizes a doping-free architecture in which source and drain regions are induced by the charge plasma concept using metal electrodes with suitable work functions, thus eliminating the need for chemical doping. The transistor features a dual-material gate structure with two metals having different work functions and a gate stack dielectric composed of high-k material and silicon dioxide layers. The proposed configuration offers superior analog performance characteristics, including improved drive current, higher transconductance, higher intrinsic gain, and reduced short-channel effects compared to conventional junctionless devices.At the same time, it enables simplified manufacturing processes and reduced effects of random doping variations.

[0008] The present disclosure relates to a gate-all-around field-effect transistor (FET) with a dual-material-gate stack of nanowires, based on charge plasma. The proposed transistor comprises: an undoped intrinsic silicon nanowire body whose thickness is less than the Debye length; a source electrode and a drain electrode induced into the undoped intrinsic silicon nanowire body by charge plasma, wherein the source and drain electrodes have metal contacts with a work function less than the sum of the electron affinity of silicon and half the band gap of silicon, and wherein the source and drain electrodes are configured to induce electron plasma in the source and drain regions of the silicon nanowire body. A gate structure surrounds the undoped intrinsic silicon nanowire body.The gate structure comprises a dual-material gate with a first and a second gate metal material arranged along the silicon nanowire body. The first gate metal material has a first work function, and the second gate metal material has a second work function, with the difference between the first and second work functions being 0.5 electron volts. A gate dielectric layer is located between the gate structure and the silicon nanowire body. This gate dielectric layer consists of a gate stack structure with a silicon dioxide layer and a layer of a high-k dielectric material. The transistor is configured to provide improved analog performance with reduced short-channel effects and operates without chemical doping in the source and drain regions.

[0009] One objective of the present disclosure is to provide a gate-all-around charge plasma-based dual-material gate stack nanowire field-effect transistor (FET).

[0010] Another objective of the present disclosure is to provide a gate-all-around nanowire field-effect transistor that eliminates physical doping in the source and drain regions by utilizing the charge plasma concept via suitable exit work metal electrodes, thereby reducing random doping variations and simplifying the manufacturing processes with lower thermal budget requirements.

[0011] Another objective of the present disclosure is to provide a dual-material gate structure with optimized output work differential, which improves analog performance parameters such as driver current, transconductance, transconductance gain factor, early voltage and intrinsic gain, while minimizing short-channel effects such as drain-induced barrier dip and subthreshold transconductance.

[0012] Another objective of the present disclosure is to provide a gate-stack dielectric configuration consisting of high-k material and silicon dioxide layers which, compared to non-gate-stack structures, increases the gate capacitance and drain saturation current, thereby improving the overall performance of the device for analog circuit applications.

[0013] Another objective of the present disclosure is to provide a cost-effective and reliable nanowire field-effect transistor suitable for analog applications, whose improved performance characteristics are achieved through the integration of doping-free charge plasma technology, dual-material gate engineering, and gate-stack dielectric optimization.

[0014] To further clarify the advantages and features of the present disclosure, the invention is described in more detail with reference to specific embodiments illustrated in the accompanying drawings. It is understood that these drawings merely show typical embodiments of the invention and are therefore not to be understood as limiting its scope of protection. The invention is described and explained in more detail and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE IMAGES

[0015] These and other features, aspects and advantages of the present disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings, in which identical symbols represent identical parts, wherein: Fig. Figure 1 shows a block diagram of a gate all-around charge plasma-based dual-material gate stack nanowire field-effect transistor (FET) according to an embodiment of the present disclosure; Fig. Figure 2 shows a 3D structure of a dual material based on a doping-free charge plasma (CP-DM) according to an embodiment of the present disclosure; Fig. Figure 3A shows a cross-section of the schematic structure of CP-DM according to an embodiment of the present disclosure; and Fig. Figure 3B shows a cross-section of the scheme of CP-GS-DM according to an embodiment of the present disclosure.

[0016] Furthermore, those skilled in the art will recognize that the elements in the drawings are simplified and not necessarily drawn to scale. For example, the flowcharts illustrate the process by highlighting the main steps to facilitate understanding of this disclosure. With regard to the construction of the device, one or more components may be represented in the drawings by conventional symbols. The drawings may show only those specific details relevant to understanding the embodiments of this disclosure, so as not to clutter the drawings with details that are already apparent to those skilled in the art from the description contained herein. DETAILED DESCRIPTION:

[0017] To facilitate understanding of the principles of the invention, reference is made below to the embodiment shown in the drawings, which is described using specific terms. It is understood, however, that this does not limit the scope of protection of the invention. Rather, modifications and further developments of the depicted system or device, as well as further applications of the inventive principles shown therein, such as would typically occur to a person skilled in the art in the field of the invention, are permitted.

[0018] It will be clear to those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not to be understood as a limitation thereof.

[0019] References to “an aspect”, “another aspect”, or similar phrases in this description mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, phrases such as “in one embodiment”, “in another embodiment”, and similar expressions in this description may, but do not necessarily, all refer to the same embodiment.

[0020] The terms "includes," "comprehensive," or similar expressions denote non-exclusive inclusion. Thus, a procedure or method containing a list of steps does not only include those steps but may also include further steps not explicitly listed or inherent in the procedure or method. Likewise, the statement "includes..." for one or more devices, subsystems, elements, structures, or components, without further limitations, does not preclude the existence of other devices, subsystems, elements, structures, or components.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as generally known to those skilled in the art in the field to which this invention belongs. The devices, methods, and examples described herein serve only for illustration and are not to be understood as limiting.

[0022] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0023] Fig. Figure 1 shows a block diagram of a gate all-around charge plasma-based dual-material gate stack nanowire field-effect transistor (FET) according to an embodiment of the present disclosure.

[0024] According to Fig. 1 The gate-all-around charge plasma-based dual-material gate stack nanowire field-effect transistor comprises: an undoped intrinsic silicon nanowire body (102) whose thickness is less than the Debye length; a source electrode (104) and a drain electrode (106) induced into the undoped intrinsic silicon nanowire body (102) by means of charge plasma, wherein the source electrode (104) and the drain electrode (106) have metal contacts with a work function that is less than the sum of the electron affinity of silicon and half the band gap of silicon, and wherein the source electrode (104) and the drain electrode (106) are configured to induce electron charge plasma in the source and drain regions of the silicon nanowire body; A gate structure (108) surrounds the undoped intrinsic silicon nanowire body (102).The gate structure (108) comprises a dual-material gate (108a) with a first and a second gate metal material arranged along the silicon nanowire body (102). The first gate metal material has a first work function, and the second gate metal material has a second work function, with the difference between the first and second work functions being 0.5 electron volts. A gate dielectric layer (110) is located between the gate structure (108) and the silicon nanowire body (102). This gate dielectric layer (110) consists of a gate stack structure with a silicon dioxide layer and a layer of high-k dielectric material. The transistor (100) is configured to provide improved analog performance with reduced short-channel effects and operates without chemical doping in the source and drain regions.

[0025] In one embodiment, the source electrode (104) and the drain electrode (106) have a work function of 3.9 electron volts hafnium, wherein this work function and the silicon film thickness of 10 nm promote the induction of electron charge plasma in the intrinsic source / drain regions of the transistor.

[0026] In one embodiment, the gate dielectric layer (110) comprises the silicon dioxide layer with a thickness of 0.6 nanometers and the high-k dielectric layer with a thickness of 0.5 nanometers, wherein the total thickness of the gate oxide of the gate stack structure is 1.1 nanometers and the high-k dielectric layer comprises hafnium dioxide.

[0027] In one embodiment, the silicon nanowire body (102) has a thickness of 10 nanometers; the total length of the gate, consisting of the sum of a first gate metal material length and a second gate metal material length, is 20 nanometers; and the transistor further comprises spacer regions with a spacer length of 10 nanometers, which are arranged between the gate structure and the source and drain electrodes.

[0028] In one embodiment, the first gate metal material is arranged next to the source electrode (104); the second gate metal material is arranged next to the drain electrode (106); the ratio of the length of the first gate metal material to the total length of the gate is configured to optimize the analog performance parameters.

[0029] In one embodiment, the transistor (100) further comprises: a high-k dielectric layer arranged between the metal contacts of the source and drain electrodes (104 and 106) and the silicon nanowire body (102); wherein the high-k dielectric layer has a thickness of 0.6 nanometers; the high-k dielectric layer consists of hafnium dioxide; and the high-k dielectric layer is configured to prevent the formation of silicide at the interfaces between the metal contacts and the silicon nanowire body.

[0030] In one embodiment, the source electrode (104) and the drain electrode (106) further comprise lateral metal electrodes and upper metal electrodes, wherein the lateral metal electrodes and the upper metal electrodes are configured to induce a plasma with constant electron charge in the source and drain regions.

[0031] In one embodiment, the transistor has the following features: improved drive current; improved transconductance; improved transconductance gain factor; reduced output conductance; increased early voltage; increased intrinsic gain; reduced drain-induced barrier drop; and reduced subthreshold transconductance.

[0032] In one embodiment, the capacitance of the gate-stack structure is greater than the capacitance of a non-gate-stack structure with equivalent physical gate oxide thickness, with the transistor providing an increased drain current in the saturation region compared to the non-gate-stack structure.

[0033] In one embodiment, the transistor exhibits reduced random doping variations compared to chemically doped field-effect transistors, while simultaneously enabling manufacturing with a low thermal budget. The transistor is configured for analog circuit applications.

[0034] The present invention relates to a nanowire field-effect transistor with gate-all-around charge plasma technology and two material-gate stacks, which overcomes the limitations of conventional doped semiconductor devices. The transistor consists of an intrinsic silicon nanowire body with a thickness of 10 nanometers, surrounded by a gate structure that enables complete electrostatic control. The source and drain electrodes are fabricated with hafnium metal contacts with a work function of 3.9 eV. These induce an electron plasma in the intrinsic silicon regions without the need for chemical doping. This plasma induction satisfies two critical conditions: the work function of the metal is less than the sum of the electron affinity of silicon and half its band gap, and the thickness of the silicon body is less than the Debye length.

[0035] The gate structure employs a dual-material configuration consisting of two metals with output functions differing by approximately 0.5 eV, arranged sequentially along the channel length. The entire gate length of 20 nanometers is divided between the first gate metal material near the source and the second gate metal material near the drain. This dual-material arrangement creates an asymmetric potential profile that improves charge transport and enhances analog performance characteristics.

[0036] The gate dielectric employs a gate-stack architecture consisting of a 0.6 nanometer thick silicon dioxide layer and a 0.5 nanometer thick layer of high-k dielectric (hafnium dioxide), resulting in an equivalent total oxide thickness of 1.1 nanometers. This gate-stack configuration offers higher gate capacitance compared to conventional single-layer dielectrics, leading to higher drive current and improved device performance. Additionally, a thin 0.6 nanometer high-k dielectric layer is positioned between the source / drain metal contacts and the silicon body to prevent silicide formation while ensuring effective charge plasma induction.

[0037] The doping-free architecture offers numerous advantages, including the avoidance of random doping variations, reduced heat requirements during fabrication, simplified processing steps, and improved device homogeneity. Compared to junction-less devices, the transistor exhibits superior analog performance characteristics, including improved transconductance, higher Early voltage, higher intrinsic gain, reduced drain-induced barrier drop, and a steeper subthreshold slope. The integration of the charge plasma concept, gate material optimization, and dielectric optimization of the gate stack make this transistor particularly well-suited for analog and mixed-signal circuits requiring high-performance transistors at the nanoscale.

[0038] Fig. Figure 2 shows a 3D structure of a dual material based on a doping-free charge plasma (CP-DM) according to an embodiment of the present disclosure.

[0039] Fig. Figure 3A shows a cross-section of the schematic structure of CP-DM according to an embodiment of the present disclosure.

[0040] Fig. Figure 3B shows a cross-section of the scheme of CP-GS-DM according to an embodiment of the present disclosure.

[0041] The 3D schematic representation of the charge plasma-based, doping-free dual-material GAA-NWFET (CP-DM) is shown in Fig. 2 shown. Fig. 3A and Fig. Figure 3B shows the cross-sectional view of the CP-DM and CP-GS-DM device structures. The CP-based structures are also sometimes referred to as doping-free structures in the following. All devices have the same silicon body thickness tsi = 10 nm, LG (L M1 + L M2) = 20 nm, gate oxide thickness tox = 1.1 nm, and spacer length LSP = 10 nm. For a fair comparison, the gate-metal work functions of all devices were adjusted to have the same threshold voltage Vth at Vds = 50 mV. To achieve optimal properties, the work function difference between M1 and M2 was set to 0.5 eV. In the charge plasma-based structures, the source and drain are generated using the charge plasma concept in the undoped intrinsic silicon body. The conditions for generating an electron plasma are: 1) The work function of the metal contacts of the source and drain must be smaller than the work function of silicon [φm < χSi + (EG / 2)], where EG is the band gap of silicon and χSi = 4.17 eV is the electron affinity; 2) The substrate thickness must be smaller than the Debye length LD = (εsi ν T / qN) 1 / 2,where εsi is the dielectric constant of silicon, VT is the thermal voltage, q is the elementary charge, and N is the charge carrier concentration. The work function φ = 3.9 eV of hafnium and the silicon film thickness tsi = 10 nm fulfill the two conditions mentioned above for generating an electron plasma in the intrinsic source / drain regions of CP-DM and CP-GS-DM. In CP-DM and CP-GS-DM, lateral and top metal electrodes are used on the source / drain side to generate a plasma with a constant electron charge. In the simulations, HfO₂ is chosen as the high-k material beneath the metal electrodes of the source / drain and the spacers. The thickness of the HfO₂ beneath the source / drain in the plasma structures is 0.6 nm. The use of a high-k dielectric between the metal contacts of the source / drain and the silicon body serves to prevent silicide formation. In gate-stack structures, the oxide layer thickness tox = 1.1 nm is divided into 0.6 nm SiO2 and 0.5 nm High-k on (dht ox = t SiO2 + t High-k = 1.1 nm). The simulations were performed using the Silvaco ATLAS 3D instrument simulator. The Auger and Shockley-Read-Hall models are used as recombination models for minority carrier recombination. The mobility models used for the simulation are concentration-dependent mobility and the high-field reduction model. Band gap narrowing is also taken into account. The Bohm quantum model is included to describe the quantum confinement effect.

[0042] In one embodiment, the effects of gate stacking on a device and those of the DM gate on the charge plasma-based NWFET are investigated. Considering both GS and unstacked gate structures with SMG, the capacitance of the non-GS layer and the GS layer is analyzed.

[0043] It was observed that the capacitance of the GS structure is higher than that of unstacked gate structures with the same physical thickness of the SiO2 oxide layer. Since the drain current I DS proportional to Co ox This suggests that the drain current of GS structures is higher compared to non-GS structures. The drain current I D In the saturation region, the function of the change in tox is analyzed for GS and non-GS structures. In GS structures, t OX varies, where t SiO2 held constant at 0.6 nm and t high-k is varied. It turns out that for higher values ​​of t OXLower saturation current values ​​are achieved for both GS and non-GS structures. Furthermore, it can be observed that the drain current values ​​for the corresponding gate oxide thickness are higher for GS structures than for non-GS structures. A simplified classical model was considered for the device structure, which can be further improved by taking into account short-channel effects (SCEs) and interface charges of the device, including quantum effects.

[0044] The variation of the saturation current as a function of the charge plasma in the DM-Gate structure (CP-DM) is analyzed based on the applied work function at the source and drain. Here, "r" is defined as the radius of the nanowire, "L" as the channel length, and "V" as the T “Assumed as thermal stress. The drain current flow in the OFF and ON states is explained below.

[0045] In the off state, in which V GS = 0 V and V DSIf the voltage is 0 V, the transition between the gate at M2 and the drain is reverse biased, resulting in zero drift current components and only diffusion current flowing in this state.

[0046] When switched on, if V GS Reducing the source voltage (sm) increases the drain current by inducing a large number of charge carriers in the source / drain region. This can shift the semiconductor's Fermi level across the conduction band, thus increasing the charge carrier concentration beyond the effective density of states. With a reduction in sm and an increase in gate voltage, the drain saturation current increases by approximately 2.5 times. The non-zero diffusion current, which increases the drain saturation current in the on-state, is due to the resulting flux of the unbalanced minority carrier concentration within the structure in a charge plasma-based, doped-free device.

[0047] The electron and hole concentration distribution along the device length in thermal equilibrium and in the on-state shows that the charge carrier concentration profile of undominated devices is similar to that of devices without a pn junction, thus confirming the charge-plasma concept. In the on-state, the hole concentration in undominated charge-plasma devices is lower, which explains the lower current in the off-state.

[0048] The simulated seamless nanowire field-effect transistor was designed for a radius r = 5 nm and a gate length L. G = 20 nm, an oxide layer thickness t OX = 1 nm and a silicon body charge carrier concentration of 1 × 10 15 cm 3 at V ds The charge plasma nanowire field-effect transistor was calibrated to 1.0 V. It was designed for a radius r = 5 nm and a gate length L. G= 20 nm, an oxide layer thickness of 2 nm and a silicon charge carrier concentration of 1 × 10 19 cm 3 at V ds = 0.7 V calibrated. The I D -V G -Charactance curves of all components at V dsThe values ​​of 0.9 V indicate that the drain current of the undoped, charge-plasma-based structures is higher than that of their junctionless counterparts. This is due to the lower mobility degradation of the undoped silicon in the undoped devices compared to the doped, junctionless devices. Furthermore, gate-stack structures exhibit a higher drain current than structures without a gate stack. The high drain current is attributed to the smaller equivalent oxide thickness and lower subthreshold slope of the gate-stack structure compared to structures without a gate stack. Due to incomplete ionization, the junctionless structures exhibit a lower drain current. This results in the highest drain current for CP-GS-DM, followed by CP-DM, JL-GS-DM, and JL-DM.

[0049] The transconductance and the transconductance gain factor as a function of the gate-source voltage at V DS= 0.9 V show that the transconductance below V GS The gate-source voltage (VGS) is almost constant at 0.4 V, but increases with increasing gate-source voltage. GS At a voltage of 0.9 V, CP-GS-DM exhibits the highest transconductance, followed by CP-DM, JL-GS-DM, and JL-DM. This increased transconductance of the doped structures CP-GS-DM and CP-DM is due to their higher mobility and higher drain current compared to their pn-less counterparts. The transconductance gain describes the efficiency with which a device converts current into transconductance. CP-GS-DM achieves higher values ​​for the transconductance gain. In the linear and saturation regions, the transconductance gain decreases.

[0050] The drain current as a function of the drain-source voltage at V GSA voltage of 0.2 V indicates that JL-DM reaches its maximum value for all components, followed by CP-DM, CP-GS-DM, and JL-GS-DM. The variation in output conductance as a function of drain-source voltage at V GS The value of 0.2 V illustrates that the operating range determines the output conductivity. In the linear region, the output conductivity is high but decreases with increasing gate-source voltage due to channel length modulation. In the saturation region, the output conductivity decreases continuously and reaches a minimum constant value due to drain-induced barrier lowering. In the saturation region, CP-GS-DM exhibits the lowest output conductivity, followed by JL-GS-DM, CP-DM, and JL-DM.

[0051] The Early voltage is a parameter used to analyze analog power. It is shown that CP-GS-DM, due to its lowest output conductivity, achieves the highest Early voltage value at higher drain-source voltages. JL-DM, due to its highest output conductivity, exhibits the lowest Early voltage.

[0052] The drain-induced barrier drop values ​​for all components show that CP-GS-DM exhibits the lowest drain-induced barrier drop. The values ​​for CP-GS-DM, JL-GS-DM, CP-DM, and JL-DM are 165.3, 167.7, 182.2, and 182.7 mV / V, respectively. Thus, doping-free structures exhibit lower drain-induced barrier drop values ​​and minimize short-channel effects.

[0053] The subthreshold slope as a function of the drain-source voltage at V GSA value of 0.9 V indicates that the doped devices CP-DM and CP-GS-DM exhibit lower subthreshold transconductance values ​​than JL-DM and JL-GS-DM, respectively. Gate-stack structures show better subthreshold transconductance than non-gate-stack structures due to their smaller equivalent oxide thickness. Therefore, CP-GS-DM exhibits the lowest subthreshold transconductance values, followed by JL-GS-DM, CP-DM, and JL-DM.

[0054] The intrinsic gain as a function of the gate-source voltage at V DSThe value of 0.9 V shows that dual-material gate-stack structures exhibit higher gain than their non-gate-stack counterparts due to their smaller equivalent oxide thickness. The same applies to the CP-GS-DM and JL-GS-DM gate-stack structures, which show higher intrinsic gain due to their higher transconductance values. Thus, CP-GS-DM exhibits the highest intrinsic gain, followed by JL-GS-DM, CP-DM, and JL-DM. This suggests that doped-free structures are preferable to highly doped, seamless structures in terms of their suitability for analog applications and the reduction of short-channel effects.

[0055] The influence of varying gate length was observed for all device configurations, with the ratio of the lengths of the first and second gate metal layers being 1:1 in each case. The ratio I ON / I OFF and the current I OFF depending on the gate length at V ds= 0.9 V and V gs = 0.9 V show for all structures that the ratio I ON / I OFF The reverse current decreases with decreasing gate length. CP-GS-DM exhibits the highest values ​​for varying gate lengths, followed by CP-DM, JL-GS-DM, and JL-DM. The reverse current increases with decreasing gate length. The lowest reverse current value is found for CP-GS-DM at every gate length. Even at smaller gate lengths, CP-GS-DM shows a lower reverse current compared to JL-GS-DM, while simultaneously exhibiting a higher inrush current. Therefore, gate-stack doped structures offer better scalability than pn-less structures.

[0056] In the analysis of the effects of the ratio of control gate to total gate length, the total gate length is kept constant at 20 nm, while the control gate length L M1 is varied. With a ratio L M1 / L G A gate with a lower work function of 0 is present. For a ratio of LM1 / L G A value of 1 indicates that only one gate with a higher work function is present. The current intensities I ON / I OFF and I ON are as a function of the ratio L M1 / L G for all components at V gs = 0.9 V and V ds The results show that an increasing ratio of L M1 to L G the inrush current is reduced, while the ratio I ON to I OFF for all components. With increasing ratio L M1 / L G The channel depletion charge increases, leading to a reduction in the turn-off current and threshold voltage. This reduction in threshold voltage, in turn, reduces the turn-on current and increases the ratio I. ON / I OFF The highest values ​​for inrush current and I ON / I OFFThe highest values ​​are achieved by CP-GS-DM, followed by CP-DM, JL-GS-DM, and JL-DM. The reduced equivalent oxide thickness of the gate-stack structures, combined with the lower mobility degradation of the undoped structures, results in the highest drain current and the highest Ig for CP-GS-DM. ON / I OFF -ratio. The optimal value of the ratio L M1 / L G is the one where a compromise is made between inrush current and I ON / I OFF A ratio is achieved. This value is approximately 0.2 for CP-GS-DM.

[0057] Transconductance as a function of the ratio L M1 / L G for all components at V gs = 0.9 V and V ds A value of 0.9 V indicates that undoped devices exhibit higher transconductance due to the higher drain current. Gate-stack structures improve transconductance. CP-GS-DM exhibits the highest transconductance. With increasing ratio L M1The transconductance of all components decreases due to the decreasing drain current. The highest transconductance value for undoped components is obtained at a ratio of L M1 / L G reached 0.2.

[0058] With increasing channel depletion charge due to increasing L M1 / L G The subthreshold slope decreases with increasing L. M1 / L G -ratio for all components with V gs = 0.9 V and V ds A value of 0.9 V indicates that gate-stack structures exhibit a lower subthreshold slope than their non-gate-stack counterparts due to the reduced equivalent oxide thickness caused by gate stacking. Gate-stack structures combined with an undoped structure exhibit the lowest possible subthreshold slope. Thus, CP-GS-DM exhibits the lowest subthreshold slope.

[0059] Applying the charge plasma concept to gate-all-around structures, two transistor structures are proposed: CP-DM NWFET and CP-GS-DM NWFET. Three-dimensional simulations were performed to determine their performance characteristics. Compared to their junctionless counterparts, the doped-free CP-DM and CP-GS-DM structures offer improved analog parameters. Doped-free devices also exhibit a reduction in drain-induced barrier drop and subthreshold transconductance. The influence of the structure parameters on performance is also investigated. It is shown that the doped-free structures can be scaled more efficiently to shorter lengths than junctionless structures. Therefore, doped-free structures are preferable in the design of analog circuits due to reduced short-channel effects and lower thermal budgets.Of all the structures, CP-GS-DM has the best analog parameters and is suitable for components that require high gain.

[0060] The drawings and the preceding description illustrate embodiments. Those skilled in the art will recognize that one or more of the described elements can be combined to form a single functional element. Alternatively, certain elements can be divided into several functional elements. Elements of one embodiment can be added to another. For example, the process flows described here can be modified and are not limited to the manner described herein. Furthermore, the actions of a flowchart need not be performed in the sequence shown; nor do all actions necessarily need to be carried out. Actions that do not depend on other actions can be performed in parallel with the other actions. The scope of protection of the embodiments is in no way limited by these specific examples. Numerous variations, whether explicitly stated in the description or not, such as...Differences in structure, dimensions, and materials are possible. The scope of protection of the embodiments is at least as comprehensive as described by the following claims.

[0061] The advantages, other benefits, and problem solutions have been described above with reference to specific embodiments. However, the advantages, benefits, problem solutions, and any components that can effect or enhance an advantage, benefit, or solution are not to be construed as critical, necessary, or essential features or components of the claims. REFERENCES 100 A Gate All-Around Charge Plasma-Based Dual-Material Gate Stack Nanowire Field-Effect Transistor (FET). 102 Undoped Intrinsic Silicon Nanowire Body 104 Source electrode 106 Drain electrode 108 Gate structure 108a Dual-Material-Gate 110 Gate dielectric layer QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited non-patent literature

[0000] The values ​​for CP-GS-DM, JL-GS-DM, CP-DM and JL-DM are 165.3, 167.7, 182.2 and

[0052] respectively.

Claims

[1] A gate all-around charge plasma-based dual-material gate stack nanowire field-effect transistor, consisting of: an undoped intrinsic silicon nanowire body whose thickness is smaller than the Debye length; a source electrode and a drain electrode generated in the undoped intrinsic silicon nanowire body by means of a charge plasma, wherein the source electrode and the drain electrode have metal contacts with a work function that is less than the sum of the electron affinity of silicon and half the band gap of silicon, and wherein the source electrode and the drain electrode are configured to generate an electron charge plasma in the source and drain regions of the silicon nanowire body; a gate structure surrounding the undoped intrinsic silicon nanowire body, wherein the gate structure comprises a dual-material gate containing a first gate metal material and a second gate metal material arranged along a length of the silicon nanowire body, and wherein the first gate metal material has a first work function and the second gate metal material has a second work function, the difference between the first and second work functions being 0.5 electron volts; and a gate dielectric layer arranged between the gate structure and the silicon nanowire body, wherein the gate dielectric layer comprises a gate stack structure containing a silicon dioxide layer and a layer of dielectric material with a high dielectric constant; the transistor is configured to provide improved analog performance with reduced short-channel effects and operates without chemical doping in the source and drain regions. [2] Transistor according to claim 1, wherein the source electrode and the drain electrode have a work function of 3.9 electron volts hafnium, wherein this work function and the silicon film thickness of 10 nm facilitate the induction of electron charge plasma in intrinsic source / drain regions of the transistor. [3] Transistor according to claim 1, wherein the gate stack structure comprises a silicon dioxide layer with a thickness of 0.6 nanometers and a layer of high-k dielectric material with a thickness of 0.5 nanometers, wherein the total thickness of the gate oxide of the gate stack structure is 1.1 nanometers and the high-k dielectric material layer comprises hafnium dioxide. [4] Transistor according to claim 1, wherein the silicon nanowire body has a thickness of 10 nanometers; the total length of the gate, consisting of the sum of a first gate metal material length and a second gate metal material length, is 20 nanometers; and the transistor further comprises spacing regions with a spacing length of 10 nanometers, arranged between the gate structure and the source and drain electrodes. [5] Transistor according to claim 1, wherein the first gate metal material is arranged next to the source electrode; the second gate metal material is arranged next to the drain electrode; a ratio of the length of the first gate metal material to the total length of the gate is configured such that the analog performance parameters are optimized. [6] Transistor according to claim 1, further comprising: a high-k dielectric layer arranged between the metal contacts of the source and drain electrodes and the silicon nanowire body; wherein the high-k dielectric layer has a thickness of 0.6 nanometers; the high-k dielectric layer comprises hafnium dioxide; and the high-k dielectric layer is configured to prevent the formation of silicide at the interfaces between the metal contacts and the silicon nanowire body. [7] Transistor according to claim 1, wherein the source electrode and the drain electrode further comprise lateral metal electrodes and upper metal electrodes, wherein the lateral metal electrodes and the upper metal electrodes are configured to induce a plasma with constant electron charge in the source and drain regions. [8] Transistor according to claim 1, wherein the transistor has the following: improved driver current; improved transconductance; improved transconductance gain factor; reduced output conductance; increased early voltage; increased intrinsic gain; reduced drain-induced barrier drop; and reduced subthreshold transconductance. [9] Transistor according to claim 1, wherein the capacitance of the gate-stack structure is greater than the capacitance of a non-gate-stack structure with equivalent physical gate oxide thickness, wherein the transistor provides an increased drain current in the saturation region compared to the non-gate-stack structure. [10] Transistor according to claim 1, wherein the transistor exhibits lower random doping variations compared to chemically doped field-effect transistors and enables manufacturing with a low thermal budget, wherein the transistor is configured for analog circuit applications.

Images