A dual-gate tunnel field-effect transistor with a germanium source

The Ge-source DG-TFET addresses MOSFET and TFET limitations by integrating a heterodielectric gate oxide and source pocket structure, achieving superior current driving and RF/analog performance with temperature-dependent optimization.

DE202026101777U1Undetermined Publication Date: 2026-07-02BORDOLOI SUSHANTA +2
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Patent Information

Application Number
DE202026101777
Authority / Receiving Office
DE · DE
Patent Type
Utility models
Current Assignee / Owner
Filing Date
2026-03-28
Publication Date
2026-07-02
Estimated Expiration
2036-03-31

AI Technical Summary

Technical Problem

Conventional MOSFETs face challenges with increased power dissipation, leakage currents, and short-channel effects, while TFETs suffer from low inrush current and ambipolar conductance, necessitating an optimized Ge-source DG-TFET design for improved current driving capability and analog/RF performance.

Method used

A Ge-source DG-TFET with a heterodielectric gate oxide structure and source pocket configuration, optimized doping concentrations, and a dual-gate architecture to enhance tunneling efficiency and reduce leakage currents, suitable for low-power, high-frequency applications.

Benefits of technology

The Ge-source DG-TFET exhibits enhanced ON-state current, reduced threshold voltage variability, and improved RF and analog performance characteristics, with temperature-dependent behavior optimized for energy-efficient operation.

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Abstract

A germanium-source double-gate tunnel field-effect transistor (Ge-source-DG-TFET) comprising: a channel region with a length of 50 nm and a silicon layer thickness of 12 nm, wherein the channel region is weakly p-doped with a concentration of 1 × 10¹⁶ cm⁻³; a germanium source region p-doped with a concentration of 1 × 10²⁰ cm⁻³ to facilitate the band-to-band tunneling process; a drain region n-doped with a concentration of 5 × 10¹⁸ cm⁻³; a heterodielectric gate oxide structure with a thickness of 2 nm, wherein the heterodielectric gate oxide structure comprises: a 30 nm long low-dielectric constant (low-k) SiO₂ region on the drain region side, and a high-dielectric constant HfO₂ region arranged on the source region side. is;and a source-pocket structure with a length of 6 nm and a doping concentration of 2 × 1019 cm-3, positioned between the germanium source region and the channel region.
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