microcontroller chip

Abstract

Chip (100) of a microcontroller unit (MCU) which has an MCU die (101, 201) wherein the MCU die (101, 201) contains an internal memory control logic circuit (101a, 201a) and is provided with a number of external first pads (2011) on a first side; at least one flash die (102, 202), wherein the flash die (102, 202) contains an internal memory array and is provided with a number of external second pads (2021) on a second side; and a number of first connecting lines (203) which connect the second pads (2021) to the corresponding first pads (2011) and thereby form multi-bit address lines (ADDR, ADDR a , ADDR b ), Multi-bit data lines (DATA, DATA a , DATA b ) and multi-bit memory control signal lines (RWCTL, RWCTL a , RWCTL b) form, wherein the MCU die (101,201), the at least one flash die (102,202) and the number of first interconnect lines (203) are packaged in a single package using an advanced packaging technique.

Description

TECHNICAL AREA

[0001] The present invention relates to the field of integrated circuit (IC) chips and in particular to a microcontroller unit (MCU) chip. BACKGROUND

[0002] Microcontroller units (MCUs) are lightweight computing chips used as control cores in many electronic devices because they consume little power and allow for flexible programming. MCUs require associated memory to store code and data generated during operation.

[0003] Flash memory is an essential component of an MCU chip, as it stores code and data generated during MCU operation. With embedded flash memory (eFlash), the circuitry is typically integrated into a standard MCU circuit on a single MCU die. The major drawback of eFlash memory is that the flash memory circuitry must be manufactured using the same process as a corresponding standard MCU circuit.As MCU chips continually evolve towards more advanced nodes, eFlash memory places additional demands on the technical resources of wafer foundries. For a given circuit area, the cost of manufacturing an eFlash memory circuit is typically 30% higher than that of a standard circuit manufactured using the same process, and the 28 / 22 nm nodes of silicon photolithography technology are considered the last cost-effective nodes for eFlash memory. Therefore, this is becoming the main obstacle to the further development of MCU technology beyond the current state of the art.

[0004] One possible solution to the problem mentioned above is the use of so-called System-in-a-Package (SiP) flash memory. More precisely, as described in Fig. As shown in Figure 1, this solution integrates a logic circuit required for an MCU chip 100, such as a memory control logic circuit 101a (also known as a memory control module), a bus 101b, and a random access memory 101c, into a single MCU die 101. This die is then packaged with a flash die 102 using SiP packaging, resulting in a co-packaged MCU chip 100. In this design, the code and data for the MCU are stored in the flash die 102, which is independent and external to the MCU die 101. The flash die 102 and the MCU die 101 communicate with each other via a serial peripheral interface (SPI). When a read access request is received via bus 101b, the requested data is copied from flash die 102 to random access memory 101c under the control of the memory control logic circuit 101a and then read from random access memory 101c by the MCU die 101.In response to a write access request received via bus 101b, the memory control logic circuit 101a writes the intended data to both the random access memory 101c and the flash die 102. This solution offers advantages such as high capacity, cost-effective storage, and a short time to market, and does not present significant manufacturing challenges. However, because the SPI interface is used between the SiP-packed flash die 102 and the MCU die 101, data must be written to and read from the flash memory byte by byte, even if the interface has 8 I / O data lines (e.g., an OSPI interface), resulting in slow code / data read and write speeds. Furthermore, this solution requires the configuration of a matching random access memory 101c, which can lead to an increase in the area of ​​the MCU die 101. OVERVIEW OF THE INVENTION

[0005] One object of the present invention is to provide an MCU chip that can be configured more flexibly and enables significantly faster data read and write speeds.

[0006] For this purpose, the present invention provides an MCU chip comprising: an MCU die containing an internal memory control logic circuit and equipped on its first side with a number of external first pads; at least one flash die containing an internal memory array and equipped on its second side with a number of external second pads; and a number of first connecting lines that connect the second pads to the corresponding first pads, thereby forming multi-bit address lines, multi-bit data lines, and multi-bit memory control signal lines, wherein the MCU die, the at least one flash die and the number of initial interconnect lines are packaged in a single package using advanced packaging technology.

[0007] This arrangement allows address signals, data signals, and read, write, and erase control signals to be transferred directly in parallel in a peer-to-peer manner between the MCU die and the flash die without protocol conversion. This enables higher data programming, read, and write speeds than SiP flash memories used in conventional MCUs. Furthermore, the data read and write performance between the MCU die and the externally connected flash die is comparable to that of an eFlash memory (i.e., a flash memory circuit integrated into a single die along with a memory control logic circuit of an MCU, etc.), without the need to integrate a flash memory circuit into the MCU die. Therefore, compared to the eFlash memory scheme, savings in chip area and simpler manufacturing can be achieved.

[0008] When the size of the flash memory circuitry in a conventional MCU chip with eFlash memory needs to be changed, the MCU chip manufacturer must perform a tape-out of various versions of the MCU die. Typically, an area corresponding to the maximum capacity required by the eFlash memory circuitry is reserved in such versions to avoid altering the layout and / or wiring of the rest of the standard MCU circuitry, which would result in wasted chip area. In contrast, if it is necessary to change the flash memory capacity of the MCU chip, according to one embodiment of the present invention, the flash die can simply be replaced without subjecting the MCU die to an additional tape-out.This reduces the time required to develop the MCU chip, and eliminates the need to reserve space for maximum eFlash storage capacity, resulting in a smaller overall area for the MCU chip.

[0009] Optionally, the MCU die and the flash die can be arranged side by side, with the first pads on the first side of the MCU die located proximal to the flash die and the second pads on the second side of the flash die located proximal to the MCU die. By placing the first and second pads in close proximity to each other, the initial interconnect lines are easier to design and can be shorter, which improves line stability and speeds up data transmission.

[0010] Optionally, the top surfaces of the MCU die and the flash die can form a fan-out area within an intermediate package. This scalable fan-out design eliminates the need for a leadframe, packaging substrate, and similar components, enabling simple die packaging using advanced packaging techniques. Furthermore, the resulting chip package has a comparable shape, smaller dimensions, and improved performance, for example, in terms of thermal simulation.

[0011] Optionally, the package can also include an internal redistribution layer formed on the fan-out area, with the first part of the redistribution layer serving as the first interconnects. This arrangement allows the first and second pads within the MCU chip to be reliably connected via redistribution wires without the use of solder joints. Furthermore, the redistribution process aids in optimizing the layout of the first and second pads and can reduce or, in extreme cases, even completely eliminate wire crossings within the package.

[0012] Optionally, at least one of the MCU die and the flash die can be further equipped with a number of third pads, with a second portion of the redistribution layer serving as the second interconnect, electrically connected to the third pads, and with the top surface of a portion of the second interconnect exposed to form an external contact pad. This arrangement allows a redistribution process to be used to simultaneously fabricate the first and second interconnects, the external contact pads, and other electrical structures required for the MCU chip, simplifying the process and reducing its cost. Furthermore, the formation of solder joints is avoided, resulting in high reliability.Furthermore, the redistribution process is helpful in optimizing the layout of the first, second and third pads and the external contact pads, and can reduce wire crossings within the packaging or, in extreme cases, even completely eliminate them.

[0013] Optionally, the redistribution layer can include a second redistribution layer, with the first part of this layer serving as the first connection lines and the second part serving as the second connection lines. In this configuration, a single redistribution layer can provide the first and second connection lines and all other necessary electrical structures, simplifying the process and reducing costs. Furthermore, the formation of solder joints is avoided, resulting in high reliability. The outcome is also a product with improved performance and even smaller dimensions.

[0014] Optionally, the redistribution layer can have a first and a second redistribution layer, stacked one above the other above the fan-out area from bottom to top. A portion of the first redistribution layer serves as the first bonding conductor, while a portion of the second redistribution layer and a portion of the second redistribution layer serve as the second bonding conductor, electrically connected to the third pads. This redistribution process is helpful in optimizing the layout of the first, second, and third pads and can reduce or, in extreme cases, completely eliminate wire crossings within the package. Furthermore, the connections linking the pads are redistribution wires produced using advanced packaging technology, not bond wires produced using conventional packaging techniques.This eliminates the formation of solder joints, resulting in high reliability and time savings. Optionally, solder balls can be formed on the external contact pads. This eliminates the need to place a packaging substrate at the bottom after the fan-out area has been formed. Instead, the redistribution layer is formed directly on the fan-out area using advanced packaging technology, and then the solder balls are formed on the external contact pads. The resulting package has a shape comparable to a BGA / WLCSP chip package, smaller dimensions, and offers improved performance.

[0015] Optionally, conductive pads can be formed on the top surfaces of the external contact pads, with the conductive pads distributed around the perimeter of the package and one top or side surface of each conductive pad exposed outside the package. This eliminates the need to place a leadframe after forming the fan-out area. Instead, the redistribution layer is formed directly on the fan-out area by the advanced packaging technique, and then the conductive pads are formed on the external contact pads. The resulting package has a shape comparable to a QFN chip package, smaller dimensions, and exhibits improved performance, for example, in thermal simulation.

[0016] Optionally, the area of ​​the first and second pads can be smaller than the area of ​​the third pad. This allows the area of ​​the first and second pads to be reduced as much as possible, thus largely avoiding the need for additional chip area expansion.

[0017] Optionally, the area and one dimension of the first and second pads each conform to a minimum specification permissible through the bonding process of the first interconnect. Since the area of ​​the first and second pads is reduced to the smallest possible size during the manufacturing process, additional chip area extensions are largely avoided.

[0018] Optionally, the packaging can further comprise a semiconductor substrate, wherein both the MCU die and the flash die are mounted in a trench in the semiconductor substrate, and the top surfaces of the MCU die, the flash die, and the semiconductor substrate together form the fan-out area, wherein the MCU die and the flash die are bonded to the bottom of the single trench or different trenches by an adhesive layer, and wherein gaps created by the mounting of the MCU die and the flash die in the trench are filled with a dielectric material.

[0019] Provided the number of first pads on the MCU die allows it, different flash dies with varying capacities and a different number of second pads can be incorporated. This enables more flexible MCU design and efficient MCU development that can be completed quickly. Optionally, two flash dies can be included, one for the online operation of the MCU chip and the other for upgrading the MCU chip.

[0020] Optionally, a number of the first connecting lines that serve as multi-bit address lines is (A+1), where a corresponding maximum physically addressable space in the memory array is [0, 2A+1-1].

[0021] Optionally, the first interconnection lines, which serve as multi-bit memory control signal lines, can be configured to transmit control signals generated by the memory control logic circuit based on appropriate read, write, and erase commands, and the number of first interconnection lines, which serve as multi-bit data lines, is (D+1), which corresponds to a bit width of the memory array for reading and writing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] It is evident to the average person skilled in the art that the following drawings serve to improve understanding of the present invention and are not intended to limit the scope of the invention in any way, showing in the drawings: Fig. Figure 1 schematically shows the system architecture of a microcontroller unit (MCU) chip containing a SiP flash memory; Fig. Figure 2 schematically shows the system architecture of an MCU chip according to a first embodiment of the present invention; Fig. Figure 3 shows a schematic cross-sectional view of an exemplary structure resulting from a fan-out packaging process carried out on an MCU die according to the first embodiment of the present invention; Fig. Figure 4 shows a schematic cross-sectional view of a structure resulting from a QFN packaging process applied to the MCU die of Fig. 3 is carried out; Fig. Figure 5 shows a schematic top view of a structure resulting from a QFN packaging process applied to the MCU die of Fig. 3 is carried out; Fig. Figure 6 shows a schematic cross-sectional view of a structure resulting from a BGA / WLCSP packaging process applied to the MCU die of Fig. 3 is carried out; Fig. Figure 7 shows a schematic top view of a structure resulting from a BGA / WLCSP packaging process applied to the MCU die of Fig. 3 is carried out; Fig. Figure 8 shows a schematic diagram of another exemplary structure resulting from a BGA / WLCSP packaging process carried out on the MCU die according to the first embodiment of the present invention; Fig. Figures 9 to 11 show schematic cross-sectional views of structures resulting from other advanced packaging processes carried out on the MCU die according to the first embodiment of the present invention; Fig. Figure 12 shows a schematic timing diagram of a data transmission between the MCU die and a flash die in the MCU chip according to the first embodiment of the present invention; Fig. Figure 13 schematically shows the system architecture of an MCU chip according to a second embodiment of the present invention; and Fig. Figure 14 shows a schematic top view of the MCU chip of Fig. 13. Reference symbol list

[0023] 100-MCU chip; 101-MCU die; 101b-bus; 101c-Rapid access memory; 102-flash die; 200-semiconductor substrate; 200a-trench; 201-MCU die; 101a, 201a-memory control logic circuit; 2011-first pad; 2012, 2012A, 2022-third pad; 202, 202a, 202b-flash die; 2021-second pad; 203-first interconnect; 204, 2041-second interconnect; 204a - external contact pads; 205 - adhesive layer; 206 - dielectric material; 207 - first dielectric layer; 208 - solder paste; 209 - conductive pad; 210 - second dielectric layer; 211 - solder ball; DATA, DATA a , DATA b - Data line; RWCTL, RWCTL a , RWCTL b -Storage control signal line; ADDR, ADDR a , ADDR b-Address line. DETAILED DESCRIPTION

[0024] For a better understanding of the present invention, numerous specific details are given in the following description. However, it is evident to those skilled in the art that the present invention can be carried out without one or more of these specific details. In other cases, known technical features have not been described in order to avoid unnecessarily obscuring the invention. It is understood that the present invention can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth below. Rather, these embodiments are provided to ensure that this disclosure is comprehensive and that those skilled in the art fully understand the scope of the invention. In the drawings, the same reference numerals consistently refer to the same elements.It is understood that when an element is described as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is described as "directly connected to" another element, there are no intervening elements. The singular forms "ein / -e" and "der / die / das" used here are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be noted that the term "exhibits" indicates the presence of specified features, steps, operations, elements, and / or components, without excluding the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.The term “and / or” used herein includes any and all combinations of the points listed.

[0025] The present invention is described in more detail below with reference to the accompanying drawings, which show certain embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the figures are shown in a highly simplified form, not necessarily drawn to scale, and serve only to illustrate the disclosed embodiments in a more convenient and clearer manner. Design 1

[0026] Referring to Fig. In embodiment 1 of the present invention, a microcontroller unit (MCU) chip is provided, comprising an MCU die 201, a flash die 202 and a number of first interconnection lines 203, which are packaged in a single package using an advanced packaging technique.

[0027] The MCU-Die 201 and the Flash-Die 202 are separate dies that can be fabricated independently using different integrated circuit processes. For a given circuit area, the cost of fabricating a flash memory circuit is typically 30% higher than the cost of a standard circuit fabricated using the same process. Accordingly, in an implementation, the process for fabricating the Flash-Die 202 may have a larger critical dimension (CD) than the process for the MCU-Die 201 to achieve cost savings.

[0028] The MCU die 201 can contain a memory control logic circuit 201a and logic circuits with other functions. In this embodiment, the MCU die 201 includes, in addition to the third pads 2012 that are also required for conventional MCU dies 201 (e.g., input / output (I / O) pads that provide an I / O interface for the MCU chip, a clock pad for transmitting a clock signal to the MCU chip, and a power pad connected to an external power supply to provide the MCU chip with a supply voltage), a number of first pads 2011.

[0029] The Flash Die 202 can contain a memory array (not shown), and read, write, and erase operations can be performed on the memory array under the control of the memory control logic circuit 201a. The memory array can be used to store code required for upgrading and operating the MCU chip, as well as data generated during the use of the MCU chip. The Flash Die 202 additionally contains a number of second pads 2021, corresponding to all or some of the first pads 2011 on the MCU Die 201.

[0030] In some examples of this embodiment, the flash die 202 can be referred to Fig. In addition to the second pads 2021, third pads 2022 are also included for external connections. In further examples, the third pads 2022 on the flash die 202 can be connected to an external power supply, ground, or the like, so that the flash die 202 can be powered by the external power supply or externally grounded. In still other examples, the flash die 202 can be implemented as SiP flash memory if required, and third pads 2022 can be provided as a general-purpose interface for the flash memory. In some other examples relating to the Fig. 3 to 7, the Flash-Die 202 can be powered by the MCU-Die 201, and such third pads 2022 for external connections can be omitted on the Flash-Die 202.

[0031] In this embodiment, the first connecting lines 203 connect the first pads 2011 on the MCU die 201 to the respective second pads 2021 on the flash die 202 and form address lines ADDR[A:0] of (A+1) bits, data lines DATA[D:0] of (D+1) bits and memory control signal lines RWCTL[x:0] of (x+1) bits, where A, D and x are all integers greater than 1.

[0032] It is understood that the system architecture of the MCU chip of this embodiment actually consists of the MCU die and the single flash die, which is located outside of and connected to the MCU die. Therefore, the number of additional first pads 2011 on the MCU die 201 can be greater than or equal to the number of additional second pads 2021 on the flash die 202. In tailored applications, the number of additional first pads 2011 on the MCU die 201 can be equal to the number of additional second pads 2021 on the flash die 202 in the MCU chip. In contrast, in more general applications, the number of additional first pads 2011 on the MCU die 201 tends to be greater than the number of additional second pads 2021 on the flash die 202.In particular, the MCU die 201 can contain a maximum permissible number of additional first pads 2011, and in this case, multiple flash dies 202 with different specifications can be used, each with a different capacity and containing a number of second pads 2021 that is less than or equal to the maximum permissible number. This allows for a more flexible MCU design and efficient MCU development that can be completed within a short time.

[0033] In particular, when a change to the flash memory circuitry of a conventional MCU chip with eFlash memory is required (e.g., to change the capacity), the manufacturer must perform a tape-out of various versions of the MCU dies. Typically, such versions reserve an area corresponding to the maximum capacity required by the eFlash memory circuitry to avoid altering the layout and / or wiring of the rest of the standard MCU circuitry, which would result in wasted chip area. In contrast, if it is necessary to change the flash memory capacity of this type of MCU chip, the Flash Die 202 can simply be replaced without subjecting the MCU Die 201 to an additional tape-out.This reduces the time required to develop the MCU chip, and eliminates the need to reserve space for maximum eFlash storage capacity, resulting in a smaller overall area for the MCU chip.

[0034] It is also understood that in this embodiment the MCU die 201 and the flash die 202 can be packaged in a single package using a suitable advanced packaging technique that is capable of forming the first interconnecting lines 203.

[0035] Referring to Fig. In an example, 3 to 5, the MCU die 201 and the flash die 202 are housed in a single package using a fan-out wafer-level packaging (FO-WLP) and a quad-flat-no-leads (QFN) packaging process.

[0036] The FO-WLP process can include, for example, the following: first, providing a semiconductor substrate 200, which can be any suitable semiconductor material known in the field, such as silicon or a compound semiconductor material; then forming a trench 200a in the semiconductor substrate 200 by photolithography and etching processes; subsequent placement of the MCU die 201 and the flash die 202 side by side in the trench 200a, with their front faces both facing upwards (i.e., the side of the MCU die 201 on which the first pads 2011 are formed and the side of the flash die 202 on which the second pads 2021 are formed facing upwards), and forming an adhesive layer 205 of any suitable chip adhesive material which bonds the MCU die 201 and the flash die 202 to a bottom surface of the trench 200a on the underside; and Subsequently, a dielectric material 206 is filled into a gap between the MCU die 201 and the flash die 202, the gap between the MCU die 201 and the side walls of the trench 200a, and the gap between the flash die 202 and the side walls of the trench 200a. Depending on the properties of the dielectric material 206, any suitable process can be used to fill the gap. For example, the dielectric material 206 can be a photoresist or another organic polymeric dielectric material. In this case, the gaps can be filled by a coating process. In another example, the dielectric material 206 can be an inorganic dielectric material such as silicon dioxide, which can be filled into the gap by vapor deposition.

[0037] The result is an intermediate package containing the semiconductor substrate 200, the MCU die 201, the flash die 202, the adhesive layer 205, and the dielectric material 206. The top surfaces of the MCU die 201, the flash die 202, and the semiconductor substrate 200 form a fan-out area of ​​the intermediate package. The dielectric material 206 can not only fill the aforementioned gaps but also be present on the fan-out area in a specific thickness.

[0038] The QFN packaging process is then carried out on the intermediate packaging resulting from the FO-WLP process. The QFN packaging process can include, for example, the following: First, suitable processes such as photolithography and etching are carried out to create openings in the dielectric material 206, which expose the surfaces of the first pads 2011 on the MCU die 201 and the second pads 2021 on the flash die 202.

[0039] Next, a redistribution layer (RDL) is formed on the top surface of the dielectric material 206 by a redistribution process. The RDL layer comprises a first RDL layer and a first dielectric layer 207, which are formed sequentially over the top surface of the dielectric material 206. A portion of the second interconnect 204, exposed from the first dielectric layer 207, serves as an external contact pad 204a. Additionally, a portion of the first RDL layer serves as the first interconnect 203, which connects the first pads 2011 and the second pads 2021, thereby forming the (A+1)-bit address lines ADDR[A:0], the (D+1)-bit data lines DATA[D:0], and the (x+1)-bit memory control signal lines RWCTL[x:0]. In one example, the redistribution process includes: depositing a metallic material onto a surface of the semiconductor substrate 200; Forming redistribution wires (made of metal), e.g.by photolithography and etching; deposition of the dielectric material; and formation of new openings (corresponding to the external contact pads) by photolithography and etching. The redistribution wires and the pads are electrically connected to allow redistribution of I / O ports for the associated signals.

[0040] Then, with combined reference to Fig. 4 and Fig. 5. A solder paste 208 based on, for example, Ni, Au, or a Ni-Au alloy is applied to each of the external contact pads 204a, and conductive pads 209 are attached to the external contact pads 204a by the solder paste 208. The conductive pads 209 are distributed along the perimeter of the semiconductor substrate 200, and their top and side surfaces are all exposed from the first dielectric layer 207. Adjacent conductive pads 209 are spaced apart. In this way, a shape similar to that of a conventional QFN package is achieved. Compared to the conventional QFN package, the use of a leadframe is eliminated, and a more compact product size and improved performance, e.g., with respect to thermal simulation, are achieved.

[0041] In this embodiment, the first pads 2011 are arranged along a first side of the MCU die 201 proximal to the flash die 202, and the second pads 2021 are arranged along a second side of the flash die 202 proximal to the MCU die 201. Thus, the first pads 2011 and the second pads 2021 are located in close proximity to each other. This simplifies the design of the first interconnect lines 203, allowing them to be shorter and run parallel, thereby eliminating the risk of wire crossings and enabling more reliable and faster signal transmission.

[0042] Furthermore, in this embodiment, the third pads 2012 on the MCU die 201 have the same size (area and dimensions) as conventional pads, and the first pads 2011 have the same size as the second pads 2021, which can be smaller than the third pads 2012. This means that the first pads 2011 and the second pads 2021 can have a smaller area and smaller dimensions than the third pads 2012. For example, the area and dimensions of the first pad 2011 and the second pad 2021 are reduced to the smallest possible size that the manufacturing process allows, as long as the minimum specification for the stability and reliability of the connection process of the first interconnect 203 is met, without increasing the area of ​​the semiconductor substrate 200.In one implementation, the first pads 2011 and the second pads 2021 consist at least partially of the metal aluminium or an aluminium-copper alloy to facilitate their connection with the first connecting leads 203 (e.g. copper).

[0043] As mentioned above, part of the first RDL layer serves as the first interconnect lines 203, which connect the first pads 2011 and the second pads 2021, thereby forming the (A+1)-bit address lines ADDR[A:0], the (D+1)-bit data lines DATA[D:0], and the (x+1)-bit memory control signal lines RWCTL[x:0]. The remainder of the first RDL layer serves as the second interconnect lines 204 mentioned above, which are electrically connected to the third pads 2012. The first dielectric layer 207 serves as a passivation layer, and the first interconnect lines 203 and part of every second interconnect line 204 are embedded within it. Furthermore, a portion of the second interconnect line 204, exposed from the first dielectric layer 207, serves as an external contact pad 204a.

[0044] Since the first and second connecting lines are formed in a redistribution process, in this embodiment the layout of the external contact pads 204a, the first pads 2011, the second pads 2021 and other structures can be optimized to reduce or even eliminate the risk of wire crossings.

[0045] Furthermore, the QFN packaging process described here, compared to conventional QFN packaging, does not require a leadframe and can directly produce a square package comparable to those produced using conventional QFN packaging. Additionally, the resulting product has even smaller dimensions and exhibits improved performance, for example, in thermal simulation.

[0046] In another example, which relates to Fig. 3, Fig. 6 and Fig. 7 refers to the MCU die 201 and the Flash die 202 being packaged in a single package using an FO-WLP process and a Ball Grid Array (BGA) or Wafer Level Chip Scale Packing (WL-CSP) process.

[0047] The FO-WLP process can be the same as described above and therefore need not be described further here. An intermediate package resulting from the FO-WLP process comprises a semiconductor substrate 200, the MCU die 201, the flash die 202, an adhesive layer 205, and a dielectric material 206. A trench 200a is formed in the semiconductor substrate 200, and the MCU die 201 and the flash die 202 are both oriented so that their front faces are facing upwards (i.e., the side of the MCU die 201 on which the first pads 2011 are formed and the side of the flash die 202 on which the second pads 2021 are formed are facing upwards) and are placed side by side in the trench 200a. The MCU die 201 and the flash die 202 are bonded to the bottom surface of the trench 200a by the adhesive layer 205.The dielectric material 206 fills a gap between the MCU die 201 and the flash die 202, a gap between the MCU die 201 and the side walls of the trench 200a, and a gap between the flash die 202 and the side walls of the trench 200a. The top surfaces of the MCU die 201, the flash die 202, and the semiconductor substrate 200 form a fan-out area. The dielectric material 206 can not only fill the gap but also be present on the fan-out area at a specific thickness.

[0048] The BGA packaging process can then be carried out on the intermediate packaging resulting from the FO-WLP process. This process can include, for example, the following: First, suitable processes such as photolithography and etching are carried out to create openings in the dielectric material 206, which expose the surfaces of the first pads 2011 on the MCU die 201 and the second pads 2021 on the flash die 202.

[0049] Next, an RDL layer is formed on the top surface of the dielectric material 206 by a redistribution process. The RDL layer comprises a first RDL layer, a first dielectric layer 207, a second RDL layer, and a second dielectric layer 210, which are formed sequentially on the top surface of the dielectric material 206. A portion of the first RDL layer serves as the first interconnect lines 203, which connect the first pads 2011 and the second pads 2021, thereby forming the (A+1)-bit address lines ADDR[A:0], the (D+1)-bit data lines DATA[D:0], and the (x+1)-bit memory control signal lines RWCTL[x:0]. A portion of the second RDL layer is electrically connected at one end to the remainder of the first RDL layer and thus to the third pads 2012 on the MCU die 201. The other end of the second RDL layer serves for the external connection of the third pads 2012 on the MCU die 201.This means that part of the first RDL layer serves as the first interconnects 203, and the remainder of the first RDL layer and part of the second RDL layer together serve as the second interconnects 204, which are electrically connected to the third pads 2012 and connect the third pads 2012 to the outside world. The second dielectric layer 210 serves as a passivation layer, and the second interconnects 204 are partially embedded within it. Furthermore, the remaining portion of each second interconnect 204 that protrudes from the second dielectric layer 210 serves as an external contact pad 204a. The first and second RDL layers can be made of the same material, e.g., copper (Cu).

[0050] Subsequently, with reference to Fig. 6 and Fig. Seven solder balls or columns (also called conductive bumps) 211 are formed on the respective external contact pads 204a. The solder balls 211 can be made of Ni, Au, a Ni-Au alloy, or the like.

[0051] Compared to conventional BGA packaging, the BGA packaging process described here requires no additional substrate and can directly produce packaging in the same shape as conventional BGA packaging. Furthermore, the resulting product has even smaller dimensions and exhibits improved performance, for example, in thermal simulation.

[0052] In particular, the third pads 2012 on the MCU die 201 can be arranged in any way. For example, they can be arranged along the circumference of the MCU die 201.

[0053] Referring to Fig. As shown in Figures 4 to 7, some of the third pads 2012 can be arranged in a circumferential region of the MCU die 201 along its first side proximal to the flash die 202, and some 2012A of these third pads 2012, which are arranged along the first side of the MCU die 201, can be connected by appropriate second connecting lines 2041 to conductive pads 209 (see Figure 4 to 7). Fig. 5) or solder balls 211 (see Fig. 7) around a first side of the Flash die 202 (which is opposite to the aforementioned second side and faces away from the MCU die 201). To reduce parasitic capacitances and other parasitic parameters, the second connecting lines 2041, which connect the third pads 2012A, can be offset relative to the first connecting lines 203.

[0054] It is understood that, although the MCU die and the flash die in the above implementations are described as being bonded by an adhesive layer to the bottom of a single trench formed in a semiconductor substrate, the present invention is not so limited, since in alternative implementations as many trenches as the total number of MCU and flash dies can be formed in the semiconductor substrate, each for a corresponding die. In these cases, the MCU and flash dies can be placed in their respective trenches during packaging. In further implementations of the present invention, the semiconductor substrate can instead consist of a plastic (composite) or another material.

[0055] It is also understood that in other examples of this embodiment, such as in the Fig. Figures 9 to 11 show that the MCU die and the Flash die can be packed together using other advanced fan-out packaging techniques.

[0056] Fig. Figure 9, for example, shows an intermediate package resulting from a different FO-WLP process in which both the MCU die 201 and the flash die 202 are oriented with their top surfaces facing downwards (i.e., the side of the MCU die 201 on which the first pads 2011 are formed and the side of the flash die 202 on which the second pads 2021 are formed are facing downwards) and are encapsulated by the dielectric material 206 by injection molding. The top surfaces of the MCU die 201 and the flash die 202 form a fan-out area. Compared to the process for forming the intermediate package of Fig. 3 are omitted in the process for forming the intermediate packaging of Fig. 9 the steps of providing the semiconductor substrate 200 and forming the trench 200a in the semiconductor substrate 200 by photolithography and etching. In contrast to the intermediate packaging of Fig. 3, in which the dielectric material 206 fills the gap between the MCU die 201 and the flash die 202, the gap between the MCU die 201 and the side walls of the trench 200a, and the gap between the flash die 202 and the side walls of the trench 200a, is possibly present on the fan-out surface in a certain thickness and does not cover the backs of the MCU die 201 and the flash die 202, and the adhesive layer 205 is located between the backs of the MCU die 201 and the flash die 202 and the bottom surface of the trench 200a, covers the dielectric material 206, which is formed by injection molding rather than by filling, during the intermediate packaging of Fig. 9 the backs of the MCU die 201 and the flash die 202, and the surfaces of the MCU die 201 and the flash die 202 at the fan-out area (the fronts of the MCU die 201 and the flash die 202) are flush with the fan-out area, and the trench 200a and the adhesive layer 205, which are in Fig. The sections shown in 3a are omitted.

[0057] As can be seen, the top surfaces of the MCU die 201 and the Flash die 202 form the two intermediate packages of the Fig. 3 and Fig. 9 together form a fan-out area.

[0058] Fig. 10 and Fig. 11 show packaging that is improved by performing further QFN- ( Fig. 10) or BGA packaging processes ( Fig. 11) on the intermediate packaging of Fig. 9 will be received. The packaging of the Fig. 10 and Fig. 11 correspond to those of the Fig. 4 and Fig. 6 and therefore do not need to be described in more detail here. In particular, the advanced packaging techniques used in the examples above are merely illustrative and exemplary and are in no way intended to limit the present embodiment to any one of these advanced packaging techniques. Furthermore, instead of one or more RDL layers, multiple RDL layers are also possible, depending on the wiring requirements.

[0059] Regardless of the advanced packaging techniques used in this embodiment to package the MCU die 201 and the Flash die 202 together, it is understood that it is necessary to connect the first pads 2011 on the MCU die 201 and the second pads 2021 on the Flash die 202 to the first interconnect lines 203 to form the multi-bit address lines ADDR[A:0], the multi-bit data lines DATA[D:0] and the multi-bit memory control signal lines RWCTL[x:0].

[0060] Fig. Figure 12 shows a schematic timing diagram of the data transmission between the MCU die 201 and the flash die 202. As shown, several bits of ADDR, DATA, and RWCTL are transmitted in parallel. The different values ​​of RWCTL correspond to the respective operating modes. Thus, read, write, and erase operations on the flash die 202 can be performed by changing the values ​​of ADDR, DATA, and RWCTL. For example, when a read access request is received via a bus in the MCU die 201, a data read mode can be initiated by setting RWCTL to an associated value, and the requested code and / or data can then be read in parallel from the flash die 202 via the multi-bit address lines ADDR[A:0] and the multi-bit data lines DATA[D:0], according to the addresses specified in the read access request.When a write access request is received over the bus in MCU die 201, a data write mode can be initiated by setting RWCTL to another associated value, and the intended code and / or data can then be written in parallel to the Flash die 202 via the multi-bit address lines ADDR[A:0] and the multi-bit data lines DATA[D:0] according to the addresses and data specified in the write access request.

[0061] In one implementation, the number of first interconnection lines 203, which serve as multi-bit address lines ADDR[A:0], is (A+1), and a corresponding maximum physically addressable space in the memory array of the flash die 202 can be [0, 2 A+1- 1]. For example, if A+1=32, the corresponding maximum physically addressable space in flash memory for the 32-bit address lines ADDR[31:0] can be 0xFFFFFFFF - 0x00000000.

[0062] In another implementation, first interconnect lines 203 are used in the multibit memory control signal lines RWCTL to transmit control signals generated by the memory control logic circuit 201a based on read, write, and erase commands. In some other implementations, the number of first interconnect lines serving as multibit data lines DATA[D:0] is (D+1), which corresponds to a bit width used to read and write data to and from the memory array in the flash die 202.

[0063] In particular, the storage control logic circuit 201a of this embodiment is implemented by a circuit that is completely different from the circuits of the conventional storage control logic circuits 101a. In the conventional circuit of Fig. 1. Communication between the flash die 102 and the MCU die 101 occurs, for example, via the serial SPI protocol. Accordingly, the memory control logic circuit 101a must perform a parallel-to-serial protocol conversion to generate I / O (DATA IO), clock (CLK), and chip select (CS) signals, as required by the SPI protocol, and requires additional buffers or latches to enable such protocol conversion. In contrast, in this embodiment, as shown in Fig. Figure 2 shows that the Flash die 202 and the MCU die 201 communicate according to a tailored, dedicated parallel protocol, and the memory control logic circuit 201a can communicate directly between the bus in the MCU die 201 (i.e., the bus of Fig. 2 can be an internal high-speed bus (such as AXI or AHB) and coupled to the first link lines 203 to control data transmission between the MCU die 201 and the flash die 202 by converting control signals from the internal high-speed bus into flash memory interface signals (i.e., address signals, data signals, and read, write, and erase control signals). The memory control logic circuit 201a can enable the MCU die 201 to store program code directly in the flash die 202 and to access this program code directly without copying data from the flash die 202 to random access memory (RAM) (typically static RAM (SRAM)). Eliminating RAM can result in space and cost savings.Furthermore, the flash memory interface signals can be transmitted in parallel without the need for parallel-to-serial protocol conversion, further reducing the circuit area of ​​the MCU die 201.

[0064] Since, in this embodiment, address signals, data signals, and read, write, and erase control signals are transmitted directly in parallel in a peer-to-peer manner and without protocol conversion between the MCU die 201 and the external flash die 202, the MCU die 201 can read, write, and erase data in the flash die 202 at a significantly increased speed, as if it were performing data read and write operations on the eFlash memory. Furthermore, because the MCU die 201 and the flash die 202 are independent dies, the eFlash memory does not undesirably occupy any area of ​​the MCU die 201.

[0065] In summary, this embodiment offers advantages such as high capacity, cost-effective storage, and a short time to market, while presenting no major manufacturing challenges. It can be used in 22 nm or smaller nodes of silicon photolithography technology and enables the development of MCU chips for more advanced processes. Design 2

[0066] Referring to Fig. In embodiment 2 of the present invention, an MCU chip is provided, comprising an MCU die 201, two flash dies 202a, 202b and a number of first interconnect lines 203, which are packaged in a single package using an advanced packaging technique.

[0067] The MCU die 201 and the flash dies 202a and 202b are independent dies that can be fabricated separately using different integrated circuit processes. In alternative implementations, the two flash dies 202a and 202b can be fabricated using a single integrated circuit process.

[0068] The MCU die 201 can contain a memory control logic circuit 201a and logic circuits with other functions, and may be provided with a number of additional first pads on its top surface. Furthermore, each of the flash dies 202a and 202b may be provided with a number of additional second pads corresponding to all or some of the first pads 2011 on the MCU die 201. Specifically, some first pads 2011 on the MCU die 201 are connected to the respective second pads 2021 on the flash die 202a via the respective first interconnect lines, thus creating address lines ADDR. a[A:0] of (A+1) bits, data lines DATA a [D:0] of (D+1) bits and memory control signal lines RWCTL a [x:0] are formed by (x+1) bits. Other first pads 2011 on the MCU die 201 are connected to the respective second pads 2021 on the Flash die 202b by other first connection lines and form address lines ADDR. b [B:0] of (B+1) bits, data lines DATA b [C:0] of (C+1) bits and memory control signal lines RWCTL b [y:0] of (y+1) bits, where A, B, C, D, x and y are all integers greater than 1.

[0069] One of the flash dies 202a, 202b is used to support the online operation of the MCU chip 201, and the other is used for upgrading the MCU chip 201. That is, the flash dies 202a, 202b contain separate, corresponding memory arrays. One of the flash dies 202a, 202b is used to store code required for upgrading the MCU chip, and the other is used to store code required for operating the MCU chip, as well as data generated during the operation of the MCU chip.

[0070] For further structural details of the MCU die 201 and the two flash dies 202a, 202b, please refer to the above description in conjunction with the Fig. Reference is made to Figures 3 to 8; and they can be packaged in a single package using the same advanced packaging techniques as in the first embodiment and therefore do not need to be described further here.

[0071] It is understood that the system architecture of the MCU chip of this embodiment actually consists of the MCU die and the two flash dies, both of which are located outside the MCU die and connected to it. Therefore, the number of additional first pads 2011 on the MCU die 201 can be greater than or equal to the total number of additional second pads 2021 on the flash dies 202a and 202b.

[0072] In contrast to the MCU chip of the first embodiment, the MCU chip of this embodiment has two flash dies, each of which performs parallel multi-bit communication with a corresponding set of first pads 2011 on the MCU die without protocol conversion. Therefore, a multi-flash-die operating mode is supported.

[0073] It is understood that the present invention is not limited to use in applications with externally attached flash die(s) 202. Instead, in MCU chip architectures according to the present invention, for example, SRAM, sensors, power management units (PMUs), and radio frequency (RF) circuits can also be packaged together with MCU dies in individual packages using advanced packaging techniques. In particular, the flash die(s) 202 in the embodiment of Fig. 2 or Fig. 13 each can be replaced by an SRAM die, a sensor die, a PMU die or an RF circuit die.

[0074] The foregoing description merely presents some preferred embodiments of the present invention and does not in any way limit its scope. All changes and modifications made by a person skilled in the art based on the above teachings fall within the scope defined in the appended claims.

Claims

[1] Chip (100) of a microcontroller unit (MCU) which has an MCU die (101, 201) wherein the MCU die (101, 201) contains an internal memory control logic circuit (101a, 201a) and is provided with a number of external first pads (2011) on a first side; at least one flash die (102, 202), wherein the flash die (102, 202) contains an internal memory array and is provided with a number of external second pads (2021) on a second side; and a number of first connecting lines (203) which connect the second pads (2021) to the corresponding first pads (2011) and thereby form multi-bit address lines (ADDR, ADDR a , ADDR b ), Multi-bit data lines (DATA, DATA a , DATA b ) and multi-bit memory control signal lines (RWCTL, RWCTL a , RWCTL b) form, wherein the MCU die (101,201), the at least one flash die (102,202) and the number of first interconnect lines (203) are packaged in a single package using an advanced packaging technique. [2] MCU chip (100) according to claim 1, wherein the MCU die (101, 201) and the flash die (102, 202) are arranged side by side, wherein the first pads (2011) are arranged on the first side of the MCU die (101, 201) proximal to the flash die (102, 202), and wherein the second pads (2021) are arranged on the second side of the flash die (102, 202) proximal to the MCU die (101, 201). [3] MCU chip (100) according to claim 1, wherein the top surfaces of the MCU die (101, 201) and the flash die (102, 202) provide a fan-out area of ​​an intermediate packaging of a packaging. [4] MCU chip (100) according to claim 3, wherein the packaging further comprises an internal redistribution layer formed on the fan-out area, wherein a first part of the redistribution layer serves as the first interconnect lines (203). [5] MCU chip (100) according to claim 4, wherein at least one of the MCU die (101,201) and the flash die (102,202) is further provided with a number of third pads (2012,2012A,2022) thereon, wherein a second part of the redistribution layer serves as second interconnect lines (204,2041) which are electrically connected to the third pads (2012,2012A,2022), and wherein a top surface of a part of the second interconnect line (204,2041) is exposed to form an external contact pad (204a). [6] MCU chip (100) according to claim 5, wherein the redistribution layer comprises a redistribution layer, wherein a first part of the redistribution layer serves as the first interconnecting lines (203) and a second part of the redistribution layer serves as the second interconnecting lines (204, 2041). [7] MCU chip (100) according to claim 5, wherein the redistribution layer comprises a first redistribution layer and a second redistribution layer formed one above the other over the fan-out area from bottom to top, wherein a first part of the first redistribution layer serves as first interconnection lines (203) and a second part of the first redistribution layer and a part of the second redistribution layer serve as second interconnection lines (204, 2041) which are electrically connected to the third pads (2012, 2012A, 2022). [8] MCU chip (100) according to claim 5, wherein solder balls (211) are formed on the external contact pads (204a). [9] MCU chip (100) according to claim 5, wherein conductive pads (209) are formed on the top surfaces of the external contact pads (204a), wherein the conductive pads (209) are distributed along a circumference of the packaging and wherein an upper or side surface of each conductive pad (209) is exposed outside the packaging. [10] MCU chip (100) according to claim 5, wherein an area of ​​each of the first and second pads (2011,2021) is smaller than an area of ​​the third pad (2012,2012A,2022). [11] MCU chip (100) according to any one of claims 1 to 10, wherein the area and dimension of each of the first and second pads (2011, 2021) conforms to a minimum specification that is achievable by a connection process of the first connecting line (203). [12] MCU chip (100) according to claim 3, wherein the packaging further comprises a semiconductor substrate (200), wherein both the MCU die (101, 201) and the flash die (102, 202) are mounted in a trench (200a) in the semiconductor substrate (200), wherein the top surfaces of the MCU die (101, 201), the flash die (102, 202) and the semiconductor substrate (200) form the fan-out area, wherein the MCU die (101, 201) and the flash die (102, 202) are bonded to a bottom of a single trench (200a) or to bottoms of different trenches (200a) by an adhesive layer (205), and wherein gaps resulting from the mounting of the MCU die (101, 201) and the flash die (102, 202) in the trench (200a) remain, are filled with a dielectric material (206). [13] MCU chip (100) according to claim 1, comprising two flash dies (202a, 202b), wherein one of the two flash dies (202a, 202b) is used to support the online operation of the MCU chip (100), and the other flash die (202a, 202b) is used for upgrading the MCU chip (100). [14] MCU chip (100) according to one of claims 1 to 10 or 12 to 13, wherein a number of the first connecting lines (203) which are configured as multi-bit address lines (ADDR, ADDR a , ADDR b ) serve, (A+1) is, and where a corresponding maximum physically addressable space in the memory array [0, 2 A+1 -1] is. [15] MCU chip (100) according to one of claims 1 to 10 or 12 to 13, wherein the first connecting lines (203) are configured as multi-bit memory control signal lines (RWCTL, RWCTL) a , RWCTL b) are designed to transmit control signals generated by the storage control logic circuit (101a, 201a) on the basis of appropriate read, write and erase commands, and wherein a number of the first connecting lines (203), which are configured as multi-bit data lines (DATA, DATA a , DATA b ) serve, (D+1) is, which corresponds to a bit width of the memory array for reading and writing data.

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