METHOD FOR DIVISION OF SIMULATION MODELS BETWEEN A PROCESSOR AND AN FPGA

Description

[0001] The invention relates to a method for dividing simulation models that are executed jointly on a processor and a programmable logic device.

[0002] Such simulation models are used, for example, in hardware-in-the-loop simulation, in which control units, especially those for motor vehicles, are tested for correct functioning. For this purpose, the control unit to be tested is connected to an electronic circuit, also known as an I / O circuit, with input and / or output channels in order to apply signals to the control unit via the circuit and / or to record signals generated by it.

[0003] The signals to be output by the I / O circuit are determined by running the software model of a test environment on a simulation environment. In the case of a motor vehicle, for example, this would be a simulation of a journey. Simulated events are applied to the output channels (e.g., the pins or registers of the circuit's output channels) by electrical signals representing the events, for transmission to the control unit. Signals are applied from the control unit to the input channels (e.g., the pins or registers of the circuit's input channels) for detection and processing in the simulation environment. In this way, a control unit can operate in a simulated environment as if it were actually operating in the real environment.

[0004] The simulation environment, or simulator for short, is formed, for example, by a real-time computer system with at least one processor that executes the software model. For example, the model can be provided by real-time capable software or a plurality of interacting software tools, which preferably have a graphical user interface and are particularly preferably programmed using software objects. The software can include MATLAB, Simulink, or even RTI (Real-Time Interface) from the applicant, which, for example, forms a link to Simulink.

[0005] In the aforementioned cases, software objects are programmed graphically as blocks, especially hierarchically. However, a simulation environment is not limited to the use of the software mentioned as examples. The software model can be executed in the simulation environment either directly after programming or after code generation and compilation.

[0006] In addition to the processor circuit, which comprises the at least one processor, the simulation environment often comprises at least one I / O circuit connected to the processor circuit, which has the aforementioned input / output channels. They serve to output electrical signals at the pins of the output channels and / or to detect electrical signals present at the pins of the input channels, e.g. by means of an analog / digital conversion, in order to feed the detected signals for further processing, be it on the aforementioned electronic circuit or on further electronics connected to the circuit. It can also be provided that at least one such I / O circuit, which comprises input and / or output channels, is connected to a circuit comprising a programmable logic component, in particular a Field Programmable Gate Array (FPGA), in order to receive signals from it or provide signals to it.The FPGA circuit, in turn, can be connected to the processor circuit so that the simulation model can be executed partly on the FPGA circuit and partly on the processor circuit.

[0007] A real-time computer system differs from commercially available computer systems in that a specified latency is not exceeded, for example, between the input of a changed sensor signal and the resulting response, such as the output of a changed control signal. Depending on the system to be simulated, a maximum latency of, for example, 1 millisecond or less may be required. In particular, a simulation of the drive of an electric vehicle (E-Drive) or a simulation of power electronics places high demands on the speed of the control loop, especially with maximum permissible latencies in the microsecond range. Therefore, real-time simulations are often no longer covered by pure processor models and processor-controlled I / O channels, but the time-critical model components are executed on a freely programmable FPGA circuit.Preferably, the FPGA circuit is designed so that various I / O circuits can be connected to it in a modular manner.

[0008] Real-time computer systems with heterogeneous computing units such as one or more processors and one or more programmable logic components are therefore used, particularly for complex real-time simulations in the areas of e-mobility, ADAS, or power electronics. Previously, users had to manually define and model which model component they wanted to execute in which domain (processor, FPGA). EP 1971944 B1 already describes the automatic outsourcing of submodels to another domain, but this approach only pursues an exploratory trial-and-error approach, which iterates until a specific performance criterion, such as a specified time response, is met.

[0009] Manual identification and shifting of the model boundary between processor and FPGA components is currently required in the following typical use cases, where model components need to be (re)distributed to different domains: Splitting the model during design, evolving FPGA models that exceed the resources of the FPGA in use, migrating a project to another FPGA platform with more / fewer resources, distributing large FPGA applications across multiple FPGAs.

[0010] US 7 509 244 B1 discloses a method for dividing a graphical simulation model, in which the time required for compiling the simulation model is reduced by distributed processing of different model parts.

[0011] Against this background, the object of the invention is to provide a method and a device which further develop the prior art and preferably enable an automatic or computer-assisted division of simulation models into processor and FPGA parts.

[0012] The task is solved by a method for dividing a graphical simulation model into a first submodel and a second submodel with the

[0013] Features of claim 1 and a computer system with the features of claim 14. Advantageous embodiments of the invention are the subject of dependent subclaims.

[0014] A method is thus provided for dividing a graphical simulation model into a first submodel and a second submodel, wherein the functionality of the simulation model is modeled in the form of blocks that are at least partially connected by signals, wherein the blocks are executed periodically and each block of the simulation model is assigned a sampling time, wherein the first submodel is intended to be executed on a first computing unit, in particular a processor, and the second submodel is intended to be executed on a second computing unit, a programmable logic device. The method comprises the following successive steps: a. Identifying at least one first block as belonging to the first submodel and at least one second block as belonging to the second submodel, wherein the membership is determined based on the sampling time and / or a resource allocation, b. Searching for cyclic groups of blocks, wherein a cyclic group comprises two or more blocks that are connected via at least one signal, wherein a first block of the cyclic group outputs a signal to a second block in the group and at least indirectly receives an output signal from the second block, wherein a cyclic group whose blocks all have the same sampling time is regarded as atomic, c. Identifying non-cyclic groups of blocks, d. Assigning the individual blocks from the groups to the first submodel or the second submodel, wherein all blocks of an atomic cyclic group are assigned to the same submodel, e.Generating code for the first computing unit, in particular program code, from the first submodel, and f. Generating code for the second computing unit, from a configuration bit stream, from the second submodel.

[0015] A cyclic group comprises two or more blocks connected via at least one signal, with a first block of the cyclic group outputting a signal to a second block in the group and at least indirectly receiving an output signal from the second block. If the cyclic group comprises three or more blocks, the output signal of the second block can initially be the input signal of a third block, and the output signal of the third block can be connected to the first block; thus, the first block does not receive the output signal of the second block directly, but an intermediate operation takes place in the third block. In larger cyclic groups, additional blocks can be interposed accordingly.

[0016] In a non-cyclic group of blocks, there is no feedback between the blocks, where an output signal from a block downstream in the signal flow is connected back to the first block in the signal flow.

[0017] The sampling time can be explicitly assigned to the blocks or result from inheritance or propagation. For example, the simulation model can be hierarchical, with several subordinate blocks implementing the functionality of a parent block, and a sampling time of the parent block being adopted for all subordinate blocks. For a block that models access to a hardware interface, such as an I / O port, the sampling time can be determined by hardware properties. For several blocks connected by a signal line, it can also be provided that a sampling time of one of the blocks is propagated or adopted for all blocks connected by signals.

[0018] The invention provides a deterministic, rule-based method that, through transformation and analysis of an overall model, proposes the boundary between the processor and FPGA portions for all signal paths at a suitable location and / or provides suggestions for shifting an existing boundary. For this purpose, the model is divided into partitions suitable for execution either on the FPGA or on the processor or FPGA.

[0019] Preferably, the proposed boundaries can be shifted by the modeler in a model view, which indicates the partitions, for example, by coloring, toward the FPGA or processor. The invention has the advantage of being suitable for cycle-accurate, i.e., clock-accurate modeling, which can be used to implement sophisticated control loops, for example, in the field of electric drives.

[0020] The method according to the invention is, in principle, applicable to various types of computing units such as CPUs, GPUs, and FPGAs. Furthermore, it can also be used for a larger number of submodels.

[0021] For hierarchically designed simulation models, in which the simulation model comprises at least one block in a first hierarchy level and at least one block in a second hierarchy level, it is preferable to combine the blocks of the simulation model into a common hierarchy level before proceeding with the next steps. This simplifies and accelerates the division of the model.

[0022] If the simulation model contains input ports, output ports, and / or buses, the step of merging the blocks of the simulation model into a common hierarchy level preferably comprises removing at least some of the input ports, output ports, and / or buses and inserting corresponding signals. Input ports and output ports primarily refer to intra-model communication blocks that connect different areas or hierarchy levels of the model. A pair of Goto and From blocks, which specifies a data connection between two blocks or model parts, can also be expediently treated as a pair of input and output ports and removed or replaced with a signal line. I / O ports that are permanently assigned to a hardware resource, such as an I / O pin of an FPGA or a converter component of an I / O board, remain in the model.

[0023] Preferably, a block is identified as belonging to the second submodel if one or more of the following conditions is / are met: I. the block is assigned a sampling time that is below a predefined sampling threshold; II. the block is assigned a latency that is below a predefined latency threshold; III. the block is assigned a resource of the programmable logic device, such as, in particular, an I / O pin of the programmable logic device.

[0024] Blocks with particularly stringent timing requirements, such as frequent sampling and / or short latency, are conveniently assigned to the second submodel, which is executed on the programmable logic device or FPGA. For blocks with direct hardware access, the model assignment follows the corresponding hardware unit directly.

[0025] Preferably, a block is identified as belonging to the first submodel if one or more of the following conditions is / are met: I. The block describes a function call, in particular a function of the operating system and / or access to a network interface; II. A processor resource is assigned to the block, such as in particular a processor register.

[0026] Blocks that model a software interface or address a hardware resource of the processor are conveniently assigned to the first submodel.

[0027] It is advantageous if the step of searching for cyclic groups includes a recursive subdivision, where, for a found cyclic group, it is checked whether all blocks have the same sampling time. In this case, the cyclic group is considered atomic and retained. Otherwise, the cyclic group between blocks with different sampling times is subdivided into new cyclic or non-cyclic subgroups until no more subdivisible cyclic groups remain. A counter can also preferably be treated as a cyclic group consisting of an adder and a register. An atomic cyclic group is expediently assigned only as a whole to the first or second submodel.

[0028] According to a preferred embodiment of the invention, the step of assigning the individual blocks from the groups to the first submodel or the second submodel is carried out based on a predefined rule. A rule set consisting of several nested conditions can also be specified. By processing rules that check one or more conditions, the assignment of the blocks can be carried out quickly and reproducibly.

[0029] According to the rule, it is particularly preferable to assign all blocks that do not need to be executed on the programmable logic device to the first submodel. This ensures that only the most time-critical blocks are executed on the FPGA, thus preserving the often scarce resources of the programmable logic device.

[0030] In particular, it can be provided that a block must be or is executed on the programmable logic component even if it is connected via a signal to a block identified as belonging to the second submodel, and the signal has a higher bit width than a width threshold and / or a higher change frequency than a change threshold and / or the signal has a shorter latency than a signal latency threshold. The bandwidth can also be viewed as the product of signal width and change frequency, with a block being executed on the FPGA if the bandwidth exceeds a predetermined bandwidth threshold. It can be provided that several signals are viewed as one signal with a cumulative or added bit width. If a large amount of data has to be transferred between two blocks, this data is expediently arranged on the same computing unit, in particular the programmable logic component.If the signal transmission between two blocks must only take place with low latency, it is advantageous to execute or implement these blocks on the programmable logic device.

[0031] Preferably, after the step of assigning the individual blocks from the groups to the first submodel or the second submodel, a graphical representation of the split model is displayed via a user interface. Changes to the split are conveniently received via the user interface.

[0032] Particularly preferably, blocks that can be assigned to both the first submodel and the second submodel are identified using an additional rule, with these blocks being highlighted on the user interface. These blocks are assigned based on user input. In particular, according to the additional rule, the absence of a resource assignment can identify a block that can be assigned arbitrarily. For example, a user can use a slider to specify a portion of the model that is executed on the programmable logic component; alternatively or additionally, it can also be provided that desired limits can be inserted into the graphical representation of the model. In particular, desired limits can be received via a mouse movement.The boundaries defined by the user are conveniently stored in the model properties or in a dedicated block within the model, in particular by storing a modified assignment as a block parameter. Alternatively, the boundaries defined by the user can be stored in a separate file or a database. This allows for the parallel existence of several different partitionings, whereby, in particular, an active partitioning can be preset.

[0033] Preferably, after the step of assigning the individual blocks from the groups to the first submodel or the second submodel, an additional step of inserting communication blocks takes place, wherein for two blocks connected by a signal, it is checked whether these are assigned to different submodels, and in this case, a pair of communication blocks is inserted which implement a data exchange between the processor and the programmable logic module.

[0034] In a preferred embodiment of the invention, the method comprises the further steps g. Transferring the program code and the configuration bit stream to a real-time computer system comprising a processor and a programmable logic device, and h. Performing a simulation, wherein the processor executes the program code and the functionality of the programmable logic device is determined by the configuration bit stream.

[0035] The application generated from a simulation model divided according to the invention, comprising program code for a processor and configuration for a programmable logic device, can be executed directly. A real-time computer operated with the corresponding program code or configuration bit stream can perform a simulation or generally provide any functionality specified in the simulation model.

[0036] The invention further relates to a computer system comprising a control computer with a user interface and a real-time computer with a processor, a programmable logic module, and I / O circuits. Instructions for carrying out a method according to the invention are stored in a non-volatile memory of the computer system.

[0037] Furthermore, the invention relates to a non-volatile data carrier with a computer-readable storage medium on which instructions are embedded which, when executed by a processor, cause the processor to be configured to carry out a method according to the invention. A control computer of a real-time computer system often has a modeling environment and is thus particularly well suited for implementing a model division according to the invention. Furthermore, program code or an FPGA configuration can be created automatically and executed on the real-time computer system, resulting in a high level of user convenience.

[0038] The invention is explained in more detail below with reference to the drawings. Similar parts are labeled with identical designations. The illustrated embodiments are highly schematic, meaning that the distances and the lateral and vertical dimensions are not to scale and, unless otherwise stated, do not have any deducible geometric relationships to one another.

[0039] It shows: Figure 1 shows a schematic view of an exemplary hardware-in-the-loop test environment, Figure 2 shows a schematic view of a simulator that executes a first submodel on a processor and a second submodel on an FPGA, Figure 3 shows a hierarchical simulation model, Figure 4 shows a simulation model merged into one level, Figure 5 shows a schematic flow chart of a method according to the invention, Figure 6 shows a schematic representation of a model with two fixed points and an atomic cyclic group, Figure 7 shows a schematic representation of a divisible cyclic group that includes an atomic cyclic group with a fast sampling rate and a non-cyclic group with a slow sampling rate, Figure 8 shows a schematic representation of a model with several cyclic and non-cyclic groups, Figure 9 shows a schematic representation for fine-tuning, orthe definition of the boundary within the non-cyclic model components, whereby several possible boundaries are indicated as examples, Figure 10a shows a schematic representation of a simple model with one boundary, Figure 10b shows a schematic representation of the simple model in which further boundaries were inserted in the signal path by shifting the boundary, and Figure 10c shows a schematic representation of the simple model in which the shifted boundary was retained but the number of further boundaries was reduced.

[0040] In Figure 1 A schematic representation of an exemplary hardware-in-the-loop test environment with a PC, an ES simulator, and a DUT under test is shown. The PC can be configured as a standard personal computer with a screen, input devices, and one or more network interfaces.

[0041] The real-time capable simulator ES comprises a computing node CN, which is connected to the operating computer PC via a network interface NET. The computing node CN has at least one processor CPU, in particular a multi-core processor, a RAM, and a non-volatile memory NVM, on which an operating system and / or a bootloader are preferably stored. A logic board with a programmable logic component FPGA, two I / O circuits ADC, DAC, and an error simulation circuit FIU are connected to the computing node via a high-speed bus SBC or a corresponding controller. The programmable logic component FPGA is preferably freely programmable and can be configured according to the present invention. It can also be provided that the simulator ES has multiple logic boards or multiple programmable logic components FPGA on one logic board.The logic board preferably has one or more slots for I / O modules. An I / O module (IOM) is shown, which is connected to the control unit (DUT) under test and can, for example, exchange digital input and output signals with it. The I / O circuit (ADC) has one or more analog-to-digital converters that receive analog signals from the control unit (DUT) under test. The simulator (ES) can output analog signals to the control unit (DUT) under test via the I / O circuit (DAC), which has one or more digital-to-analog converters. The fault simulation circuit (FIU) can apply defined electrical faults to connected devices, such as a short circuit between two channels.

[0042] Freely programmable logic components (FPGAs) are used primarily in applications such as electric drives and power electronics, where particularly fast control loops are required. Logic boards with such FPGAs conveniently feature multiple slots for I / O modules; for example, dSPACE offers the DS6601 FPGA Base Board with five slots that can be equipped with various I / O modules. An existing test environment can be expanded by installing a new I / O module, for example, to include high-resolution analog-to-digital conversion.

[0043] Figure 2shows a schematic view of a simulator that executes a first submodel on a processor and a second submodel on an FPGA. A first submodel RTA is stored on the compute node CN, which is executed as a real-time application by the processor of the compute node. The programmable logic component FPGA#1 is configured such that a second submodel CNF is implemented on one part of the area and a control module CTL is implemented on another part of the area. The control module CTL is connected via component IOF to an I / O module IOM, which has analog-to-digital converters ADC#1, ADC#n and digital-to-analog converters DAC#1 and DAC #n. The compute node and the programmable logic component are connected via the high-speed bus SBC. The programmable logic component FPGA#1 is connected to a second programmable logic component FPGA#n via an inter-FPGA bus.

[0044] The method according to the invention can optionally also be used for dividing the system into multiple submodels, such as a third submodel implemented on the second programmable logic device FPGA#n. In addition to processors and programmable logic devices, other components of a heterogeneous computing system can be supported, such as GPUs or AI cores. The steps would be analogous, with only the assignment of the individual blocks to the submodels being based on a respective set of rules adapted to the different architectures.

[0045] In principle, the method according to the invention can be extended with a correspondingly adapted set of rules to the boundary between any domains such as programmable logic module - programmable logic module, programmable logic module - graphics card or GPU, processor and processor / microcontroller, processor and graphics card or GPU, first graphics card and second graphics card, or even more than 2 domains per model.

[0046] In Figure 3 A hierarchical simulation model is shown schematically. Several blocks B1, B2, B3, B4, and B5 are arranged at a first hierarchy level E1. These blocks implement the model's functionality and are connected by signals. Block B4 is a subsystem whose functionality is implemented by subordinate blocks at a second hierarchy level. The second hierarchy level E2 includes input port P11, blocks B21, B22, B23, and output port P22.

[0047] Figure 4shows the simulation model after merging the blocks into a common hierarchy level. Blocks B1, B2, B3, and B5 are still present. Subsystem B4 has been replaced by the subordinate blocks B21, B22, and B23. Input port P11 and output port P22, which served for intra-model communication and were not connected to a hardware resource, have been removed and replaced with direct signal connections to blocks B2 and B3.

[0048] In Figure 5 a schematic flow chart of a method according to a preferred embodiment of the invention is shown.

[0049] The starting point of a method according to the invention is expediently an overall model with sampling times, i.e., an overall model in which each block is assigned a sampling time either explicitly or implicitly (e.g., via default settings or inheritance). A sampling time is understood, in particular, to be the time after which the block is executed again, or after which the block reads its input signals again and / or a new output value of the block is available. Furthermore, it is expediently assumed that blocks are atomic, meaning that the resulting partitioning cannot run through blocks, but only between the blocks. The method preferably proceeds in the following steps:

[0050] In step S1 (Remove Hierarchy) - as in Figures 3 and 4As shown, the blocks of a hierarchical model are merged into a common hierarchy level. Analyzing a hierarchically structured Simulink model with data buses would be complex and time-consuming; therefore, in the preparatory step, structural elements such as subsystems and buses are expediently removed or replaced with individual signals. This enables a high-performance graph-based analysis in which all in / out ports of a node and their origins are directly known and connected to their origin and destination by an edge. This step is optional and can be performed using conventional methods. For example, the Vivado development environment from Xilinx offers such a method for netlist optimization under "flatten_hierarchy."

[0051] In step S2 (Identify fixed blocks), at least one first block is identified as belonging to the first submodel and at least one second block as belonging to the second submodel. Constraints resulting from the architecture mean that some blocks must be implemented on the FPGA, and some must be implemented on the processor. The assignment (processor or FPGA) of these blocks is therefore already fixed in advance, which is why these fixed points are identified in a first step. For example, blocks with low latency must be implemented on the FPGA, while blocks that contain complex interactions with the operating system (e.g., network protocols) must be executed on the processor. In addition, blocks whose sampling time is below a given threshold are assigned to the FPGA. Special I / O blocks are usually clearly assigned to a domain.

[0052] In step S3 (search for cyclic groups), groups of blocks are searched for whose output values ​​are cyclically dependent on each other. If the model contains such cyclic groups or cycles, these cycles are assigned to one of two classes. Cycles in which all nodes have the same sample time are considered atomic and are not further partitioned. This means that they are implemented entirely on the FPGA or entirely on the processor and can only be moved across a hardware / software boundary as a whole. I / O blocks are conveniently not considered part of a cycle. Figure 6 shows a schematic representation of a model with two fixed points and an atomic cyclic group in which all blocks have the same sampling time.

[0053] In step S4 (Is the group divisible?), a check is made to determine whether the cyclic group can be further subdivided. If the nodes of the cycle have different sampling times, they are considered non-atomic and can be further subdivided. This occurs in step S5 (Divide cyclic group). The subdivision occurs at the transitions between parts with different sampling times. This creates new non-cyclic and cyclic sub-regions, which are then recursively processed according to the present method. This recursion is indicated here by a repeated execution of step S3. Figure 7 shows a schematic representation of a divisible cyclic group that has a part with fast sampling time or high sampling rate and a part with slow sampling time or low sampling rate and can thus be divided into two parts, an atomic cyclic group and a non-cyclic group.

[0054] In step S6 (Identify Groups), non-cyclic groups of blocks are identified. In this step, all non-cyclic (feedforward) parts of the model are identified. These are generally located before (fan-in) or after (fan-out) the fixed points and the cycles. These model parts contain the possible partition boundaries between the FPGA and the processor, meaning that the boundary between the first and second submodels between the blocks of a non-cyclic group can be freely chosen.

[0055] In step S7 (Assign Blocks), the individual blocks in non-cyclic groups, or all blocks in a cyclic group, are assigned to the first submodel or the second submodel. After identifying the fixed points, cycles, and non-cyclic dependencies, the overall model can be divided according to a predefined set of rules.

[0056] The rules for deciding where a given model component should be implemented can be determined by considering the performance of the overall model, available resources, communication costs, and sampling times. The underlying parameters can be selected based on user input; they can also be specified using a heuristic or measured through design-space exploration.

[0057] It is useful to first decide for each atomic cycle where it should be implemented. Figure 8shows a schematic representation of the assignment of the cyclic groups of an example simulation model to the first submodel or the second submodel; the upper cyclic group (white filled circles) is assigned to the first submodel and executed on the processor, the lower cyclic group (black filled circles) is assigned to the second submodel and executed on the FPGA.

[0058] After the cycles have been assigned, the hardware-software boundary between the blocks in non-cyclic groups is preferably fine-tuned. This boundary can now be shifted toward the FPGA or processor within the non-cyclic portions. The same criteria can be applied to the assignment of blocks in non-cyclic groups as for the assignment of cycles. The key difference is that the boundary can be shifted block by block, which corresponds to a finer granularity. Optionally, cycles from a slower domain can also be shifted to faster ones (e.g., processor to FPGA) if their assignment was determined solely by the sampling time. Figure 9 shows a schematic representation of the fine-tuning or setting of the limit within the non-cyclic model components, with five possible limits indicated as examples.

[0059] A method according to the invention can be used to partition an as yet unsplit overall model into processor and FPGA components, or to re-subdivide an existing overall model already subdivided into processor and FPGA components. The following steps are preferably performed: 1. Partitioning 2. Automatic proposal of boundaries between processor and FPGA 3. Interactive shifting of the boundary

[0060] The method according to the invention is preferably used in conjunction with a transformation tool such as the HDL Coder from MathWorks or the Xilinx System Generator. Model blocks or entire subsystems can then be easily used in both the processor and FPGA models by using these tools to generate source code for a processor or HDL code for an FPGA for each block.

[0061] Automatically suggesting boundaries between processor and FPGA is useful for partitioning an entire model that doesn't yet have a fixed block assignment and consists only of processor or FPGA components, or for repartitioning an entire model with already defined partitions for processor and FPGA. By ignoring any existing block assignment to a domain, both cases can be treated equally.

[0062] According to a preferred embodiment of the invention, the model components are divided into domains based on the following two rules: Rule 1: Model components that do not need to run on the FPGA are offloaded to the processor. Rule 2 must be observed here. Rule 2: Since data transfer often offsets the time savings when offloading calculations to a possibly faster computing device, data transfer must be minimized. Therefore, the minimum possible cut in the data width of the model graph, taking Rule 1 into account, is set as the limit. This minimizes the data transfer time.

[0063] Additionally or alternatively, criteria such as a processor model's task turnaround time, a maximum number of available logic resources such as flip-flops, LUTs, DSPs, RAM, AI cores of an FPGA model, or a specified clock speed of the programmable logic component can be considered. These values ​​can be determined based on a synthesis of the entire model, even if the model as a whole would be far too large for the FPGA. In this synthesis, a "virtual" netlist is conveniently generated from which the resources of the individual model blocks / subsystems and the approximately achievable clock speed are determined and used as a basis for defining the model limits. The steps of placement and routing to a specific FPGA, which follow in a regular build for a programmable logic component, are preferably omitted.

[0064] After the automatic subdivision of a model, an interactive shift of the boundary between processor and FPGA can preferably be performed.

[0065] Starting from a model divided into partitions for the FPGA and partitions for the processor, the different partitions are preferably highlighted graphically in the model or displayed in a graphical user interface. In addition, all currently existing or proposed model boundaries are preferably drawn into the model. Alternatively or additionally, these partitions and the boundaries can also be displayed in a graph of the model created using the method according to the invention. The currently drawn boundary can also run within a partition, instead of between two partition boundaries, as discussed further below. It is important that an FPGA model is usually not represented by a single connected graph, but rather by several island graphs.This is because an FPGA often implements multiple, independent functionalities that do not communicate with each other. Instead, they provide a fixed functionality connected only via I / O pins, or each communicates only with its processor component. Therefore, there is usually not just one boundary between the processor and the FPGA, but one for each island graph, i.e., for completely independent functionalities.

[0066] The user now preferably has the option of interactively moving a boundary in the model or graph, for example, by clicking on it with a slider or directly moving it in the model or graph, closer to the processor or FPGA. Additionally, the granularity of the model representation can be reduced by grouping parts that can only be moved as a whole (such as atomic cyclic groups) into individual subsystems / nodes.

[0067] One or more of the following information is preferably updated interactively: Interface width between processor and FPGA in bits and communication duration for transmitting these bits at a specified maximum data rate (e.g., 2.5 Gbit / s). This allows the user to see by how much their minimum achievable task period will change due to communication. In one embodiment, the changes in the corresponding values ​​compared to the existing / suggested limits can also be displayed. Required logic resources in the FPGA. These resources of the individual model blocks / subsystems and the approximately achievable clock speed can be determined based on a synthesis of the overall model, which is preferably aborted after creating an unimplemented netlist. This makes it possible to determine in advance whether an appropriately partitioned model can be executed on the real-time computer system.

[0068] The significance of partitions for shifting boundaries is discussed below. The partition view with defined boundaries provides the user with a wealth of information at a glance, making it immediately clear whether a boundary already lies on a partition boundary or within a partition. If the boundary lies within a partition suitable for the processor or FPGA, it can easily be shifted in one direction of the two partition boundaries toward the processor or FPGA, potentially changing the data communication interface widths.

[0069] Figure 10ashows a schematic representation of a simple model with a boundary. On the left is a block to be executed on the FPGA (FPGA fixed point), and on the right is a block to be executed on the processor (processor fixed point). In between are several blocks, each connected by a signal line. Blocks to be executed on the FPGA are shown in black, blocks to be executed on the processor are shown in white, and blocks that can be arranged flexibly are shown in gray. With the partitioning shown, the user can enlarge their FPGA portion (the second submodel) by moving the boundary to the right. Then, apart from the processor fixed point shown, a pure FPGA model is available.

[0070] Based on the Figure 10aAlternatively, the user can increase the processor portion of the model and, if necessary, even shift the boundary across multiple partitions. With such a left-shifted boundary, a block to be executed on the FPGA would initially be located behind the boundary of the processor model (the right-hand black circle). If the user leaves the block to be executed on the FPGA and the boundary unchanged, in a preferred embodiment of the invention, additional boundaries are automatically inserted along the signal path. Figure 10bshows a schematic representation of the simple model, in which additional boundaries were automatically inserted into the signal path. These boundaries require communication between the processor and the FPGA, thus increasing the communication overhead. This communication may be blocking. Blocking communication specifically means that further calculations can only be performed after the data transfer between the processor and the FPGA has been completed.

[0071] If the user adapts his modeling in the FPGA partition or the corresponding block assigned to the FPGA (right black circle) and enables an assignment of this block to the processor partition, the communication overhead is reduced. Figure 10cshows a schematic representation of the simple model in which the shifted boundary was retained, but the number of additional boundaries was reduced by changing the setting of the middle block. The graphical representation of the model's division in a partition view makes it easier for the user to see that a modified modeling leads to a reduced number of boundaries, or transitions, between the processor and the FPGA. Due to the reduced communication overhead, the modified modeling can result in faster execution of the overall model.

[0072] Alternative embodiments of the invention also allow the definition of a larger number of boundaries, in particular two each, between the processor and the FPGA portion. By defining suitable rules, additional portions can be defined at the boundary between the FPGA and the processor, whose execution can be flexibly specified. For example, if not just one dividing line but two are defined for each input and output boundary between the model portions in the overall model or in the model graph of the overall model, one has a zone between each model portion. The blocks in the intermediate zones can then, for example, be executed on the processor, while the rest of the model is implemented on the FPGA.

[0073] The invention enables automatic or computer-assisted decomposition of models for execution on heterogeneous simulators, which can significantly reduce the time required to design a simulation.

Claims

1. A method for dividing a graphical simulation model into a first submodel and a second submodel, the functionality of the simulation model being modeled in the form of blocks at least partially connected by signals, the blocks being executed periodically and a sampling time being associated with each block of the simulation model, the first submodel being intended to be executed on a first computing unit, in particular a processor, and the second submodel being intended to be executed on a second computing unit, a programmable logic device, the method comprising the sequential steps: a. identifying at least one first block as associated with the first submodel and at least one second block as associated with the second submodel, the association being determined on the basis of the sampling time and / or a resource allocation, b. searching for cyclic groups of blocks, a cyclic group comprising two or more blocks connected by means of at least one signal, a first block of the cyclic group outputting a signal to a second block in the group and receiving an output signal of the second block at least indirectly, a cyclic group comprising blocks all having the same sampling time being considered atomic, c. identifying non-cyclic groups of blocks, d. associating the individual blocks from the groups to the first submodel or the second submodel, all blocks of an atomic cyclic group being associated with the same submodel, e. generating code for the first computing unit, in particular program code, from the first submodel, and f. generating code for the second computing unit, a configuration bitstream, from the second submodel.

2. The method according to claim 1, characterized in that the simulation model comprises at least one block in a first hierarchy level and at least one block in a second hierarchy level, and in that merging of the blocks of the simulation model into a common hierarchy level takes place prior to the further steps.

3. The method according to claim 2, characterized in that the simulation model comprises input ports, output ports, and / or buses, and in that the step of merging the blocks of the simulation model in a common hierarchy level comprises removing at least some of the input ports, output ports, and / or buses and inserting corresponding signals.

4. The method according to any one of the preceding claims, characterized in that a block is identified as being associated with the second submodel if one or more of the following conditions is / are fulfilled: I. the block is associated with a sampling time below a specified sampling threshold; II. the block is associated with a latency below a specified latency threshold; III. a resource of the FPGA is associated with the block, such as in particular an I / O pin of the FPGA.

5. The method according to any one of the preceding claims, characterized in that a block is identified as being associated with the first submodel if one or more of the following conditions is / are fulfilled: I. the block describes a function call, in particular a function of the operating system and / or access to a network interface; II. the block is associated with a resource of the processor, such as in particular a register of the processor.

6. The method according to any one of the preceding claims, characterized in that the step of searching cyclic groups comprises recursively subdividing, wherein a found cyclic group is checked as to whether all blocks have the same sampling time, wherein if so, the cyclic group is regarded as atomic and retained, and otherwise the cyclic group is divided by blocks having different sampling times into new cyclic or non-cyclic subgroups until there are no more divisible cyclic groups.

7. The method according to any one of the preceding claims, characterized in that the step of associating the individual blocks from the groups with the first submodel or the second submodel is carried out on the basis of a specified rule.

8. The method according to claim 7, characterized in that, according to the rule, all blocks which do not have to be executed on the programmable logic device are associated with the first submodel.

9. The method according to claim 8, characterized in that a block must also be executed on the programmable logic device if said block is connected via a signal to a block identified as associated with the second submodel, and the signal has a higher bit width than a width threshold and / or a higher change frequency than a change threshold and / or the signal has a shorter latency than a signal latency threshold.

10. The method according to any one of the preceding claims, characterized in that, after the step of associating the individual blocks from the groups with the first submodel or the second submodel, a graphical representation of the divided model is displayed via a user interface, and in that changes to the division are received via the user interface.

11. The method according to claim 10, characterized in that blocks able to be associated with both the first submodel and to the second submodel are identified on the basis of an additional rule, in particular on the basis of the absence of a resource assignment, wherein said blocks are highlighted on the user interface and said blocks are associated based on user input.

12. The method according to any one of the preceding claims, characterized in that, after the step of associating the individual blocks from the groups with the first submodel or the second submodel, an additional step of inserting communication blocks takes place, wherein for two blocks connected by a signal it is checked whether said blocks are associated with different submodels and, if so, a pair of communication blocks is inserted for implementing a data exchange between the processor and programmable logic device.

13. The method according to any one of the preceding claims, characterized by the additional steps of g. transmitting the program code and the configuration bitstream to a real-time computer system comprising a processor and a programmable logic device, and h. performing a simulation wherein the processor executes the program code and the functionality of the programmable logic device is determined by the configuration bitstream.

14. A computer system comprising an operating computer having a user interface and a real-time computer having a processor, a programmable logic device, and I / O circuits, characterized in that instructions for performing a method according to any one of the preceding claims are stored in a non-volatile memory of the computer system.

15. A non-volatile data carrier having a computer-readable storage medium on which commands are embedded for bringing about, when implemented by a processor, the state that the processor is configured to implement a method according to any one of the claims 1 through 13.