TRANSMITTERS AND DEVICES FOR MONITORING A TRANSMITTER

Description

[0001] The invention relates to encoders, such as rotary encoders or linear encoders that output sine and cosine signals, and devices for monitoring such encoders.

[0002] The monitoring of encoders, especially rotary encoders or linear encoders with analog sine and cosine waveforms, is typically performed using integrated circuits that monitor the vector length of the encoder signals analogously. This allows for monitoring the correct function of the encoder with a high degree of fault coverage.

[0003] Accurately monitoring the vector length with discrete components is very complex. Commercially available solutions are limited to a frequency of 100 kHz. Software solutions require a very high sampling rate and unacceptable computing power.

[0004] US Patent 5,777,223 A discloses a measuring system for linear and angular motion with a first length or angle sensor that operates according to a first measuring method and converts an input value in the form of a linear or angular motion into an electrically processable first output value. Furthermore, a second length or angle sensor, which is mechanically coupled to the first length or angle sensor and operates according to a different measuring method, is used to convert the linear and angular motion into an electrically processable second output value. The first and second output values ​​are available for further processing and evaluation.

[0005] CN 206 578 635 U relates to a main shaft of a high-speed, high-precision lathe, with an FPGA interpolation subdivision circuit. It determines the position of the main shaft, emphasizing the accuracy of repeated positioning, the overall measurement accuracy of the digitally controlled machine tool, and machining efficiency.

[0006] CN 107 769 630 B relates to a position decoding monitoring system for a permanent magnet synchronous motor. The monitoring system includes functions for monitoring the stimulation amplitude, stimulation frequency, and feedback of a rotary transformer. When used as a control system for a permanent magnet synchronous motor position sensor, the system can be used to monitor the states of a simulation source and the rotary transformer in a rotary transformer simulation and demodulation system, and to ensure the accuracy of the rotary transformer simulation and demodulation system.

[0007] The object of the invention is to provide a cost-effective solution using standard components for a functionally reliable evaluation of encoders with sine and cosine signals.

[0008] The problem is solved by a device for monitoring a sensor having the features of claim 1 and a system having the features of claim 9.

[0009] A device according to the invention for monitoring a sensor (e.g., a rotary encoder or rotary angle encoder; English: (rotary) encoder or also a linear encoder that generates sine and cosine signals) comprises: a programmable logic gate arrangement; a first analog-to-digital converter (in other words: first analog-to-digital converter), configured to receive a first sensor signal from the sensor and to output a first data signal to the programmable logic gate arrangement; and a second analog-to-digital converter (in other words: second analog-to-digital converter), configured to receive a second sensor signal from the sensor and to output a second data signal to the programmable logic gate arrangement;wherein the programmable logic gate arrangement is configured to process the first data signal and the second data signal to obtain a monitoring result, calculating a sum of the square of the first encoder signal and the square of the second encoder signal and verifying that the sum equals the square of a desired vector length, wherein the first analog-to-digital converter and the second analog-to-digital converter are synchronized, and wherein the programmable logic gate arrangement is configured to output a synchronization signal to the first analog-to-digital converter and the second analog-to-digital converter; and wherein the first analog-to-digital converter and the second analog-to-digital converter are configured to synchronize themselves based on the synchronization signal.

[0010] In other words, a programmable logic gate array receives two input signals, acquired via separate (discrete) analog-to-digital converters, and the programmable logic gate array uses these signals to determine a monitoring result. Single-channel analog-to-digital converters can be used.

[0011] In another embodiment, a digital signal processor (DSP) can be used instead of the programmable logic gate array. The first analog-to-digital converter and the second analog-to-digital converter can be integrated into the DSP.

[0012] Monitoring the movement to be detected by the sensor can involve monitoring whether the first sensor signal and the second sensor signal are (at least approximately) the coordinates of a circle with a given radius.

[0013] The encoder can be a rotary encoder. The rotary movement of the encoder can then be monitored using the device according to the invention.

[0014] The sensor can be a linear sensor, for example a linear encoder. The device according to the invention can then be used to monitor the linear movement of the linear sensor.

[0015] In an orthogonal coordinate system, the two quantities sine and cosine describe a circle. According to the invention, this circle can be monitored with the programmable logic gate arrangement, which advantageously determines whether the first and second encoder signals reproduce or approximate a circle.

[0016] The solution according to the invention provides vector length monitoring (for example by monitoring sine and cosine components of the vector) with several, preferably two, separate analog-to-digital converters (ADCs) and a (single, common) field-programmable gate array (FPGA).

[0017] The solution according to the invention is very cost-effective and enables real-time monitoring at very high frequencies using standard components.

[0018] For example, cost-effective discrete ADCs with an appropriate sampling rate and serial interface can be used. This makes it possible to implement vector length monitoring with discrete components. By combining standard components (ADCs, FPGAs (or DSPs)), cost-effective signal monitoring is possible without relying on specialized components. Furthermore, the monitoring characteristics, such as the sampling rate, can be adapted by selecting the appropriate components.

[0019] In one embodiment, the first analog-to-digital converter can be synchronized with the second analog-to-digital converter. For example, the combination of two synchronized discrete ADCs and parallel signal processing can be implemented in a generic FPGA. The mathematical equation (explained later) can be represented in the FPGA and solved (or analyzed) efficiently and quickly.

[0020] For example, the sum of the squares of the two encoder signals (i.e., the sum of the square of the first encoder signal and the square of the second encoder signal) can be calculated, and it can be checked whether this sum corresponds to the square of the desired vector length. If the encoder is functioning correctly, the calculation "sin 2< + cos 2<" is intuitively performed, which corresponds to the square of the radius of the circle described by sin and cos, i.e., 1. It can then be checked whether "sin 2< + cos 2<" lies within a predefined interval around 1. The interval can be chosen symmetrically around 1, for example, [0.7;1.3], [0.8;1.2], [0.9;1.1], [0.95;1.05], or [0.99;1.01].

[0021] In one embodiment, the programmable logic gate array can be configured to output a synchronization signal to the first analog-to-digital converter and the second analog-to-digital converter, and the first and second analog-to-digital converters can be configured to synchronize based on the synchronization signal. For example, the synchronization signal can be used by the first and second analog-to-digital converters to trigger the analog-to-digital conversion. Thus, the synchronization signal ensures that the first and second analog-to-digital converters perform the analog-to-digital conversion at the same time, i.e., that the sampling occurs simultaneously.

[0022] In one embodiment of the device, the first encoder signal can represent a time progression of a (rotational angle) position of a first reference point of the encoder, and the second encoder signal can represent a time progression of a (rotational angle) position of a second reference point of the encoder.

[0023] The time profiles of the (rotational angle) positions of the first reference point and the second reference point can be determined during normal operation of the encoder, so that no additional data that is not already available during normal operation of the encoder needs to be determined.

[0024] Advantageously, the first reference point and the second reference point are separated by a (rotational) angle of 90°.

[0025] This allows the first and second encoder signals to be phase-shifted by 90°, so that the first encoder signal can be, for example, a sinusoidal signal and the second a cosine signal. If the first and second encoder signals are then interpreted as coordinates, a representation of the first and second encoder signals, assuming the encoder is functioning correctly, will form a circle. This can be monitored using an analog simulation of the mathematical equation sin 2 ≤ + cos 2 ≤ = 1, which can be implemented, for example, using discrete components.

[0026] The programmable logic gate array can have multiple physical elements whose interconnections can be programmed. This allows the programmable logic gate array to emulate a logic circuit and perform repetitive calculations very efficiently.

[0027] The device can be configured to determine the monitoring result at a frequency of at least 1 MHz.

[0028] Advantageously, the device is set up to determine the monitoring result without performing a (direct) comparison of the first sensor signal with the second sensor signal.

[0029] The two encoder signals are intuitively checked for consistency using the equation sin 2< + cos 2< = 1. Here, 1 represents the ideal result. In real-world applications, this calculation result, sin 2< (corresponding to the first ADC) + cos 2< (corresponding to the second ADC), is expected to fall within a range around 1, for example, approximately 0.8 to 1.2. If the calculation result falls outside this range, an error message can be generated. Besides the actual monitoring, the programmable logic gate array (FPGA) can provide the timing for cyclically reading the ADCs. Furthermore, the reading process can be implemented in such a way that the data from the ADC is correctly interpreted. The calculation result can also be passed on to a processing unit. Additionally, functionalities such as position counting via a quadrature counter can be implemented in the programmable logic gate array.

[0030] In a further development, the device may include: a further first analog-to-digital converter, configured to receive a further first encoder signal from a further encoder and to output a further first data signal to the programmable logic gate array; and a further second analog-to-digital converter, configured to receive a further second encoder signal from the further encoder and to output a further second data signal to the programmable logic gate array. The programmable logic gate array may further be configured to process the further first data signal and the further second data signal in order to obtain a further monitoring result.

[0031] This training course clearly demonstrates how signals from multiple sensors, each with its own analog-to-digital converter, are processed by a common programmable logic gate arrangement to determine a monitoring result for each sensor.

[0032] Advantageously, the first analog-to-digital converter and the second analog-to-digital converter are synchronized, and the further first analog-to-digital converter and the further second analog-to-digital converter are synchronized. The first / second analog-to-digital converter and the further first / second analog-to-digital converter can also be synchronized, so that all analog-to-digital converters are synchronized. In another embodiment, the first and second analog-to-digital converters can be unsynchronized with the further first and further second analog-to-digital converters.

[0033] The object of the invention is further achieved by a system comprising the device described above and an encoder coupled to the device. The device described above can, for example, be arranged on a mounting rail, such as a DIN rail. The encoder can then be used, for example, for a programmable logic controller (PLC), such as a small controller, and the described device can be integrated into the PLC.

[0034] Advantageously, the transmitter also includes measuring means for receiving the first transmitter signal and measuring means for receiving the second transmitter signal.

[0035] The measuring instruments can be those already used in the normal operation of the sensor, so that no additional measuring instruments are required to determine the monitoring result. For example, the measuring instruments can optically scan / detect a code disc rotating with a shaft.

[0036] In one embodiment, the transmitter further comprises an output unit configured to issue a warning signal based on the monitoring result, and / or a shutdown unit configured to shut down the transmitter based on the monitoring result.

[0037] This allows the sensor to react appropriately to the monitoring result if, for example, a sensor fault is detected (i.e., if the signals are too far from the desired circuit). For example, a warning can be issued in such a case, or operation can be completely stopped. Alternatively, the sensor can determine how far the signals are from the desired circuit and then issue a warning signal or switch off the sensor (and any connected devices).

[0038] According to the invention, the monitoring result can be determined at a receiving location, which may be different from the location where the sensor is arranged. This allows for the detection of errors that occur along the path from the sensor to the receiving location.

[0039] Further advantageous embodiments of the methods according to the invention will become apparent from the dependent claims, the drawing and the description.

[0040] The invention is described below with reference to exemplary embodiments and the drawings. The drawings show, in schematic representations: Fig. 1 a block diagram of a device for monitoring the movement of an encoder according to one embodiment; Fig. 2 an illustration of the first encoder signal and the second encoder signal according to one embodiment; and Fig. 3 a representation of the first encoder signal and the second encoder signal in another representation according to one embodiment.

[0041] The device according to the invention is explained below using exemplary embodiments.

[0042] Fig. 1Figure 1 shows a block diagram of a device 100 for monitoring the movement of an encoder according to one embodiment. The device 100 includes a first input and a second input. The first input is configured to receive a first encoder signal 102 from the encoder. The second input is configured to receive a second encoder signal 104 from the encoder. The device 100 further includes a first analog-to-digital converter 106, which receives the first encoder signal 102, and a second analog-to-digital converter 108, which receives the second encoder signal 104. An output 110 of the first analog-to-digital converter 106 and an output 114 of the second analog-to-digital converter 108 are fed to a programmable logic gate array 116, which processes the data supplied to it and thus generates and outputs a monitoring result 118.

[0043] For example, the first sensor signal 102 corresponds to a sine wave and the second sensor signal 104 to a cosine wave. The sum of the squares of the sensor signals is then calculated, which is intuitively represented as "sin 2 < + cos 2 <". The result is compared to a lower limit (e.g., 0.8) and an upper limit (e.g., 1.2). If the calculated result lies within the interval defined by the lower and upper limits, a positive result is output as monitoring result 118.

[0044] In one implementation, in addition to calculating the sum of the squares, further calculation steps may be necessary because the first input signal 102 (which corresponds, for example, to sine) and the second input signal 104 (which corresponds, for example, to cosine) do not oscillate around the zero point, but are instead offset. The subsequent calculation steps then compensate for this offset.

[0045] The first analog-to-digital converter 106 and the second analog-to-digital converter 108 are synchronized via a synchronization signal 112 output by the programmable logic gate array 116. For example, the synchronization signal 112 can trigger the sampling (i.e., determining the digital data signal corresponding to the analog encoder signal) of the first analog-to-digital converter 106 and the second analog-to-digital converter 108 simultaneously.

[0046] In another embodiment, triggering is achieved by a separate comparator, which, for example, determines the zero crossing of one of the signals (i.e., the first sensor signal 102 or the second sensor signal 104). This determination could also be used for further diagnostic purposes, e.g., for amplitude determination.

[0047] As in Fig. 1As demonstrated, vector length monitoring can be implemented using specific switching elements, such as multiple ADCs and an FPGA. The ADCs acquire encoder signals, which are then evaluated in the FPGA. Threshold monitoring is performed to ensure that the values ​​of sin 2 and cos 2 are within a permissible range.

[0048] Advantageously, the ADCs have a minimum sampling frequency f_sample of f_sample ≥ n × f_Encoder_Signal .

[0049] Here, f_Encoder_Signal is the maximum output frequency of the encoder and n is a factor that is determined based on the assumed error scenarios and their probability of detection.

[0050] Determining n solely using the sampling theorem (n ≥ 2 ) would not reveal the errors that may be expected.

[0051] According to the invention, with n = 5, among other things, the assumed error "short circuit between sine and cosine" can be detected within one encoder signal period.

[0052] Fig. 2Figure 200 shows a first encoder signal 206 (which can be supplied to the first input of the device 100) and a second encoder signal 208 (which can be supplied to the second input of the device 100) according to one embodiment. Time is plotted on a horizontal axis 202, and the value of the time course of the first encoder signal 206 and the second encoder signal 208 is plotted on a vertical axis 204.

[0053] The first encoder signal 206 can represent the time course of a (rotational angle) position of a first reference point of the encoder, and the second encoder signal 208 can represent the time course of a (rotational angle) position of a second reference point of the encoder. In the example shown, the first and second reference points are separated by a (rotational) angle of 90°. For example, the first encoder signal 206 can be a sinusoidal signal, and the second encoder signal 208 can be a cosine signal.

[0054] For the functionally reliable evaluation of encoders with sine and cosine signals, monitoring of these signals can be provided according to the invention. As in Fig. 2In an orthogonal and orthonormal coordinate system, the two quantities sine and cosine describe a circle. This circle can be monitored with two thresholds representing a lower and an upper limit (as shown by circles 308 and 310 in [reference missing]). Fig. 3 (shown).

[0055] Mathematically, monitoring via vector length can be realized by monitoring the following equation: sin 2 x + cos 2 x = 1 = VL .

[0056] Here, VL is the square of the given vector length. The given vector length corresponds to the radius of the circle described by the sine and cosine signals.

[0057] This allows the amplitude, offset, and phase shift of the signals to be checked within a single value of the vector length.

[0058] Fig. 3Figure 300 shows a representation of the first encoder signal 206 and the second encoder signal 208 in another representation according to one embodiment. The first encoder signal 206 is plotted over a horizontal axis 302, and the second encoder signal 208 is plotted over a vertical axis 304. This results in a circle 306 whose coordinates are the first encoder signal 206 and the second encoder signal 208.

[0059] If the encoder malfunctions, for example because a signal source is misplaced on one of the encoder's axes, or because the first or second reference point has shifted, the resulting shape will not be a circle 306, but rather an ellipse other than a circle. Therefore, to verify that the encoder is functioning correctly, one can check whether the first encoder signal 206 and the second encoder signal 208 are displayed in a representation with axes as shown in Fig. 3The monitoring result 118 of the device 100 can therefore indicate, for example, whether the first encoder signal 102, 206 and the second encoder signal 104, 208 are coordinates of a circle with a given radius.

[0060] According to the invention, it is checked whether the representation of the first encoder signal 102, 206 and the second encoder signal 104, 208 results in a circle by feeding the first encoder signal 102, 206 and the second encoder signal 104, 208 via separate analog-to-digital converters 106, 108 to a common programmable logic gate arrangement 116, which then performs the necessary calculations for monitoring. Reference symbol list

[0061] 100 Device for monitoring a sensor 102 First sensor signal 104 Second sensor signal 106 First analog-to-digital converter 108 Second first analog-to-digital converter 110 First data signal 112 Synchronization signal 114 Second data signal 116 Programmable logic gate array 118 Monitoring result 200 Illustration of the first and second encoder signals 202 horizontal axis 204 vertical axis 206 first encoder signal 208 second encoder signal 300 Representation of the first and second encoder signals 302 Horizontal axis 304 Vertical axis 306 Circle 308 Inner circle 310 Outer circle

Claims

1. An apparatus (100) for monitoring a vector length of an encoder, wherein the apparatus has: a programmable logic gate arrangement (116); a first analog-to-digital converter (106) configured to receive a first encoder signal (102, 206) of the encoder and to output a first data signal (110) to the programmable logic gate arrangement (116); and a second analog-to-digital converter (108) configured to receive a second encoder signal (104, 208) of the encoder and to output a second data signal (114) to the programmable logic gate arrangement (116); wherein the programmable logic gate arrangement (116) is configured to process the first data signal (110) and the second data signal (114) in order to obtain a monitoring result (118), wherein a sum of a square of the first encoder signal (102, 206) and a square of the second encoder signal (104, 208) is calculated and it is checked whether the sum corresponds to a square of a desired vector length; wherein the first analog-to-digital converter (106) and the second analog-to-digital converter (108) are synchronized; wherein the programmable logic gate arrangement (116) is configured to output a synchronization signal (112) to the first analog-to-digital converter (106) and to the second analog-to-digital converter (108); and wherein the first analog-to-digital converter (106) and the second analog-to-digital converter (108) are configured to synchronize based on the synchronization signal (112).

2. An apparatus (100) according to claim 1, wherein the first encoder signal (102, 206) represents a time development of a position of a first reference point of the encoder, and wherein the second encoder signal (104, 208) represents a time development of a position of a second reference point of the encoder.

3. An apparatus (100) according to claim 2, wherein the first reference point and the second reference point are remote from one another by an angle of 90°.

4. An apparatus (100) according to any one of the preceding claims, wherein the monitoring of the encoder comprises a monitoring whether the first encoder signal (102, 206) and the second encoder signal (104, 208) are coordinates of a circle with a predefined radius.

5. An apparatus (100) according to any one of the preceding claims, wherein the programmable logic gate arrangement (116) comprises a plurality of physical elements whose interconnection is programmable.

6. An apparatus (100) according to any one of the preceding claims, wherein the apparatus (100) is configured to determine the monitoring result with a frequency of at least 1 MHz.

7. An apparatus (100) according to any one of the preceding claims, further comprising: a further first analog-to-digital converter configured to receive a further first encoder signal of a further encoder and to output a further first data signal to the programmable logic gate arrangement (116); and a further second analog-to-digital converter configured to receive a further second encoder signal of the further encoder and to output a further second data signal to the programmable logic gate arrangement (116); wherein the programmable logic gate arrangement (116) is further configured to process the further first data signal and the further second data signal in order to obtain a further monitoring result.

8. An apparatus (100) according to claim 7, wherein the first analog-to-digital converter (106) and the second analog-to-digital converter (108) are synchronized; and wherein the further first analog-to-digital converter and the further second analog-to-digital converter are synchronized.

9. A system comprising: the apparatus (100) according to any one of the preceding claims; and an encoder coupled to the apparatus.

10. A system according to claim 9, wherein the encoder further has: measurement means for picking up the first encoder signal (102, 206); and measurement means for picking up the second encoder signal (104, 208).

11. A system according to one of the claims 9 or 10, wherein the encoder further has: an output unit configured to output a warning signal based on the monitoring result (118).

12. A system according to any one of the claims 9 to 11, wherein the encoder further has: a switch-off unit configured to switch off the encoder based on the monitoring result (118).