QC-LDPC CODE ENCODING

Description

TECHNICAL field

[0001] Implementations of the present disclosure relate to the communications field, and in particular, to an encoding method, a communication method, and an apparatus.Background

[0002] A low-density parity-check (low density parity check, LDPC for short) code denotes a family of linear block codes each with a sparse check matrix. LDPC has desirable performance approaching to a Shannon limit, and features a flexible structure and relatively low decoding complexity. Therefore, the LDPC can be widely applied to various communications systems.

[0003] A quasi-cyclic low-density parity-check (quasi-cyclic low density parity check, QC-LDPC for short) code is an important branch of the LDPC code. A check matrix of the QC-LDPC code includes a plurality of block matrices of a same size. These block matrices are all-zero matrices and cyclic shift matrices. The QC-LDPC code is easily implemented and therefore has been used in a plurality of communications systems.

[0004] After a location of a non-zero cyclic shift matrix in the check matrix of the QC-LDPC code is determined, offset values of various cyclic shift matrices greatly influence error floors of corresponding code words. For a QC-LDPC code supporting a flexible and adjustable code length, sizes of a series of block matrices are usually defined by setting lifting factors z of the block matrices. A size of each block matrix is z×z. In this way, check matrices of different sizes are obtained to adapt to different code lengths.

[0005] However, an existing computing method for a check matrix of an LDPC code needs to be further optimized.

[0006] HUAWEI ET AL, "LDPC design for eMBB data", vol. RAN WG1, no. Spokane, USA; 20170116 - 20170120, (20170116), 3GPP DRAFT; R1-1700092 LDPC DESIGN FOR EMBB DATA, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, URL: http: / / www.3gpp.org / ftp / Meetings_3GPP_SYNC / RAN1 / Docs, relates LDPC design for eMBB data.

[0007] LG ELECTRONICS, "LDPC Codes Design for eMBB data channel", vol. RAN WG1, no. Spokane, USA; 20170116 - 20170120, (20170116), 3GPP DRAFT; R1-1700518_LDPC CODES DESIGN FOR EMBB_FINAL, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, URL: http: / / www.3gpp.org / ftp / Meetings_3GPP_SYNC / RAN1 / Docs, relates to LDPC code design for eMBB data channel.

[0008] LG ELECTRONICS, "Performance results of LDPC codes for eMBB", vol. RAN WG1, no. Spokane, USA; 20170116 - 20170120, (20170116), 3GPP DRAFT; R1-1700519, 3RD GENERATION PARTNERSHIP PROJECT (3GPP), MOBILE COMPETENCE CENTRE ; 650, ROUTE DES LUCIOLES ; F-06921 SOPHIA-ANTIPOLIS CEDEX ; FRANCE, URL: http: / / www.3gpp.org / ftp / Meetings_3GPP_SYNC / RAN1 / Docs relates to performance results of LDPC codes for eMBB.

[0009] Nikita Polyanskii ET AL, "Floor Scale Modulo Lifting for QC-LDPC codes", (20170125), pages 1 - 7, URL: https: / / arxiv.org / pdf / 1701.07521v1.pdf relates to floor scale modulo lifting for QC-LDPC codes.

[0010] ZTE ET AL, "Consideration on LDPC design for NR", (20161010), pages 1-13, 3GPP TSG RAN WG1 #86bis, R1-1608974 relates to some considerations for LDPC code design, as well as LDPC codes with flexibility of code block sizes, code rates and IR-HARQ.Summary

[0011] The invention has been defined in the independent claims. Further specific technical features have been defined in the dependent claims.

[0012] According to the principles described in this application, a relatively low bit-error-rate floor can be maintained, and storage space occupied can be reduced.Brief description of drawings

[0013] FIG. 1 is a schematic flowchart of an encoding method according to an implementation of this application; FIG. 2 is a performance simulation diagram of an encoding method according to an example not falling under the scope of the claimed invention; FIG. 3a to FIG. 3e are performance simulation diagrams of an encoding method according to an example not falling under the scope of the claimed invention; FIG. 4 is a performance simulation diagram of an encoding method according to an example not falling under the scope of the claimed invention; FIG. 5 is a schematic flowchart of a communication method according to an implementation of this application; FIG. 6 is a schematic diagram of an encoding and processing process according to an implementation of this application; FIG. 7 is schematic structural diagram of an apparatus according to an implementation of this application; and FIG. 8 is a schematic structural diagram of a communications device according to an implementation of the present disclosure. description of implementations

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the following further describes various implementations in detail with reference to the accompanying drawings. The implementations described below are not all claimed, they are included to help understanding the context of the invention. While the description refers to various implementations, the embodiments of the invention are those that comprise at least all the features of an independent claim. Any implementation that does not fall within the scope of the claims does not form part of the invention, but rather included as an illustrative example that is useful for understanding the invention.

[0015] Implementations of this application may be applied to a wireless communications system including wireless communications devices such as a network device and a terminal device (terminal device or terminal equipment). The wireless communications system is, for example, an LTE system, or another wireless communications system using various wireless access technologies, for example, a system using access technologies such as code division multiple access, frequency division multiple access, time division multiple access, orthogonal frequency division multiple access, and single-carrier frequency division multiple access, and a subsequent evolved system such as a fifth-generation (5G) system. The wireless communications device in the implementations of this application may be any device in the wireless communications system, for example, the network device or the terminal device.

[0016] The terminal device may be a device that provides a user with voice or data connectivity, a handheld device with a wireless connection function, or another processing device connected to a wireless modem. The wireless terminal may communicate with one or more core networks through a radio access network (radio access network, RAN for short). The wireless terminal may be a mobile terminal, such as a mobile phone (also referred to as a "cellular" phone) and a computer with a mobile terminal, for example, may be a portable, pocket-sized, handheld, computer's built-in, or in-vehicle mobile apparatus, which exchanges voice or data with the radio access network. For example, it may be a device such as a personal communication service (personal communication service, PCS for short) phone, a cordless telephone set, a session initiation protocol (session initiation protocol, SIP for short) phone, a wireless local loop (wireless local loop, WLL for short) station, or a personal digital assistant (personal digital assistant, PDA for short). The wireless terminal may also be referred to as a system, a subscriber unit (subscriber unit, SU for short), a subscriber station (subscriber station, SS for short), a mobile station (mobile station, MS for short), a remote station (remote station, RS for short), an access point (access point, AP for short), a remote terminal (remote terminal, RT for short), an access terminal (access terminal, AT for short), a user terminal (user terminal, UT for short), a user agent (user agent, UA for short), a user device, or user equipment (user equipment, UE for short).

[0017] The network device may be a base station, or an access point, or may be a device in communication with a wireless terminal via one or more sectors at an air interface in an access network. The base station may be configured to mutually convert a received over-the-air frame and an IP packet and serve as a router between the wireless terminal and a remaining portion of the access network. The remaining portion of the access network may include an Internet protocol (Internet protocol, IP for short) network. The base station may coordinate attribute management of the air interface. For example, the base station may be a base transceiver station (Base Transceiver Station, BTS for short) in GSM or CDMA, or may be a NodeB (NodeB) in WCDMA, or may be an evolved NodeB (evolvedNodeB, eNodeB for short) in LTE. This is not limited in this application.

[0018] An implementation of this application provides an encoding method. The encoding method may be implemented by using, for example, an encoder on a communications device. As shown in FIG. 1, the encoding method includes the following steps.

[0019] S101: Encode a first information sequence by using a first matrix to obtain a second information sequence, where the first matrix is a matrix whose size is m b z×n b z, z is a lifting factor, the first matrix includes m b ×n b submatrices whose sizes are z×z, the m b ×n b submatrices whose sizes are z×z include at least one cyclic shift matrix whose size is z×z and that is based on an identity matrix, and a cyclic shift value of each cyclic shift matrix is an element that is in a matrix E(H) and that is at a location corresponding to the cyclic shift matrix, where the matrix E(H) is a 11 a 12 … a 1 n b a 21 a 22 … a 2 n b ⋮ ⋮ ⋱ ⋮ a m b 1 a m b 2 … a m b n b , an element a ij in E(H) meets a ij = a ijE max if a ijE max < 1 f r 1 a ijE max z , r 2 z otherwise , a ij ∈ {-1, 0,1, 2,... z - 1}, and a ijEmax is an element in a cyclic shift value matrix E max (H) corresponding to a maximum lifting factor z max , r 1 (a ijEmax ,z) represents a function whose parameters are a ijEmax and z, r 2 (z) represents a function whose parameter is z, f(r 1 (a ijEmax ,z), r 2 (z)) represents a function whose parameters are r 1 (a ijEmax ,z) and r 2 (z), and a value of f(r 1 (a ijEmax ,z), r 2 (z)) is less than z.

[0020] In a possible implementation, r 2 (z) may be a predefined value. Therefore, E max (H) may also be a fixed value.

[0021] It may be understood that the first matrix may further include an all-zero submatrix whose size is z×z. For the all-zero submatrix, a value of an element of the all-zero submatrix at a corresponding location in E(H) is -1.

[0022] E(H) is understood as a result obtained after adjustment performed based on E max (H). Specifically, E max (H) may be stored in the communications device. For different liftina factors. corresponding E(H) is obtained by using E max (H), and then the first matrix is finally obtained.

[0023] For example, it is assumed that z max =8, and an LDPC code matrix whose size is (8z max , 4z max ) may be represented by using H zmax and E zmax (H) as follows: H z max = P 0 O O P 0 P 1 P 0 O O O P 3 P 4 O O P 0 P 0 O O P 2 O P 6 P 0 O P 0 P 0 P 3 O P 5 O P 1 O O P 0 , where O represents a submatrix of an all-zero matrix, and P a ij E max< represents a cyclic shift matrix whose offset value is a ijEmax . A specific value of a ijEmax is determined based on E zmax (H), where E z max H = 0 − 1 − 1 0 1 0 − 1 − 1 − 1 3 4 − 1 − 1 0 0 − 1 − 1 2 − 1 6 0 − 1 0 0 3 − 1 5 − 1 1 − 1 − 1 0 .

[0024] in an example not falling under the scope of the claimed invention, Therefore. when z=4, assuming that E(H) is determined by using a ij = a ijE max if a ijE max < 1 a ijE max + 3 mod z otherwise , corresponding E(H) and H obtained may be as follows: E H = 0 − 1 − 1 0 1 0 − 1 − 1 − 1 2 3 − 1 − 1 0 0 − 1 − 1 1 − 1 1 0 − 1 0 0 2 − 1 0 − 1 0 − 1 − 1 0 and H = P 0 O O P 0 P 1 P 0 O O O P 2 P 3 O O P 0 P 0 O O P 1 O P 1 P 0 O P 0 P 0 P 2 O P 0 O P 0 O O P 0

[0025] In a possible implementation, a value of z may be determined by the encoder based on a length of the first information sequence. Alternatively, in a possible implementation, a value of z may be determined by another functional unit and then input into the encoder. In different scenarios or rules, the encoder or the another functional unit may determine the value of z in different manners. In this implementation of this application, a manner of determining the value of z by the encoder or the another functional unit is not limited.

[0026] Optionally, to further improve performance, after the encoder determines a lifting factor value based on the first information sequence or the another functional unit inputs a lifting factor value into the encoder, the encoder corrects the value. The corrected value is z, which is finally used. A specific correction manner is described in subsequent implementations.

[0027] Further, the communications device completes the encoding of the first information sequence by using the first matrix, to obtain the second information sequence.

[0028] In a possible implementation, the first information sequence may be padded through zero padding (zero padding), or be padded by using another known bit sequence, so that a length of the padded information sequence is equal to that of an input information sequence supported by the first matrix. Then, an operation is performed by using the first matrix and the padded information sequence to obtain a parity bit. An information bit and the parity bit are merged for outputting, to obtain an encoded sequence, namely, the second information sequence.

[0029] In a possible implementation, the cyclic shift matrix based on the identity matrix is a matrix obtained based on the identity matrix and the cyclic shift value. The cyclic shift value represents a quantity of times that the identity matrix is cyclically shifted rightward. For example, the cyclic shift matrix is obtained by performing cyclical shift rightward on each row of the identity matrix for a same quantity of times. When the cyclic shift value is 0, the cyclic shift matrix is represented as the identity matrix.

[0030] In an example, it is assumed that an identity matrix having a size of 4 is 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 , and the cyclic shift value is 1. In this case, a corresponding cyclic shift matrix is 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 .

[0031] S102: Output the second information sequence.

[0032] In a possible implementation, the second information sequence obtained in S101 is output by the encoder.

[0033] In this implementation of this application, the first matrix meets a function related to a lifting factor and an element in E max (H), a relatively low bit-error-rate floor can be maintained, and storage space occupied can be reduced. In addition, performance can be improved while a relatively small granularity of the lifting factor is ensured. The granularity of the lifting factor refers to an interval between two neighboring lifting factors.

[0034] Specifically, for different lifting factors, E max (H) is used to obtain corresponding E(H). There may be different methods. To be specific, each function of r 1 (a ijEmax ,z), r 2 (z), and f(r 1 (a ijEmax ,z), r 2 (z)) may be expressed in a plurality of different forms.

[0035] r 1 (a ijEmax ,z) is expressed in the form d) below. The other forms for r 1 below do not form part of the invention. a) r 1 a ij z = a ijE max + Int a ijE max / c ⋅ s z ; b) r 1 a ij z = a ijE max + Int c / a ij E max ⋅ s z ; c) r 1 a ij z = a ij E max + Int s z / a ij E max ; d) r 1 a ij z = a ij E max + Int a ij E max / z ; e) r 1 a ij z = a ij E max + z max − a ij E max ⋅ s z ; f) r 1 a ij z = a ij E max + s z mod z max ; and g) r 1 a ij E max z = a ij E max + Int s z ⋅ a ij E max / c .

[0036] In the foregoing formulas, c is a preset constant, s z is a value corresponding to z, and the value of s z may be a nonnegative integer in a range. In an implementation not forming part of the invention, s z corresponding to z may be obtained through table lookup. Int() is a rounding function, and may be a rounding-up function or a rounding-down function. mod is a modulo operation. In the foregoing description, (a) to (g) may all be understood as the forms of adding an offset value to a ijEmax , but a difference lies in that in the manner shown in (f), a result obtained by adding the offset value to a ijEmax is limited to a range. Further, the offset value is determined in different forms. For example, an offset value corresponding to z may be determined based on z. Examples are not enumerated for description in this implementation of this application.

[0037] r 2 (z) is expressed in the form j) or k) below, the other forms do not form part of the claimed invention: h) r 2 z = z ; i) r 2 z = z / z max ; and j) r 2 z = 2 floor log 2 z , where floor represents rounding down; k) r 2 z = N z , where N z is a positive integer less than z. For example, N z corresponding to z may be obtained through table lookup. A value range of N z may be 2 t< or k·2 t< , where k and t are both nonnegative integers.

[0038] f(r 1 (a ijEmax ,z), r 2 (z)) is expressed in the form m) below and the form n) do not form part of the claimed invention: m) f r 1 a ij E max z , r 2 z = r 1 a ij E max z modr 2 z ; and n) f r 1 a ij E max z , r 2 z = Int r 1 a ij E max z ⋅ r 2 z

[0039] The foregoing r 1 (a ijEmax ,z), r 2 (z), and f(r 1 (a ijEmax ,z), r 2 (z)) may use different combination manners based on different expression forms thereof. Finally, a value of f(r 1 (a ijEmax ,z), r 2 (z)) is less than z. (1) When a range of r 1 (a ijEmax ,z) is not limited, r 1 (a ijEmax ,z) may be further restricted, for example, by using r 2 (z) and f(r 1 (a ijEmax ,z), r 2 (z)), so that a result of an offset value is not greater than z. For r 2 (z), one of (j), (k) is selected, and r 1 (a ijEmax ,z) is further restricted in the form, (m) in f(r 1 (a ijEmax ,z), r 2 (z)).

[0040] In an example not forming part of the claimed invention, it is assumed that r 1 (a ijEmax ,z) uses the form (c) for rounding down, r 2 (z) uses the form (h), and f(r 1 (a ijEmax ,z), r 2 (z)) uses the form (m). In this case, a ij meets: a ij = a ij E max if a ij E max < 1 a ij E max + s z / a ij E max mod z otherwise

[0041] Various first matrices corresponding to different values of z may be obtained by using the formula (1).

[0042] Values of s z may be shown in Table 1. It may be understood that Table 1 is merely an example of the values of s z . Based on the example shown in Table 1, values of s z / 256 are obtained through table lookup based on z. The values of s z may be obtained through a further multiplication operation. Table 1Zs z / 256Zs z / 256Zs z / 256Zs z / 256Zs z / 256673711723140327297538474714432808039276131486288690401783152112966101411080415623046119427821016043120123431484116473200131044086916863281141445148813172113366155 1146790517603446164712924180635241794810940184636081804912960188036812 0191150198141920376020151210011961438462112521010222001392102245321042204240062314541106220810408122410556108421234160252561411062161342412610571211214220443282735871141322404404282591411622281448229146041181223210456430561812042366464133114628122124014724320630124724424806330640126102486488234666312811252114966351468101321256150423677014136626405120

[0043] Further, FIG. 2 shows block error rate (BLER) simulation results when the formula (1) and Table 1 are used, the length of the first information sequence ranges from 96 to 8192, and bit rates are 8 / 9, 5 / 6, 3 / 4, 2 / 3, 1 / 2, 2 / 5, 1 / 3, 1 / 4, and 1 / 5. A modulation scheme is quadrature phase shift keying (QPSK). A simulation algorithm is a belief propagation (belief propagation, BP for short) algorithm. A quantity of iteration times is 50.

[0044] It may be learned from FIG. 2 that at various bit rates and in the full length range, block error rate curves are all relatively smooth.

[0045] (2) When the range of r 1 (a ijEmax ,z) is limited, for example, in (f), a value is limited within 0-z max through a modulo operation, the value may be further corrected by using r 2 (z) = z / z max and f(r 1 (a ij E max ,z), r 2 (z)) = Int(r 1 (a ijEmax ,z)·r 2 (z)). To be specific, a ij meets: a ij = a ij E max if a ij E max < 1 Int a ij E max + s z MOD z max ⋅ z z max otherwise .

[0046] FIG. 3a to FIG. 3e show block error rate simulation results when the formula (2) is used, and lengths of the first information sequence are 8000, 6000, 4000, 2000, and 1000. Bit rates used during simulation include 1 / 5, 1 / 4, 1 / 3, 2 / 5, 1 / 2, 2 / 3, 3 / 4, 5 / 6, and 8 / 9. A modulation scheme is QPSK. An algorithm is a BP algorithm. It may be learned from FIG. 3a to FIG. 3a to FIG.3e that performance is all relatively desirable within the foregoing code lengths and bit rates.

[0047] Optionally, as described before, to further improve performance, a corrected lifting factor value may be used. A lifting factor value may be corrected in a plurality of manners. For example, an originally obtained lifting factor z orig may be corrected by using a lifting factor offset value, or values of z allowed to be used are stored. When z orig is not a value of z allowed to be used, a smallest value of the values of z allowed to be used that are greater than z orig is used as the corrected lifting factor.

[0048] In a possible implementation, z orig may be, for example, the lifting factor value that is determined by the encoder based on the first information sequence, or may be the lifting factor value that is input by the another functional unit into the encoder. This is not limited in this implementation of this application. In this implementation of this application, the lifting factor value is corrected by using a lifting factor offset value, for example, z= z orig + Δz, where Δz is the lifting factor offset value.

[0049] A value of Δz may be related to different factors, for example, related to at least one of the following factors: a formula that a ij meets, a system requirement, z orig , or the like. A specific value of Δz may be obtained through table lookup.

[0050] In an example not forming part of the invention, it is assumed that for r 1 (a ijEmax ,z), the form (b) is used, where s z =0; for r 2 (z), the form (k) is used; and for f(r 1 (a ijEmax ,z), r 2 (z)). , the form (m) is used. In this case, a ij meets: a ij = a ij E max if a ij E max < 1 a ij E max mod 2 t otherwise .

[0051] Values of Δz and t may be determined from Table 2. It may be understood that Table 2 is merely an example. A correspondence between Δz and t and z orig may be different from that in the forms shown in Table 2. This is not limited in this implementation of this application. Table 2ZorigΔzz = z orig + Δzt718381939110310111311112312113313316414216415116416117417017418018419221420222421223422123423124424226425227426127427027428028429332530232531132532234533134534337535338536137537239538341539342540343541243542244543346544347545348546349547249548351549352550151551152552355553255554155555358556258557360558260559362560363561364662264663164664064665166666369667269668169669069670171671071672173673174674074675176676177677380678280679079680282681182682183683083684185685186686288687087688391689291690191691091692395693396694195695297696096697097698199699099610001006101210361021103610321056104010461051106610601066107010761083111610921116110111161110111611201126113211561141115611501156116311961172119611811196119112061201121612111226122212461231124612401246125312871263129712721297128313171290129713011317131013171323135713321357134113571350135713601367137314071382140713911407140014071413144714201427143314671441145714511467146314971470147714811497149014971500150715101517152315571530153715411557155315871562158715711587158216071590159716001607161116271620162716311647164016471653168716621687167317071681169716911707170217271711172717201727.........5125128

[0052] Further, FIG. 4 shows block error rate simulation results when the formula (3) and Table 2 are used, a length of the first information sequence ranges from 96 to 8000, and bit rates are 8 / 9, 5 / 6, 3 / 4, 2 / 3, 1 / 2, 2 / 5, 1 / 3, 1 / 4, and 1 / 5. A modulation scheme used during simulation is QPSK. A simulation algorithm is a BP algorithm. A quantity of iteration times is 50. It may be learned from FIG. 4 that performance is further optimized through correction of a lifting factor.

[0053] In FIG. 2 to FIG. 4, Es / No is a signal-to-noise ratio in dB, Rate or CR is a bit rate, and information length K is an information sequence length.

[0054] In another example not falling under the scope of the claimed invention, it is assumed that a ij meets the formula (1). The value of Δz may be determined from Table 3. It may be understood that Table 3 is merely an example. A correspondence between z orig and Δz may be different from that in the forms in Table 3. This is not limited in this implementation of this application. For example, Δz may be stored as a non-zero z orig , or Δz may be stored as a zero z orig . Table 3ZorigΔz708090101110120131140150160171181190200211221230240251261...0371381391400411...0501510521...0681...0781...01281...01681...02121

[0055] In this implementation of this application, z is marked by correcting z, so that some particular values of z are not used, and a lower BLER is produced.

[0056] In a possible implementation, the encoding method in this implementation of this application is applicable to a check matrix of a QC-LDPC code.

[0057] It may be understood that the first matrix in the implementations of the encoding method may also be applicable to a decoding method. That is, in a decoding process, a matrix same as that in the encoding process is used for decoding. In a possible implementation, an obtaining manner of the first matrix may also be the same as that in the foregoing implementations. In an example, the first matrix is used to decode a third information sequence to obtain a fourth information sequence. In a possible implementation, the third information sequence may correspond to the second information sequence, and the fourth information sequence may correspond to the first information sequence.

[0058] In a possible implementation, the decoding method may be applied to a corresponding communication method. The communication method is implemented by a corresponding communications device.

[0059] An implementation of this application further provides a communication method. The communication method applies various encoding methods described in the foregoing implementations. As shown in FIG. 5, the communication method includes the following steps.

[0060] S501: Encode a first information sequence by using a first matrix to obtain a second information sequence.

[0061] For a method for encoding the first information sequence, refer to the related descriptions of the foregoing embodiments. Details are not described herein.

[0062] Optionally, before S501, some processing may be further included. To be specific, the first information sequence may be input into an encoder after being processed by another functional unit. In this implementation of this application, a source and content of the first information sequence are not limited.

[0063] S502: Process the second information sequence and send the processed second information sequence.

[0064] In a possible implementation, processing such as bit rearrangement, rate matching, interleaving, and symbol mapping and modulation may be performed on the second information sequence and then the processed second information sequence may be sent. FIG. 6 schematically shows a process of encoding the first information sequence and performing a series of processing on the first information sequence. It may be understood that for different systems or application scenarios, processing processes of the second information sequence may be different. For example, bit rearrangement may be used as optional processing. Examples of various processing processes are not enumerated for description in this implementation of this application.

[0065] In this implementation of this application, various encoding methods described in the foregoing implementations are applied in the communication method, so that data transmission performance can be improved.

[0066] An implementation of this application provides an apparatus 700. As shown in FIG. 7, the apparatus 700 includes: a memory 701, configured to store a first information sequence; and a processor 702, configured to encode the first information sequence by using a first matrix to obtain a second information sequence. Specifically, for a method for encoding the first information sequence by the processor 702, refer to the related descriptions of the foregoing embodiments. Details are not described herein.

[0067] In a possible implementation, the processor 702 is further configured to determine z based on z = z orig + Δz. z orig is an originally obtained lifting factor value. z orig may be obtained by the processor 702 based on a length of the first information sequence. Alternatively, in a possible implementation, a value of z orig may be determined by another functional unit and then input to the apparatus 700.

[0068] An implementation of this application further provides an apparatus. The apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to execute an instruction in the memory, to encode a first information sequence by using a first matrix to obtain a second information sequence. For a method for encoding the first information sequence by the processor, refer to the related descriptions of the foregoing embodiments. Details are not described herein.

[0069] In a possible implementation, the apparatus in the foregoing implementations may be an encoder. The second information sequence is used as an output of the encoder.

[0070] An implementation of this application further provides a communications device 800. As shown in FIG. 8, the communications device 800 includes: an encoder 801, configured to encode a first information sequence by using a first matrix to obtain a second information sequence; at least one processor 802, configured to process the second information sequence; and a transceiver 803, configured to send the processed second information sequence.

[0071] Specifically, for a method for encoding the first information sequence by the encoder 801, refer to the related descriptions of the foregoing embodiments. For a structure and an implementation of the encoder, refer to the foregoing embodiments. Details are not described herein.

[0072] In a possible implementation, the at least one processor 802 may implement a series of processing such as bit rearrangement, rate matching, interleaving, and symbol mapping and modulation. It may be understood that for different systems or application scenarios, processing processes implemented by the processor 802 and composition structures of the processor 802 may be different. Examples are not enumerated for description in this implementation of this application.

[0073] In a possible design, the communications device 800 may be a terminal device or a network device.

[0074] All or some of the foregoing implementations may be implemented by using software, hardware, firmware, or any combination thereof. When the software is used to implement the implementations, the implementations may be implemented completely or partially in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedure or functions according to the implementations of the present disclosure are all or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable apparatuses. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, a coaxial cable, an optical fiber, or a digital subscriber line (DSL)) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by a computer, or a data storage device, such as a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), a semiconductor medium (for example, a Solid State Disk (SSD)), or the like.

[0075] A person skilled in the art may clearly understand that, the technologies in the implementations of this application may be implemented by software in addition to a necessary general hardware platform. Based on such an understanding, the technical solutions in the implementations of this application essentially or the part contributing to the prior art may be implemented in a form of a software product. The software product may be stored in a storage medium such as a ROM / RAM, a magnetic disc, or a compact disc, and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform the methods described in the implementations or some parts of the implementations of this application.

[0076] Same and similar parts between implementations in the specification may refer to each other.

[0077] The scope of protection is defined by the appended claims.

Claims

1. A quasi-cyclic low density parity check, QC-LDPC, encoding method, comprising: encoding (S101) a first information sequence by using a first matrix to obtain an encoded sequence, wherein the first matrix is a matrix whose size is mbz×nbz, z is a lifting factor, the first matrix comprises mb×nb submatrices whose sizes are z×z, the mb×nb submatrices whose sizes are z×z comprise at least one cyclic shift matrix whose size is z×z and that is based on an identity matrix, and a cyclic shift value of each cyclic shift matrix is an element that is in a matrix E(H) and that is at a location corresponding to the cyclic shift matrix, wherein the matrix E(H) is a 11 a 12 ⋯ a 1 n b a 21 a 22 ⋯ a 2 n b ⋮ ⋮ ⋱ ⋮ a m b 1 a m b 2 ⋯ a m b n b , an element aij in E(H) meets a ij = a ij E max if a ij E max < 1 f r 1 a ij E max z , r 2 z otherwise , and aijEmax is an element in a cyclic shift value matrix Emax(H) corresponding to a maximum lifting factor zmax, r1(aijEmax,z) represents a function whose parameters are aijEmax and z, r2(z) represents a function whose parameter is z, f(r1(aijEmax,z), r2(z)) represents a function whose parameters are r1(aijEmax,z) and r2(z), and a value of f(r1(aijEmax,z), r2(z)) is less than z; and outputting (S102) the encoded sequence; wherein a value of r1(aijEmax,z) is determined based on a sum of an offset value corresponding to z and aijEmax; the method characterised in that: r1(aijEmax,z) is expressed by the following form: r 1 a ij E max z = a ij E max + Int a ij E max / z ; wherein Int() is a rounding function; and in that r2(z) is expressed by any one of the following forms: r 2 z = 2 floor log 2 z ; and r 2 z = N z ; wherein Nz is a positive integer less than z, and floor is a rounding-down function; and wherein f r 1 a ijE max , z , r 2 z = r 1 a ijE max z modr 2 z .

2. The method according to claim 1, wherein the lifting factor z is provided as an input or wherein the lifting factor z is calculated based on a length of the first information sequence; and wherein the lifting factor z is corrected by adding a lifting factor offset value thereto.

3. The method according to claim 1, wherein the lifting factor z is provided as an input or wherein the lifting factor z is calculated based on a length of the first information sequence; wherein when the lifting factor z is not one of a set of stored values of the lifting factor z that are allowed to be used, the lifting factor z is corrected to be the smallest value among the set of stored values of lifting factor z that are greater than the lifting factor z.

4. A communication method, comprising: encoding (S501) a first information sequence by applying the encoding method according to any one of claims 1 to 3 to obtain an encoded sequence; and processing (S502) the encoded sequence and sending the processed encoded sequence.

5. An apparatus, comprising at least one processor and a memory coupled to the at least one processor, wherein the at least one processor is configured to perform the method according to any one of claims 1 to 3.

6. A communications device, comprising: an encoder (801), configured to: encode a first information sequence by using the method according to any one of claims 1 to 3 to obtain an encoded sequence; and output the encoded sequence; a processor (802), configured to process the encoded sequence; and a transceiver (803), configured to send the processed encoded sequence.

7. A computer-readable storage medium, comprising instructions which, when executed by a computer, cause the computer to perform the method according to any one of claims 1 to 3.