REINFORCED THIN-LAYER BUILDING ELEMENT
Patent Information
- Application Number
- DE602019079544
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2019-04-23
- Publication Date
- 2025-12-24
- Estimated Expiration
- 2039-04-23
AI Technical Summary
The integration of III-V semiconductor materials on silicon wafers for CMOS technology is challenging due to lattice mismatch, leading to cracking, dislocation propagation, and complex doping requirements, which limits the scalability and performance of integrated circuits.
A reinforced thin-film device with vertically embedded semiconductor needles is used to support III-V semiconductor growth, providing a lattice-matched and dislocation-free epitaxial layer on silicon wafers, allowing for high-mobility charge carrier materials like graphene and III-V semiconductors to be integrated without cracking, even on large substrates.
The solution enables high-quality epitaxial growth of III-V materials on silicon wafers up to 30 cm in diameter, facilitating the production of high-performance electronic components and quantum computing devices with improved heat dissipation and reduced manufacturing time.