Circuit and method for random-edge injection lock

Description

[0001] The invention relates to injection locking techniques for injection-locked digital phase locked loop (IL-DPLLs), especially for DPLLs that support frequency modulation in Bluetooth Low Energy (BLE) technology.

[0002] The BLE technology is widely deployed in Internet-of-Things (IoT) applications due to its low energy consumption. Generally, a phase locked loop (PLL) which can support frequency modulation needs to be implemented in BLE systems. In order to reduce the die area of a BLE transceiver, small area oscillators are implemented along with injection-locking techniques in order to suppress the phase noise performance of the oscillators. Moreover, the system often requires the clock generator to support fractional-N mode. This makes the possibility for the system to tune the frequency offset of the crystal oscillator and enables the clock generator to generate small frequency step without using very small oscillator frequency.

[0003] For example, the document EP 3 249 817 A1 shows a DTC-based PLL operable at fractional-N mode with an improved PLL output spectral purity. However, during the fractional-N, the delay of the DTC changes periodically and the period depends on the fractional part of the frequency control word (FCW). Thus, the non-linearity of the DTC introduces periodic error and this error leads to fractional spur at the output spectrum. In addition the frequency offset of the oscillator and the timing error between the injection path and the PLL path generate periodic error lead to reference spur at the output spectrum.

[0004] Publication US9306585B1 shows a circuit according to the preamble of claim 1, and a method according to the preamble of claim 13.

[0005] Accordingly, an object of the invention is to provide a circuit, a digital phase locked loop and a method that can overcome the aforementioned limitations.

[0006] The object is solved by the features of the claim 1 for the circuit, by the features of the claim 8 for the digital phase locked loop and by the features of the claim 13 for the method. The dependent claims contain further developments.

[0007] According to a first aspect of the invention, a circuit for facilitating random edge injection locking of an oscillator is provided. The circuit comprises a clock signal and a digitally controlled delay line, where said digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence.

[0008] Moreover, the circuit preferably comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal. Therefore, the injection pulses are no longer injected to a fixed phase of the oscillator. Rather, the pulses are injected to different phases of the oscillator in order to break the repeating patterns that cause the spurs.

[0009] Preferably, the pulse generator is further configured to generate a first set of injection pulses for one phase of the at least two phases of the oscillator when the phase select signal is high and a second set of injection pulses for other phase of the at least two phases of the oscillator when the phase select signal is low.

[0010] For instance, the oscillator may generate RF signals at 90 degrees phase separation, i.e. at phases 0, 90, 180 and 270. In this regard, the pulse generator may generate a first set of pulses for the RF signals at phase 0 and a second set of pulses for the RF signals at phase 180, for example. Using the signal level of the phase select signal as a control input, the respective sets of pulses are injected to the respective phases of the oscillator. This advantageously facilitates the injection of the injection pulses at different phases of the oscillator in a simplified and an effective manner.

[0011] Preferably, the circuit further comprises control means configured to tune a delay of the digitally controlled delay line based on a duty cycle of the clock signal in order to compensate at least one half of oscillator period when injecting the injection pulses from one phase to the other phase of the at least two phases of the oscillator. This advantageously prevents the injection of pulses at an opposite or unwanted phase of the oscillator.

[0012] Further preferably, the edge selector comprises a pseudo-random binary sequence generator and the phase select signal preferably comprises a pseudo-random binary sequence. Therefore, random selection of phases of the oscillator to be injected is incorporated.

[0013] Preferably, the oscillator is an inverter-based oscillator, preferably an inverter-based ring oscillator, more preferably a quadrature four-stage ring oscillator operable with a minimum phase separation equal to pi / 2. Advantageously, the proposed random edge injection locking technique can be implemented in a cost-effective manner due to the smaller area of the oscillator.

[0014] Further preferably, the oscillator is a multi-phase oscillator and wherein the pulse generator is configured to generate injection pulses for phases of the multi-phase oscillator based on the phase select signal. In this regard, the circuit further comprises switching means downstream to the pulse generator in order to inject the injection pulses at the phases of the multi-phase oscillator, and wherein the switching means is configured to be operable via a random switching logic. Advantageously, the proposed solution can be implemented with oscillators operable with a minimum phase separation of pi / N, where N is an even integer.

[0015] According to a second aspect of the invention, a digital phase locked loop (DPLL) is provided. The DPLL comprises a reference clock signal, and a digital to time converter. Said digital to time converter is configured to delay the reference clock signal, thereby generating a delayed reference clock signal. The DPLL further comprises an oscillator configured to generate radio frequency signals at at least two phases. Furthermore, the DPLL comprises a time to digital converter configured to generate an error signal by comparing an edge of the delayed reference clock signal and an edge of the radio frequency signals.

[0016] Moreover, the DPLL comprises a circuit configured to input the delayed reference clock signal and further to perform random edge injection locking of the oscillator according to the first aspect of the invention. Preferably, the DPLL further comprises a feedback path from the time to digital converter to a loop filter, and wherein the loop filter is configured to tune the oscillator based on the error signal generated by the time to digital converter.

[0017] Therefore, the digital to time converter delays the reference signal where the delayed reference signal phase is compared to the phase of the RF signals of the oscillator in order to phase-lock the oscillator output. On the other hand, the circuit, especially the digitally controlled delay line, takes the delayed reference clock signal as clock signal input and further delays the delayed reference clock signal. The latter is preferably used by the pulse generator along with the phase select signal in order to generate and further to inject pulses at different phases of the oscillator, thereby resetting the noisy phase in the oscillator.

[0018] Further preferably, the DPLL further comprises injection control means configured to control the generation of injection pulses at the pulse generator. In this regard, the injection control means is further configured to enable or disable the generation of injection pulses at the pulse generator for a predefined number of cycles of the reference clock signal. This advantageously keeps the balance between the reference spur and the effectiveness of the proposed random edge injection locking scheme, especially by disabling the injection in different numbers of reference cycles.

[0019] Preferably, the digital phase locked loop is an injection-locked fractional-N digital phase locked loop, preferably, an injection-locked ring-oscillator based fractional-N digital phase locked loop. Advantageously, the proposed DPLL supports BLE technology, especially the Gaussian-FSK modulation, and further provides a cost-effective solution due to the smaller size oscillator.

[0020] According to a third aspect of the invention, a method for facilitating random edge injection locking of an oscillator is provided. The method comprises the steps of providing a clock signal, generating a delayed clock signal, generating a phase select signal with a random pulse sequence, and generating injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal. Therefore, the injection pulses are injected to different phases of the oscillator in order to break the repeating patterns, thereby suppressing the level of reference spur and fractional spur effectively.

[0021] Preferably, the method further comprises the step of generating a first set of injection pulses for one phase of the at least two phases of the oscillator when the phase select signal is high. In addition, the method further comprises the step of generating a second set of injection pulses for another phase of the at least two phases of the oscillator when the phase select signal is low. This advantageously facilitates the injection of the injection pulses at different phases of the oscillator in a simplified and an effective manner.

[0022] Preferably, the method further comprises the step of compensating at least one half of an oscillator period when injecting the injection pulses from one phase to the other phase of the at least two phases of the oscillator. This advantageously prevents the injection of pulses at an opposite or unwanted phase of the oscillator.

[0023] Exemplary embodiments of the invention are now further explained with respect to the drawings by way of example only, and not for limitation. In the drawings: Fig. 1shows a first exemplary embodiment of the circuit according to the first aspect of the invention; Fig. 2shows an exemplary embodiment of the pulse generator according to the first aspect of the invention; Fig. 3shows an exemplary embodiment of the oscillator according to the first aspect of the invention; Fig. 4shows an exemplary timing diagram of operations according to the first aspect of the invention; Fig. 5shows a second exemplary embodiment of the circuit according to the first aspect of the invention; Fig. 6shows an exemplary embodiment of the digital phase locked loop according to the second aspect of the invention; Fig. 7shows the digital phase locked loop of Fig. 6 in detail; Fig. 8Ashows exemplary operation phases of the digital phase locked loop according to the second aspect of the invention; Fig. 8Bshows an exemplary timing diagram of operations of the digital phase locked loop according to the second aspect of the invention; Fig. 9Ashows an exemplary embodiment of the injection control means according to the second aspect of the invention; Fig. 9Bshows an exemplary timing diagram of operations of the injection control means of Fig. 9A; Fig. 10Ashows measurement results for fractional spur level at the output spectrum; Fig. 10Bshows measurement results for reference spur level at the output spectrum; and Fig. 11shows an exemplary embodiment of the method according to the third aspect of the invention.

[0024] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the following embodiments of the present invention may be variously modified and the range of the present invention is not limited by the following embodiments.

[0025] In Fig. 1, a first exemplary embodiment of the circuit 100 according to the first aspect of the invention is illustrated. The circuit 100 comprises a clock signal 101 that is fed to a digitally controlled delay line or DCDL 110, where the DCDL 110 generates a delayed clocked signal 102 by delaying the clock signal 101. The circuit 100 further comprises an edge selector 120 that generates a phase select signal 103 with a random pulse sequence. Preferably, the edge selector 120 comprises a pseudo-random binary sequence generator that generates a pseudo-random binary sequence, i.e. PRBS-k as the phase select signal 103, where k defines the size of a unique word of data in the sequence. However, other random sequences, e.g., true random sequences, chaotic sequences and the like, as known in the art can also be implemented in order to generate the phase select signal 103.

[0026] The circuit 100 further comprises a pulse generator 130 downstream to the DCDL 110 and an oscillator 140 downstream to the pulse generator 130. Said oscillator 140 is configured to generate radio frequency (RF) signals 106,107 at at least two phases, preferably more. In this regard, the pulse generator 130 generates injection pulses 104,105 from the delayed clock signal 102 for the two phases of the oscillator 140 based on the phase select signal 103. The generation of said phase select signal 103 and the injection arrangement for the oscillator 140 will be discussed in the later sections in detail.

[0027] Therefore, the circuit 100 effectively solves the two main limitations specially associated with a fractional-N injection-locked oscillator, namely the high reference spur and the high fractional spur at the output spectrum. The circuit 100 effectively breaks the repeating patterns of pulse injection, especially by injecting pulses at different phases of the oscillator 140.

[0028] For instance, if the above-mentioned injection locking is to be performed for a PLL with fractional-N mode having an injection-locked oscillator, the clock signal may correspond to the reference clock signal and the DCDL 110 can be extended to have a first DCDL and a second DCDL. The first DCDL (i.e. a digital to time converter) may generate a first delayed reference clock signal by delaying the reference clock signal and the second DCDL may generate a second delayed reference clock signal by delaying the first reference clock signal. Then, the pulse generator 130 may generate the injection pulses 104,105 from the second delayed reference clock signal for the two phases of the oscillator 140 based on the phase select signal 103. Therefore, the oscillator 140 will be locked with respect to the first delayed reference clock signal whereas the second delayed reference clock signal is used to generate the injection pulses 104,105.

[0029] It is important that when the pulses are sent from one phase to another phase of the oscillator 140, one-half of the oscillator period needs to be compensated by the DCDL 110. Otherwise, a large error will introduce which, in itself, may cause large spurious at the output spectrum. In order to do so, the circuit 100 comprises control means 150 that is configured to tune the delay of the DCDL 110 based on the duty cycle of the clock signal 101 or the reference clock signal coming from, for instance, a crystal oscillator. In this regard, the control means 150 is configured to tune the DCDL 110 according to the digital RF duty-cycle of the oscillator 140 and further to perform static timing offset calibration of the DCDL 110 by taking into account the random pulse sequence from the edge selector 120, for instance.

[0030] In Fig. 2, an exemplary embodiment of the pulse generator 130 according to the first aspect of the invention is illustrated. Here, the implementation of said pulse generator 130 is illustrated with digital logic gates, namely NOT gates or inverters and AND gates. However, it is to be noted that any alternative logic gate arrangements are feasible so long the output results in short pulses from a continuous signal. During the operation, the delayed clock signal 102 is inputted at a first inverter 201 that inverts the polarity of the delayed clock signal 102. The output of the first inverter 201 acts as a common node, which serves two propagation paths 205,206. The output of the first inverter 201 passes through a second inverter 202 along the propagation path 205, reverting the polarity again that results in the delayed clock signal 102, along with the propagation delay caused by the first and second inverter 201,202, respectively.

[0031] Along the propagation path 206, the output of the first inverter 201 is inverted twice, by a third inverter 203 and a fourth inverter 204, respectively. This results in the delayed clock signal 102 with an opposite polarity along with propagation delay caused by the first inverter 201, the third inverter 203 and the fourth inverter 204. The signals at the propagation paths 205,206 are fed to a first AND gate 207. Due to the inversion stages, the signal at the propagation path 205 has an opposite polarity than the signal at the propagation path 206, however with the additional delay caused by the fourth inverter 204, the signals will have same polarity for a brief moment, especially defined by the delay time cause by each delay stage of the inverters 201,202,203,204,205. For this brief moment, the AND gate output will be high and will produce a pulse or injection pulse 208 with a width corresponding to the delay time of each inverter delay stage.

[0032] The injection pulse 208 is then fed to a second AND gate 209 where the second input of said AND gate 209 is the phase select signal 103. Therefore, the output 104 of the second AND gate 209 will be high when the phase select signal 103 is high. Additionally, the injection pulse 208 is fed to a third AND gate 210 where the second input of said AND gate 210 is also the phase select signal, however with an opposite polarity, i.e. inverted via an inverter in-between. Therefore, the output 105 of the third AND gate will be high when the phase select signal 103 is low. In order to facilitate complementary arrangements, e.g. CMOS implementation, the outputs 104, 105 of the second AND gate 209 and the third AND gate 210, respectively, are further inverted. In Fig. 2, the outputs 104 of the second AND gate 209 are shown as INJ 0P and INJ 0N for P-type and N-type transistors, respectively, in CMOS configuration. Similarly, the outputs 105 of the third AND gate 210 are shown as INJ 180P and INJ 180N for P-type and N-type transistors, respectively, in CMOS configuration.

[0033] In Fig. 3, an exemplary embodiment of the oscillator 140 according to the first aspect of the invention is illustrated. Particularly, Fig. 3 shows the injection scheme for injecting the injection pulses at different phases of the oscillator 140. The oscillator 140 illustrated herein as a quadrature four-stage ring oscillator having a 90 0< of phase separation. The four stages correspond to four inverters, namely a first inverter 301, a second inverter 302, a third inverter 303 and a fourth inverter 304. The first inverter 301 results a first stage output 106, the second inverter 302 results a second stage output 317, the third inverter 303 results a third stage output 107 and the fourth inverter 304 results a fourth stage output 316.

[0034] The first stage output 106 and the third stage output 107 carry complementary waveforms and so do the second stage output 317 and the fourth stage output 316. In addition, the latter two are 90 0< out of phase with respect to the former two. Hence, the oscillator 140 consists of four one-pole stages, thereby generating 90 0< phase separations between consecutive nodes when oscillates. However, the outputs 106,317,107,316 prefer to latch up and then the loop can indefinitely maintain the first stage output 106 and the third stage output 107 high, and the second stage output 317 and the fourth stage output 316 low, or vice versa.

[0035] In order to prevent said indefinite latch up, a first pair of cross-coupled inverters 305 is included between the first stage output 106 and the third stage output 107 and further a second pair of cross-coupled inverters 306 is included between the second stage output 317 and the fourth stage output 316. The first pair of cross-coupled inverters 305 and the second pair of cross-coupled inverters 306 prevent equal logical states at their respective input and output nodes.

[0036] The injection pulses INJ 0P , INJ 0N and INJ 180P , INJ 180N , as shown in Fig. 2, are injected in a complementary arrangement at the respective phases of the oscillator 140. In particular, the injection pulse INJ 0P is injected at the first stage output 106 whereas the injection pulse INJ 0N is injected at the third stage output 107, which carries complementary waveform to the first stage output 106. Similarly, the injection pulse INJ 180P is injected at the third stage output 107 whereas the injection pulse INJ 180N is injected at the first stage output 106, which carries complementary waveform to the second stage output 107.

[0037] In other words, the RF signals from the first stage output 106 correspond to RF signals at phase 0 of the oscillator 140 and the RF signals from the third stage output 107 correspond to RF signals at phase 180 of the oscillator 140. It is to be noted that said injection principle can be analogously implemented for the second stage output 317 and the fourth stage output 316, thereby injection locking the oscillator 140 at phases 90 and 270, respectively.

[0038] In Fig. 4, an exemplary timing diagram of operations according to the first aspect of the invention is illustrated. The signal CLK represents the clock input signal 101 of the DCDL 110 and the signal O DCDL represents the delayed clock signal 102. The signal SEL ED represents the phase select signal 103 with random sequences for the polarity of the signal. The signal INJ 0 and INJ 180 represent the injection pulses 104 and 106, respectively, generated by the pulse generator 130. It can be seen that, the injection pulses INJ 0 are generated when SEL ED is high and the injection pulses INJ 180 are generated when SEL ED is low.

[0039] The signal RF 0 represents the RF signals at the phase 0 of the oscillator 140 and the signal RF 180 represents the RF signals at the phase 180 of the oscillator 140. It can be seen that, when SEL ED is high, the injection pulses INJ 0 are injected at the phase 0 of the oscillator 140 as a clean reference pulse to reset RF 0 . Further, when SEL ED is low, the injection pulses INJ 180 are injected at the phase 180 of the oscillator 140 as a clean reference pulse to reset RF 180 .

[0040] In Fig. 5, a second exemplary embodiment of the circuit 500 according to the first aspect of the invention is illustrated. The circuit 500 differs from the circuit 100 of Fig. 1 in that the circuit 500 comprises a multi-phase oscillator 540 and additional switching means 510 in order to drive the injection pulses 501 to a respective phase of the oscillator 540. The multi-phase oscillator 540 can be a multi-stage ring oscillator, a multi-stage LC oscillator, or any oscillators operable with a minimum phase separation of pi / N, where N is an integer greater than 1, preferably an even integer.

[0041] The switching means 510 is configured to be operable via a random switching logic 503, preferably generated by the edge selector 120. In this regard, the edge selector may further tune the DCDL 110 based on the random switching logic 503, for instance via normalization, in order to synchronize the injection pulses 501 with the respective phases of the multi-phase oscillator 540.

[0042] In Fig. 6, an exemplary embodiment of the digital phase locked loop (DPLL) 600 according to the second aspect of the invention is illustrated. Said DPLL 600 comprises a reference clock signal 601, preferably generated from an on-board crystal oscillator (not shown), and a digital to time converter (DTC) 610. The DTC 610 generates a delayed reference clock signal 602 by delaying the reference clock signal 601. The DPLL 600 further comprises the circuit 100 according to the first aspect of the invention, downstream to the DTC 610 so that the circuit 100 is able to take the delayed reference clock signal 602 as its input clock signal. The DPLL 600 further comprises the oscillator 140 that generates RF signals at phases 0 and 180, for example, as described along Fig. 3.

[0043] As described along Fig. 1, the circuit 100 generates injection pulses 604,605 from the delayed reference clock signal 602 for the two phases of the oscillator 140. The oscillator 140 outputs RF signals at two phases 606,607 that are reset by the injection pulses 604,605 and are further fed to a multiplexer 620. The multiplexer 620 is implemented as, for instance a 2x1 multiplexer, which takes the RF signals at inputs and outputs a selective RF signal 608 out of the two based on a control signal. Said control signal is preferably the phase select signal 103 provided by the edge selector 120. Hence, when the phase select signal 103 is high, the multiplexer 620 will output the RF signal at phase 0 of the oscillator 140 and when the phase select signal 103 is low, the multiplexer 620 will output the RF signal at phase 180 of the oscillator.

[0044] The DPLL 600 further comprises a time to digital converter (TDC) 630 that compares an edge of the delayed reference clock signal 602 at the output of DTC 610 with an edge of the RF signals 606,607 at the output 608 of the multiplexer 620. Therefore, the TDC 630 generates an error signal based on the difference between the edges, i.e. phase difference, of said signals. The error signal is fed to a loop filter 640 through a feedback path 609, where the loop filter 640 tunes the oscillator 140 based on said error signal.

[0045] It is to be noted that, if the proposed injection locking technique, as performed by the circuit 100, is not implemented in the DPLL 600, the DPLL 600 would align the phases between the output 602 of the DTC 610 and the output 608 of the multiplexer 620 with a random pattern. In other words, the DTC output 602 sometimes may align with the oscillator phase RF 0 and sometimes may align with RF 180 in a random manner. Hence, the injection pulses may sometimes be sent to the opposite RF edge if the DTC output 602 is directly used to generate the injection pulses without any compensation for said random patterns. This may result in huge disturbances to the oscillator 140 and may cause large spurious.

[0046] The proposed random edge injection technique, as facilitated by the circuit 100, allows the DPLL 600 to align the DTC output 602, for instance with rising edges of RF 180 when the phase select signal 103 is high, and, for instance with rising edges of RF 0 when the phase select signal 103 is low. The proposed random edge injection technique further ensures the polarity of the injection signals as described along Fig. 2 and Fig. 3, so that the injection pulses INJ 0P and INJ 0N are generated if the phase select signal 103 is high otherwise the injection pulses INJ 180P and INJ 180N are generated.

[0047] The DPLL 600 further comprises an accumulator 660 that comprises a control input 611 and a data input 612. The control input 611 corresponds to frequency control input, e.g. a frequency control word (FCW) and the data input 612 corresponds to the transmission data, especially during modulation. The accumulator 660 generally comprises a counter or counters for counting, e.g. the edges of the oscillator 140 in one reference clock to coarsely tune the oscillator 140 to the target frequency. Preferably, the accumulator 660 is disabled during the fine-tuning of the oscillator 140, i.e. the correction of the phase error between the RF edge 608 and the delayed reference edge 602.

[0048] The DPLL 600 further comprises so-called estimators 650, which estimate and further calibrate, for instance, the duty cycle of the reference clock signal 601 (crystal oscillator duty cycle), the duty cycle of the oscillator 140, static timing offset for the DCDL, and so on. The DPLL 600 further comprises injection control means 670 that is configured to control the generation of the injection pulses 604,605 at the pulse generator 130. In particular, the injection control means enables or disables the injection path for a selective number of cycles or periods of the reference clock signal 601. The operation of said injection control means will be described in a later section in detail.

[0049] In Fig. 7, the DPLL 600 of Fig. 6 is illustrated in detail. The reference clock signal 601 is generated from a crystal oscillator (not shown) at a clock frequency of 64MHz and the DTC 610 generates the delayed reference clock signal 602 at a clock frequency of 128MHz (i.e. double edge). The DCDL 110 takes in the delayed reference clock signal 602 and further delays the signal 602. The DCDL output 603 is fed to the pulse generator 130 along with the phase select signal 613 coming from the edge selector 120. The pulse generator 130 generates a set of injection pulses 604 for the phase 0 of the oscillator 140 and a set of injection pulses 605 for the phase 180 of the oscillator 140 from the DCDL output 110 and the phase select signal 613.

[0050] The oscillator 140 therefore generates RF signals, which are already reset by the injection pulses, particularly the RF signal at the phase 0 of the oscillator 606 and the RF signal at the phase 180 of the oscillator 607. The multiplexer 620 outputs the respective pulses 606,607 to the TDC 630 with respect to the phase select signal 613. The TDC 630 generates phase error signals by comparing the edges of the DTC output 602 with the respective RF signals 606,607 and feeds to the loop filter 640 via the feedback path 609.

[0051] The loop filter 640 generates oscillator tuning words correspond to the phase error in order to tune the oscillator phases. The phase error signals are further fed to the estimators 710,720,730. Particularly, the estimator 710 estimates and / or calibrates the duty cycles of crystal oscillator and the oscillator 140 and further tunes the DTC edges. The estimator 720 estimates and / or calibrates the static timing offset of the DCDL and the duty cycle of the oscillator 140 in order to tune the DCDL 110. Moreover, the estimator 730 estimates or calibrates the DPLL 600 for the modulation of the transmitting data, especially when the DPLL 600 operates in the transmitter mode.

[0052] Along Fig. 8A and Fig. 8B, the operation phases of the DPLL 600 are illustrated. In particular, Fig. 8A shows the operation phases of the DPLL 600 over the required lock time. During the initial phase, the DPLL 600 uses the accumulator 660, especially the counter, to count the edges of the oscillator 140 in one reference clock to coarsely tune the oscillator 140 close to the target frequency. Then the counter is disabled to reduce power consumption and the fine tuning of the oscillator 140 stats correcting the phase error between the RF edge 608 and the delayed reference edge 602, where the phase error is measured by the TDC 630.

[0053] During the PLL only phase, the TDC output, i.e. the phase error, is used to compute or estimate the duty cycle error of the reference clock and the RF signal and further to estimate the gain of the DTC 610. Next, the injection path is enabled and the phase-locking path is frozen to avoid racing conditions between the two loops. During the injection lock only phase, the TDC output, i.e. the phase error, is used for calibrating the duty cycle of the crystal oscillator and further to tune the delay of the DCDL 110 in order to reduce the static timing offset. Finally, the phase-locking path and the injection path are enabled while the aforementioned calibrations are running in the background in order to decrease the level of spurious tones.

[0054] Fig. 8B shows the timing diagram for the operations of the DPLL 600. The signal REF represents the reference clock signal 601. The signal O DTC represents the DTC output, i.e. the delayed reference clock signal 602. The signal O DCDL represents the DCDL output, i.e. the further delayed reference clock signal 603. The signal SEL ED represents the phase select signal 613 generated from the edge selector 120. The signal INJ 0 represents the injection pulses 604 to be injected at the phase 0 of the oscillator 140 and the signal INJ 180 represents the injection pulses 605 to be injected at the phase 180 of the oscillator 140. The signal RF 0 represents the RF signal 606 from the oscillator 140 at the phase 0 and the signal RF 180 represents the RF signal 607 from the oscillator 140 at the phase 180.

[0055] It can be seen that, by the virtue of the proposed random edge injection technique, the DPLL 600 aligns O DTC with rising edges of the RF 180 when the SEL ED is high and with rising edges of the RF 0 when the SEL ED is low. The proposed random edge injection technique further ensures the polarity of the injection signals such that the injection pulses INJ 0 are generated when SEL ED is high and the injection pulses INJ 180 are generated when SEL ED is low. As such, the random pattern of the DTC output 602 is effectively compensated, thereby eliminating any erroneous alignment between the phases of the O DTC and the RF signals.

[0056] Along Fig. 9A and Fig. 9B, the operation of the injection control means 670 is illustrated. Particularly, Fig. 9A shows an exemplary embodiment of the injection control means 670 in a simplified block diagram, where the components of the DPLL 600 are simplified into three basic blocks in order not to repeat the DPLL 600 operation as described along Fig. 6 and Fig. 7. Generally, the injection control means 670 comprises a number pool 901 that is configured to select a number N 902 from a pool of numbers with a geometric distribution for selection. It is conceivable that the pool of numbers may comprise any random distribution. It is further conceivable that the number pool 901 may select the number N 902 from the pool of numbers in a random manner.

[0057] The injection control means 670 further comprises a nonuniform selector 903 that is configured to generate an enable signal 904 with a pulse duration corresponds to the number of clock periods based on the selected number N 902. The pulse generator 130 is then configured such that the pulse generator 130 will be enabled when the enable signal 904 is high and the pulse generator 130 will be disabled when the enable signal 904 is low.

[0058] Fig. 9B shows the timing diagram for the operations performed by the injection control means 670. The signal REF represents the reference clock signal. The signal N represents the number selected from the number pool 901. The signal EN INJ represents the enable signal. The signal P INJ represents the injection pulses in general. The signal PE represents the phase error from the TDC 630.

[0059] It can be seen that, for example, if the output of the number pool 901 is updated to 3, the pulse generator 130 is enabled for 3 cycles of the reference clock REF. The TDC 630 compares the phase difference between the reference and the RF signal, and the output is used for tuning as described above. After 3 reference cycles, the EN INJ goes low, therefore no injection pulse is sent to the oscillator 140. At this moment, the TDC output represents the phase (frequency) error of the oscillator 140 and the oscillator frequency is tuned, which further reduces the reference spur level. After that, a new number N is selected, e.g. 5 as shown, in order to prevent quasi static states from occurring.

[0060] Along Fig. 10A and Fig. 10B, measurement results are illustrated for the output spectrum indicating the spur level reduction by means of the proposed random edge injection technique. In particular, Fig. 10A shows the fractional spur level for two output spectrums, where the first spectrum 1001 represents the DPLL output without the proposed random edge injection technique and the second spectrum 1002 represents the DPLL output with the proposed random edge injection technique. Fig. 10B shows the reference spur level at the DPLL output 1003 where the proposed random edge injection technique is implemented.

[0061] Fig. 10A shows the fractional spur at 2.434GHz where the fractional part is 2MHz. It can be seen that the fractional spur is -34dBc at the DPLL output 1001 if the random edge injection technique is not implemented. Whereas, the fractional spur is -44dBc at the DPLL output 1002 where the proposed random edge injection technique is implemented. From Fig. 10B, it can be seen that the reference spur at the DPLL output is -51dBc.

[0062] In Fig. 11, an exemplary embodiment of the method according to the third aspect of the invention is illustrated. In a first step S1, a clock signal is provided. In a second step S2, a delayed clock signal is generated from the clock signal. In a third step S3, a phase select signal is generated with a random pulse sequence. In a fourth step S4, injection pulses are generated from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

[0063] Particularly, a first set of injection pulses are generated for one phase of the at least two phases of the oscillator when the phase select signal is high and a second set of injection pulses are generated for other phase of the at least two phases of the oscillator when the phase select signal is low.

[0064] The embodiments of the present invention can be implemented by hardware, software, or any combination thereof. Various embodiments of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or the like.

[0065] Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

Claims

1. A circuit (100) for facilitating random edge injection locking of an oscillator (140) comprising: a digitally controlled delay line (110) configured to receive a clock signal (101) and further to delay the clock signal (101), thereby generating a delayed clock signal (102), an edge selector (120) configured to generate a phase select signal (103) with a pulse sequence, and a pulse generator (130) downstream to the digitally controlled delay line (110) configured to generate injection pulses (104,105) from the delayed clock signal (102) for at least two phases of the signals generated by the oscillator (140) based on the phase select signal (103), characterised in that said edge selector is configured to generate said phase select signal with a random pulse sequence.

2. The circuit according to claim 1, wherein the pulse generator (130) is further configured to generate a first set of injection pulses (104) for one phase of the at least two phases of the signals generated by the oscillator (140) when the phase select signal (103) is high and a second set of injection pulses (105) for an other phase of the at least two phases of the signals generated by the oscillator (140) when the phase select signal (103) is low.

3. The circuit according to claim 1 or 2, wherein the circuit further comprises control means (150) configured to tune a delay of the digitally controlled delay line (110) based on a duty cycle of the clock signal (101) in order to compensate at least one half of oscillator period when injecting the injection pulses (104,105) from one phase to the other phase of the at least two phases of the signals generated by the oscillator (140).

4. The circuit according to any of claims 1 to 3, wherein the edge selector (120) comprises a pseudo-random binary sequence generator and the phase select signal (103) preferably comprises a pseudo-random binary sequence.

5. A digital phase locked loop (600) comprising: a reference clock signal (601), a digital to time converter (610) configured to delay the reference clock signal (601), thereby generating a delayed reference clock signal (602), an oscillator (140) configured to generate radio frequency signals (606,607) at at least two phases, a time to digital converter (630) configured to generate an error signal by comparing an edge of the delayed reference clock signal (602) and an edge of the radio frequency signals (606,607), and a circuit (100) according to claims 1 to 4 configured to input the delayed reference clock signal (602) and further to perform random edge injection locking of the oscillator (140)6. The digital phase locked loop according to claim 5, wherein the digital phase locked loop (600) further comprises a feedback path (609) from the time to digital converter (630) to a loop filter (640), and wherein the loop filter (640) is configured to tune the oscillator (140) based on the error signal generated by the time to digital converter (630).

7. The digital phase locked loop according to claim 5 or 6, wherein the digital phase locked loop (600) further comprises injection control means (670) configured to control the generation of injection pulses at the pulse generator (130).

8. The digital phase locked loop according to claim 7, wherein the injection control means (670) is further configured to enable or disable the generation of injection pulses at the pulse generator (130) for a predefined number of cycles of the reference clock signal (601).

9. The digital phase locked loop according to any of claims 5 to 8, wherein the oscillator (140) is an inverter-based oscillator, preferably an inverter-based ring oscillator, more preferably a quadrature four-stage ring oscillator operable with a minimum phase separation equal to pi / 2.

10. The digital phase locked loop according to any claims 5 to 9, wherein the oscillator is a multi-phase oscillator (540) and wherein the pulse generator (130) is configured to generate injection pulses for phases of the multi-phase oscillator (540) based on the phase select signal (103).

11. The digital phase locked loop according to claim 10, wherein the circuit further comprises switching means (510) downstream to the pulse generator (130) in order to inject the injection pulses at the phases of the multi-phase oscillator (540), and wherein the switching means (510) is configured to be operable via a random switching logic (503).

12. The digital phase locked loop according to any of claims 5 to 11, wherein the digital phase locked loop (600) is an injection-locked fractional-N digital phase locked loop, preferably, an injection-locked ring-oscillator based fractional-N digital phase locked loop.

13. A method for facilitating random edge injection locking of an oscillator comprises the steps of: providing a clock signal, generating a delayed clock signal, generating a phase select signal with a pulse sequence, and generating injection pulses from the delayed clock signal for at least two phases of the signals generated by the oscillator based on the phase select signal, characterised in that said phase select signal has a random pulse sequence.

14. The method according to claim 13, wherein the method further comprises the steps of: generating a first set of injection pulses for one phase of the at least two phases of the signals generated by the oscillator when the phase select signal is high, and generating a second set of injection pulses for an other phase of the at least two phases of the signals generated by the oscillator when the phase select signal is low.

15. The method according to claim 13 or 14, wherein the method further comprises the step of compensating at least one half of oscillator period when injecting the injection pulses from one phase to the other phase of the at least two phases of the signals generated by the oscillator.