Semiconductor substrate arrangement and method for its preparation
Patent Information
- Application Number
- DE602020072840
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2020-08-06
- Publication Date
- 2026-06-03
- Estimated Expiration
- 2040-08-06
AI Technical Summary
Power semiconductor module arrangements face issues with cracks in solder connections due to differing coefficients of thermal expansion (CTEs) among materials, leading to mechanical and electrical connection failures.
A substrate arrangement with a dielectric insulation layer and a first metallization layer featuring protrusions and recesses, where a connection layer covers these features, and a hollow rivet is positioned to redirect stress, preventing cracks by redirecting strain from a purely horizontal direction to a partly vertical direction.
The solution significantly reduces the risk of cracks in the connection layer, enhancing the mechanical and electrical stability of the substrate arrangement, thereby improving the reliability and performance of power semiconductor modules.