Device with elements for compensating local variability of electrostatic potential

Description

TECHNICAL FIELD AND PRIOR ART

[0001] The invention relates to the field of electrostatic control gate devices. The invention applies in particular to the field of quantum devices, quantum information processing and quantum computing.

[0002] Quantum computing is based on the use of a quantum state with two measurable levels as an information carrier, called a qubit or quantum bit, and the laws of quantum mechanics (superposition, entanglement, measurement) to execute algorithms. A quantum device with spin qubits allows the quantum state of these qubits to be manipulated.

[0003] Spin qubits can be formed in semiconductors, advantageously silicon. Semiconductor technologies are being studied for the production of qubits due to their high integration potential, similar to classical electronics. Electrons or holes are individually confined in quantum wells located in a cryostat at cryogenic temperatures (below 4 K, or even below 1 K) and produced within confinement structures of nanometric sizes defined electrostatically and, in the case of silicon, with an architecture close to that of MOSFETs. These confinement structures correspond to quantum dots. A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.

[0004] The application of a static magnetic field (for example between 100 mT and 1 T) makes it possible to lift the spin degeneracy of the quasi-particles, thus forming a quantum system with two measurable levels, called "spin down" and "spin up". The quantum state of the quantum system is a superposition of these two states represented by the direction of an arrow within a sphere, called a Bloch sphere. The manipulation (rotation) of these spins is carried out using an alternating component of the magnetic field (of frequency for example between 1 GHz and several tens of GHz) or using an alternating electric field at the same frequencies in the case of a sufficient spin-orbit interaction (case of holes in silicon for example). Reading the spins (up or down) makes it possible to extract part of the quantum information according to its probability of being in each state, determined by the quantum superposition.

[0005] To achieve good performance with large numbers of qubits, qubits are preferably arranged in a 2D matrix, with potential barriers separating the qubits. These barriers and quantum wells are defined by locally applying electrostatic potentials to the semiconductor regions in which the barriers and wells are formed. With such an arrangement, individually controlling N qubits requires the creation of at least N electrostatic control gates. However, this becomes problematic when the number of qubits becomes large, for example, greater than 100.

[0006] To address the problem of the number of control gates to be produced, it has been proposed to produce these gates in the form of a grid arranged parallel to the semiconductor layer used to form the qubits. First gates comprise first conductive portions arranged in rows and second gates comprise second conductive portions arranged in columns. The first and second conductive portions are produced in two distinct levels and separated from each other by a dielectric layer. Individual control of each of the qubits is possible by simultaneously controlling the four potential barriers located around each qubit, via the electrostatic potentials applied by the four gates formed around the qubit to be controlled.

[0007] This row and column architecture of the gates requires parallel control of all the tunnel barriers of the same row or column via the application of a single electrical potential on the conductive portion forming the control gate of these tunnel barriers. This assumes that the operating points of the qubits are known and contained within a small polarization range. However, the disorder generated in particular by the densities of states at the interface between the semiconductor, in which the potential barriers and quantum dots are formed, and the gate dielectrics, but also by the charges present in the gate dielectrics or the fluctuations in the gate work function, induces local modifications of the electrostatic potential which prevent the charges from being confined in the same way inside the quantum dots.This observed local stochastic disorder is of the same order of magnitude as the confinement voltages and is therefore particularly troublesome because it prevents the use of a wide polarization range for all qubits.

[0008] The paper JM Boter et al., "A sparse spin qubit array with integrated control electronics," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 31.4.1-31.4.4, describes a solution proposing, to account for local variability, that each qubit has its own bias voltage generation unit, which allows for the local generation of voltages adapted to each local disorder configuration. However, this requires the qubits to be separated from each other by a distance of the order of a few microns. Since this distance is too large for the qubits to interact with each other, it is therefore necessary to add a long-distance transport module for quantum information to move the qubits to an interaction site during operations between two qubits. This solution has several drawbacks: the feasibility of the long-distance communication module in silicon has not been demonstrated, the proposed solution requires the production of digital-analog converters and analog-digital converters in the form of local electronic blocks resulting in high energy consumption. This also requires operating the device at high temperature (above 1K), which has the counterpart of degrading the performance of the device, the number of interconnection wires coming out of the quantum chip is greater than that of the row and column architecture of the gates, which potentially leads to an increase in cryogenic power consumption, an increase in noise and a complexity of the assemblies.

[0009] The paper M. Veldhorst et al., “Silicon CMOS architecture for a spin-based quantum computer,” Nat Commun 8, 1766 (2017), proposes, to correct local variability, the application of a local voltage to each qubit. This voltage is applied via a transistor connected to a capacitor accessed by a transistor located above the qubit plane, in the interconnections. However, this solution is difficult to achieve given the small dimensions required for the realization of the transistors. Indeed, the pitch of a qubit network is of the order of 100 nm. The proposed solution requires the realization, in the interconnection levels, of four transistors for each qubit, which is not feasible with current technologies.

[0010] Similar problems to those discussed above for quantum devices also arise for other types of electrostatic control gate devices. STATEMENT OF THE INVENTION

[0011] An object of the present invention is to provide an electrostatic control grid device in which the local variability of electrostatic potential is compensated, and which does not have the disadvantages of the prior art devices previously described.

[0012] For this, the present invention proposes a device comprising at least: a semiconductor layer comprising first regions, second regions arranged such that each of the first regions is delimited by two of the second regions aligned parallel to a first direction and that two of the neighboring first regions aligned parallel to the first direction are delimited by one of the second regions, and third regions arranged such that each of the first regions is delimited by two of the third regions aligned parallel to a second direction different from the first direction (and not parallel to the first direction) and that two of the first regions aligned parallel to the second direction are delimited by one of the third regions, first electrostatic control gates comprising first conductive portions extending parallel to the second direction, directly above the second regions,second electrostatic control grids comprising second conductive portions extending parallel to the first direction, directly above the third regions, wherein each first grid comprises an electrostatic control voltage adjustment element forming first and second impedances connected in series with each other by their first ends, a second end of the first impedance being electrically coupled to the first conductive portion of the first grid and a second end of the second impedance being electrically coupled to a third conductive portion configured to apply an adjustment electrical potential to the second end of the second impedance, and wherein the value of at least one of the first and second impedances is adjustable.

[0013] In this device, it is proposed to compensate for the local variability, in each first region of the semiconductor layer, by means of an element for adjusting the electrostatic control voltage applied by each first gate. This adjustment element makes it possible to locally apply an electrical adjustment potential, which makes it possible to electrostatically control each of the second regions of the semiconductor layer, taking into account the local variability.

[0014] In the device described above, the first conductive portions are arranged directly above the second regions. In other words, considering projections of the first conductive portions and the second regions in a plane parallel to the front face of the semiconductor layer and which passes through this front face, at least a portion of these projections are superimposed. The same is true for the second conductive portions which are arranged directly above the third regions.

[0015] A quantum device is also proposed comprising at least: a matrix of qubits made in a semiconductor layer and arranged in rows and columns, each qubit comprising at least one quantum dot, first potential barriers arranged such that each quantum dot is delimited by two first potential barriers aligned parallel to the columns of qubits and that two neighboring quantum dots of the same column are delimited by a first potential barrier, and whose potential energy levels are controlled by first electrostatic control gates comprising first conductive portions extending parallel to the lines of qubits, second potential barriers arranged such that each quantum dot is delimited by two second potential barriers aligned parallel to the lines of qubits and that two neighboring quantum dots of the same line of qubits are delimited by a second potential barrier,and whose potential energy levels are controlled by second electrostatic control grids comprising second conductive portions extending parallel to the columns of qubits, , wherein each first grid comprises an electrostatic control voltage adjustment element forming first and second impedances connected in series with each other by their first ends, a second end of the first impedance being electrically coupled to the first conductive portion of the first grid and a second end of the second impedance being electrically coupled to a third conductive portion configured to apply an adjustment electrical potential to the second end of the second impedance, and wherein the value of at least one of the first and second impedances is adjustable.

[0016] Throughout the document, the terms "row" and "column" have been arbitrarily chosen and associated with the first and second potential barriers and with the conductive portions of the first and second grids. In a plane, the term "row" is generally associated with a horizontal arrangement and the term "column" is generally associated with a vertical arrangement. These terms should not, however, be interpreted solely according to this arrangement, but as designating, in a plane, two different orientations, for example substantially perpendicular to each other. For example, the term "row" may be associated, in a plane, with a vertical arrangement, and the term "column" may be associated with a horizontal arrangement.

[0017] Throughout this document, the terms "conductive" and "conductor" shall be interpreted as meaning "electrically conductive" and "electrically conductive."

[0018] The third conductive portions may extend parallel to the first direction.

[0019] Considering the device set out above, the electrostatic control voltage adjustment elements of the first gates controlling the potential energy levels of first potential barriers delimiting the quantum boxes of the same column of qubits may comprise a third conductive portion common to these elements and extending parallel to the columns of qubits.

[0020] The device may further comprise first dielectric portions each arranged between one of the third conductive portions and one of the second conductive portions, each second conductive portion being able to be arranged between the semiconductor layer and one of the first dielectric portions.

[0021] The device may further comprise second dielectric portions, each arranged between one of the third conductive portions and the first conductive portions.

[0022] The electrostatic control voltage adjustment element of each first grid may comprise a memory element forming one of the first and second impedances whose value is adjustable.

[0023] In this case, in each first grid, the memory element may be in direct contact with the third conductive portion or the first conductive portion.

[0024] The electrostatic control voltage adjustment element of each first gate may comprise a fourth conductive portion comprising a first end electrically coupled to the memory element and: a second end electrically coupled to the first conductive portion of said first gate when the memory element is in direct contact with the third conductive portion, and forming the other of the first and second impedances, or a second end electrically coupled to the third conductive portion of said first gate when the memory element is in direct contact with the first conductive portion, and forming the other of the first and second impedances.

[0025] In the above configuration, the other of the first and second impedances is formed at the interface between the fourth conductive portion and the first or third conductive portion. The fixed value of this other of the first and second impedances can be adjusted by surface treatment or dielectric deposition.

[0026] The first and second gates may comprise gate dielectrics formed by a same gate dielectric layer disposed between the second conductive portions and the semiconductor layer and between the fourth conductive portions and the semiconductor layer.

[0027] The memory elements can be non-volatile memories of the OxRAM or FeRAM or PCRAM type.

[0028] The first regions can be arranged in rows and columns, and the first direction can be perpendicular to the second direction.

[0029] In a particular configuration: the device corresponds to a quantum device, the first regions form quantum dots, the second regions form first potential barriers, and the third regions form second potential barriers.

[0030] There is also provided a method for producing a device, comprising at least the implementation of the following steps from a semiconductor layer comprising first regions, second regions arranged such that each of the first regions is delimited by two of the second regions aligned parallel to a first direction and that two of the neighboring first regions aligned parallel to the first direction are delimited by one of the second regions, and third regions arranged such that each of the first regions is delimited by two of the third regions aligned parallel to a second direction different from the first direction and that two of the first regions aligned parallel to the second direction are delimited by one of the third regions: production, on the semiconductor layer, of first electrostatic control grids comprising first conductive portions extending parallel to the second direction, directly above the second regions, production, on the semiconductor layer, of second electrostatic control grids comprising second conductive portions extending parallel to the first direction, directly above the third regions, wherein each first grid comprises an electrostatic control voltage adjustment element forming first and second impedances connected in series with each other by their first ends, a second end of the first impedance being electrically coupled to the first conductive portion of the first grid and a second end of the second impedance being electrically coupled to a third conductive portion, and wherein the value of at least one of the first and second impedances is adjustable.

[0031] A method of producing a quantum device is also proposed, comprising at least the implementation of the following steps: production, in a semiconductor layer, of a matrix of qubits arranged in rows and columns, each qubit comprising at least one quantum dot, production of first potential barriers arranged such that each quantum dot is delimited by two first potential barriers aligned parallel to the columns of qubits and that two neighboring quantum dots of the same column are delimited by a first potential barrier, and whose potential energy levels are controlled by first electrostatic control gates comprising first conductive portions extending parallel to the lines of qubits, production of second potential barriers arranged such that each quantum dot is delimited by two second potential barriers aligned parallel to the lines of qubits and that two neighboring quantum dots of the same line are delimited by a second potential barrier,and whose potential energy levels are controlled by second electrostatic control grids comprising second conductive portions extending parallel to the columns of qubits, , wherein each first grid comprises an electrostatic control voltage adjustment element forming first and second impedances connected in series with each other by their first ends, a second end of the first impedance being electrically coupled to the first conductive portion of the first grid and a second end of the second impedance being electrically coupled to a third conductive portion configured to apply an adjustment electrical potential to the second end of the second impedance, and wherein the value of at least one of the first and second impedances is adjustable.

[0032] The second grids and the third conductive portions can be made by implementing the following steps: producing, on the semiconductor layer, a stack of layers comprising at least, in this order, a gate dielectric layer arranged against the semiconductor layer, a first conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer, etching the stack of layers with a stop on the gate dielectric layer, such that the remaining portions of the stack of layers form the second conductive portions arranged against the semiconductor layer, first dielectric portions arranged on the second conductive portions, third conductive portions arranged on the first dielectric portions, and second dielectric portions arranged on the third conductive portions.

[0033] The method may further comprise, after the production of the second grids and the third conductive portions: production of dielectric spacers against lateral faces of the remaining portions of the stack of layers, etching, for example lateral directional or lateral isotropic, of a portion of the dielectric spacers located against one of the lateral faces of the remaining portions of the stack of layers, forming an access to a lateral face of each third conductive portion, conformal deposition of a third conductive layer, covering the remaining portions of the stack of layers, the dielectric spacers, portions of the gate dielectric layer not covered by the remaining portions of the stack of layers and the dielectric spacers, and said lateral face of each third conductive portion, etching of the third conductive layer such that remaining portions of the third conductive layer extend parallel to the qubit lines and comprise portions arranged above the second regions,depositing a third dielectric layer on the remaining portions of the third conductive layer, on parts of the gate dielectric layer not covered by the remaining portions of the stack of layers, the dielectric spacers and the remaining portions of the third conductive layer, and on parts of the remaining portions of the stack of layers and the dielectric spacers not covered by the remaining portions of the third conductive layer, planarizing the third dielectric layer and the remaining portions of the third conductive layer with a stop on the second dielectric portions, producing third dielectric portions and fourth conductive portions forming the other of the first and second impedances.

[0034] In a first embodiment, the method may further comprise, after planarization of the third dielectric layer and the remaining portions of the third conductive layer: removing a portion of the fourth conductive portions, forming cavities of which a portion of the side walls is formed by said side face of each third conductive portion, producing, in the cavities, memory elements each forming part of the electrostatic control voltage adjustment element of one of the first gates and electrically coupled to a first end of the fourth conductive portion of said electrostatic control voltage adjustment element, and fourth dielectric portions arranged on the memory elements, producing the first conductive portions such that they are in contact with second ends of the fourth conductive portions.

[0035] In a second embodiment, the method may further comprise, after planarization of the third dielectric layer and the remaining portions of the third conductive layer: removal of a portion of the fourth conductive portions, forming cavities of which a portion of the side walls is formed by said side face of each third conductive portion, deposition of fourth dielectric portions in the cavities, production of memory elements each forming part of the electrostatic control voltage adjustment element of one of the first gates and electrically coupled to a first end of the fourth conductive portion of said electrostatic control voltage adjustment element, production of the first conductive portions such that they are in contact with the memory elements.

[0036] Also provided is a method of controlling a device as previously disclosed, wherein: the device forms a quantum device, the first regions form quantum dots, the second regions form first potential barriers, the third regions form second potential barriers, and wherein the value of said at least one of the first and second impedances is adjusted and electrical potentials are applied to the first and second gates to control the quantum dots.

[0037] Generally, throughout this document, the term "layer" should be understood to mean either a single layer of material or a stack of several distinct layers of material. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be better understood by reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which: There figure 1 schematically represents part of a device according to the invention. The Figures 2 and 3 schematically represent the operating principle of a first electrostatic control grid of a device according to first and second embodiments. The Figures 4 and 5 schematically represent two exemplary embodiments of the first electrostatic control grid of a device according to the first and second embodiments. The figures 6 to 13 schematically represent steps of a method of producing a device according to the first embodiment. The figures 14 and 15schematically represent part of the steps of a method for producing a device according to the second embodiment.

[0039] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0040] The different parts represented in the figures are not necessarily on a uniform scale, to make the figures more readable.

[0041] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other. DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0042] A device 100 comprising elements for compensating for local variability of electrostatic potential is described below in connection with the figure 1. In the exemplary embodiment described here, the device 100 corresponds to a quantum device with a qubit matrix.

[0043] The device 100 comprises a semiconductor layer, or substrate, 102 comprising first regions 104, second regions 106 and third regions 110. The second regions 106 are arranged such that each of the first regions 104 is delimited by two of the second regions 106 aligned parallel to a first direction and that two of the neighboring first regions 104 aligned parallel to the first direction are delimited by one of the second regions 106. The third regions 110 are arranged such that each of the first regions 104 is delimited by two of the third regions 110 aligned parallel to a second direction different from the first direction and that two of the first regions 104 aligned parallel to the second direction are delimited by one of the third regions 110.

[0044] The layer 102 comprises, for example, silicon, germanium or SiGe. Other semiconductors may be used. Alternatively, the layer 102 may correspond to a stack of several layers each comprising silicon and / or germanium, or other semiconductor materials. The thickness of the layer 102 may be between 5 nm, for example when the layer 2 corresponds to a surface layer of an SOI substrate, and 775 µm, for example when the layer 102 corresponds to a bulk substrate or a heterostructure.

[0045] In the embodiment described here, a matrix of qubits is produced in the semiconductor layer 102, and arranged in lines (parallel to the X axis in the example of the figure 1 ) and columns (parallel to the Y axis in the example of the figure 1). The rows are parallel to the second direction, and the columns are parallel to the first direction. The number of rows and / or the number of columns of qubits in this matrix can be between 3 and 10000.

[0046] Each first region 104 of the layer 102 forms, in the exemplary embodiment described, at least one quantum dot. On the figure 1 , one of the first 104 regions is symbolically represented by dotted lines.

[0047] The second regions 106 of the layer 102 form, in the described embodiment, first potential barriers. These first barriers are arranged such that each quantum box is delimited by two of the first barriers aligned parallel to the columns of qubits and that two neighboring quantum boxes of the same column of qubits are delimited by one of the first barriers.

[0048] On the figure 1, two second regions 106 are symbolically represented by dotted lines.

[0049] The potential energy levels of the second regions 106 are controlled by first electrostatic control gates comprising in particular first conductive portions 108 extending parallel to the second direction, i.e. parallel to the qubit lines in the embodiment described. On the figure 1 , three first conductive portions 108 are shown. The first conductive portions 108 each have, for example, a thickness (dimension parallel to the Z axis shown on the figure 1 ) between 5 nm and 200 nm and a width (dimension parallel to the Y axis on the figure 1 ) between 10 nm and 50 nm. The first conductive portions 108 are for example produced with a pitch between 30 nm and 120 nm. The first conductive portions 108 are arranged directly above the second regions 106.

[0050] The third regions 110 of the layer 102 form, in the described embodiment, second potential barriers. These second barriers are arranged such that each quantum box is delimited by two of the second barriers aligned parallel to the qubit lines and that two neighboring quantum boxes of the same qubit line are delimited by one of the second barriers.

[0051] On the figure 1 , two third regions 110 are symbolically represented by dotted lines.

[0052] The potential energy levels of the third regions 110 are controlled by second electrostatic control gates comprising in particular second conductive portions 112 extending parallel to the first direction, i.e. parallel to the columns of qubits in the embodiment described here. On the figure 1, three second conductive portions 112 are shown. The second conductive portions 112 each have, for example, a thickness (dimension parallel to the Z axis shown on the figure 1 ) between 5 nm and 200 nm and a width (dimension parallel to the X axis on the figure 1 ) between 10 nm and 50 nm. The second conductive portions 112 are for example produced with a pitch between 30 nm and 120 nm. According to an exemplary embodiment, each of the second conductive portions 112 comprises a stack of a portion of metal, advantageously superconducting, such as TiN or NbN, with a thickness between 1 nm and 50 nm, advantageously between 2 nm and 5 nm, and a portion of polysilicon between 2 nm and 50 nm, advantageously between 5 nm and 10 nm. The second conductive portions 112 are arranged directly above the third regions 110.

[0053] The locations and dimensions of the second and third regions 106, 110 are determined by the locations and dimensions of the first and second electrostatic control grids. In addition, the locations and dimensions of the first regions 104 are determined by the locations and dimensions of the second and third regions 106, 110.

[0054] Although this is not visible on the figure 1 , the first conductive portions 108 are produced in a level separate and electrically isolated from that in which the second conductive portions 112 are produced.

[0055] Separate electrical potentials are applied to each of the first and second conductive portions 108, 112 to electrostatically control each of the first and second barriers formed by the second and third regions 106, 110.

[0056] In order to be able to correct the local variability of electrostatic potential at the level of each qubit of the matrix, each first gate comprises an electrostatic control voltage adjustment element making it possible to adjust the potential electrostatically controlling each of the first barriers 106.

[0057] There figure 2 schematically represents the operating principle of one of the first grids of the device 100 according to a first embodiment.

[0058] In the device 100, a constant electrical potential is applied to each first conductive portion 108. This potential is the same for all the first grids of the row which comprise this first conductive portion 108. In the example of the figure 2, this electric potential is called Vrj. Thanks to the electrostatic control voltage adjustment element present in each first grid, the value of this electric potential is adapted locally at the level of each of the first grids so that the value of the electric potential electrostatically controlling the potential energy level in the corresponding second region 106 corrects the local variability in this region.

[0059] On the example of the figure 2, this adaptation of Vrj is carried out by an element forming first and second impedances Z1 and Z2 connected in series to each other at their first ends. The potential Vrj is applied to the second end of the first impedance Z1. An electric potential Vci* is applied to the second end of the second impedance Z2 from a third conductive portion 118. This electric potential Vci* is the same for all the first grids aligned in the first direction, that is to say located for example on the same column. This electric potential Vci* has a dual role: it is used firstly to program the value of the memory element, and secondly, it participates in the definition of the potential Vrji defined below. It may advantageously be polarized to ground in this second stage.The adapted electric potential electrostatically controlling the potential energy level of the first barrier 106 corresponds to the potential called “Vrji” obtained at the first ends of the first and second impedances Z1 and Z2 and which is equal to: . Vr ji = Z 2 Z 1 + Z 2 Vr j − Vc i ∗

[0060] In the first embodiment shown in the figure 2 , the value of the second impedance Z2 is adjustable and that of the first impedance Z1 is constant.

[0061] There figure 3 schematically represents the operating principle of one of the first grids of the device 100 according to a second embodiment. This operation is similar to that described previously in connection with the figure 2 , except that the value of the first impedance Z1 is adjustable and that of the second impedance Z2 is constant.

[0062] There figure 4schematically represents an exemplary embodiment of one of the first grids of the device 100 according to the first embodiment.

[0063] A gate dielectric layer 114 is arranged on the semiconductor layer 102. The gate dielectric layer 114 comprises, for example, SiO 2 and has, for example, a thickness of between 2 nm and 20 nm. This gate dielectric layer 114 is used to form the gate dielectrics of the first and second gates, and may cover the entire surface of the semiconductor layer 102. Alternatively, this layer 114 may comprise a stack of semiconductors intended to form a potential barrier between the conductive layers formed on the layer 114 and the semiconductor layer 102 in which the quantum dots are formed. This stack of semiconductors may contain SiGe layers with a thickness of between 5 nm and 50 nm with Ge % of between 10% and 50%.

[0064] The second conductive portions 112 are arranged on this grid dielectric layer 114. In the diagram of the figure 4, the second conductive portions 112 extend parallel to the Y axis (they have a larger dimension parallel to the Y axis), that is to say here parallel to the columns of qubits of the device 100.

[0065] First dielectric portions 116 are arranged on the second conductive portions 112. The first dielectric portions 116 comprise, for example, SiO 2 . The thickness (dimension parallel to the Z axis) of each of the first dielectric portions is, for example, between 5 nm and 50 nm, and advantageously between 5 nm and 15 nm.

[0066] The third conductive portions 118 are arranged on the first dielectric portions 116 which provide electrical insulation between the second and third conductive portions 112, 118. These third conductive portions 118 have, for example, materials and dimensions similar to the second conductive portions 112.

[0067] Second dielectric portions 120 are arranged on the third conductive portions 118. The first conductive portions 108 rest partly on the second dielectric portions 120 which thus provide electrical insulation between the first and third conductive portions 108, 118. These second dielectric portions 120 comprise for example SiO 2 , SiN, or Al 2 O 3 , and have for example a thickness (dimension parallel to the Z axis) of between 10 nm and 100 nm, and advantageously of between 5 and 30 nm.

[0068] In the embodiment described here, the first and second dielectric portions 116, 120 and the third conductive portions 118 have, in the plane (X, Y), a shape and dimensions similar to those of the second conductive portions 112. Thus, in the diagram of the figure 4, the first and second dielectric portions 116, 120 and the second and third conductive portions 112, 118 extend parallel to the Y axis, i.e. here parallel to the first direction or, in the embodiment described, to the columns of qubits of the device 100.

[0069] The electrostatic control voltage adjustment elements of the first gates controlling the potential energy levels in the second regions 106 delimiting first regions 104 aligned parallel to the first direction, i.e. of the same column of qubits in the example described here, comprise one of the third conductive portions 118 which extends parallel to the columns of qubits and which is common to the first gates of the same column. These third conductive portions 118 are used to apply the electric potential Vci* intended in particular to compensate for the local variability at the level of the qubit controlled by each of the first gates. The value of this electric potential will be the same for all the first gates which share the same third conductive portion 118.

[0070] The voltage adjustment element of each of the first grids also comprises a memory element 122. In the first embodiment described here, the memory element 122 forms the second impedance Z2 whose value is adjustable. This memory element 122 is electrically coupled to the third conductive portion 118 at one of the lateral faces 138 (faces parallel to the plane (Y, Z) in the example of the figure 4 ) of the third conductive portion 118. The memory element 122 is directly in contact with the third conductive portion 118.

[0071] According to a particular embodiment, the memory element 122 may be a resistive non-volatile memory of the OxRAM type (oxide-based resistive memory), corresponding in this case to a variable resistance, or of the FeRAM type (ferroelectric layer memory) or PCRAM (phase change material memory), corresponding in this case to a variable capacitance. The memory element 122 corresponds for example to a portion of HfO 2 or HfZrO 2 or any other dielectric material having memory effects, covered with a metal electrode comprising for example Ti.

[0072] The voltage adjustment element of each of the first grids also comprises a fourth conductive portion 124. In the exemplary embodiment of the figure 4, the first impedance Z1 whose value is constant corresponds to the contact resistance between the fourth conductive portion 124 and the first conductive portion 108. The fourth conductive portion 124, in contact with the memory element 122, forms a second metal electrode in contact with the portion of dielectric material with memory effect of the memory element 122. The fourth conductive portion 124 advantageously comprises a superconducting material such as TiN, NbN or Nb or Ti or a stack of several of these materials (and advantageously with Ti which provides oxygen vacancies subsequently used for the memory effect of the memory element 122). The use of a superconducting material to form the fourth conductive portion 124 makes it possible to guarantee a constancy of the value of the potential which will make it possible to control the first barriers 106.The fourth conductive portion 124 may come from a layer of material deposited conformally with a thickness of between 2 nm and 20 nm, and advantageously equal to 5 nm.

[0073] In addition to these elements, the device 100 comprises dielectric spacers 126, 127 arranged against lateral faces of the stacks formed of the second and third conductive portions 112, 118 and of the first and second dielectric portions 116, 120. The dielectric spacers 126, 127 comprise, for example, SiN and / or SiO 2 and / or a material with low dielectric permittivity such as SiCO or SiCBN. For each of these stacks, one of the dielectric spacers 127 is partially etched such that one of the lateral faces 138 of each third conductive portion 118 is not covered by this spacer 127 and is in electrical contact with one of the memory elements 122.

[0074] The device 100 also comprises third dielectric portions 128 which in particular provide electrical insulation between the memory elements 122 and the first conductive portions 108. The third dielectric portions 128 comprise, for example, SiO 2 .

[0075] In addition to the first and second impedances Z1 and Z2 formed in this structure, a leakage path of impedance Z3 can be formed between the end of the fourth conductive portion 124 coupled to the memory element 122 and the third conductive portion 118. In order to have the value of the impedance Z3 which is much greater than those of the impedances Z1 and Z2, to avoid malfunctions of the device 100, the fourth conductive portion 124 is produced in such a way that it is remote and well electrically insulated from the third conductive portion 118, as described later in connection with the method of producing the device 100.

[0076] There Figure 5 schematically represents an exemplary embodiment of one of the first grids of the device 100 according to the second embodiment.

[0077] Each of the first gates of the device 100 according to the second embodiment comprises all the elements previously described for the first gates of the device 100 according to the first embodiment. However, in this second embodiment, in each voltage adjustment element of the first gates, the memory element 122 is not in direct contact with the third conductive portion 118 but with the first conductive portion 108. In addition, the fourth conductive portion 124 is directly coupled to the third conductive portion 118.

[0078] Thus, in this second embodiment, the value of the impedance Z1, formed by the memory element 122, is adjustable and that of the impedance Z2, formed by the contact resistance between the third and fourth conductive portions 118, 124, is constant.

[0079] For example, whatever the embodiment of the device 100: the value of the potential Vrji can be between -1V and 1 V, the value of the variable value impedance, formed by the memory element 122, can be between a few kΩ and a few GΩ, the value of the constant value impedance, formed by the contact resistance between the fourth conductive portion 124 and the third conductive portion 118 or the first conductive portion 108, can be between a few kΩ and a few MΩ, for example between 5 kΩ and 5 MΩ.

[0080] In order to be able to compensate for the local variability in each first region 104, it is necessary to determine the values ​​of the variable impedance as well as the values ​​of the potentials Vci* to be applied. For this, it is for example possible to: first characterize all the first semiconductor regions 104 via the implementation of stability diagram measurements carried out using the first and second gates of the device 100, with the aim of determining which voltage levels applied to these gates allow access to the charge energies and input voltages of the first electron, i.e. allow initialization of the qubits with one electron per quantum dot in the example described here.Furthermore, this characterization step can also make it possible to determine the individual bias voltages which will make it possible to control each qubit, to individually program the variable impedances formed by the memory elements 122, via the application of voltages to its terminals through the first, third and fourth conductive portions 108, 118, 124, to allow each potential Vrji applied locally to lead to the same configuration of the control potential of the second and third regions 106, 110 for the applied voltages Vrj and Vci, during operation of the device 100, to apply the calculated voltage levels Vrj, Vci and Vci* making it possible to obtain the local variability compensation for each first region 104.

[0081] For example, determining the single-electron regime of each quantum dot can be achieved by implementing a charge detection protocol within the quantum dots. To do this, it is possible to integrate charge detectors (e.g., single-electron transistors, or SETs) near the qubits. These detectors provide information on the number of charges confined in the surrounding quantum dots. For example, by measuring the current flowing through a SET while varying the voltages applied to the first and second gates of a quantum dot to which this SET is associated, it is possible to trace the voltage ranges for which a single electron is well confined in this quantum dot.If this voltage range is incompatible with that determined for other quantum boxes sharing these control grids, i.e. located on the same row or column, programming the variable impedances Z1 and Z2 will make it possible to overcome this. Other techniques are possible to determine the number of charges contained in a quantum box, for example via the use of a resonant circuit ("reflectometry circuit") connected to a control grid.

[0082] A method of producing the device 100 according to the first embodiment is described below in connection with the figures 6 to 13 .

[0083] A stack of layers, intended for the production of the gate dielectric layer 114, the first and second dielectric portions 116, 120 and the second and third conductive portions 112, 118, is produced on the layer 102 (see figure 6 ).

[0084] The gate dielectric layer 114 is first made on the layer 102, for example by thermal oxidation.

[0085] A first conductive layer 130, formed of one or more stacked conductive materials, is then deposited on the gate dielectric layer 114.

[0086] A first dielectric layer 132 is then produced on the first conductive layer 130.

[0087] A second conductive layer 134, formed from one or more stacked conductive materials, is then deposited on the first dielectric layer 132.

[0088] A second dielectric layer 136 is produced on the second conductive layer 134. This second dielectric layer 136 is intended to form the second dielectric portions 120, but will also be used to produce an etching mask and also serve as a stop layer for implementing planarization.

[0089] This stack is etched, first forming an etch mask from the second dielectric layer 136, then etching the other layers of the stack until reaching the gate dielectric layer 114. The remaining portions of the stack form the first and second dielectric portions 116, 120 and the second and third conductive portions 112, 118 (see Figures 7A and 7B , corresponding respectively to a sectional view and a top view of the structure obtained at this stage of the process).

[0090] The dielectric spacers 126 are then produced by depositing at least one dielectric material, then etching this or these dielectric materials in order to retain only portions of this or these materials arranged against the lateral flanks of the portions 112, 116, 118, 120 (see Figures 8A and 8B ).

[0091] An etching, for example lateral directional or lateral isotropic, of a part of the spacers 126 located against one of the lateral faces of the portions 112, 116, 118, 120 is implemented, forming an access to a lateral face 138 of each third conductive portion 118. On the Figures 9A and 9B , the etched spacers are designated by the reference 127. This etching can advantageously be carried out in a self-aligned manner by implementing an ion implantation forming, with respect to a straight line perpendicular to the face of the layer 114 on which the spacers 126 rest, a non-zero angle (commonly called “tilt”), or by using a directional plasma, then by implementing a reactive chemical or ion etching. Alternatively, this etching can be carried out by implementing photolithography and etching.

[0092] A layer of conductive material, for example metallic and advantageously comprising a superconductive material, is then deposited conformally, that is to say by forming a layer of constant thickness on the walls against which this layer is deposited. This layer of conductive material covers the remaining portions 112, 116, 118, 120 of the stack of layers (and in particular the lateral faces 138 of the third conductive portions 118), the dielectric spacers 126, 127, as well as the parts of the gate dielectric layer 114 not covered by the remaining portions 112, 116, 118, 120 and the dielectric spacers 126, 127. This layer of conductive material is intended to form the fourth conductive portions 124.After this deposition, this layer of conductive material is etched so that remaining portions 140 of this layer extending parallel to the qubit lines, and having parts arranged above the regions of the layer 102 in which the first barriers 106 are intended to be formed, are preserved (see . Figures 10A and 10B ).

[0093] A third dielectric layer 142, comprising for example an oxide such as SiO 2 , is then deposited on the entire structure previously produced, filling the spaces present between the stacks of the portions 112, 116, 118 and 120 and covering the remaining portions 140 of the layer of conductive material previously deposited.

[0094] A planarization of this third dielectric layer 142 and of the parts of the remaining portions 140 located on the second dielectric portions 120 is then implemented, stopping on the second dielectric portions 120. The parts of the portions 140 retained at the end of this planarization form the fourth conductive portions 124, each in electrical contact with one of the third conductive portions 118 via the lateral face 138. Remaining parts of the third dielectric layer 142 correspond to the third dielectric portions 128 (see Figures 11A and 11B ).

[0095] Parts of the fourth conductive portions 124 are then removed by etching, forming cavities 144 in the layer of dielectric material 142, part of the side walls of which are formed by the side faces 138 of the third conductive portions 118. These cavities 144 provide access to the fourth conductive portions 124 and to the third conductive portions 118 (see figure 12 ). This etching is for example preceded by photolithography. The etching implemented is for example of the selective RIE (reactive ion etching) type or a chemical etching implemented for example with a solution of HCl or H 2 O 2 and the etching speed of which is controlled in order to etch these parts of the fourth conductive portions 124 without etching the third conductive portions 118. This etching is stopped when the bottom walls of the cavities 144 reach at least the first dielectric portions 116.

[0096] The memory elements 122 are then produced in the cavities 144, for example by depositing HfO 2 , HfZrO 2 or any other dielectric material having a memory effect, then a metal electrode comprising for example Ti. The memory elements 122 are produced without completely filling the cavities 144 in order to limit leaks with the future first conductive portions 108 which will be produced subsequently. For this, a distance of at least 5 nm between the upper face of the memory elements 122 and the upper face of the second dielectric portions 120 can for example be maintained. The remaining empty spaces above the memory elements 122 are filled with dielectric material, forming fourth dielectric portions 146 arranged on the memory elements 122 (see figure 13 ).

[0097] The device 100 is completed by producing the first conductive portions 108, for example by implementing a metal deposition, lithography and etching, or by a damascene-type deposition process. Before this deposition, a surface treatment can be implemented to define the fixed values ​​of the impedances Z1 which correspond, in this first embodiment, to the contact resistances between the material of fourth conductive portions 124 and that of the first conductive portions 108. Finally, one or more Back-end type interconnection levels are produced to allow connections to the different conductive elements of the device 100.

[0098] A method of producing the device 100 according to the second embodiment is described below.

[0099] The steps previously described in connection with the figures 6 to 12 are first implemented.

[0100] The cavities 144 are then filled with a dielectric material, forming the fourth dielectric portions 146 (see figure 14 ).

[0101] A layer of dielectric material with a memory effect, for example similar to that previously described for the production of the memory elements 122 of the device 100 according to the first embodiment, is then deposited (see figure 15 ), then optionally etched in order to form the memory elements 122 coupled to the fourth conductive portions 124 to obtain a structure such as previously described in connection with the Figure 5 .

[0102] The first conductive portions 108 are then produced such that they are in contact with the memory elements 122. In this second embodiment, the first conductive portions 108 can be produced in the form of a stack of several integrating in particular a first layer comprising for example Ti and serving as electrodes for the memory elements 122.

[0103] The device 100 is completed as in the first embodiment, by producing one or more Back-end type interconnection levels allowing connections to the different conductive elements of the device 100.

[0104] In the various embodiments and examples previously described, it is possible that: the device 100 corresponds to a quantum device, the first regions 104 form quantum dots, the second regions 106 form first potential barriers, and the third regions 110 form second potential barriers.

[0105] Alternatively, the device 100 may correspond to a CMOS type device, in this case with the electrostatic control voltage adjustment element serving to modulate the gate voltage of the transistors, or the device 100 may correspond to an image sensor in which the different regions of the layer 102 form diodes.

Claims

1. A device (100) including at least: - a semiconductor layer (102) comprising first regions (104), second regions (106) arranged such that each of the first regions (104) is delimited by two of the second regions (106) aligned parallel to a first direction and that two of the neighbouring first regions (104) aligned parallel to the first direction are delimited by one of the second regions (106), and third regions (110) arranged such that each of the first regions (104) is delimited by two of the third regions (110) aligned parallel to a second direction different from the first direction and that two of the first regions (104) aligned parallel to the second direction are delimited by one of the third regions (110); - first electrostatic control gates including first conductive portions (108) extending parallel to the second direction, in vertical alignment with the second regions (106); - second electrostatic control gates including second conductive portions (112) extending parallel to the first direction, in vertical alignment with the third regions (110); wherein each first gate includes an electrostatic control voltage adjustment element forming first and second impedances (Z1, Z2) connected in series to each other through their first ends, a second end of the first impedance (Z1) being electrically coupled to the first conductive portion (108) of the first gate and a second end of the second impedance (Z2) being electrically coupled to a third conductive portion (118), and wherein the value of at least one of the first and second impedances (Z1, Z2) is adjustable.

2. The device (100) according to claim 1, wherein the third conductive portions (118) extend parallel to the first direction.

3. The device (100) according to claim 2, further including first dielectric portions (116) each disposed between one of the third conductive portions (118) and one of the second conductive portions (112), each of the second conductive portions (112) being disposed between the semiconductor layer (102) and one of the first dielectric portions (116).

4. The device (100) according to one of claims 2 or 3, further including second dielectric portions (120) each disposed between one of the third conductive portions (118) and the first conductive portions (108).

5. The device (100) according to one of the preceding claims, wherein the electrostatic control voltage adjustment element of each first gate includes a memory element (122) forming one of the first and second impedances (Z1, Z2) whose value is adjustable.

6. The device (100) according to claim 5, wherein, in each first gate, the memory element (122) is directly in contact with the third conductive portion (118) or the first conductive portion (108).

7. The device (100) according to one of claims 5 or 6, wherein the electrostatic control voltage adjustment element of each first gate includes a fourth conductive portion (124) comprising a first end electrically coupled to the memory element (122) and: - a second end electrically coupled to the first conductive portion (108) of said first gate when the memory element (122) is directly in contact with the third conductive portion (118), and forming the other of the first and second impedances (Z1, Z2), or - a second end electrically coupled to the third conductive portion (118) of said first gate when the memory element (122) is directly in contact with the first conductive portion (108), forming the other of the first and second impedances (Z1, Z2).

8. The device (100) according to claim 7, wherein the first and second gates include gate dielectrics formed by a same gate dielectric layer (114) disposed between the second conductive portions (112) and the semiconductor layer (102) and between the fourth conductive portions (124) and the semiconductor layer (102).

9. The device (100) according to one of claims 5 to 8, wherein the memory elements (122) are OxRAM or FeRAM or PCRAM type resistive non-volatile memories.

10. The device (100) according to one of the preceding claims, wherein the first regions (104) are arranged in rows and columns, and wherein the first direction is perpendicular to the second direction.

11. A method for making a device (100), comprising at least the implementation of the following steps from a semiconductor layer (102) comprising first regions (104), second regions (106) arranged such that each of the first regions (104) is delimited by two of the second regions (106) aligned parallel to a first direction and two of the neighbouring first regions (104) aligned parallel to the first direction are delimited by one of the second regions (106), and third regions (110) arranged such that each of the first regions (104) is delimited by two of the third regions (110) aligned parallel to a second direction different from the first direction and that two of the first regions (104) aligned parallel to the second direction are delimited by one of the third regions (110): - making, on the semiconductor layer (102), first electrostatic control gates including first conductive portions (108) extending parallel to the second direction, in vertical alignment with the second regions (106); - making, on the semiconductor layer (102), second electrostatic control gates including second conductive portions (112) extending parallel to the first direction, in vertical alignment with the third regions (110); wherein each first gate includes an electrostatic control voltage adjustment element forming first and second impedances (Z1, Z2) connected in series to each other through their first ends, a second end of the first impedance (Z1) being electrically coupled to the first conductive portion (108) of the first gate and a second end of the second impedance (Z2) being electrically coupled to a third conductive portion (118), and wherein the value of at least one of the first and second impedances (Z1, Z2) is adjustable.

12. The method according to claim 11, wherein the second gates and the third conductive portions (118) are made by implementing the following steps of: - making, on the semiconductor layer (102), a stack of layers comprising at least, in this order, a gate dielectric layer (114) disposed against the semiconductor layer (102), a first conductive layer (130), a first dielectric layer (132), a second conductive layer (134), and a second dielectric layer (136); - etching the stack of layers with a stop on the gate dielectric layer (114), such that the remaining portions of the stack of layers form the second conductive portions (112) disposed against the semiconductor layer (102), first dielectric portions (116) disposed on the second conductive portions (112), the third conductive portions (118) disposed on the first dielectric portions (116), and second dielectric portions (120) disposed on the third conductive portions (118).

13. The method according to claim 12, further including, after making the second gates and third conductive portions (118): - making dielectric spacers (126, 127) against side faces of the remaining portions (112, 116, 118, 120) of the stack of layers; - etching part of the dielectric spacers (127) located against one of the side faces of the remaining portions (112, 116, 118, 120) of the stack of layers, forming access to a side face (138) of each third conductive portion (118); - conformally depositing a third conductive layer, covering the remaining portions (112, 116, 118, 120) of the stack of layers, the dielectric spacers (126, 127), parts of the gate dielectric layer (114) not covered by the remaining portions (112, 116, 118, 120) of the stack of layers and the dielectric spacers (126, 127), and said side wall (138) of each third conductive portion (118); - etching the third conductive layer such that remaining portions (140) of the third conductive layer extend parallel to the qubit rows and include parts disposed over the second regions (106); - depositing a third dielectric layer (142) on the remaining portions (140) of the third conductive layer, on parts of the gate dielectric layer (114) not covered by the remaining portions (112, 116, 118, 120) of the stack of layers, the dielectric spacers (126, 127) and the remaining portions (140) of the third conductive layer, and on parts of the remaining portions (112, 116, 118, 120) of the stack of layers and the dielectric spacers (126, 127) not covered by the remaining portions (140) of the third conductive layer; - planarising the third dielectric layer (142) and the remaining portions (140) of the third conductive layer with a stop on the second dielectric portions (120), making third dielectric portions (128) and fourth conductive portions (124).

14. The method according to claim 13, further including, after planarising the third dielectric layer (142) and the remaining portions (140) of the third conductive layer: - removing part of the fourth conductive portions (124), forming cavities (144), part of the side walls of which are formed by said side face (138) of each third conductive portion (118); - making, in the cavities (144), memory elements (122) each being part of the electrostatic control voltage adjustment element of one of the first gates and electrically coupled to a first end of the fourth conductive portion (124) of said electrostatic control voltage adjustment element, and fourth dielectric portions (146) disposed on the memory elements (122); - making the first conductive portions (108) such that they are in contact with second ends of the fourth conductive portions (124).

15. The method according to claim 13, further including, after planarising the third dielectric layer (142) and the remaining portions (140) of the third conductive layer: - removing part of the fourth conductive portions (124), forming cavities (144), part of the side walls of which are formed by said side face (138) of each third conductive portion (118); - depositing fourth dielectric portions (146) in the cavities (144); - making memory elements (122) each being part of the electrostatic control voltage adjustment element of one of the first gates and electrically coupled to a first end of the fourth conductive portion (124) of said electrostatic control voltage adjustment element; - making the first conductive portions (108) such that they are in contact with the memory elements (122).

16. A method for controlling a device (100) according to one of claims 1 to 10, wherein: - the device (100) forms a quantum device; - the first regions (104) form quantum boxes; - the second regions (106) form first potential barriers; - the third regions (110) form second potential barriers; and wherein the value of said at least one of the first and second impedances (Z1, Z2) is adjusted and electric potentials are applied to the first and second gates to control the quantum boxes.