Non-volatile storage device that can only be read a predetermined number of times

Description

[0001] Implementations and embodiments relate to non-volatile memories, and in particular memories that can be read only once or a predefined number of times.

[0002] FR3059458A1 describes a compact non-volatile memory device of the charge trapping type in a dielectric interface. Each memory cell comprises a state transistor selectable by a vertical selection transistor buried in a substrate and having a buried selection gate. The columns of memory cells comprise pairs of twin memory cells, the two selection transistors of a pair of twin memory cells having a common selection gate, the two state transistors of a pair of twin memory cells having a common control gate.The device further comprises, for each pair of twin memory cells, a dielectric region located between the control gate and the substrate and overlapping said common selection gate so as to form on either side of the selection gate the two dielectric charge trapping interfaces respectively dedicated to the two twin memory cells.

[0003] There is a need to provide a non-volatile memory structure capable of storing multi-bit information in a manner that makes it difficult or impossible to retrieve the correct value of the stored information using a conventional memory reading method.

[0004] There is also a need to provide such a memory structure that can only be read once, or at least a predefined number of times, so as to prevent, for example, numerous repetitive readings of the memory by a malicious third party with the aim of using the stored data a large number of times to carry out fraudulent actions.

[0005] According to one aspect, there is provided a non-volatile memory device, comprising a memory plane comprising at least one memory area including an array of memory cells having two rows and N columns.

[0006] Each memory cell includes a state transistor having a control gate and a floating gate, selectable by a vertical select transistor buried in a substrate and having a buried select gate.

[0007] Each column of memory cells includes a pair of twin memory cells.

[0008] Two memory cells are said to be twins when the two selection transistors of this pair of memory cells have a common selection gate.

[0009] The memory device also comprises processing means configured to store in the memory area, information comprising a succession of N bits.

[0010] This N-bit information can include useful data to be stored in N bits, for example a key, or useful data to be stored in M ​​bits, with M less than N, and NM dummy bits having for example a predefined value.

[0011] The storage of said information is advantageously carried out so that, with the exception of the last bit of the succession, a current bit of said succession of bits is stored in two memory cells located on the same row and on two adjacent columns, and a current bit and the following bit are respectively stored in two twin cells.

[0012] Such a twin cell structure combined with this checkerboard-like filling of the memory area and redundant storage of the current bit in two memory cells, leads to a robust storage of the information and makes it difficult to restore the correct value of the information bits, especially with a conventional method of reading these memory cells.

[0013] In this regard, in order to ensure correct reading of a bit, the processing means are advantageously configured to, in order to be able to read a bit stored in a first twin cell, first replace the bit stored in the second twin cell with a reference bit having a reference value chosen to allow correct restitution of the value of the bit stored in the first twin cell. This reference value is for example the logic value 0 corresponding to a programmed state of the twin memory cell.

[0014] Indeed, since the two twin cells are selected simultaneously, the value of the bit stored in the second twin cell must not possibly "mask" (for example if this value is equal to 1) the value of the bit stored in the first twin cell.

[0015] Furthermore, the processing means are further advantageously configured to sequentially read the N bits of the information and, for each bit of the succession except the last, replace a current bit already read of said information with the reference bit, before being able to read the next bit of said succession.

[0016] Such reading with replacement of each bit already read by the reference bit, before being able to read the next bit of information, amounts to "destroying" the bits as they are read, with the exception of the last one, and therefore makes it impossible to restore the stored information again.

[0017] The memory area and therefore the memory device can only be read once to deliver the stored information only once.

[0018] Of course, according to one embodiment, it is possible for the memory device to comprise several memory areas intended to contain the same N-bit information, and the processing means are then configured to successively read the different memory areas.

[0019] Thus, with this embodiment it becomes possible to read the stored information as many times as there are memory zones.

[0020] This number of memory areas depends of course on the intended application for using the memory device.

[0021] According to one embodiment, the memory area comprises a single bit line per column connected to the drains of the state transistors of the pair of twin cells of the corresponding column, and a gate control line, per row of memory cells, connected to all the control gates of the state transistors of the memory cells of the corresponding row.

[0022] According to one embodiment, the processing means comprise a column decoder configured to individually select the two bit lines associated with the two columns located at the two ends of the memory area and to simultaneously select two adjacent bit lines, both for the operation of storing the information and for the operation of reading and prior replacement of the bits.

[0023] Such a non-limiting example of a column decoder makes it possible to implement the particular storage and reading mentioned above.

[0024] Each memory cell has a first state, for example an erased state, in which it stores a bit having a first logical value, for example the logical value 1, and a second state, for example a programmed state, in which it stores a bit having a second logical value, for example the logical value 0, and the reference bit (which replaces a bit already read to allow the reading of the next bit, advantageously has the second logical value.

[0025] The state transistor of a memory cell is advantageously configured to be on when the memory cell is in its first state and to be off when the memory cell is in its second state.

[0026] A simple way to obtain such a state transistor is to provide a depletion-type state transistor.

[0027] Furthermore, according to one embodiment, the state transistor has, in the first state of the memory cell, a negative threshold voltage lower than the threshold voltage of the state transistor of the memory cell in the blank state while in the second state of the memory cell, the threshold voltage of the state transistor is positive and higher than the threshold voltage of the state transistor of the memory cell in the blank state.

[0028] Although not essential, it is particularly interesting that the state transistor channel of each memory cell includes a channel implanted on the surface in the substrate and configured so that the memory cell operates in a depletion mode.

[0029] In fact, this will allow, for example, the application of zero voltage to the control grid in reading mode.

[0030] Indeed, the state transistor being of the depletion type, the passing character (“normally on”) of the state transistor when the memory cell is in a virgin state and a zero voltage is applied to the control gate, is linked to the value of its threshold voltage in the virgin state of the memory cell which can for example be chosen to be negative or substantially zero.

[0031] And the threshold voltages of the state transistor in the two states (erased and programmed) of the memory cell are on either side of the threshold voltage of the state transistor of the memory cell in the blank state.

[0032] It therefore becomes possible to configure the processing means so that they apply a zero reading voltage to the control gate of the state transistor of a memory cell during a reading operation of this memory cell.

[0033] Indeed, with such a zero reading voltage, it is possible to differentiate the state of the memory cell since the state transistor of a memory cell in its first state (erased cell for example) will be conducting since its threshold voltage will be lower than that of a blank cell and it will be blocked in the presence of a memory cell in its second state (programmed cell for example) since the threshold voltage will this time be positive.

[0034] When the first state of a memory cell corresponds to an erased state of the cell and the first logic value is a 1, and the second state of a memory cell corresponds to a programmed state of the cell and the second logic value is a 0, and the processing means are configured to, in order to replace a bit already read, program the two memory cells containing this bit already read.

[0035] It is particularly advantageous that prior to storing information in the memory area, all memory cells in the memory area are in an erased state.

[0036] In fact, in this case, it is simply necessary to program the memory cells to store a logical zero.

[0037] According to another aspect, there is provided a method comprising storing information comprising a succession of N bits in a non-volatile memory device.

[0038] The device comprises a memory plane comprising at least one memory area including a matrix of memory cells having two rows and N columns, each memory cell comprising a state transistor having a control gate and a floating gate, selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate, each column of memory cells including a pair of twin memory cells, the two selection transistors of a pair of twin memory cells having a common selection gate.

[0039] The storage of the N bits is carried out so that, with the exception of the last bit of the succession, a current bit of said succession is stored in two memory cells located on the same row and on two adjacent columns and that a current bit and the following bit are respectively stored in two twin cells.

[0040] According to one embodiment, the method comprises, in order to be able to read a bit stored in a first twin cell, a prior replacement of the bit stored in the second twin cell by a reference bit having a reference value chosen to allow correct restitution of the value of the bit stored in the first twin cell.

[0041] According to one embodiment, the method further comprises a sequential reading of the N bits and for each bit of the succession except the last, a replacement of a current bit already read by the reference bit, before being able to read the next bit of said succession.

[0042] According to one embodiment, the method comprises applying a zero read voltage to the control gate of the state transistor of a memory cell during a read operation of this memory cell.

[0043] According to one embodiment, the method comprises an individual selection of the two bit lines associated with the two columns located at the two ends of the memory area and a simultaneous selection of two adjacent bit lines, both for the operation of storing the information and for the operation of reading and prior replacement of the bits.

[0044] According to one embodiment, in which each memory cell has a first state corresponding to an erased state of the cell in which it stores a logical 1, and a second state corresponding to a programmed state of the cell in which it stores a logical 0, the method comprises, in order to replace a bit already read, programming the two memory cells containing this bit already read.

[0045] According to one embodiment, the method comprises, prior to storing the information in the memory area, erasing all the memory cells in the memory area.

[0046] According to one embodiment, the method comprises storing said information in several memory areas, and successive reading of the different memory areas.

[0047] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment, which are in no way limiting, and the appended drawings in which: [ Fig 1 ] [ Fig 2 ] [ Fig 3 ] [ Fig 4 ] [ Fig 5 ] [ Fig 6 ] [ Fig 7 ] [ Fig 8 ] [ Fig 9 ] [ Fig 10 ] [ Fig 11 ] [ Fig 12 ] [ Fig 13 ] [ Fig 14 ] [ Fig 15 ] [ Fig 16 ] [ Fig 17 ] [ Fig 18 ], And [ Fig 19 ] schematically illustrate modes of implementation and embodiment of the invention.

[0048] On the figure 1 , the reference M denotes a non-volatile memory cell of the split-gate type, for example of the selection transistor type having a vertical gate buried in the substrate of an integrated circuit.

[0049] More precisely, the memory cell M comprises a state transistor T comprising a floating gate FG surmounted by a control gate CG connected to a gate control line CGL.

[0050] The drain (D) of the state transistor T is connected to a bit line BL while the source (S) of the state transistor T is connected to the drain of a selection transistor ST.

[0051] The selection transistor ST has a gate CSG connected to a word line WL.

[0052] The source (S) of the selection transistor ST is connected to a source line SL.

[0053] For example, the figure 2 represents a PM memory plane structure with a single bit line per column and comprising memory cells Mi,j; Mi,j+1; Mi-1,j; Mi-1,j+1 of the type described in patent application US 2013 / 0228846.

[0054] The memory cells Mi,j and Mi,j+1 of rank "i" belong to the row or line of rank i of the memory plane and are connected to a word line WLi-1,i and to a gate control line CGLi.

[0055] The memory cells Mi-1,j and Mi-1,j+1 of rank "i-1" belong to the row or line of rank "i-1" of the memory plane and are connected to the word line WLi-1,i and to a gate control line CGLi-1.

[0056] The memory cells Mi,j and Mi-1,j of rank "j" belonging to column j are accessible in reading and writing via a single bit line BLj and the memory cells Mi,j+1 and Mi-1,j+1 of rank "j-1" are accessible in reading and writing via a single bit line BLj+1.

[0057] Each memory cell comprises a floating gate transistor FG, respectively Ti,j; Ti,j+1; Ti-1,j; Ti-1,j+1. The drain regions (D) of transistors Ti,j and Ti-1,j are connected to bit line BLj and the drain terminals of transistors Ti,j+1 and Ti-1,j+1 are connected to bit line BLj+1. The control gates CG of transistors Ti,j and Ti,j+1 are connected to gate control line CGLi and the control gates CG of floating gate transistors Ti-1,j and Ti-1,j+1 are connected to gate control line CGLi-1.

[0058] Each floating gate transistor has its source terminal (S) connected to a source line SL via the selection transistor ST. The selection transistors ST of the memory cells Mi,j and Mi-1,j have a common selection gate CSG and the two memory cells are therefore called "twins". Similarly, memory cells Mi,j+1 and Mi-1,j+1 are twin memory cells and their selection transistors ST have a common selection gate CSG.

[0059] Each CSG selection gate is a vertical gate buried in a substrate in which the memory plane PM is realized, the source line SL being also buried. These common CSG selection gates of twin memory cells are connected to the word line WLi-1,i.

[0060] As illustrated in the figure 3 , and as indicated above, each state transistor of the memory device of the figure 2 cooperates with a vertical selection transistor buried in the SB substrate.

[0061] The ZCH channel of the state transistor is referenced ZCH.

[0062] The selection transistors ST connected to the two state transistors Ti,j and Ti+1,j each have a vertical channel ZCV and a buried vertical common selection gate CSG. It should be noted that for the purpose of simplifying the figure, the contact for connecting the buried common gate CSG to the corresponding word line WLi,i+1 is not shown.

[0063] There figure 3 more precisely illustrates two twin cells Mi,j and Mi+1,j belonging to the same column j and to the two rows i and i+1.

[0064] Their drain is connected to the same bit line BLj which is the only bit line for column j.

[0065] Each memory cell has a first state, for example an erased state, in which it stores a bit having a first logical value, for example the logical value 1, and a second state, for example a programmed state, in which it stores a bit having a second logical value, for example the logical value 0.

[0066] The state transistor of a memory cell is advantageously configured to be on when the memory cell is in its first state and to be off when the memory cell is in its second state.

[0067] A simple way to obtain such a state transistor is to provide, for example, a depletion-type state transistor as described in the French patent application published under No. 3049380.

[0068] As is well known to those skilled in the art, the depletion MOS transistor is conductive without a control voltage applied to the control gate of the state transistor (control gate connected to ground), and consequently to the floating gate by capacitive coupling. The state transistor is therefore said to be "normally on". On the other hand, the transistor becomes less and less conductive as the control voltage present on the control gate increases in absolute value (becomes more and more negative) to finally turn off beyond a blocking voltage.

[0069] The ZCH channel of the state transistor is advantageously a surface channel so that it may be possible to block the conduction of the channel by applying an acceptable control voltage to the control gate of the state transistor.

[0070] The implantation energy of the dopants defines the depth of the ZCH channel. As an indication, this energy can be between 5keV and 100keV, leading to a channel depth of around 100 nm.

[0071] In the case of a channel of conductivity type N, the implanted dopants can be for example arsenic As, and the concentration of dopants determines the threshold voltage Vth0 of the state transistor of a memory cell in the virgin state. The state transistor is here configured to have such a negative threshold voltage Vth0. In this regard, a dose of implanted dopants between 10 12< atoms / cm 2< and 10 14< atoms / cm 3< can be used.

[0072] With such a dose of dopants, a negative voltage Vth0 can be obtained, for example, between -1 volt and -0.5 volt.

[0073] On the figure 4 , we have schematically represented the different threshold voltages Vthe, Vth0 and Vthp corresponding respectively for example to erased, blank and programmed memory cells.

[0074] In read mode, a zero read voltage can be applied to the control gate CG of the state transistor and a positive voltage can be applied to the bit line BL.

[0075] The state transistor being depletion with a negative voltage Vth0, it is normally conductive for a blank memory cell, that is to say when no charge is present in the floating gate.

[0076] It then emerges from the figure 4 that a state transistor of an erased memory cell will be on while the state transistor of a programmed memory cell will be off. And, applying a zero voltage to the control gate and therefore to the floating gate FG of the state transistor, does not induce read stress.

[0077] Furthermore, the programming or erasure of a floating gate transistor is carried out here by injecting or extracting electrical charges into the gate of the transistor by injecting hot electrons using high voltage(s).

[0078] More specifically, erasure of a memory cell is achieved by combining a positive voltage applied to the substrate with a negative voltage applied to the control gate of its floating-gate state transistor.

[0079] As for the twin cell, if we want it not to be simultaneously erased, we apply a positive voltage to the control gate of its state transistor.

[0080] Programming a memory cell can be achieved, for example, by applying a positive voltage to the relevant bit line, applying a zero voltage to the substrate, and a positive voltage to the control gate of its floating-gate state transistor.

[0081] The selection of such a memory cell to be programmed is carried out by applying a positive voltage greater than the threshold voltage of the state transistor, on the word line concerned.

[0082] As for the twin cell, if we want it not to be simultaneously programmed, we apply a weakly negative voltage, for example -0.5 Volt or -1 Volt, or zero on the control gate of its state transistor.

[0083] Finally, as indicated above, reading a memory cell is ensured by applying a zero voltage to the control gate CG of its state transistor, as well as a positive voltage to the corresponding bit line.

[0084] The selection of such a memory cell to be read is carried out by applying a positive voltage greater than the threshold voltage of the state transistor, on the word line concerned.

[0085] In practice, in read mode, a zero voltage will be applied to all cells in the memory plane.

[0086] As a result, two selected twin cells will be read simultaneously.

[0087] And if in addition the column decoder is configured, as will be seen in more detail below, to simultaneously select two adjacent bit lines, the two corresponding pairs of twin cells will be simultaneously read.

[0088] We now refer more particularly to the figures 5 and following to more precisely describe embodiments and implementations of the invention.

[0089] On the figure 5 , the reference DM designates a memory device comprising a memory plane PM including a memory zone ZM.

[0090] This memory area ZM contains here a matrix of memory cells Mi,j having two rows or lines L0 and L1 and N columns, here 32 columns.

[0091] The memory cells Mi,j are memory cells such as those described with reference to the previous figures.

[0092] In this example, i denotes the row or line index and i is either 0 or 1.

[0093] The index j denotes the column index and ranges from 0 to 31 in this example.

[0094] The memory area ZM is intended to store information comprising N binary data D0-D31.

[0095] The memory device DM also comprises processing means MTR comprising in particular a line decoder DECR, of conventional structure, and configured to deliver voltages on the word line WL0,1 as well as on the gate control lines CGL0 and CGL1.

[0096] The processing means also include a DECC column decoder.

[0097] This DECC column decoder includes a set of switches SW0-SW31, each comprising two MOS transistors in parallel.

[0098] A first terminal of the switch SWj is connected to the corresponding bit line BLj.

[0099] A second terminal of the switch SWJ is connected either to a read amplifier circuit AMP via a MOS transistor controlled on its gate by a read signal READ or to a programming means PRGL, of conventional structure, via another MOS transistor controlled on its gate by a programming control signal PROG.

[0100] These READ and PROG signals are delivered by the MTR processing means depending on whether the reading phase or the programming phase is in progress.

[0101] As illustrated in the figure 5 , the column decoder DECC is configured to individually select the two bit lines BL0 and BL31 associated with the two columns located at the two ends of the memory area ZM, via the logic signals COL0 and COL31.

[0102] Furthermore, the column decoder is also configured to simultaneously select two adjacent bit lines BLj and BLj+1 by the logic signal COLjj+1.

[0103] This individual selection of the two bit lines BL0 and BL31 and the simultaneous selection of two adjacent bit lines is carried out both for the operation of storing the information D0-D31 in the memory cells of the memory area ZM and for the reading operation which, as will be seen in more detail below, involves prior replacements of bits by a reference bit, in this case a bit with logic value 0.

[0104] The logic signals COLO, COL31 and COL jj+1 are delivered by MCC logic means.

[0105] As stated above, the memory area is intended to store 32 bits of data D0-D31.

[0106] And, as illustrated on the figure 6 , prior to storing this information in the memory area ZM, all the memory cells in the memory area ZM are in an erased state, that is to say they all contain the logical value 1.

[0107] We now refer more particularly to the figures 7 à 10 to illustrate the successive writing of the N bits D0-D31 of the information in the memory zone ZM.

[0108] Generally speaking, since the initial state of the memory cells in the memory zone ZM is an erased state, i.e. containing a logical "1", no operation will be carried out in a memory cell to write data having a logical value of "1".

[0109] On the other hand, we will carry out a programming operation of a memory cell in the case where the data to be written in this cell is a “0”.

[0110] The voltages to be applied to the bit line, substrate, control gate and word line to select and program a cell have been indicated above.

[0111] Similarly, the voltages to be applied to the bit line, the control grid and the word line to select and read a cell have been indicated above.

[0112] On the figure 7 , the column decoder DECC selects, using the logic signal COL1, the two bit lines BL0 and BL1.

[0113] Furthermore, the CGL1 grid control line is selected.

[0114] As a result, data D0 is written to both memory cell M1,0 and memory cell M1,1.

[0115] Then, as illustrated in the figure 8 , the column decoder selects the two bit lines BL1 and BL2 using the logic signal COL12.

[0116] Furthermore, this time it is the CGL0 grid control line that is selected.

[0117] As a result, the second data D1 of the information is stored simultaneously in the two memory cells M0,2 and M0,3 of the first line L0.

[0118] The write operation then continues sequentially until the last data item D31 of the information is written into the memory cell M0,31.

[0119] This is done by selecting bit line BL31 using logic signal COL31 and selecting gate control line CGL0 ( figure 9 ).

[0120] At the end of this writing operation, we obtain, as illustrated in the figure 10 , a filling of the memory area in a checkerboard pattern such that a data item, with the exception of the last data item D31, is stored in two adjacent memory cells of the same row and that two successive data items are respectively stored in two twin cells of the same column.

[0121] Furthermore, the twin cell M0,0 of that M1,0 storing the data D0 stores the value 1 while the last data D31 is stored in the memory cell M0,31 twin of the memory cell M1,31 storing the data D30.

[0122] We now refer more particularly to the figures 11 à 18 to illustrate an example of reading information stored in the memory area ZM.

[0123] Since zero voltage (GND) is applied in reading on the control gates of all the memory cells in the memory area, reading a first twin memory cell in a column simultaneously causes the second twin cell to be read.

[0124] Now, if the first twin cell contains a logical “1”, then this logical “1” will mask the value read from the data located in the second twin cell.

[0125] In fact, reading these two twin cells will always give a logical “1” regardless of the value of the stored data.

[0126] This is why it is necessary, before reading a memory cell, to replace the value stored in its twin cell with a reference bit chosen so as to allow the correct restitution of the stored data. In this case, this reference bit will have the value "0" which corresponds to a prior programming of the twin cell so as to store a "0" there.

[0127] This is illustrated on the figure 11 .

[0128] More precisely, using the logic signal COLO, the bit line BL0 is selected and, using the line control signal CGL0, the memory cell M0,0 is programmed so as to store a logic "0" there.

[0129] Then, we can read the two twin cells M0,0 in order to store a logical “0” there.

[0130] Then, we can proceed to read the two twin cells M0,0 and M1,0 still by selecting the bit line BL0 using the logic signal COLO, as illustrated in the figure 12 .

[0131] And, this time, the D0 data is correctly read.

[0132] Indeed, if the data D0 is equal to 0, then the value 0 will actually be read by the reading amplifier circuit AMP.

[0133] And, if the logical value of the data D0 is equal to 1, then a logical “1” will be read by the sense amplifier circuit AMP.

[0134] We then proceed as illustrated in the figures 13 And 14 when reading data D1.

[0135] And, as this time the column decoder will select the two bit lines BL0 and BL1 simultaneously, and the zero voltage GND is applied to the control gates of the state transistors of all the memory cells, there will be a simultaneous reading of the two twin cells located on the "0" column and the two twin cells located on the "1" column.

[0136] Also, in order to obtain a correct restitution of the logical value of the data D1, it is necessary, prior to reading this data D1, not only to program the twin cell of the cell D1 with the value "0" but also to program the cell which contained the data D0 previously read.

[0137] This is illustrated on the figure 13 .

[0138] We see that in this preliminary programming step, by selecting the bit lines BL0 and BL1 by the logic signal COL01 and by applying the programming voltage to the gate control line CGL1, the memory cells M1,0 and M1,1 are programmed with the logic value "0".

[0139] Therefore, as illustrated in the figure 14 , the selection of the two bit lines BL0 and BL1 and the application of the zero voltage GND on the control gates of the state transistors lead to simultaneously reading the logic value of the data D1 and the three logic values ​​“0” stored in the memory cells M0,0, M1,0 and M1,1.

[0140] As a result, the logical value of data D1 is correctly restored. In fact, if this data is equal to 0, then the sense amplifier circuit will actually read a “0” while if this logical value is equal to 1, the sense amplifier circuit will actually read a “1”.

[0141] It should therefore be noted here that not only does prior programming allow for correct restitution of the data to be read, but this prior programming also destroys the data that has been previously read.

[0142] THE figures 15 And 16 illustrate the reading of the following data D2.

[0143] Prior to this reading, we carry out programming of cells M0,1 and M0,2 ( figure 15 ) then a reading of the data D2 stored in the memory cell M1,2 ( figure 16 ).

[0144] Data D1 was therefore destroyed.

[0145] THE figures 17 And18 illustrate the reading of the last D31 data.

[0146] In this regard, as illustrated in the figure 17 , we proceed to a preliminary programming of the twin cell M1,31 then as illustrated on the figure 18 to a reading of cell D31 stored in memory cell M0,31.

[0147] At the end of this reading, we notice that all the memory cells except the last cell M0,31, store a logical 0.

[0148] Reading the N binary data of the stored information has therefore destroyed all the bits of this information except the last one.

[0149] And, we can no longer read this information again.

[0150] The memory device therefore behaves here like a read-once memory.

[0151] If one wishes to provide a memory device that can be read a predetermined number of times, for example K times, then one can, as schematically illustrated in the figure 19 , provide a PM memory plan comprising K zones ZM, ZM1-ZMK.

[0152] These zones will be read successively as indicated above for zone ZM, so as to allow the information to be read only K times.

Claims

1. A non-volatile memory device, comprising a memory plane (PM) including at least one memory zone (ZM) including a matrix of memory cells (Mi,j) having two rows and N columns, each memory cell comprising a state transistor having a control gate and a floating gate, selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, each column of memory cells including a pair of twin memory cells, the two selection transistors of a pair of twin memory cells having a common selection gate, and processing means (MTR) configured to store in the memory zone a piece of information (D0-D31) including a succession of N bits so that, with the exception of the last bit in the succession, a current bit in said succession is stored in two memory cells situated on the same row and on two adjacent columns and a current bit and the next bit are respectively stored in two twin cells.

2. The device according to claim 1, wherein the processing means (MTR) are configured to, in order to be able to read a bit stored in a first twin cell, replace beforehand the bit stored in the second twin cell with a reference bit having a reference value chosen to allow proper restitution of the value of the bit stored in the first twin cell.

3. The device according to claim 2, wherein the processing means (MTR) are further configured to read the N bits of the piece of information sequentially, to replace a current already read bit of said piece of information with the reference bit before being able to read the next bit in said succession.

4. The device according to one of claims 1 to 3, wherein the memory zone (ZM) includes a single bit line per column, connected to the drains of the state transistors of the pair of twin cells of the corresponding column, and a gate control line, per row of memory cells, connected to all the control gates of the state transistors of the memory cells of the corresponding row.

5. The device according to one of claims 1 to 4, wherein the processing means (MTR) comprise a column decoder (DECC) configured to individually select the two bit lines associated with the two columns situated at the two ends of the memory zone and to simultaneously select two adjacent bit lines (BLj; BLj+1), both for the information storage operation and for the operation of reading and replacing beforehand the bits.

6. The device according to one of the preceding claims taken in combination with claim 2 or 3, wherein each memory cell (Mi,j) has a first state in which it stores a bit having a first logic value and a second state in which it stores a bit having a second logic value 1, and the reference bit has the second logic value.

7. The device according to claim 6, wherein the state transistor of a memory cell (Mi,j) is configured to be on when the memory cell is in its first state and to be off when the memory cell is in its second state.

8. The device according to claim 7, wherein the state transistor is of the depletion type, and the state transistor has, in the first state of the memory cell (Mi,j), a threshold voltage that is negative and lower than the threshold voltage of the state transistor of the memory cell in the virgin state, whereas in the second state of the memory cell, the threshold voltage of the state transistor is positive and higher than the threshold voltage of the state transistor of the memory cell in the virgin state.

9. The device according to claim 8, wherein the processing means (MTR) are configured to apply a zero read voltage to the control gate of the state transistor of a memory cell during an operation of reading this memory cell.

10. The device according to claim 8 or 9, wherein the first state of a memory cell (Mi,j) corresponds to an erased state of the cell and the first logic value is 1, the second state of a memory cell corresponds to a programmed state of the cell and the second logic value is 0, and the processing means are configured to, in order to replace an already read bit, program the two memory cells containing this already read bit.

11. The device according to claim 10, wherein prior to storing the piece of information in the memory zone (ZM), all the memory cells (Mi,j) of the memory zone are in an erased state.

12. The device according to one of the preceding claims, comprising several memory zones (ZM1-ZMK) for containing the same piece of information of N bits, and the processing means are configured to successively read the different memory zones.

13. A method, comprising storing a piece of information including a succession of N bits (DO-D31) in a non-volatile memory device (DM), the device comprising a memory plane (PM) including at least one memory zone (ZM) including a matrix of memory cells (Mi,j) having two rows and N columns, each memory cell including a state transistor having a control gate and a floating gate, selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, each column of memory cells including a pair of twin memory cells (Mi,j ; Mi-1,j), the two selection transistors of a pair of twin memory cells having a common selection gate, storing the N bits being carried out so that, with the exception of the last bit in the succession, a current bit in said succession is stored in two memory cells situated on a same row and on two adjacent columns and that a current bit and the next bit are respectively stored in two twin cells.

14. The method according to claim 13, comprising, in order to be able to read a bit stored in a first twin cell (Mi,j), replacing beforehand the bit stored in the second twin cell (Mi-1,j) with a reference bit having a reference value chosen to allow proper restitution of the value of the bit stored in the first twin cell.

15. The method according to claim 14, further comprising sequentially reading the N bits (DO-D31) and replacing a current already read bit in said succession with the reference bit before being able to read the next bit in said succession.

16. The method according to claim 14 or 15, comprising applying a zero read voltage to the control gate of the state transistor of a memory cell (Mi,j) during an operation of reading this memory cell.

17. The method according to one of claims 13 to 16, comprising individually selecting the two bit lines associated with the two columns situated at the two ends of the memory zone and simultaneously selecting two adjacent bit lines (BLj; BLj+1), both for the information storage operation and for the operation of reading and replacing beforehand the bits.

18. The method according to one of claims 13 to 17, wherein each memory cell (Mi,j) has a first state corresponding to an erased state of the cell in which it stores a logic 1, and a second state corresponding to a programmed state of the cell in which it stores a logic 0, and the method comprises, in order to replace an already read bit, programming the two memory cells containing this already read bit.

19. The method according to claim 18, comprising, prior to storing the piece of information in the memory zone (ZM), erasing all the memory cells of the memory zone.

20. The method according to one of claims 13 to 19, comprising storing of said piece of information in several memory zones (ZM1-ZMK), and successively reading the different memory zones.