NEUROMORPHERIC CIRCUIT BASED ON 2T2R-RRAM CELLS

Description

[0001] The present invention relates to a neuromorphic circuit suitable for implementing a neural network.

[0002] For numerous applications, including automated data processing, diagnostic assistance, predictive analytics, autonomous vehicles, bioinformatics, and surveillance, machine learning algorithms are commonly used as part of programs that can run on processors such as CPUs or GPUs. A CPU is a processor; the acronym CPU comes from the English term " Central Processing Unit » literally meaning central processing unit, while a GPU is a graphics processor, the acronym GPU coming from the English term " Graphics Processing Unit » literally meaning graphic processing unit.

[0003] Among the learning implementation techniques, the use of neural networks is becoming increasingly widespread, these structures being considered very promising due to their performance for many tasks such as automatic data classification, pattern recognition, automatic translation and language understanding, robotic control, automatic navigation, recommendation systems, anomaly detection, fraud detection, DNA study or even the discovery of new molecules.

[0004] A neural network is generally composed of a succession of layers of neurons, each taking its inputs from the outputs of the previous layer. More precisely, each layer comprises neurons whose inputs are taken from the outputs of the neurons in the previous layer. Each layer is connected by a plurality of synapses. A synaptic weight is associated with each synapse. This is a real number that can take positive or negative values. For each layer, the input of a neuron is the weighted sum of the outputs of the neurons in the previous layer, the weighting being determined by the synaptic weights.

[0005] For implementation in a CPU or GPU, a Von Neumann bottleneck problem (also called " Von Neumann bottleneck » (according to its English name) arises from the fact that implementing a deep neural network (with more than three layers and up to several dozen) requires using both the memory(ies) and the processor, even though these components are spatially separated. This results in congestion on the communication bus between the memory(ies) and the processor, both while the trained neural network is being used to perform a task, and, even more so, while the neural network is being trained—that is, while its synaptic weights are being tuned to solve the task in question with maximum performance.

[0006] It is therefore desirable to develop dedicated hardware architectures, intertwining memory and computing, to create fast, low-power neural networks capable of learning in real time.

[0007] A neural network based on optical technologies is known.

[0008] Another area of ​​research focuses on the creation of neurons and synaspes in neural networks using CMOS technology. This is understood by the acronym "CMOS," which stands for Complementary Metal-Oxide Semiconductor (an acronym derived from the English expression " Complementary Metal-Oxide-Semiconductor "). The acronym CMOS refers both to a manufacturing process and to a component obtained by such a manufacturing process.

[0009] However, with each of these technologies, each neuron occupies several tens of micrometers on each side. Furthermore, each synapse also occupies several tens of micrometers on each side. Consequently, on a limited surface area, such as an electronic chip, the number of neurons and synapses that can be integrated is limited, resulting in reduced performance of the neural network.

[0010] Therefore, to reduce clutter, architectures in which synapses are memritive are specifically studied.

[0011] Memoristic synapses are synapses that utilize memristors. In electronics, a memristor (or memristor) is a passive electronic component. The name is a portmanteau of the English words "memory" and "resistor." A memristor is a non-volatile memory component; its electrical resistance changes when a voltage is applied for a certain duration and remains at that value when the voltage is removed.

[0012] An example of such an implementation is proposed in an article by L. Wang et al. entitled "Efficient and Robust Nonvolatile Computing-In-Memory based on Voltage Division 2T2R RRAM with Input-Dependent Sensing Control" published on March 19, 2021 in the journal Transactions on Circuits and Systems II: Express Briefs .The neural network is made up of a set of memory cells connected to a specific reading circuit.

[0013] It is worth noting that this implementation uses a specific type of neural network: a binary neural network, meaning a network in which neurons and synapses can only take binary values. These neural networks offer the advantage of simpler computations while still exhibiting good performance during inference, particularly for surveillance applications.

[0014] However, the implementation proposed by L. Wang et al. is relatively bulky and difficult to integrate into a memory cell structure. The article by T. Hirtzil et al., entitled "Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays," published on August 12, 2019, provides another implementation of a neuromorphic circuit based on 2T2R RRAM cells.

[0015] There is therefore a need for a neuromorphic circuit that enables the realization of a binary neural network that is less bulky and offers better integrability into a set of memory cells.

[0016] To this end, the description outlines a neuromorphic circuit designed to implement a neural network, the neuromorphic circuit comprising: word lines, pairs of complementary bit lines, source lines, a set of elementary cells organized according to a two-dimensional matrix comprising rows and columns, the set of elementary cells comprising a memory set grouping a set of rows of elementary cells, the elementary cells of the memory set being memory cells, the memory cells of the same row being selectable by a word line, the memory cells of the same column being connected to a pair of complementary bit lines and a source line, each memory cell comprising two memristors and two switches, each memristor being connected to the same source line and to a respective switch, each memristor storing respectively a weight or the inverse of the same weight by presenting respectively different first and second resistance values, the switches being connected,for their activation, to a word line and respectively connected to a pair of complementary bit lines, an electronic circuit implementing a neuron presenting an output and comprising: a set of logic components, each logic component presenting a logic unit including an input connected to a respective source line, the logic unit being suitable for performing a logic operation presenting a toggling between a low value and a high value depending on the value of the input(s) of the logic unit, each logic unit performing a logic function of the inverter or double inverter type, a counting unit, the counting unit being suitable for counting the number of high or low values ​​at the output of the logic components, the counting unit being a bridge, a bridge being a set of identical elements in parallel and connected to each other on one of their terminals to an output of the counting unit,Each element is connected to a respective logic component and is either a resistor or a capacitor. A comparison unit includes a comparator and a comparison voltage generator. The comparator compares the output of the counting unit to the comparison voltage generated by the comparison voltage generator, thereby emitting an output signal that depends on the comparison and corresponds to the output of the electronic circuit implementing a neuron.

[0017] In specific embodiments, the neuromorphic circuit exhibits one or more of the following characteristics, taken individually or in all technically possible combinations: each memristor has a blank state, the counting unit being a row of elementary cells, each elementary cell of the counting unit being a cell comprising two memristors in the blank state and two switches, each memristor in the blank state being connected to the other memristor in the blank state and to a respective switch, the switches being connected together; each logic unit includes an inverter formed from an elementary cell comprising two memristors and two switches, each memristor being connected to the other memristor and to a respective switch, a short-circuit track being arranged to short-circuit the two memristors, one of the switches being connected to ground and to the input of the logic unit for its control and the other switch being connected to a supply potential and mounted as a diode;Each logic unit includes an inverter formed from an elementary cell comprising two memristors and two switches, each memristor being connected to the other memristor and to a respective switch, a first switch being connected to ground and to the input of the logic unit for its control and the second switch being connected to a supply potential and mounted as a diode, a short-circuit track being arranged to short-circuit the memristor connected to the first switch;a first controller allowing the selection of the elementary cells of a line which are connected to the same line of words, and comprising a second controller connected to the pairs of bit lines and allowing the application on each pair of bit lines of different voltages which are symmetrical with respect to an average voltage, the voltage applied on a bit line being greater or less than that applied on the associated complementary bit line according to the value of an input signal, each input signal corresponding to an input of a synapse connected to said neuron; the set formed by each logic unit is made up of at least one line of elementary cells not belonging to the memory set;Each logic unit corresponds to an inverter formed by said switches of each elementary cell of the counting unit and a PMOS transistor whose drain is connected to a supply voltage, the gate is connected to a source line SL and the source is connected to the drains of said switches; the comparator voltage generator is a fixed voltage generator; the comparator voltage generator is a second bridge having the same elements as the counting unit, each element of the second bridge being connected to an inverter connected to a respective logic unit; the elements of the two bridges are capacitors having the same capacitance, the comparator voltage generator and the counting unit having an offset capacitor, the offset capacitor having a capacitance equal to half the capacitance of a capacitor of one of the two bridges;The logical operation performed by each logic unit is chosen from: an XOR with one input set to 0, an inversion, a NOR with one of the two inputs set to 1, a NOR with one of the two inputs set to 0; the neuromorphic circuit includes pull-up transistors, one of the pull-up transistors being connected to all the elements of the counting unit and the other pull-up transistors being connected to a respective source line, the pull-up transistors being used to clear the elements; the neuromorphic circuit includes several distinct sets of elementary cells designed to operate in parallel; the source lines have several portions, portions of these lines being specific to a set of elementary cells; the neuromorphic circuit is a three-dimensional integrated circuit; the neuromorphic circuit includes bias units modifying the comparison voltage;The neuromorphic circuit takes as input values ​​coded on several bits, each bit taking 2 possible values; the neuromorphic circuit comprises a transfer unit followed by an accumulation unit; the transfer unit and the accumulation unit each include a switch and a capacitor; the neuromorphic circuit includes a comparator upstream of the two units, and the transfer unit and the accumulation unit are implemented in a differential configuration.

[0018] Features and advantages of the invention will become apparent from the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which: there figure 1 is a schematic representation of an example of a neuromorphic circuit physically implementing a neural network, the figure 2 is a schematic representation of an example of a memory cell that is part of the neuromorphic circuit, the figure 3 is a graph showing the effect of the variability of the resistance values ​​of the states of a memristor, the figure 4 is a schematic representation of an example of an electronic circuit implementing a neuron, the figure 5 is a schematic representation of another example of an electronic circuit implementing a neuron, the figure 6 is a schematic representation of an example implementation of a component performing an XNOR operation and forming part of the neuron of the figure 4 , there figure 7 illustrates the four possible operating cases of the XNOR component of the figure 6 , there figure 8 is a schematic representation of the output voltage of the XNOR component of the figure 6 in some cases of the figure 7 , there figure 9 is a schematic representation of a circuit implementing the neurons of the neuromorphic circuit based on static RAM, according to an initial prior art document, the figure 10 is a schematic representation of a first circuit implementing the neurons of the neuromorphic circuit based on static RAM according to a second prior art document, the figure 11 is a schematic representation of the electronic circuit by directly transposing the circuit of the figure 9 In the case of a resistive memory cell, the figure 12 is a schematic representation of a concrete implementation of a first part of the neuron of the figure 4 , there figure 13 is a schematic representation of a MOS inverter, the figure 14 is a schematic representation of a first example of an inverter made from an RRAM cell, the figure 15 is a schematic representation of a second example of an inverter implemented using an RRAM cell, the figure 16 is a schematic representation of two inverters in series made from two RRAM cells, the figure 17 is a schematic representation of the implementation of a first step in a process for converting unformed RRAM cells to the two inverters of the figure 16 , there figure 18 is a schematic representation of the implementation of a second step in a process for converting unformed RRAM cells to the two inverters of the figure 16 , there figure 19 is a schematic representation of the implementation of a third step in a process for converting unformed RRAM cells to the two inverters of the figure 16 , there figure 20 is a schematic representation of a concrete implementation of the entire neuron of the figure 4 , there figure 21 is a schematic representation of the implementation of the figure 20 in an erasure configuration, the figure 22 is a schematic representation of an example implementation of the neuromorphic circuit with calculations performed in parallel, the figure 23 is a schematic representation of another example of a neuromorphic circuit implementation with calculations performed in parallel, the figure 24 is a schematic representation of yet another example of a neuromorphic circuit implementation with calculations performed in parallel, the figure 25 is a schematic representation of another example of a neuromorphic circuit, the figure 26 is a schematic representation of an equivalent electrical diagram of a part of the neuromorphic circuit of the figure 25 , there figure 27 is a schematic representation of an equivalent electrical diagram of another part of the neuromorphic circuit of the figure 25 , there figure 28 is a graph showing the different possible configurations of the two represented parts of the figures 26 And 27 , and the figure 29 is a schematic representation of yet another example of a neuromorphic circuit, the figure 30 is a schematic representation of another example of a neuromorphic circuit, the figure 31 is a schematic representation of yet another example of a neuromorphic circuit, the figures 32 à 34 are a schematic representation of the functioning of yet another example of a neuromorphic circuit, the figure 35 is a schematic representation of part of a neuromorphic circuit for one-bit inputs, and the figures 36 à 38 are a schematic representation of part of a neuromorphic circuit for multi-bit inputs.

[0019] A neuromorphic circuit 10, suitable for implementing a neural network, is represented on the figure 1 .

[0020] The neuromorphic circuit 10 here implements a binary type neural network, that is to say, as explained previously, a network for which the synaptic weights and the neurons are binary.

[0021] The neuromorphic circuit 10 comprises a plurality of elementary cells 12.

[0022] The elementary cells 12 are organized according to a two-dimensional matrix 14 comprising rows 16 and columns 18.

[0023] The matrix will be referred to as the 14-cell matrix in the rest of the description.

[0024] An elementary cell 12 has the coordinates (i,j) when said elementary cell 12 is positioned at the intersection of the i-th row 16 i and the j-th column 18 j with i and j two integers.

[0025] In the case of the figure 1 , the number of rows 16 and columns 18 is equal to N, so the indices i and j are broadly understood to be between 1 and N.

[0026] In the case of the figure 1 , a 14-cell matrix was represented for which N is equal to 9.

[0027] However, as an alternative, the number of rows (16) and columns (18) may be different.

[0028] The neuromorphic circuit 10 also includes WL word lines, BL and BLb complementary bit line pairs, SL source lines and two controllers 20 and 22.

[0029] In the preceding notations, a line of text is referenced as WL, the abbreviation WL referring to the corresponding English designation of " word line » ; the complementary bit lines BL and BLb use the abbreviation BL which refers to the corresponding English name of " bit line » and the source lines are referenced with the abbreviation SL, which refers to the corresponding English designation of " source line ».

[0030] In the example of the figure 1 , each elementary cell is connected to a respective WL word line, a respective SL source line and a respective pair of BL and BLb complementary bit lines.

[0031] Each elementary cell 12 of the same row 14 shares the same word line WL, so the word lines WL can also be indexed with the index i. Thus, the first word line, that is, the one which links the elementary cells 12 of the first row 16, can be referenced WL 1.

[0032] The elementary cells 12 of the same column 18 share the same pair of complementary bit lines BL and BLb and the same source line SL. These three lines can therefore also be indexed with the index j.

[0033] For clarity, all source lines SL are shown, but only the pairs of complementary bit lines BL and BLb from the first column 181, the fifth column 185, and the ninth column 189 are shown as dashed lines on the figure 1 .

[0034] The first controller 20 is responsible for controlling each word line WL while the second controller 22 is responsible for controlling the complementary bit line pairs BL and BLb and the source lines SL.

[0035] The first controller 20 and the second controller 22 are configured to be controlled in a coordinated manner to control the elementary cells 12 using the lines they control according to the desired operation.

[0036] In particular, the second controller 22 will be able to supply the input data circulating on each of the pairs of complementary bit lines BL and BLb. It is this input data that will feed the neural network implemented by the neuromorphic circuit 10.

[0037] In the example described, the elementary cells 12 of the first three rows 161, 162, and 163 are used to create a neuron in the neural network. These elementary cells 12 are therefore part of an electronic circuit implementing a neuron 24. For simplicity, and to simplify the description that follows, such an electronic circuit is simply called neuron 24.

[0038] The elementary cells 12 of the first three rows 161, 162 and 163 will be described later when neuron 24 is described.

[0039] The elementary cells 12 of the other lines 16 4 to 16 N are each associated with a respective binary weight of the neural network.

[0040] The elementary cells 12 of these lines 16 4 to 16 N serve to store the weights of the neural network.

[0041] Therefore, in the following, these elementary cells 12 of these lines 16 4 to 16 N are called memory cells 26 and form a memorization set 27.

[0042] The structure of a memory cell 26 in the row environment is represented more precisely on the figure 2 for the case of memory cell 26 having coordinates (i,j).

[0043] Each memory cell 26 has two memristors, namely a first memristor 28 and a second memristor 30, as well as two switches, a first switch 32 and a second switch 34.

[0044] Because memristors 28 and 30 are present, such a memory cell 26 is a resistive random-access memory cell. Memory cell 26 is more often referred to by the acronym RRAM or ReRAM, which refers to the corresponding English designation of " Resistive random-access memory ».

[0045] Furthermore, such an arrangement is generally called a 2T2R structure, referring to the presence of two switches (designated 2T) and two memristors (designated 2R). Memory cell 26 is sometimes referred to as a 2T2R cell.

[0046] A memristor is a component whose electrical resistance changes permanently when a current is applied. This allows data to be recorded and rewritten by a control current. Such behavior is observed in phase-change materials, ferroelectric tunnel junctions, and redox memories based on oxides such as HfO₂ₓ or TiO₂ₓ.

[0047] The change in conductance of a memristor depends on the amplitude and duration of the voltage pulses applied through the memristor as well as the maximum current value that can pass through the memristor, for example for a "SET" operation, i.e. the transition from a high resistance to a low resistance.

[0048] A memristor can therefore have two states, a high state and a low state.

[0049] The high state corresponds to strong resistance and is generally designated by the abbreviation HRS, referring to the English term " High Resistive State » which literally means highly resistive state. The high state is, therefore, referred to as the high HRS state in the following.

[0050] The low state corresponds to low resistance and is generally designated by the abbreviation LRS, referring to the English term " Low Resistive State » which literally means weak resistance state. The low state is, therefore, referred to as the LRS low state in the following.

[0051] However, due to the variability of the memristors in operation, the resistance in the high state HRS may be less than the resistance in the low state LRS, which generates errors if the information (weight) is encoded in a single memristor.

[0052] This variability is presented schematically on the figure 3 This figure shows the probability that a memristor will actually exhibit a resistance value as a function of the memristor's state.

[0053] More specifically, the first curve, the curve marked 36, schematically represents the probability for all the values ​​observed in practice for the low state LRS while the second curve 38 represents the same curve for the high state HRS.

[0054] The graph of the figure 3 This clearly shows that there is an overlap zone 40. In this overlap zone 40, distinguishing between low LRS and high HRS states may be impossible.

[0055] This overlap can be greater with long-term temporal drifts of memristors.

[0056] To remedy this problem, in the present example, the information is encoded by the ratio between the two resistances of the two states thanks to a differential configuration of the two memristors 28 and 30.

[0057] Also, according to the example described, memristors 28 and 30 are serial and complementary memristors respecting the same logic coding.

[0058] By complementary, it is understood here that memristors 28 and 30 have a different state, a low state LRS for one and a high state HRS for the other.

[0059] Following the example of the figure 2 , a strong weight, i.e. a logical “1”, is represented by a high HRS state of the first memristor 28 (respectively a low LRS state of the second memristor 30) while a weak weight, i.e. a logical “0”, is represented by a low LRS state of the first memristor 28 (respectively a high HRS state of the second memristor 30).

[0060] In the example described, each of the two memristors 28 and 30 is connected to the common source line SL.

[0061] Each of the two switches 32 and 34 is, for example, a transistor and more specifically a field-effect transistor.

[0062] A field-effect transistor is often referred to by the abbreviation FET, which corresponds to the English term for " Field-Effect Transistor ».

[0063] According to the example described, the two switches 32 and 34 are insulated-gate field-effect transistors. Such a transistor is more often referred to by the acronym MOSFET, which stands for MOSFET. « Metal Oxide Semiconductor Field Effect Transistor ».

[0064] Thus, each switch 32 and 34 has three electrodes, a grid G, a source S and a drain D.

[0065] In general, for a transistor whose reference sign is X, the electrodes will be marked on the figures according to the following notation: the gate XG, the source XS and the drain XD.

[0066] This notation is chosen here to simplify the representation, given that the positions of the source XS and the drain XD are defined relative to the principal polarization direction, that is, the one most commonly used for the circuit. Of course, if the polarization is reversed, those skilled in the art know that the roles and positions of the source XS and the drain XD are reversed.

[0067] Each grid 32G and 34G of the two switches 32 and 34 is connected to the word line WL. Depending on the voltage level present on the word line, switches 32 and 34 are either conducting or not conducting. The first controller 20 will, in practice, select a line of cells by making the switches of the memory cells on that line conductive.

[0068] The 32S source of the first switch 32 is connected to the bit line BL while the 34S source of the second switch 34 is connected to the complementary bit line BLb.

[0069] The drain 32D of the first switch 32 is connected to one terminal of the first memristor 28, the other terminal of the first memristor 28 being connected to the common source line SL.

[0070] The drain 34D of the second switch 34 is connected to one terminal of the second memristor 30, the other terminal of the second memristor 30 being connected to the common source line SL.

[0071] The second controller 22 will control the power supply to the pairs of bit lines, so that the voltage presented on a bit line BL i is different and complementary to the voltage presented on the complementary bit line BL j. Thus, when a cell with coordinates i,j is selected (its switches being made conducting by the activation voltage presented on the associated word line WL i), the memristors 28 and 30 of this cell are in series and constitute a resistive bridge between the bit lines BL j and BLb j.

[0072] In this particular case, memristors 28 and 30 are thus powered by voltages present on the bit lines BL j and BLb j, which are symmetrical with respect to a voltage, for example V dd 2 , called the midpoint voltage. In this notation, V dd corresponds to a supply potential V dd. Furthermore, ground is denoted interchangeably as GND or gnd hereafter. Of course, another midpoint voltage could be chosen, such as, for example, a voltage of V dd 3 .

[0073] Neuron 24, that is, the electronic circuit implementing it, is now described with reference to figures 4 à 8 .

[0074] To better understand what follows, it can be observed that a binary neural network exhibits a specificity in inference compared to a classical neural network.

[0075] When a classical neural network is applied to an input vector to calculate an output vector, each neuron receives input values ​​corresponding to output values ​​from neurons in a previous layer. a j and calculates a weighted sum Σ j W ij . a j and the neuron then applies a non-linear function f to the result of the weighted sum.

[0076] In contrast, in a binary neural network, the weighted sum is obtained by performing the following operation: a i = sign popcount j XNOR W ij a j − T i Or: a i And a j represent the output values ​​calculated by the neurons of the current layer, respectively by the previous layer; W ij represents the respective binary weights for the neurons in the current layer; XNOR is the logical function giving the complement of the exclusive OR function (this function is sometimes called exclusive NOT-OR for this reason); popcount is the function that counts the number of 1s in a series of bits; T i is a predefined threshold, and sign is a function that associates the value 1 with a positive input and associates -1 with a negative value.

[0077] This means that, in the case of a binary network, it is possible to physically realize neuron 24 as represented on the figure 4 , namely that neuron 24 has XNOR components 42, a counting unit 44 and a comparison unit 46.

[0078] To fully understand the functioning of neuron 24, the operation of a single XNOR 42 component is first explained with reference to the figure 6 .

[0079] The XNOR 42 component performs an XNOR operation on two signals, namely a weight denoted W and an input signal denoted in.

[0080] In this case, the XNOR 42 component comprises two memristors M1 and M2 and an inverter 48.

[0081] The two memristors M1 and M2 are complementary memristors connected in series corresponding to the weight W.

[0082] Also, similarly to what has been described previously, following the example of the figure 6 , a logical "1" is represented by a high HRS state of memristor M1 (the other memristor M2 being in the low LRS state) while a logical "0" is represented by a low LRS state of memristor M1 (the other memristor M2 being in the high HRS state).

[0083] The memristors M1 and M2 are connected at one end to the inverter 48 and at the other end to a respective voltage.

[0084] We will denote the first voltage V in and the second voltage V inb.

[0085] The electrical configuration is therefore that of a voltage divider 50 connected on one side to the first voltage Vin and on the other side to the second voltage Vinb, and whose midpoint 52 is connected to the input of the inverter 48. In other words, one of the memristors M1 is subjected to a voltage |Vin - Vmid| and the other memristor M2 is subjected to a voltage |Vmid - Vinb|. The notation Vmid designates the voltage at the midpoint 52 of the voltage divider 50.

[0086] Thus, in the case described, the input signal in corresponds to the pair of the first voltage V in and the second voltage V inb.

[0087] These voltages Vin and Vinb have the particularity of being symmetrical with respect to half of the supply potential. VDD 2 In practice, it is advantageous to choose to have Vin equal to Vdd or gnd, and respectively Vinb equal to gnd or Vdd.

[0088] In the example described, the input signal in codes for a logic "1" when the first voltage V in is strictly greater than the second voltage V inb, i.e., V in > V inb.

[0089] Conversely, the input signal in codes for a logic "0" when the first voltage V in is strictly less than the second voltage V inb, i.e. V in < V inb.

[0090] This schematic representation of two memresistors M1 and M2 in series between two voltages Vin and Vinb corresponds in practice to the equivalent circuit formed by a selected cell 26 (the associated word line WL has a voltage that makes its switches conduct) and receiving bias voltages corresponding to Vin and Vinb via the bit lines BL and BLb. In other words, the input signal in is brought to a selected cell via the associated bit lines BL and BLb by the action of the controller 22. The midpoint 52 of the voltage divider then corresponds to the source line SL connected to the cell in question.

[0091] The inverter 48 is an element designed to receive an incident signal on an input 48E and perform a logic inversion calculation to output on an output 48S an output signal which is the inverse of the incident signal.

[0092] Here, the 48E input of the inverter 48 is connected to the midpoint 52 of the divider bridge 50 formed by the two memristors M1 and M2.

[0093] The output 48S of the inverter 48 gives the result of the XNOR operation applied to the input signal in and the weight W.

[0094] The operation of the XNOR 42 component is now described with reference to figures 7 And 8 These diagrams schematically represent the four possible operating modes of the XNOR 42 component and the output voltage values ​​for two of the four possible modes. Reference symbols are omitted from this figure to avoid making it too complex.

[0095] More specifically, the case in the top left corner of the figure 7 corresponds to the case where the input signal in is 0 and the value of the weight W is equal to 0.

[0096] In such a case, as explained previously, the first voltage V in is strictly less than the second voltage V inb, that is, V in < V inb (with for example V in = gnd and V inb = Vdd).

[0097] Furthermore, the first memristor M1 is in the low state LRS while the second memristor M2 is in the high state HRS.

[0098] Due to the configuration, the memristor in the high state HRS absorbs almost all of the voltage dynamics, pushing the voltage V mid from the midpoint 52 towards the voltage at the end of the memristor in the low state LRS.

[0099] In this case, it means that the midpoint voltage V of point 52 is pushed back towards the first voltage Vin as schematically represented by curve 54 on the figure 8 .

[0100] As apparent on this figure 8 The midpoint voltage (Vmid) is distinctly below half the supply potential. VDD 2 .

[0101] The output of inverter 48 is then at 1.

[0102] This shows that for a signal in at 0 and for a weight at 0, the output of inverter 48 is then at 1, which corresponds well to XNOR(0,0) = 1.

[0103] The case in the bottom right corner of the figure 7 corresponds to the corresponding case in which the input signal in is 0 and the value of the weight W is equal to 1.

[0104] In such a case, compared to the previous case, the only difference is that the first memristor M1 is in the high state HRS while the second memristor M2 is in the low state LRS.

[0105] As a result, the midpoint voltage Vmid is pushed towards the second voltage Vinb, as schematically represented by curve 56 on the figure 8 .

[0106] The output of inverter 48 is then at 0.

[0107] This shows that for a signal in at 0 and for a weight at 1, the output of inverter 48 is then at 1, which corresponds well to XNOR(0,1) = 0.

[0108] The same remarks apply to the cases on the right of the figure 7 .

[0109] The upper case corresponds to an input signal in with a value of 1 (V in > V inb, with, for example, V in = Vdd and V inb = Gnd) and a weight of 0 (first memristor M1 in the low state LRS and second memristor M2 in the high state HRS), so that the midpoint voltage V mid is pushed back towards the first voltage V in, that is to say that V mid > VDD 2 As a result, the output of inverter 48 is at 0. This corresponds to performing the operation XNOR(1,0) = 0.

[0110] The lower case corresponds to an input signal in of value 1 (V in > V inb ) and a weight of 1 (first memristor M1 in the high state HRS and second memristor M2 in the low state LRS) so that the midpoint voltage V mid is pushed towards the second voltage V inb, that is to say that V mid < VDD 2 As a result, the output of inverter 48 is at 1. This corresponds to performing the operation XNOR(1,1) = 1.

[0111] The various cases described do indeed lead to obtaining the truth table visible on the figure 7 , which clearly illustrates that the inverter's output (out) performs an XNOR operation.

[0112] Such an XNOR 42 component allows obtaining a voltage output that does not exhibit the resistance variability of memristors M1 and M2.

[0113] The reduction in variability stems from two complementary elements.

[0114] An initial reduction in variability is achieved by using a differential configuration of the two memristors M1 and M2. However, at the midpoint 52 of the voltage divider 50, the signal is still subject to the variability of the memristors M1 and M2. In fact, the midpoint voltage depends on the ratio between the resistance values ​​of memristors M1 and M2, which reduces the variability but not eliminates it completely.

[0115] The second reduction in variability is achieved with the use of inverter 48, as shown in reference to the figure 8 .

[0116] As a result, the output signal of inverter 48 is not sensitive to variations in the resistance of the memristors.

[0117] Following the example of the figure 4 , the counting unit 44 is formed by a capacitive bridge 58.

[0118] As previously stated, the counting unit 44 is suitable for counting the number of 1s in a series of bits, that is to say, for implementing a popcount operation.

[0119] A capacitive bridge 58 is a set of capacitors 60 connected in parallel and connected to each other on one of their terminals.

[0120] Furthermore, according to the example described, each capacitor 60 has the same capacitance value.

[0121] Each capacitor 60 is connected to its own specific XNOR component 42.

[0122] Therefore, the output voltage of the counting unit 44 is proportional to the number of 1s at the output of the XNOR components 42.

[0123] The output 44S of the counting unit 44 is connected to the comparator unit 46 which is used to compare an incident voltage to a comparator voltage.

[0124] More specifically, the comparison unit 46 comprises two elements: a comparator 62 and a comparison voltage generator 64. The output of the counting unit 44 is thus connected to an input 62E1 of the comparator 62, the other input 62E2 of the comparator 62 being connected to the comparison voltage generator 64.

[0125] According to the example described, the comparator voltage generator 64 is a second capacitive bridge 66 whose inputs are the inverses of the XNOR components 42 of the first capacitive bridge 58.

[0126] For this purpose, each capacitor 68 of the second capacitive bridge 66 is connected to an inverter 70 which is itself connected to a respective XNOR component 42.

[0127] The comparator voltage generator 64 thus generates a voltage proportional to the number of 0s at the output of the XNOR components 42.

[0128] The comparator 62 then compares the two voltages coming from the two capacitive bridges 58 and 66, that is to say here the number of 1s at the output of the XNOR components 42 and the number of 0s at the output of the XNOR components 42.

[0129] Comparator 62 generates a "1" at the output if the number of 1s is greater than the number of 0s and "0" otherwise.

[0130] The output of comparator 62 corresponds to the output of neuron 24.

[0131] According to another example illustrated by the figure 5 , the counting unit 44 is formed by a resistive bridge 96 with N resistances 98 instead of a capacitive bridge.

[0132] Furthermore, in this case of the figure 5 , the comparator voltage generator 46 is also a resistive bridge 100 also comprising N resistors 102.

[0133] Thus, the operation is similar to that described for the capacitive bridge 56. More precisely, a resistive bridge 96 is obtained where a certain number x of resistors 98 are subjected to the supply potential VDD (which corresponds to an output of 1 for the associated XNOR component), while the other Nx resistors 98 are subjected to ground GND (which corresponds to an output of 0 for the associated XNOR component 42). The resulting voltage is therefore a reflection of the ratio between the number of XNOR components 42 with a value of 1 and the number of XNOR components with a value of 0.

[0134] This approach has the advantage of working with all resistive memories, even those that cannot operate in capacitive mode.

[0135] Alternatively, the comparator voltage generator 64 is a generator that produces a fixed reference voltage. Typically, the comparator voltage generator 64 will be able to generate a voltage corresponding to half the supply potential, namely VDD 2 .

[0136] In this variant, comparator 62 generates a "1" as the neuron's output value if the number of 1s outputting the XNOR comparisons 42 corresponds to a voltage higher than the reference voltage. Otherwise, comparator 62 generates a "0" as the neuron's output value. At this point, it can be noted that the proposed use of a capacitive bridge 58 as a counting unit 44 in the case of RRAM cells is original.

[0137] In fact, the use of capacitive points for such a purpose is only found in the prior art in the case of static random access memory or SRAM (which comes from the corresponding English name of « Static Random Access Memory ») and in particular in the following two articles: an article by D. Bankmann et al. entitled "An always-on 3.8 mµJ / 86 % cifar 10 mixed-signal cnn processor with all memory on chip in 28-nm CMOS" published in 2018 from the ISSCC (International Solid-State Circuits Conference) organized by the IEEECC and an article by Hossein Valavi et al. entitled "A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement" published at the VLSI circuits symposium in 2018.

[0138] The first article proposes the assembly of the figure 9 As before, for a given neuron, the multiplications between the inputs and the weights are performed using XNOR gates, and the pop count operation is performed using the capacitive bridge: each XNOR gate is connected to a capacitor at its output, and all the capacitors are then connected together at their other ends, thus forming the capacitive bridge. To count the number of '0's at the output of the capacitive bridge, a second bridge is built using XOR gates this time: the voltage of the second bridge is proportional to the number of '0's at the output of the XNOR gates of the first bridge. Then, the voltages of the two bridges are compared by a comparator, generating a value '1' at the neuron's output if the voltage of the first bridge is greater than that of the second bridge.

[0139] Applying the structure proposed in this first article directly to an RRAM memory would require reading the weights from RRAM and the inputs from SRAM or RRAM to route each of these read values ​​to the capacitive neuron. This would necessitate complex routing at the memory's periphery to transport the weights stored in RRAM and the inputs stored in SRAM to the capacitive neurons. Therefore, this is not feasible, or at least would be far more complex than the present case.

[0140] The second article, by Valavi et al., presents the same structure, but integrates the XNOR operation and capacities directly into the SRAM cells, thus gaining in terms of bandwidth. figure 10 This illustrates the structure of the SRAM cell proposed in this article. The set of circuits in bold allows for the calculation of an XNOR operation between an input value and the weight stored in the SRAM cell, and then the loading of the XNOR operation value into a capacitor.

[0141] Applying the structure proposed in this second article directly to an RRAM memory allows us to obtain the assembly of the figure 11 .

[0142] However, this configuration is still unsatisfactory. This circuit charges the capacitor directly via the memristor, which transfers the memristor's variability to the capacitor's charge. Therefore, the problem remains, as the memristor's variability is still a limiting factor.

[0143] Furthermore, adding two transistors within each memory cell increases the overall memory area, so not only is variability still a nuisance, but the assembly is also more cumbersome.

[0144] In contrast, the present neuron 24 allows us to benefit from the advantages of a capacitive bridge 58 (low power consumption in particular) while cleverly managing the large variability of the memristors as explained previously with reference to the figure 8 .

[0145] Furthermore, as depicted on the figure 1 , such a neuron 24 is feasible in a very integrated manner since neuron 24 can be physically realized on only three lines 16 1 , 16 2 and 16 3 of the cell matrix 14.

[0146] An example of such an integrated implementation is now described with reference to figures 12 à 17 .

[0147] There figure 12 represents a realization of counting unit 44 on the first line 16 1.

[0148] The first line 16 1 therefore forms the capacitive bridge 58.

[0149] Before describing the first line 16 1 more precisely, it is appropriate to explain that a memristor exhibits the programmable resistance operation described previously with a low state LRS and a high state HRS only after a training step.

[0150] One of the forming steps involves applying a relatively high voltage (called forming voltage) to the memristor, typically a voltage between 3V and 4V depending on the technologies used.

[0151] Put another way, before formation, a memristor is in a so-called blank state and after formation exhibits the aforementioned behavior with the high HRS and low LRS states.

[0152] In its unformed state, the memristor exhibits capacitive behavior. Hereafter, such a memristor is called a "unformed memristor" to distinguish it from a formed memristor.

[0153] The first line 16 1 represented on the figure 12 is a line of elementary cells 12 in which each memristor is a blank memristor MV1 and MV2. Such a line 16 1 could therefore be described as a line of capacitive cells 2T2C, denoting each blank memristor MV1 and MV2 by "C". To clarify, the elementary cells 14 of the first line 16 1 are called capacitive cells 72.

[0154] In addition, the two switches T1 and T2 of each capacitive cell 68 are connected to each other.

[0155] This allows the two blank memristors MV1 and MV2 of the same capacitive cell 72 to be connected in parallel. As a result, the capacitance of a capacitive cell 72 is twice the capacitance of a single blank memristor MV1 or MV2.

[0156] All the capacitive cells 68 are connected to the same output line 74.

[0157] The output line 74 is connected to the midpoint located between the two blank memristors MV1 and MV2.

[0158] Such an implementation of the counting unit 44 is advantageous because it is based on a row 16 of standard memory cells taken before the memristor formation stage. The only modifications required are the addition of the output row 74 and the connections of each capacitive cell 72 to this output row 74. These modifications are made simply by changing the routing of the cell architecture (more commonly referred to by its English name, "layout") without any change to the architecture itself, which remains unchanged. The cell architecture is more commonly referred to by its English name, "layout." Here, it is indeed the layout that remains unchanged.

[0159] Furthermore, it will be explained later that such an arrangement makes it possible to obtain a procedure for erasing the blank memristors MV1 and MV2 which is relatively simple to implement.

[0160] With reference to figures 13 à 19 , it is explained how to perform the inversion part of neuron 24 using the second and third rows 16 2 and 16 3 of the cell matrix 14.

[0161] Before detailing the adaptation of these second and third lines 16 2 and 16 3, it is appropriate to specify that the memory cells 26 use switches 32 and 34 which are generally NMOS transistors, that is to say n-type MOSFETs.

[0162] Furthermore, it can be recalled that an INV inverter can be made from transistors as shown in the figure 13 .

[0163] The INV inverter consists of two transistors, TR and TT, connected in series. The left transistor, TR, is connected to ground (GND), and the right transistor, TT, is connected to the supply voltage (Vdd). Additionally, the right transistor, TT, is connected as a diode.

[0164] In such a configuration, the left-hand transistor TR is usually called the pull-up transistor or more often " pull-down transistor » in reference to the corresponding English name. The transistor on the right, TT, is usually called a pull-up transistor or more often « pull-up transistor ».

[0165] The input of the INV inverter is the gate of the pull-up transistor TR and the output of the INV inverter is the midpoint of the two transistors TR and TT.

[0166] Therefore, to obtain an inverter from a memory cell 26, two circuits can be considered. The first circuit is illustrated in the figure 14 and the second assembly corresponds to the figure 15 .

[0167] In the first setup, the two memristors M1 and M2 are short-circuited using a short-circuit track P cc.

[0168] Such an approach involves sizing the pull-up transistor TT to be more resistive than the pull-up transistor TR, in order to obtain a good quality low level.

[0169] In the second configuration, the pull-up transistor TT is still connected as a diode, but the short-circuit trace Pcc is different. Instead of being connected to short-circuit both memristors, the short-circuit trace Pcc is arranged only to short-circuit the memristor M1 of the pull-up transistor TR. Furthermore, the second memristor M2 is set to a high HRS state.

[0170] In the example described, the second memristor M2 should be in the high (HRS) state because the upper electrode (more commonly called the "top electrode" in reference to the corresponding English term) is connected to the midpoint of the 2T2R structure. Of course, in a configuration where the lower electrode ("bottom electrode" in English terminology) is connected to the midpoint, the second memristor M2 should be in the low (LRS) state.

[0171] This approach allows for a more resistive pull-up transistor (TR) without increasing the resistivity of the pull-up transistor (TT) connected as a diode. In such a circuit, only the connections are modified, not the cell architecture as previously described.

[0172] These two assemblies can be integrated into the cell matrix 14 by being implemented on a single line 16 of memory cells 26.

[0173] However, with reference to the figure 16 It is more favorable to put two inverters 48 and 76 in series as will be explained below.

[0174] The first inverter 48 and the second inverter 76 each have the structure described on the figure 15 , noting each element with a "1" in the reference sign for the first inverter 48 and a "2" for the second inverter 76.

[0175] With these notations, it is the first memristors M11 and M21 which are short-circuited respectively in the first inverter 48 and the second inverter 76.

[0176] The 48E input of the first inverter 48 is intended to be connected to a source line and is connected to the first transistor TR1 of this inverter.

[0177] The output 48S of the first inverter 48 is connected to the input 76E of the second inverter 76 and through to the first transistor TR2 of the second inverter 76.

[0178] The output 76S of the second inverter 76 is intended to be connected to the counting unit 44.

[0179] Thus, in this configuration, this implies that neuron 24 has two inverters 48 and 76 in series for each capacitor 60 of bridge 58.

[0180] Such a configuration offers several advantages.

[0181] It should be noted that the input 48E of the first inverter 48, which performs the XNOR operation, is quite close to half the supply potential. VDD 2 Therefore, the output signal of the first inverter 48 does not necessarily offer two widely separated "1" and "0" levels. The presence of the second inverter 76 allows the output signal of the first inverter 48 to be purified, resulting in significantly separated high and low levels.

[0182] Furthermore, such a configuration with two inverters 48 and 76 also allows the MV1 and MV2 memristors of the counting unit 44 to remain in their blank state. In fact, it is essential that the voltage across these blank memristors MV1 and MV2 does not exceed the forming voltage. With the proposed configuration of two inverters 44 and 76 in series, the first inverter 48 can be supplied with a high voltage to clearly distinguish between high and low levels, and the second inverter 76 can be supplied with a sufficiently low voltage so as not to exceed the forming voltage of the blank memristors MV1 and MV2 of the counting unit 44.

[0183] Finally, such a configuration can easily be achieved, as will be shown with reference to the figures 17 à 19 which illustrate how, in three successive steps, it is possible to go from two memory cells with blank memristors to memristors in the high HRS state. This illustration is also performed in the case where the upper electrode of the memristors is connected to the midpoint of the 2T2R structure.

[0184] In each of these steps, the word line WL of the counting unit 44 is grounded GND, the gate of the transistors of both inverters 48 and 76 is brought to supply potential VDD and the input 48E of the first inverter 48 is grounded GND.

[0185] The first step illustrated by the figure 17 consists of switching the second memristor M12 of the first inverter 48 from the blank state to the low state LRS.

[0186] For this, the output 48S of the first inverter 48 is connected to a voltage V1 greater than the forming voltage by activating a switch 78 connected to a first voltage source and the source TT1S of the first pull-up transistor TT1 is connected to ground GND.

[0187] The second step illustrated by the figure 18 consists on the one hand of switching the second memristor M12 of the first inverter 48 from the low state LRS to the high state HRS and on the other hand of switching the second memristor M22 of the second inverter 76 from the blank state to the low state LRS.

[0188] To transition from the low state LRS to the high state HRS, the output 48S of the first inverter 48 is connected to ground (GND) while leaving switch 78 activated but connecting it to ground. In parallel, the source TT1S of the first pull-up transistor TT1 is connected to the supply voltage VDD.

[0189] The transition from the blank state to the LRS low state is achieved by connecting the output 76S of the second inverter 76 to a voltage V2 higher than the forming voltage by activating a switch 80 connected to a second voltage source. In parallel, the TT2S source of the second pull-up transistor TT2 is connected to ground (GND).

[0190] The third step illustrated by the figure 19 consists of switching the second memristor M22 of the second inverter 76 from the low state LRS to the high state HRS.

[0191] For this purpose, the output 76S of the second inverter 76 is connected to ground (GND), and the source TT2S of the second pull-up transistor TT2 is connected to the supply voltage (VDD). In parallel, the voltages across the first inverter 48 are the same as in the second stage.

[0192] The operating configuration of two inverters 48 and 76 is thus easily obtained from two memory cells with blank memristors.

[0193] Through the description of figures 12 à 19 It was explained progressively how to make neuron 24 from only three lines 161, 162 and 163 of the cell matrix 14.

[0194] There figure 20 represents the details of the circuits of these three lines 161, 162 and 163 connected together and connected to their immediate environment.

[0195] As explained previously, the first line 16 1 allows obtaining the counting unit 44, the second line 16 2 allows obtaining a set of second inverters 76 and the third line 16 3 allows obtaining a set of first inverters 48.

[0196] In the figure 20 , only the extreme elements of each row 16, that is to say those corresponding to the first column 18 1 and the last column 18 n are represented.

[0197] As mentioned previously, the other lines 164 to 16N are used to store the weights of the neural network. In the figure 20 , only the fourth line 16 4 of the memorization set 27 is represented in an effort to simplify this figure.

[0198] Starting from the fourth line 16 4 towards the first line 16 1, the description can be made.

[0199] The 48E inputs of the first 48 inverters are connected to a respective SL source line from the fourth line 16 4. In the example of the figure 20 , the first source line SL 1 is therefore connected to the input 48E of the first inverter 48 on the left and the last source line SL n is connected to the input 48E of the first inverter 48 on the right.

[0200] With reference to the figure 4 Or 6 This means that the memristors M1 and M2 of the XNOR component 42 are the memristors 28 and 30 of a memory cell 26, and that the first voltages Vin and Vinb are generated by the complementary bit line pair BL and BLb. As follows from the explanation given in connection with the figure 4 , the values ​​of the first complementary voltages V in and V inb thus correspond to an input data value of the neuron, this input data being applied to the equivalent of a synapse of the neuron made by the elements of the column of the matrix (in particular the memristors 28 and 30 storing the synaptic weights).

[0201] As explained previously, the outputs 48S of the first inverters 48 are connected to the inputs 76E of the second inverters 76.

[0202] Each output 76S of a second inverter 76 is then connected to a capacitive cell 72. In this embodiment, this implies that neuron 24 presents two inverters 48 and 76 in series for each capacitor 60.

[0203] In the example provided, the power supplies for the two blank memristors MV1 and MV2 are connected in parallel so that their capacitances add up. Also, an output 76S of a second inverter 76 is connected to both the source of the first transistor of a capacitive cell 72 and the source of the second transistor of the same capacitive cell 72. It is worth recalling here that, by convention, in this document, the concepts of source and drain are defined with respect to the main bias direction, and that with reverse bias, the drain and source are reversed.

[0204] The output line 74 connected to the output of the capacitors 60 is connected to the comparator 62 which is located on the periphery of the cell matrix 14.

[0205] The output line 74 is also connected to a pull-up transistor 82 used to clear the blank memristors MV1 and MV2 after calculation.

[0206] Similarly, a pull-up transistor 84 is inserted on each source line SL to be able to bring it to zero potential.

[0207] The operation of these pull-up transistors 82 and 84 is described with reference to the figure 21 which illustrates the configuration to use to erase the blank memristors MV1 and MV2.

[0208] Thus, to implement such an erasure between two calculations, it is sufficient to activate the pull-up transistors 82 and 84 while grounding the WL word lines to GND, while the WL word line of the counting unit 44 is brought to the supply potential VDD.

[0209] The present implementation of the neuromorphic circuit 10 therefore allows for the accumulation of several advantages.

[0210] Since most of the components are contained within the area occupied by the cell matrix 14, the neuromorphic circuit 10 is less bulky compared to an embodiment in which each neuron would be realized at the periphery of the cell matrix 14.

[0211] Moreover, the neuromorphic circuit 10 exhibits good integrability into a set of memory cells 26. In fact, the conversion of an initial memory cell matrix 26 into the neuromorphic circuit 10 is relatively easy since only the top metal connections are impacted.

[0212] Furthermore, the neuromorphic circuit 10 uses capacitive bridges 58 and 66, and in each XNOR component, the current passes through a high resistance. This results in reduced power consumption.

[0213] Furthermore, the neuromorphic circuit 10 gains in robustness because it allows the variability of memristors 28 and 30 to be eliminated.

[0214] The neuromorphic circuit 10 that has just been described can advantageously be organized into banks to perform calculations in parallel.

[0215] For this, for example, with reference to the figure 22 , one approach may be to store the weights of a neuron on the same line 16 of the cell matrix 14, to activate the WL word line corresponding to this line 16 and to retrieve the result as output from neuron 24.

[0216] Several neurons 24 can be calculated in parallel by putting the weights of the different neurons on the same line and one after the other.

[0217] There figure 22 This illustrates an example for an implementation with three input neurons connected to two output neurons. Elements related to calculating the value given to the first output neuron are represented by solid lines, while elements related to calculating the value given to the second output neuron are represented by dashed lines.

[0218] To increase parallelism, it is possible to use the configuration proposed in the figure 23 . In this configuration, the SL source lines are cut in the middle of the 14-cell matrix to form several 86 subsets (mini-matrices) within the 14-cell matrix and allow independent control of its 86 subsets. In the example shown, the number n of 86 subsets is equal to 4.

[0219] The n subsets 86 sharing the same WL word lines constitute a group of subsets 88. Each subset 86 is associated with a neuron 24. Thus, by activating one WL word line per group of subsets 88, it is possible to calculate 2n outputs of neurons 24 in parallel.

[0220] In addition, it could be considered to cut the BL bit lines.

[0221] As illustrated by the figure 24 , a configuration with improved parallelism can be considered. The neuromorphic circuit 10 thus comprises several sets 90 (two in the case of the figure 24 ) each consisting of several subsets 92 created by interrupting the SL source lines in the middle of their set 90. Thus, by selecting one WL word line per set group 94, it is possible to calculate the outputs of each subset 92 in parallel. The SL source lines of each subset 92 can be connected to global SL source lines to allow the writing and reading of the stored weights in the conventional manner.

[0222] As is obvious to anyone skilled in the art, writing weights to memristors is done in a preliminary step before the actual neural computation. Similarly, the values ​​of the weights to be stored are defined during a training operation of the neural network before they are written to memory, and therefore before the neural computation, particularly when performing a neural inference calculation.

[0223] Each of the configurations described above allows calculations to be performed leading to the output of several neurons 24 in parallel and thus to increase the computational capacities of the neuromorphic circuit 10.

[0224] Each of the embodiments just described is compatible with other embodiments of neuron 24.

[0225] In particular, it has been described that the XNOR 42 component is made by two inverters 48 and 76 in series.

[0226] These inverters can, alternatively, perform another logical operation.

[0227] Thus, the first inverter 48 is replaced by a logic unit performing another operation involving an intermediate switching between ground (GND) and the supply voltage (VDD). In other words, the XNOR component 42 includes a logic unit 48 capable of performing a logic operation that toggles between a low and a high value depending on the value of the input to the logic unit 48 connected to the source line SL. This means that the XNOR component 42 depends solely on the value of the source line SL. Alternatively, the logic unit 48 may include other "inputs" besides the "input" corresponding to the source line SL, for example, in an embodiment such as the one described below in connection with the figure 25 However, these other inputs must have a neutral value during a neural computation operation. Therefore, the output value of logic unit 48 depends solely on the value present on the source line SL during a neural computation operation. Outside of neural computation operations, the other inputs of logic unit 48 can, as in the example in figure 25 , take non-neutral values ​​so as to participate in establishing the output value of the logic unit which is connected to the capacitive bridge.

[0228] Ideally, the switching voltage of the operation performed by such a logic unit is centered around half the supply potential, i.e. VDD 2 , within a margin, for example within 5%.

[0229] This means that logic unit 48 is, in the described example, an inverter or a double inversion (which is equivalent to the operation performed by a buffer). For example, the logic unit replacing the first inverter 48 is an XOR gate with an input set to 0. XOR is the English name for the logical "exclusive OR" operation.

[0230] According to another example, the logic unit replacing the first inverter 48 is a NAND gate with an input set to 1. NAND is the English name for the "not AND" operand.

[0231] In yet another example, the logic unit replacing the first inverter 48 is a NOR gate with an input set to 0. NOR is the English name for the "not OR" operand.

[0232] According to yet another variant depicted on the figure 25 , the counting unit 44 and the comparator voltage generator 64 are both formed by capacitive bridges and each include a CD offset capacitor.

[0233] It can be noted that the counting unit 44 is here controlled by a bit string whose number of 1s defines the comparison threshold and therefore any comparison threshold can be used.

[0234] The CD offset capacitor has a capacitance equal to C / 2.

[0235] In such a configuration, the equivalent electrical diagram of the counting unit 44 is that of the figure 26 .

[0236] The counting unit 44 corresponds electrically to a capacitance divider 114 comprising m capacitors 68 on one side and nm capacitors 68 on the other. In the preceding notation, n and m are integers, m denoting the number of capacitors 60 connected to an XNOR component 42 having an output corresponding to 1, and n the total number of capacitors 60. The midpoint 116 of the capacitance divider 114 is connected to one terminal of the offset capacitor CD, the other terminal of the offset capacitor CD being at the supply potential VDD.

[0237] With the capacitance divider 114 connected on one side to the supply voltage VDD and on the other side to ground GND, the following occurs: m + 0 , 5 . Δ = m + 0 , 5 n + 0 , 5 VDD

[0238] Where Δ is the tension interval between two states corresponding to two successive values ​​of m.

[0239] Similarly, with reference to the figure 27 The comparator voltage generator 64 corresponds electrically to a capacitance divider 110 comprising m capacitors 60 on one side and nm capacitors 60 on the other side. The midpoint 112 of the capacitance divider 110 is connected to one terminal of the offset capacitor CD, the other terminal of the offset capacitor CD being connected to ground GND.

[0240] With the 110 capacitance divider connected on one side to the supply voltage VDD and on the other side to ground GND, using the same notation as before, we have: m . Δ = m n + 0 , 5 VDD

[0241] From the two preceding formulas, two observations follow: firstly, the interthreshold Δ is such that Δ = 1 n + 0 , 5 VDD and on the other hand, there is a 0.5 Δ offset between the voltage levels of the counting unit 44 and those of the comparator voltage generator 46.

[0242] As shown in the schematic figure of the figure 28 This allows us to have a suitable comparison value for each level.

[0243] Alternatively, as shown on the figure 29 It is possible to use a configuration in which the thresholds are stored in a 118-cell matrix and controllable by selecting the desired WL word row. This allows for easy generation of a desired bit string.

[0244] Finally, from a physical implementation standpoint, it has been proposed to integrate neuron 24 across the three lines 161, 162, and 163 of the cell matrix 14, notably by using RRAM cells to obtain two components: memristors and capacitors. This effectively saves space.

[0245] However, it is also possible to position neuron 24 at the periphery of the cell matrix 14.

[0246] It is also possible to implement the 12 elementary cells using 1T1R cells in which the source lines are connected in pairs during computation. In such a configuration, two 1T1R cells behave during computation like a single 2T2R cell.

[0247] Moreover, as described, the neuromorphic circuit 10 is well suited for implementation in a planar, or two-dimensional (2D) integrated circuit, that is to say a circuit made on a single substrate, the electronic components of this circuit being made next to each other on this substrate.

[0248] Alternatively, the neuromorphic circuit 10 is made on a three-dimensional (3D) integrated circuit which corresponds to an electronic circuit whose electronic components are distributed in several distinct layers (levels or substrates) superimposed one on top of the other and electrically connected to each other.

[0249] In particular, three-dimensional structures with stacked nanowires or with multiple tiers can be considered. In the latter case, each line 16 of the cell matrix 14 has its SL source lines connected to a neuron located in the upper third. It is then possible to consider that the SL source lines are interconnected in the third tier.

[0250] It is also possible to consider more compact realizations of neuron 24, as schematically illustrated by the figure 30 Compared to the example shown in figure 20 The two series inverters connected to the bridge are removed. The inverter function is implemented here using the switches associated with the MV1 and MV2 memories that form the bridge elements.

[0251] In this example, the switches are NMOS transistors. A PMOS 120 transistor is added to the end of each SL source line. For each column, we therefore have a PMOS 120 transistor whose drain is connected to a Vdd supply and whose gate is connected to the SL source line of that column. The source of the PMOS 120 transistor is connected to the drains of the switches, which are connected to the memresistors MV1 and MV2 of that same column. This connection constitutes the equivalent of the output of an inverter formed by the PMOS 120 transistor and the two NMOS switches thus connected in parallel.

[0252] Another PMOS transistor can be placed at the end of each SL source line to reset the state of the bridge elements, namely the memristors MV1 and MV2. This complementary PMOS transistor, when activated, biases the source line to Vdd and consequently biases the output of the inverter formed by the PMOS transistor 120 and the switches to Gnd. Both electrodes of each memristor are then biased to Vdd during this memristor reset phase.

[0253] As is obvious to those skilled in the art, these reset operations are performed prior to a neural computation operation in which, as previously described, particularly in connection with the figures 4 And 5, the calculation of popcount from the input values ​​of the neuron applied to the pairs of complementary bit lines and the set of synaptic weights previously programmed (by writing) in the different memory cells based on memristors constituting the synaptic weights.

[0254] Since only the way in which logic unit 48 is implemented is modified, the operation of neuromorphic circuit 10 of the figure 30 is similar to what has been described previously.

[0255] Furthermore, this neuromorphic circuit 10 offers the same advantages, plus the following additional advantages.

[0256] It is no longer necessary to use the cell lines connected to the WL2 and WL3 word lines. However, it is necessary to provide n PMOS transistors outside the cell matrix. The area occupied by neuron 24 is generally smaller.

[0257] This variant is also advantageous because physically implementing the inversion with a "true CMOS inverter" consisting of a PMOS transistor and an NMOS transistor (the two switches in parallel) allows for a higher-quality inversion. Consequently, this results in better immunity to memristor variability, and therefore improved reliability of the calculations performed.

[0258] Furthermore, it is no longer necessary to implement the procedure for converting unformed 2T2R cells to two inverters as described in reference to figures 17 à 19 .

[0259] This makes it easier to implement the neuromorphic circuit 10.

[0260] According to one embodiment of the double capacitive bridge shown in figure 5 , it is possible to add an extension to the double capacitive bridge and the memory cell matrix to be able to adjust the threshold T i of the neuron to a desired value, other than the mid-power level V DD / 2.

[0261] To do this, we can use bias units 200, each bias unit 200 corresponding to a set of two bias capacitors mounted in differential according to a structure similar to that described previously for the capacitive bridge.

[0262] As seen on the figure 30 Each bias unit 200 is linked to an additional column and is controlled by a set of 2T2R cells connected to a pair of complementary bit lines BL, BLb and an additional source line SL. In this case, only the column linked to a bias unit 200 is shown on the figure 31 Furthermore, as with the other columns of the matrix, a logical unit is placed between each additional column and each bias unit of 200.

[0263] Thus, it is possible to set each bias unit 200 to 1 (or 0, respectively) by programming the memory cells of these additional columns similarly to what was described previously by monitoring the state of the memristors. A bias unit 200 is said to be "set to '1' or '0'" when the output of the inverter at the column's base delivers, for example, a voltage value of VDD or GND, respectively.

[0264] The bias units of 200 allow the neuron threshold to be shifted around V DD / 2, as will be explained in the diagrams. figures 32 à 34 .

[0265] As a reminder, the aforementioned calculation function expressed in terms of voltages is written as: a i = sign V DD n popcount j XNOR W ij a j − T i avec T i = V DD 2

[0266] Taking into account the bias units of 200, it becomes: a i = sign V DD n + b popcount j XNOR W ij a j − T i ′ avec T i ′ = V DD 2 − V DD n + b ∗ k i Or : ki corresponds to the number of bias units 200 to 1, and b is the total number of bias units 200.

[0267] The same equation expressed in the domain of integers gives: a i = sign popcount j XNOR W ij a j − T i avec T i = n 2 + b 2 − k i

[0268] In each of these figures, the elements of the counting unit 44 and the bias units 200 are represented by two facing capacitors. The elements of the counting unit 44 are to the left of a dotted line 202 which separates them from the bias units 200 on the right.

[0269] In this diagram, five elements for the counting unit 44 (corresponding to five input "synaptic branches" of the same neuron in the previous layer) are shown. As described earlier, each element of the counting unit 44 can take the value 1 or 0 depending on the voltage level present at the output of the inverter connected to the element. Thus, the signal on the load-pooling line connected to the + input of comparator 62 can take one of six possible voltage values, which we will call V1, V2, V3, V4, V5, and V6. In other words, this signal (at the + input) actually corresponds to the result of the popcount operation. The result of the popcount can also be expressed as an integer, with, for example, the integer value 0 corresponding to the voltage V1, the integer value 1 corresponding to V2, and so on up to the integer value 5 corresponding to V6.

[0270] Note that the bias units 200 always have the same logic control value for a given neuron (or in other words, for the same selected line). Consequently, regardless of their number, it does not change the number of possible voltage values ​​on the "popcount" signal (on the + input). However, the choice of the value assigned to each bias unit 200 will impact the voltage levels corresponding to the 6 values ​​V1 to V6.

[0271] In the absence of 200 bias units, the values ​​V1 to V6 correspond, for example, respectively to 0 V, VDD / 5, 2*VDD / 5, and so on up to V6 = VDD. With two 200 bias units set to "1", the values ​​V1 to V6 then correspond respectively to (2 / 7)*VDD, (3 / 7)*VDD, etc., up to VDD. With two 200 bias units set to "0", the values ​​V1 to V6 then correspond respectively to 0, (1 / 7)*VDD, (2 / 7)*VDD, up to (5 / 7)*VDD.

[0272] The comparison performed by comparator 62 corresponds to the implementation of the sign() function in the aforementioned equations, as well as the operation of subtracting the threshold value Ti. In the case of a differential capacitive bridge such as the one represented in figure 32 The output of comparator 62 will be high or low depending on whether the input + (terminal 62E1) is greater or less than the input - (terminal 62E1) of comparator 62. In other words, if the voltage on the popcount signal (input +) is greater than V DD / 2 the output of comparator 62 is "1" and if it is less than V DD / 2 the output of comparator 62 is 0.

[0273] In the absence of bias units 200, the values ​​V1 to V6 are distributed symmetrically around V DD / 2 and the result of the comparison gives the result of the function sign(popcount) with a threshold Ti equal to V DD / 2 if the popcount signal is expressed in Volts, or in other words with an equivalent threshold Ti equal to 2.5 if the popcount signal is expressed as a corresponding integer between 0 and 5.

[0274] With bias units of 200, the values ​​V1 to V6 are distributed differently on either side of VDD / 2. In the first example mentioned above (2 bias units of 200 to "1"), we thus have 2 values ​​V1 and V2 lower than VDD / 2 and 4 values ​​V3 to V6 higher than VDD / 2. The result of the comparison therefore gives the result of sign(popcount - Ti), with the threshold Ti = (3 / 14) VDD Volt.

[0275] With 2 units of bias 200, it is therefore possible to obtain 3 distinct threshold values ​​Ti.

[0276] More generally, with m units of bias 200, m+1 thresholds are obtained. The value of these thresholds depends in practice on the number of "input" branches of the neuron, in other words, the number of columns used to create the neuron and the number of bias 200 units.

[0277] This allows for a simple structure to be implemented that can provide threshold values ​​different from the mid-power VDD / 2. In practice, if the number of columns connected to the neuron is high, the threshold voltage Ti' can be varied around VDD / 2 with a few additional bias units. This is generally sufficient, as in most applications the desired threshold value Ti' will be equal to or close to VDD / 2.

[0278] Furthermore, this allows for a more "complete" training of a neural network by adding the possibility of also training threshold values ​​in addition to weight values.

[0279] In all the embodiments described above, the "input" and "output" values ​​of each neuron were coded on a single bit. In this sense, the neuromorphic circuit 10 implements a purely binary neural network, namely binary input and binary output.

[0280] However, the neuromorphic circuit 10 can also be modified to take "multi-bit" values ​​as input, that is, values ​​coded on several bits (each bit can take two possible values), and output a binary value. In such a case, the neural network implemented by the neuromorphic circuit 10 can be described as a binary output neural network.

[0281] To achieve this, as previously mentioned, at the level of a neuron, we want to perform an operation that can be written as: a i = sign popcount j XNOR W ij a j − T i in which the popcount operation is written: popcount j XNOR W ij x j = V DD n ∗ ∑ j = 1 n x j ⊙ W ij

[0282] The integer n here denotes the number of synaptic branches (or number of columns) to which neuron i is connected.

[0283] Furthermore, in this expression, to simplify understanding of what follows, for the neuron's inputs, instead of using the notation "aj," which can be confused with the notation "ai," the notation "xj" will be used. This "xj" notation clearly distinguishes these inputs from the "ai" outputs.

[0284] The operator ⊙ denotes bitwise multiplication performed by an XNOR gate, so it follows that: popcount j XNOR W ij x j k = ∑ j = 1 n x j k ⊙ W ij k Or : x j k denotes the k-th bit of the j-th input of the neuron, and W ij k denotes the k-th bit of the binary weight for the j-th input of the neuron, k can vary from 1 to m, m denoting the total number of bits for each input xj.

[0285] Now, as schematically represented on the figure 35 which aims to schematize the circuits previously exposed for an example with 5 synaptic branches per neuron and 1 single bit for each input (on each pair of bit lines BL and BLb), the neuromorphic circuit 10 has a first part 204 performing the popcount function and a second part 206 of comparison performing the sign operation and subtraction of the threshold Ti.

[0286] Rather than representing each component of the first part 204 in its entirety, a representation is used in which we see a table with cells storing a weight (respectively w i 1, w l1 and so on up to w l5). Each entry (x 1 to x 5) is to be multiplied by a weight indicated by a respective arrow pointing downwards in the figure and touching the weight box.

[0287] This simplified representation shows that the circuits described above, with the notations used in this paragraph, allow for the easy execution of only the following weighted summation operation: x 1 . w i 1 + x 2 . w i 2 + x 3 . w i 3 + x 4 . w i 4 + x 5 . w i 5

[0288] Note that in such an operation, a single bit is taken into account for each value xj.

[0289] Therefore, to reuse the previous 10 neuromorphic circuits, it will be necessary to first implement the sum over j (between 0 and n, the number of columns / synapses) and then the sum over k (between 1 and m), so that the popcount operation is written as: popcount j XNOR W ij x j = V DD n ∗ 1 2 m + 1 ∑ k = 1 m 2 k ∗ ∑ j = 1 n x j k ⊙ W ij k

[0290] Where m denotes the total number of bits for each input xj.

[0291] Such an operation can be implemented sequentially, for example using the implementation proposed on the figure 36 described in a simple example with 5 synapses (n=5) with 8 bits (m=8) for each input data xj.

[0292] By reusing a representation similar to that of the figure 35 In this case, a weight is used for each k-th bit of an input data xj instead of a single weight.

[0293] This leads, for the entry x 1, to a column with successively W i 1 1 , W i 1 2 … W i 1 8 and we will perform the calculation of the multiplications of each of these weights by each value of the corresponding bit of the input x 1. Thus, it is calculated x 1 1 ∗ W i 1 1 , Then x 1 2 ∗ W i 1 2 and so on until x 1 8 ∗ W i 1 8 As in the examples described previously, this calculation requires in practice the use of complementary bit lines BL and BLb connected to memory cells storing complementary values ​​in the two memristors of each memory cell. Thus, the second column, as before, stores the complementary weight values ​​( W ι 1 1 ¯ , W ι 1 2 ¯ … W ι 1 8 ¯ ) and receives additional data values ​​( x 1 1 ¯ , … , x 1 8 ¯ The circuit thus allows the output to provide all the results of each of the operations of the type x j k ∗ W ij k and this, in a sequential manner.

[0294] It is still necessary to accumulate these elements which arrive sequentially. This is the role of the counting device 208 at the output of the first part 204.

[0295] The metering device 208 comprises a first transfer unit 210 followed by a second accumulation unit 212.

[0296] For this purpose, the first transfer unit 210 includes a first switch S1 and a capacitor, called transfer capacitor 214, while the second unit 212 includes a second switch S2 and another capacitor, called accumulation capacitor 216.

[0297] An example of the operation of the counting device 208 is now described.

[0298] Prior to the operations described below, the two capacitors 214 and 216 are reset, and in the example described here the charges across the terminals of capacitors 214 and 216 are removed so that a zero voltage is present across their terminals.

[0299] The first part 204 first performs operations of the type x j 1 ∗ W ij 1 with both switches S1 and S2 open. These operations are performed by selecting a first row storing the weights with the index k=1.

[0300] Then, the first switch S1 is closed to transfer the result of the operations into the transfer capacitor 214, which stores a charge corresponding to a voltage value encoding the result of the sum over j des x j 1 ∗ W ij 1 .

[0301] The first switch S1 is then opened so that the first part 204 can perform new operations, here operations of the type x j 2 ∗ W ij 2 ,by selecting the line storing the weights with the index k=2.

[0302] Meanwhile, the second switch S2 is closed so that the transfer capacitor 214 and the accumulation capacitor 216 are connected.

[0303] The storage capacitor 216 is thus charged to a charge corresponding to half the value of the voltage of the transfer capacitor 214, that is: V DD n ∗ 1 2 ∑ j = 1 n x j 1 ∗ W ij 1 .

[0304] Then, the second switch S2 is opened again and the transfer capacitor 214 is reset to 0.

[0305] The first switch S1 then goes into the closed state and thus the transfer capacitor 214 is charged to a charge corresponding to a voltage value encoding the result of ∑ j = 1 n x j 2 ∗ W ij 2 operations of the type x j 2 ∗ W ij 2 having just been completed by the first part 204.

[0306] The first switch S1 is then opened so that the first part 204 can continue to perform operations, here type operations x j 3 ∗ W ij 3 .

[0307] Meanwhile, the second switch S2 is closed so that the transfer capacitor 214 and the accumulation capacitor 216 are connected.

[0308] The storage capacitor 216 is thus charged to a charge corresponding to: V DD n ∗ 1 2 1 2 ∑ j = 1 n x 1 1 ∗ W ij 1 + ∑ j = 1 n x j 2 ∗ W ij 2 = V DD n ∗ 1 4 ∑ j = 1 n x j 1 ∗ W ij 1 + 1 2 ∑ j = 1 n x j 2 ∗ W ij 2 .

[0309] And so on, up to operations of the type x j 8 ∗ W ij 8 to obtain a charge on the accumulator capacitor 216 corresponding to: V DD n ∗ 1 2 m + 1 ∑ k = 1 m 2 k ∗ ∑ j = 1 n x j k ∗ W ij k

[0310] Once the accumulation is complete, comparator 206 compares the voltage present on the accumulation capacitor 216 with a reference voltage which is chosen according to a threshold T i that we wish to apply in performing the subtraction (with T i ), the result of the comparison performed by comparator 206 being the output value ai.

[0311] In such an embodiment, the charge values ​​that the transfer capacitor 210 can take are very numerous, and consequently, the number of possible charge values ​​on the storage capacitor 216 after m transfers can quickly become very high if the number of inputs n is high. As a result, discrimination by the comparator 206 between two successive possible values, necessarily close to each other, can be difficult in practice or may require a very precise comparator, which is therefore bulky and energy-intensive.

[0312] To address this problem, according to a variant illustrated by the figure 37 , a second comparator 220 is inserted upstream of the counting device 208.

[0313] The second comparator 220 performs a comparison with a threshold noted T ki .

[0314] Using the previous notation, this leads to the following operation: a i = sign 1 2 m + 1 ∑ k = 1 m 2 k ∗ sign V DD n ∑ j = 1 n x j k ∗ W ij k − T ki − T i

[0315] The reference voltage applied to the input of comparator 206 is a function of the threshold T ki . According to the simplest embodiment, the same reference voltage value is applied throughout the iterative process explained above (with successive selection of the m lines).

[0316] In this example, the transfer capacitor 214 will take one of two possible values, namely VDD or Gnd. Consequently, the storage capacitor 216 can take, at the end of the m accumulation cycles, one of 129 possible values ​​in the case m=8 (if both capacitors 214 and 216 have the same capacitance), which can make it easier to discriminate between two successive levels using a relatively simple, compact comparator.

[0317] According to yet another variant corresponding to the figure 38 , while retaining the second comparator 220, the first unit 210 and the second unit 212 are made according to a differential assembly.

[0318] This means that each of the two units 210 and 212 have similar switches and capacitors placed opposite each other in two ways.

[0319] Such a variant allows for better robustness conferred by the differential mounting in terms of discrimination between several levels, at the level of the second comparator 220 while having a "single" capacitive bridge and not differential in part 204 which allows to limit the bulk of this part 204 because its size can quickly become significant in the case of a differential bridge with a high number of columns.

[0320] According to a variant of the two embodiments represented respectively in figures 37 And38 , it is possibly possible not to provide the accumulation capacitor 216 and the comparator 206 and to use in practice only the comparator 220 to provide a sequence of binary values ​​at the output of the neuron, this sequence of m binary values ​​(on 1 bit) forming the equivalent of a "multi-bit" binary value at the output of the neuron.

[0321] Furthermore, according to a variant of the scheme shown in figure 25It is possible to provide a different reset device for the capacitive bridge. In such a variant, the AND gates are removed, and the inverter outputs are directly connected to the capacitors on each side of the capacitive bridge. During a reset operation, a bias control device for each source line SL of the matrix applies a zero voltage (GND) to the SLs, so that the "right-hand" inverters (connected to the capacitors otherwise connected to the positive input of comparator 62) have an output voltage equal to VDD, and the "left-hand" inverters (connected to the capacitors otherwise connected to the negative input of the comparator) have an output voltage equal to GND.The "right-hand" NMOS transistor 82 (the one connected to the comparator's positive input) is replaced by a PMOS transistor 82' whose source is connected to VDD and whose drain is connected to the common line of the "right-hand" capacitors (which is connected to the comparator's positive input). Thus, during a reset operation, prior to a neural computing operation, the capacitors on the left see a zero voltage across each of their terminals, and the capacitors on the right see a voltage equal to VDD across each of their terminals; this leads to the discharge of charges in all the capacitors. It should be noted that the bias control device for each SL line is, of course, rendered inoperative during a neural computing operation (its output being, for example, set to a high impedance state to avoid conducting interfering current).

[0322] In all the embodiments presented, an implementation of a neural network was thus presented which can be made compact and exhibit low power consumption.

Claims

1. A neuromorphic circuit (10) suitable for implementing a neural network with binary output, the neuromorphic circuit (10) comprising: - word lines (WL), - pairs of complementary bit-lines (BL, BLb), - source lines (SL), - a set of elementary cells (12) organized according to a two-dimensional matrix (14) comprising rows (16) and columns (18), the set of elementary cells (12) including a storage assembly (27) grouping together a set of lines (16) of elementary cells (12), the elementary cells (12) of the storage assembly (27) being memory cells (26), where the memory cells (26) of the same line (16) can be selected by a word line (WL), the memory cells (26) of the same column (18) being connected to a pair of complementary bit-lines (BL, BLb) and a source line (SL), each memory cell (26) comprising two memristors (28, 30) and two switches (32, 34), each memristor (28, 30) being connected to the same source line (SL) and to a corresponding switch (32, 34)), each memristor (28, 30) storing a weight or the inverse of the same weight, respectively, and having different first and second resistance values, respectively, the switches being connected for the activation thereof, to a word line (WL) and correspondingly connected to a pair of complementary bit-lines (BL, BLb), each pair of complementary bit lines receiving complementary input voltages (Vin, Vinb) during a neural calculation operation, - an electronic circuit implementing a neurone (24) having an output and including: - a set of logic components (42), each logic component (42) having a logic unit (48) comprising an input connected to a corresponding source line (SL), the logic unit (48) being suitable for performing a logic operation which switches between a low value and a high value depending only on the value of the input of the logic unit (48) which is connected to the source line (SL) during said neuronal calculation operation, each logic unit (48) performing a logic function such as an inverter or a double inverter, - a counting unit (44), the counting unit (44) being suitable for counting the number of high or low values at the output of the logic components (42), the counting unit (44) being a bridge (58, 96), a bridge (58, 96) being a set of the same elements (60, 98) in parallel and connected to each other at one of the terminals thereof to an output of the counting unit, each element (60, 98) being connected to a corresponding logic component (42) and being a resistor (98) or a capacitor (60), - a comparison unit (46) comprising a comparator (62) and a comparison voltage generator (64), the comparator (62) being suitable for comparing the output of the counting unit (44) with the comparison voltage generated by the comparison voltage generator (64) so as to output a signal depending on the comparison and corresponding to the output of the electronic circuit implementing a neurone (24).

2. The neuromorphic circuit according to claim 1, wherein each memristor (28, 30) has a virgin state, the counting unit (44) being a line (16) of elementary cells (12), each elementary cell (12) of the counting unit (44) being a cell comprising two memristors in the virgin state (MV1, MV2) and two switches (T1, T2), each memristor in the virgin state (28, 30) being connected to the other memristor in the virgin state (MV1, MV2) and to a corresponding switch (T1, T2), the switches (T1, T2) being connected to each other.

3. The neuromorphic circuit according to claim 1 or 2, wherein each logic unit (48) comprises an inverter formed from an elementary cell (12) comprising two memristors (M1, M2) and two switches (TR, TT), each memristor (M1, M2) being connected to the other memristor (M1, M2) and to a corresponding switch (TR, TT), a short-circuit track (Pcc) being arranged for short-circuiting the two memristors (M1, M2), one of the switches (T1, T2) being connected to ground and to the input of the logic unit for the control thereof and the other switch being connected to a supply potential and mounted as a diode.

4. The neuromorphic circuit according to claim 1 or 2, wherein each logic unit (48) comprises an inverter formed from an elementary cell (12) comprising two memristors (M1, M2) and two switches (TR, TT), each memristor (M1, M2) being connected to the other memristor (M1, M2) and to a corresponding switch (TR, TT), a first switch (TR) being connected to the ground and to the input of the logic unit for the control thereof and the second switch (TT) being connected to a supply potential and mounted as a diode, a short-circuit track (Pcc) being arranged for short-circuiting the memristor (M1) connected to the first switch (TR).

5. The neuromorphic circuit according to any one of claims 1 to 4, comprising a first controller (20) for selecting the elementary cells of a line, which are connected to a same word line (WL), and comprising a second controller connected to the pairs of bit-lines and used for applying different voltages to each pair of bit-lines and symmetrical with respect to a middle voltage, where the voltage applied to a bit-line is either higher or lower than the voltage applied to the associated complementary bit-line depending on the value of an input signal, each input signal corresponding to an input of a synapse connected to said neurone.

6. The neuromorphic circuit according to claim 5, wherein the set formed by each logic unit (48) is formed from at least one line (162, 163) of elementary cells (12) not belonging to the storage assembly (27).

7. The neuromorphic circuit according to claim 2, wherein each logic unit corresponds to an inverter (76) formed of said switches of each elementary cell (12) of the counting unit (44) and a PMOS transistor (120) the drain of which is connected to a supply voltage (Vdd), the gate of which is connected to a source line SL and the source of which is connected to the drains of said switches.

8. The neuromorphic circuit according to any one of claims 1 to 7, wherein the comparison voltage generator (64) is a fixed voltage generator.

9. The neuromorphic circuit according to any one of claims 1 to 8, wherein the comparison voltage generator (64) is a second bridge (66, 100) having the same elements (68, 102) as the counting unit (44), each element (68, 102) of the second bridge (66, 100) being connected to an inverter (70) connected to a corresponding logic unit (42).

10. The neuromorphic circuit according to claim 9, wherein the elements of the two bridges (58, 66) are capacitors (68) having the same capacitance, the comparison voltage generator (64) and the counting unit (44) having an offset capacitor (CD), the offset capacitor (CD) having a capacitance equal to one half of the capacitance of a capacitor (60, 68) of one of the two bridges (58, 66).

11. The neuromorphic circuit according to any one of claims 1 to 10, wherein the logic operation performed by each logic unit (48) is selected from: an exclusive-or with an input set to 0, an inversion, a non-and with one of the two inputs set to 1, a non-or with one of the two inputs set to 0.

12. The neuromorphic circuit according to any one of claims 1 to 11, wherein the neuromorphic circuit includes pull-down transistors (82, 84), one of the pull-down transistors (82) being connected to all of the elements (60, 98) of the counting unit (44) and the other pull-down transistors (84) being connected to a corresponding source line (SL), the pull-down transistors (82, 84) being suitable for erasing the elements (60, 68, 98, 102).

13. The neuromorphic circuit according to any one of claims 1 to 12, wherein the neuromorphic circuit (10) includes a plurality of distinct sets of elementary cells (12) suitable for working in parallel.

14. The neuromorphic circuit according to claim 13, wherein the source lines (SL) have a plurality of portions, where portions of the lines are specific to a set of elementary cells (12).

15. The neuromorphic circuit of any one of claims 1 to 14, wherein the neuromorphic circuit (10) is a three-dimensional integrated circuit.