BATTERY CHARGING CIRCUIT, BATTERY PACK AND BATTERY PACK CHARGING SYSTEM

Description

TECHNICAL FIELD

[0001] The disclosure relates to the technical field of battery pack charging, in particular to a battery charging circuit, a battery pack and a battery pack charging system.BACKGROUND

[0002] At present, in the battery pack industry, battery pack charging is generally controlled by the MCU controlling the on-off of one or more PMOS transistors on the charging circuit. In the low-current charging mode, this solution has obvious advantages. It can prevent charging from overvoltage and ensure that there is no voltage when the charging port is not used, which is safe and reliable. However, with the continuous innovation of battery technology and the increasing capacity of battery packs, high-current fast charging technology has become more and more widely used. Due to process limitations, the conventional solution of PMOS transistors has a relatively large internal resistance and a high temperature rise in the fast charging mode, which requires additional cooling devices to cool down and results in a large volume and high cost.

[0003] US2020381917 discloses a secondary battery protection circuit for protecting a secondary battery, including a low-voltage detecting circuit configured to detect a voltage across the secondary battery that is lower than a second voltage for low voltage detection. The second voltage being set to be lower than a first voltage for overdischarge detection and a switching circuit configured to cause a gate of a charge control NMOS transistor to be fixed at a potential at a high side power supply terminal, upon detecting, by the low-voltage detecting circuit, that the voltage across the secondary battery is lower than the second voltage for low voltage detection.

[0004] US2012112686 discloses a control circuit of a battery power-path management circuit that establishes a first power path between a battery input node and an output node when the input node voltage is larger than a charger input node voltage and a second power path between the charger input node and the output node when the voltage on the charger input node is larger than the battery input node voltage. It controls the second power path to provide power to the output node, enabling battery charging and protection over a battery voltage range from about zero volts. It has low power consumption and can support wide-swing power supply voltage from as low as one volt to as high as maximum allowed Vds of drain-extended devices. It can use smaller device sizes because the PMOS switch gate voltage is 0V when the power supply is not too high.

[0005] US 2009197156 discloses a battery pack including a secondary battery, a discharge-control transistor, a charge-control transistor connected in series with the discharge-control transistor between a negative power source terminal of the secondary battery and either a terminal of a load or a negative power source terminal of a charger, and a battery protection semiconductor device for protecting a secondary battery. The battery protection semiconductor device includes a detection circuit that detects at least one of an excessively charged state, an excessive discharging state, an overcurrent state, a short-circuit state, and an overheating state of the secondary battery, a control circuit that turns on and off the discharge-control transistor and the charge-control transistor, and a charge prevention circuit that prevents the secondary battery from being charged by turning off the charge-control transistor when a voltage of the secondary battery is not greater than a predetermined low-voltage criterial voltage variable by trimming a portion of the charge prevention circuit. Other examples of prior art documents are CN 110 429 833 A and EP 1 533 882 A2.SUMMARY

[0006] The disclosure provides a battery charging circuit, a battery pack and a battery pack charging system. It is used to solve technical problems of a need of additional heat dissipation devices to cool when using conventional PMOS transistors to control a charging of a battery pack, which results in a large volume and high cost.

[0007] The disclosure provides battery charging circuits as claimed in claim 1 and claim 7. Preferred embodiments are described in the dependent claims. The invention is set out in the appended claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 shows a circuit view of a first embodiment of a battery charging circuit of the disclosure. FIG. 2 shows a circuit view of a second embodiment of the battery charging circuit of the disclosure. FIG. 3 shows a circuit view of a third or fourth embodiment of the battery charging circuit of the disclosure. FIG. 4 shows a circuit view of a fifth or sixth embodiment of the battery charging circuit of the disclosure. FIG. 5 shows a circuit view of a seventh or eighth embodiment of the battery charging circuit of the disclosure. FIG. 6 shows a schematic view of a direct current charger of an embodiment of the disclosure. FIG. 7 shows a schematic view of an alternating current charger of an embodiment of the disclosure. FIG. 8 shows a charging logic view of a battery pack of an embodiment of the disclosure. FIG. 9 shows an exploded schematic view of the battery pack and the charger of an embodiment of the disclosure. DETAILED DESCRIPTION

[0009] The following describes the implementation of the disclosure through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the disclosure from the content disclosed in this specification. The disclsoure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the disclosure.

[0010] Please refer to FIG.1 through FIG.9, it should be noted that the figures provided in this embodiment only illustrate the basic idea of the disclosure in a schematic manner. The figures only show the components related to the disclosure instead of drawing according to the number, shape and size of the components during actual implementation. The type, number and proportion of each component during actual implementation can be changed at will, and the layout of its components may also be more complicated.

[0011] In order to solve the technical problem of a need to add an additional cooling device when using a battery pack with a PMOS transistor to charge and control, which results in large volume and high cost, please refer to FIG. 1 through FIG. 5, the disclosure provides a battery charging circuit. The battery charging circuit includes a charging terminal, an NMOS transistor Q11, a switch control unit 20 and a power supply unit 10. According to different connection positions of the NMOS transistor Q11, the NMOS transistor Q11 may be high-side driving as shown in FIG. 1, FIG. 2 and FIG. 4, or low-side driving as shown in FIG. 3 and FIG.5. The NMOS transistor Q11 is an NMOS transistor with a body diode. The charging terminal is used to connect with a charger, the switch control unit 20 is used to sample a voltage between the source and the drain of the NMOS transistor Q11 to control on-off of the NMOS transistor Q11, and the power supply unit 10 is used to supply power to the switch control unit 20. A power source of the power supply unit 10 may be provided by a voltage at the charging terminal as shown in FIG. 1 through FIG. 3, which means that it is powered by the charger. It may also be directly provided by a battery unit 40 as shown in FIG. 4 and FIG. 5. The battery unit 40 may also be called a battery module, or a battery string, which includes several battery cells (also called cells). The disclosure controls on-off of the charging circuit through the NMOS transistor. Compared with conventional PMOS transistor control, it has characteristics of strong overcurrent capability, low heat generation, high charging efficiency and prevention of discharge from a charging port. It should be noted that the battery charging circuit of the disclosure may be integrated into the battery pack or into a corresponding charger.

[0012] Please refer to FIG. 1, FIG. 2 and FIG. 4, the NMOS transistor Q11 is a high-side driving NMOS transistor with a body diode, and the charging terminal includes a charging positive terminal 91 and a charging negative terminal 92. A source of the NMOS transistor Q11 is connected with the charging positive terminal 91, and a drain of the NMOS transistor Q11 is connected with a positive electrode of the battery unit 40. The switch control unit 20 is respectively connected with a gate, source, and drain of the NMOS transistor Q11, and the switch control unit 20 controls the on-off of the NMOS transistor Q11 by sampling a voltage between the source and the drain of the NMOS transistor Q11. An output end of the power supply unit 10 is connected with a power source end of the switch control unit 20 for supplying power to the switch control unit 20.

[0013] Please refer to FIG. 1, FIG. 2 and FIG. 4, the battery charging circuit further includes an NMOS transistor Q12, a controller 30, and a low-dropout linear regulator 60. A drain of the NMOS transistor Q12 is connected with the drain of the NMOS transistor Q11. A source of the NMOS transistor Q12 is connected with the positive electrode of the battery unit 40, wherein a second control switch 12 is a secondary protection of NMOS to prevent the charger from over charging. The NMOS transistor Q12 is, for example, a NMOS transistor with a body diode. The controller 30 is used to control on-off of the NMOS transistor Q12. A power supply end of the controller 30 is connected with the positive electrode of the battery unit 40 through the low-dropout linear regulator 60, and the low-dropout linear regulator 60 is used to supply power to the controller 30.

[0014] Please refer to FIG. 3 and FIG. 5, the NMOS transistor Q11 is a low-side drive NMOS transistor with a body diode, and the charging terminal includes a charging positive terminal 91 and a charging negative terminal 92. The source of the NMOS transistor Q11 is connected with a negative electrode of the battery unit 40, and the drain of the NMOS transistor Q11 is connected with the negative charging terminal 92. The switch control unit 20 is respectively connected with the gate, source, and drain of the NMOS transistor Q11. The switch control unit 20 controls the on-off of the NMOS transistor Q11 by sampling a voltage between the source and the drain of the NMOS transistor Q11. An output terminal of the power supply unit 10 is connected with a power source end of the switch control unit 20 for supplying power to the switch control unit 20. Please refer to FIG. 3 and FIG. 5, the battery charging circuit further includes an NMOS transistor Q12, a controller 30, and a low-dropout linear regulator 60. A source of the NMOS transistor Q12 is connected with the source of the NMOS transistor Q11, and a drain of the NMOS transistor Q12 is connected with the negative electrode of the battery unit 40. The controller 30 is used to control on-off of the NMOS transistor Q12. A power supply end of the controller 30 is connected with the positive electrode of the battery unit 40 through the low-dropout linear regulator 60, and the low-dropout linear regulator 60 is used to supply power to the controller 30.

[0015] Please refer to FIG.1 through FIG. 5, the battery charging circuit further includes a voltage collection unit 70 and a temperature collection unit 50 connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as a PTC sensor) or a negative temperature coefficient sensor (abbreviated as an NTC sensor).

[0016] Please refer to FIG.1 through FIG. 5, the battery charging circuit further includes a communication terminal and a communication module 80. The communication terminal is connected with the controller 30 through the communication module 80, and the communication module 80 provides information interaction for the battery unit 40 and the charger.

[0017] According to a power supply mode of the power supply unit 10 (powered by the battery unit 40 as shown in FIG. 4 and FIG. 5 and powered by the voltage at the charging terminal as shown in FIG.1 through FIG.3), a driving mode of a first control unit (the high-side driving shown in FIG. 1, FIG. 2 and FIG. 4 and the low-side driving shown in FIG. 3 and FIG. 5) and charging types (alternating current and direct current), the battery charging circuit has eight different control modes , which respectively correspond to following first embodiment to eighth embodiment.

[0018] The disclosure also provides a battery pack charging system. The battery pack charging system includes a charger, the battery charging circuit shown in FIG. 1 through FIG. 5 and a battery unit 40. The battery unit 40 is connected with the charger through the battery charging circuit, and the charger includes an alternating current charger 700 as shown in FIG. 7 or a direct current charger 600 as shown in FIG. 6.

[0019] Hereinafter, the battery charging circuit of the disclosure will be described in detail with reference to the drawings.The first embodiment

[0020] In this embodiment, please refer to FIG. 1, a battery charging circuit 100 is suitable for direct current charging high-side control. The power supply unit 10 is powered by a voltage at a charging terminal. The battery charging circuit 100 is connected with an output terminal of a direct current charger 600 as shown in FIG. 6 through the charging terminal. The NMOS transistor Q11 is an NMOS transistor with a body diode.

[0021] Please refer to FIG. 1, the power supply unit 10 includes a boost circuit chip U1 (for example, a model may be MC34063), a first resistor R11, a second resistor R12, a third resistor R13, a first diode D11, a second diode D12, an inductor L11, a first capacitor C11, and a second capacitor C12. An anode of the first diode D11 is respectively connected with the charging positive terminal 91 and a source of the NMOS transistor Q11, a cathode of the first diode D11 is connected with the charging negative terminal 92 via the first capacitor C11, at the same time, the cathode of the first diode D11 is respectively connected with a VCC pin of the boost circuit chip U1 and one end of the first resistor R11, the other end of the first resistor R11 is connected with one end of the inductor L11 and a second end of the boost circuit chip U1, the other end of the inductor L11 is respectively connected with a SW pin of the boost circuit chip U1 and an anode of the second diode D12, a cathode of the second diode D12 is further connected with the charging negative terminal 92 via the second capacitor C12, at the same time, the cathode of the second diode D12 is further respectively connected with a power source end of the switch control unit 20 and one end of the third resistor R13, the other end of the third resistor R13 is connected with a COM pin of the boost circuit chip U1, simultaneously, the other end of the third resistor R13 is connected with the charging negative terminal 92 via the second resistor R12, and a GND pin of the boost circuit chip U1 is connected with the charging negative terminal 92.

[0022] Please refer to FIG. 1, the switch control unit 20 includes an intelligent synchronous rectification control chip U2 (for example, the model may be MP6905), a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, and a Zener diode ZD21. A VSS pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the charging positive terminal 91, at the same time, the VSS pin of the intelligent synchronous rectification control chip U2 is connected with one end of the first resistor R21. The other end of the first resistor R21 is connected with an LL pin of the intelligent synchronous rectification control chip U2. A PGND pin of the intelligent synchronous rectification control chip U2 is respectively connected to the source of the NMOS transistor Q11 and the charging positive terminal 91. A VG pin of the intelligent synchronous rectification control chip U2 is connected with a gate of the NMOS transistor Q11 via the fourth resistor R24. A VD pin of the intelligent synchronous rectification control chip U2 is connected with a drain of the NMOS transistor Q11 via the third resistor R23. An EN pin of the intelligent synchronous rectification control chip U2 is respectively connected with one end of the second resistor R22 and a cathode of the Zener diode ZD21. An anode of the Zener diode ZD21 is connected with the charging negative terminal 92. The other end of the second resistor R22 is respectively connected with the VCC pin of the intelligent synchronous rectification control chip U2 and the output end of the power supply unit 10.

[0023] In this embodiment, please refer to FIG. 1, the battery charging circuit 100 further includes an NMOS transistor Q12, a controller 30, a low-dropout linear regulator 60, a PMOS transistor Q13, a first resistor R31, and a Zener diode ZD31. The NMOS transistor Q12 is an NMOS transistor with a body diode, which is used for secondary protection to prevent the charger from running out of control and over charging. A source of the PMOS transistor Q13 is connected with the output of the power supply unit 10. A drain of the PMOS transistor Q13 is connected with one end of the first resistor R31. The other end of the first resistor R31 is respectively connected with a gate of the NMOS transistor Q12 and a cathode of the Zener diode ZD31. An anode of the Zener diode ZD31 is respectively connected with a source of the NMOS transistor Q12 and a positive electrode of the battery unit 40. A drain of the NMOS transistor Q12 is connected with the drain of the NMOS transistor Q11. A gate of the PMOS transistor Q13 is connected with the controller 30. The controller 30 controls on and off of the output terminal of the power supply unit 10 and the gate of the NMOS transistor Q12 by controlling on and off of the PMOS transistor Q13, thereby controlling the on and off of the NMOS transistor Q12.

[0024] In this embodiment, please refer to FIG. 1, the battery charging circuit 100 further includes a voltage collection unit 70 and a temperature collection unit 50. The voltage collection unit 70 and the temperature collection unit 50 are connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as PTC sensor) or a negative temperature coefficient sensor (abbreviated as NTC sensor).

[0025] Please refer to FIG. 1 and FIG. 6. When charging, a positive output terminal 11 and a negative output terminal 12 of the direct current charger 600 as shown in FIG. 6 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 100. A communication port 13 of the direct current charger 600 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 100 and a communication module 80, thereby realizing an information interaction between the battery unit 40 and the charger. As shown in FIG. 8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the direct current charger 600 is connected with the battery charging circuit 100; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0026] Please refer to FIG. 1 and FIG. 6. When charging, a direct current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a positive line (high end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. The power source of the power supply unit 10 is provided by a voltage at the charging terminal, so that a self-consumption of the battery during storage may be reduced.The second embodiment

[0027] In this embodiment, please refer to FIG. 2. A battery charging circuit 200 is suitable for an alternative current charging high-side control. A power supply unit 10 is powered by a voltage at a charging terminal. The battery charging circuit 200 is connected with an output terminal of an alternative current charger 700 as shown in FIG. 7 through the charging terminal. The NMOS transistor Q11 is an NMOS transistor with a body diode.

[0028] Please refer to FIG. 2. The power supply unit 10 includes a fourth resistor R14, a fifth resistor R15, an NPN triode Q14, a third capacitor C13, a third diode, and a Zener diode ZD11. A base of the NPN triode is respectively connected with a cathode of the Zener diode ZD11 and one end of the fifth resistor R15. An anode of the Zener diode ZD11 is respectively connected with a charging positive terminal 91 and a source of the NMOS transistor Q11. The other end of the fifth resistor R15 is respectively connected with one end of the fourth resistor R14 and a cathode of the third diode D13. An anode of the third diode D13 is connected with a charging negative terminal 92. The other end of the fourth resistor R14 is connected with a collector of the NPN triode Q14. An emitter of the NPN triode Q14 is connected with the charging positive terminal 91 and the source of the NMOS transistor Q11 via the third capacitor C13, and at the same time the emitter of the NPN triode Q14 is connected with a power terminal of the switch control unit 20.

[0029] Please refer to FIG. 2. The switch control unit 20 includes an intelligent synchronous rectification control chip U2 (for example, the model may be MP6905), a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, and a Zener diode ZD21. A VSS pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the charging positive terminal 91, and at the same time the VSS pin of the intelligent synchronous rectification control chip U2 is connected with one end of the first resistor R21. The other end of the first resistor R21 is connected with an LL pin of the intelligent synchronous rectification control chip U2. A PGND pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the charging positive terminal 91. A VG pin of the intelligent synchronous rectification control chip U2 is connected with a gate of the NMOS transistor Q11 via the fourth resistor R24. A VD pin of the intelligent synchronous rectification control chip U2 is connected with a drain of the NMOS transistor Q11 via the third resistor R23. An EN pin of the intelligent synchronous rectification control chip U2 is respectively connected with one end of the second resistor R22 and a cathode of the Zener diode ZD21. An anode of the Zener diode ZD21 is connected with the charging negative terminal 92. The other end of the second resistor R22 is respectively connected with a VCC pin of the intelligent synchronous rectification control chip U2 and an output end of the power supply unit 10.

[0030] In this embodiment, please refer to FIG. 2. The battery charging circuit 200 further includes an NMOS transistor Q12, a controller 30, a low-dropout linear regulator 60, a PMOS transistor Q13, a resistor R31, and a Zener diode ZD31. The NMOS transistor Q12 is an NMOS transistor first with a body diode, which is used for secondary protection to prevent a charger from running out of control and over charging. A source of the PMOS transistor Q13 is connected with the output end of the power supply unit 10. A drain of the PMOS transistor Q13 is connected with one end of the first resistor R31. The other end of the first resistor R31 is respectively connected with a gate of the NMOS transistor Q12 and a cathode of the Zener diode ZD31. An anode of the Zener diode ZD31 is respectively connected with a source of the NMOS transistor Q12 and a positive electrode of the battery unit 40. A drain of the NMOS transistor Q12 is connected with a drain of the NMOS transistor Q11. A gate of the PMOS transistor Q13 is connected with the controller 30. The controller 30 controls on and off of the output terminal of the power supply unit 10 and the gate of the NMOS transistor Q12 through controlling on and off of the PMOS transistor Q13, thereby controlling on and off of the NMOS transistor Q12.

[0031] In this embodiment, please refer to FIG. 2. The battery charging circuit 200 further includes a voltage collection unit 70 and a temperature collection unit 50 connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as PTC sensor) or a negative temperature coefficient sensor (abbreviated as NTC sensor).

[0032] Please refer to FIG.2 and FIG.7. When charging, a positive output terminal 11 and a negative output terminal 12 of the alternative current charger 700 as shown in FIG. 7 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 200. A communication port 13 of the alternative current charger 700 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 200 and a communication module 80, so as to realize an information interaction between the battery unit 40 and the charger. Please refer to FIG.8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the alternative current charger 700 is connected with the battery charging circuit 200; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0033] Please refer to FIG. 2 and FIG. 7. When charging, an alternative current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a positive line (high end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of a source and a drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. The power source of the power supply unit 10 is provided by a voltage at the charging terminal, so that a self-consumption of the battery during storage may be reduced.The third embodiment

[0034] In this embodiment, please refer to FIG. 3. A battery charging circuit 300 is suitable for a direct current charging low-side control. A power supply unit 10 is powered by a voltage at a charging terminal. The battery charging circuit 300 is connected with an output terminal of a direct current charger 600 as shown in FIG. 6 through the charging terminal. The NMOS transistor Q11 is an NMOS transistor with a body diode.

[0035] Please refer to FIG. 3. The power supply unit 10 includes a fourth resistor R14, a fifth resistor R15, an NPN triode Q14, a third capacitor C13, a third diode D13, and a Zener diode ZD11. A base of the NPN triode is respectively connected with a cathode of the Zener diode ZD11 and one end of the fifth resistor R15. An anode of the Zener diode ZD11 is respectively connected with a charging negative terminal 92 and a drain of the NMOS transistor Q11. The other end of the fifth resistor R15 is respectively connected with one end of the fourth resistor R14 and a cathode of the third diode D13. An anode of the third diode D13 is connected with a charging positive terminal 91 and a positive electrode of the battery unit 40. The other end of the fourth resistor R14 is connected with a collector of the NPN transistor Q14. An emitter of the NPN transistor Q14 is connected with the charging negative terminal 92 and the drain of the NMOS transistor Q11 via the third capacitor C13, and at the same time an emitter of the NPN transistor Q14 is connected with a power source end of the switch control unit 20.

[0036] Please refer to FIG. 3. The switch control unit 20 includes an intelligent synchronous rectification control chip U2 (for example, the model may be MP6905), a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, and a Zener diode ZD21. A VSS pin of the intelligent synchronous rectification control chip U2 is connected with a source of the NMOS transistor Q11 and a negative electrode of the battery unit 40 respectively, and at the same time the VSS pin of the intelligent synchronous rectification control chip U2 is connected with one end of the first resistor R21. The other end of the first resistor R21 is connected with an LL pin of the intelligent synchronous rectification control chip U2, a PGND pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the negative electrode of the battery unit 40. A VG pin of the intelligent synchronous rectification control chip U2 is connected with a gate of the NMOS transistor Q11 via the fourth resistor R24. A VD pin of the intelligent synchronous rectification control chip U2 is connected with a drain of the NMOS transistor Q11 via the third resistor R23. An EN pin of the intelligent synchronous rectification control chip U2 is respectively connected with one end of the second resistor R22 and a cathode of the Zener diode ZD21. An anode of the Zener diode ZD21 is connected with the charging negative terminal 92. The other end of the second resistor R22 is respectively connected with a VCC pin of the intelligent synchronous rectification control chip U2 and an output end of the power supply unit 10.

[0037] In this embodiment, please refer to FIG. 3. The battery charging circuit 300 further includes an NMOS transistor Q12, a controller 30 and a low-dropout linear regulator 60. The NMOS transistor Q12 is an NMOS transistor with a body diode, which is used for secondary protection to prevent a charger from running out of control and over charging. The controller 30 is connected with a gate of the NMOS transistor Q12. A source of the NMOS transistor Q12 is connected with the source of the NMOS transistor Q11. A drain of the NMOS transistor Q12 is connected with the negative electrode of the battery unit 40. The controller 30 is used to control on and off of the NMOS transistor Q12.

[0038] In this embodiment, please refer to FIG. 3. The battery charging circuit 300 further includes a voltage collection unit 70 and a temperature collection unit 50 connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as PTC sensor) or a negative temperature coefficient sensor (abbreviated as NTC sensor).

[0039] Please refer to FIG.3 and FIG.6. When charging, a positive output terminal 11 and a negative output terminal 12 of the direct current charger 600 as shown in FIG. 6 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 300. A communication port 13 of the direct current charger 600 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 300 and a communication module 80, thereby realizing an information interaction between the battery unit 40 and the charger. As shown in FIG. 8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the direct current charger 600 is connected with the battery charging circuit 300; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0040] Please refer to FIG. 3 and FIG. 6. When charging, a direct current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a negative line (low end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control the NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. The power source of the power supply unit 10 is provided by a voltage at the charging terminal, so that a self-consumption of the battery during storage may be reduced.The fourth embodiment

[0041] In this embodiment, please refer to FIG. 3. A battery charging circuit 300 is suitable for an alternative current charging low-side control. A power supply unit 10 is powered by a voltage at a charging terminal. A circuit diagram of the battery charging circuit 300 in this embodiment is the same as the circuit diagram of the battery charging circuit 300 in the third embodiment. The difference is that the battery charging circuit 300 is connected with an output terminal of the alternative current charger 700 as shown in FIG. 7 through the charging terminal.

[0042] Please refer to FIG.3 and FIG.7. When charging, a positive output terminal 11 and a negative output terminal 12 of the alternative current charger 700 as shown in FIG. 7 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 300. A communication port 13 of the alternative current charger 700 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 300 and a communication module 80, so as to realize an information interaction between the battery unit 40 and the charger. Please refer to FIG.8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the alternative current charger 700 is connected with the battery charging circuit 300; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0043] Please refer to FIG. 3 and FIG. 7. When charging, an alternative current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a negative line (low end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. The power source of the power supply unit 10 is provided by a voltage at the charging terminal, so that a self-consumption of the battery during storage may be reduced.The fifth embodiment

[0044] In this embodiment, please refer to FIG. 4. a battery charging circuit 400 is suitable for direct current charging high-side control. The power supply unit 10 is powered by a battery unit 40. The battery charging circuit 400 is connected with an output terminal of a direct current charger 600 as shown in FIG. 6 through the charging terminal. The NMOS transistor Q11 is an NMOS transistor with a body diode.

[0045] Please refer to FIG. 4, the power supply unit 10 includes a boost circuit chip U1 (for example, a model may be MC34063), a first resistor R11, a second resistor R12, a third resistor R13, a first diode D11, a second diode D12, an inductor L11, a first capacitor C11, and a second capacitor C12. An anode of the first diode D11 is connected with a charging positive terminal 91 of the NMOS transistor Q12. A cathode of the first diode D11 is connected with a charging negative terminal 92 via the first capacitor C11, and at the same time the cathode of the first diode D11 is respectively connected t with a VCC pin of the boost circuit chip U1 and one end of the first resistor R11. The other end of the first resistor R11 is connected with one end of the inductor L11 and a second end of the boost circuit chip U1. The other end of the inductor L11 is respectively connected with a SW pin of the boost circuit chip U1 and an anode of the second diode D12. A cathode of the second diode D12 is further connected with the charging negative terminal 92 via the second capacitor C12, and at the same time the cathode of the second diode D12 is further respectively connected with a power source end of the switch control unit 20 and one end of the third resistor R13. The other end of the third resistor R13 is connected with a COM pin of the boost circuit chip U1, and at the same time the other end of the third resistor R13 is connected with the charging negative terminal 92 via the second resistor R12. A GND pin of the boost circuit chip U1 is connected with the charging negative terminal 92.

[0046] Please refer to FIG. 4, the switch control unit 20 includes an intelligent synchronous rectification control chip U2 (for example, the model may be MP6905), a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, and a Zener diode ZD21. A VSS pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the charging positive terminal 91, at the same time, the VSS pin of the intelligent synchronous rectification control chip U2 is connected with one end of the first resistor R21. The other end of the first resistor R21 is connected with an LL pin of the intelligent synchronous rectification control chip U2. A PGND pin of the intelligent synchronous rectification control chip U2 is respectively connected to the source of the NMOS transistor Q11 and the charging positive terminal 91. A VG pin of the intelligent synchronous rectification control chip U2 is connected with a gate of the NMOS transistor Q11 via the fourth resistor R24. A VD pin of the intelligent synchronous rectification control chip U2 is connected with a drain of the NMOS transistor Q11 via the third resistor R23. An EN pin of the intelligent synchronous rectification control chip U2 is respectively connected with one end of the second resistor R22 and a cathode of the Zener diode ZD21. An anode of the Zener diode ZD21 is connected with the charging negative terminal 92. The other end of the second resistor R22 is respectively connected with the VCC pin of the intelligent synchronous rectification control chip U2 and the output end of the power supply unit 10.

[0047] In this embodiment, please refer to FIG. 4, the battery charging circuit 400 further includes an NMOS transistor Q12, a controller 30, a low-dropout linear regulator 60, a PMOS transistor Q13, a first resistor R31, and a Zener diode ZD31. The NMOS transistor Q12 is an NMOS transistor with a body diode, which is used for secondary protection to prevent the charger from running out of control and over charging. A source of the PMOS transistor Q13 is connected with the output of the power supply unit 10. A drain of the PMOS transistor Q13 is connected with one end of the first resistor R31. The other end of the first resistor R31 is respectively connected with a gate of the NMOS transistor Q12 and a cathode of the Zener diode ZD31. A drain of the NMOS transistor Q12 is connected with the drain of the NMOS transistor Q11. An anode of the Zener diode ZD31 is respectively connected with a source of the NMOS transistor Q12 and a positive electrode of the battery unit 40. A gate of the PMOS transistor Q13 is connected with the controller 30. The controller 30 controls on and off of the output terminal of the power supply unit 10 and the gate of the NMOS transistor Q12 by controlling on and off of the PMOS transistor Q13, thereby controlling the on and off of the NMOS transistor Q12.

[0048] In this embodiment, please refer to FIG. 4, the battery charging circuit 400 further includes a voltage collection unit 70 and a temperature collection unit 50. The voltage collection unit 70 and the temperature collection unit 50 are connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as PTC sensor) or a negative temperature coefficient sensor (abbreviated as NTC sensor).

[0049] Please refer to FIG. 4 and FIG. 6. When charging, a positive output terminal 11 and a negative output terminal 12 of the direct current charger 600 as shown in FIG. 6 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 400. A communication port 13 of the direct current charger 600 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 400 and a communication module 80, thereby realizing an information interaction between the battery unit 40 and the charger. As shown in FIG. 8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the direct current charger 600 is connected with the battery charging circuit 400; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0050] Please refer to FIG. 4 and FIG. 6. When charging, a direct current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a positive line (high end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. Since a power source of the power supply unit 10 is provided by the battery unit 40, the boost circuit chip U1 and the intelligent synchronous rectification control chip U2 are always in a wake-up working state.The sixth embodiment

[0051] In this embodiment, please refer to FIG. 4. A battery charging circuit 400 is suitable for an alternative current charging high-side control. A power supply unit 10 is powered by a battery unit 40. A circuit diagram of the battery charging circuit 400 in this embodiment is the same as the circuit diagram of the battery charging circuit 400 in the fifth embodiment. The difference is that the battery charging circuit 400 is connected with an output terminal of the alternative current charger 700 as shown in FIG. 7 through a charging terminal.

[0052] Please refer to FIG.4 and FIG.7. When charging, a positive output terminal 11 and a negative output terminal 12 of the alternative current charger 700 as shown in FIG. 7 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 400. A communication port 13 of the alternative current charger 700 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 400 and a communication module 80, so as to realize an information interaction between the battery unit 40 and the charger. Please refer to FIG.8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the alternative current charger 700 is connected with the battery charging circuit 400; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging it; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0053] Please refer to FIG. 4 and FIG. 7. When charging, an alternative current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a positive line (high end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. Since a power source of the power supply unit 10 is provided by the battery unit 40, the boost circuit chip U1 and the intelligent synchronous rectification control chip U2 are always in a wake-up working state.The seventh embodiment

[0054] In this embodiment, please refer to FIG. 5. A battery charging circuit 500 is suitable for a direct current charging low-side control. A power supply unit 10 is powered by a battery unit 40. The battery charging circuit 500 is connected with an output terminal of a direct current charger 600 as shown in FIG. 6 through a charging terminal. The NMOS transistor Q11 is an NMOS transistor with a body diode.

[0055] Please refer to FIG. 5. The power supply unit 10 includes a fourth resistor R14, a fifth resistor R15, an NPN triode Q14, a third capacitor C13, a third diode D13, and a Zener diode ZD11. A base of the NPN triode is respectively connected with a cathode of the Zener diode ZD11 and one end of the fifth resistor R15. An anode of the Zener diode ZD11 is respectively connected with a negative electrode of the battery unit 40 and a source of the NMOS transistor Q11. The other end of the fifth resistor R15 is respectively connected with one end of the fourth resistor R14 and a cathode of the third diode D13. An anode of the third diode D13 is connected with a positive electrode of the battery unit 40 and a charging positive terminal 91. The other end of the fourth resistor R14 is connected with a collector of the NPN transistor Q14. An emitter of the NPN transistor Q14 is connected with the negative electrode of the battery unit 40 and the source of the NMOS transistor Q11 via the third capacitor C13, and at the same time the emitter of the NPN transistor Q14 is connected with a power source end of the switch control unit 20.

[0056] Please refer to FIG. 5. The switch control unit 20 includes an intelligent synchronous rectification control chip U2 (for example, the model may be MP6905), a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24, and a Zener diode ZD21. A VSS pin of the intelligent synchronous rectification control chip U2 is connected with a source of the NMOS transistor Q11 and a negative electrode of the battery unit 40, and at the same time the VSS pin of the intelligent synchronous rectification control chip U2 is connected with one end of the first resistor R21. The other end of the first resistor R21 is connected with an LL pin of the intelligent synchronous rectification control chip U2, a PGND pin of the intelligent synchronous rectification control chip U2 is respectively connected with the source of the NMOS transistor Q11 and the negative electrode of the battery unit 40. A VG pin of the intelligent synchronous rectification control chip U2 is connected with a gate of the NMOS transistor Q11 via the fourth resistor R24. A VD pin of the intelligent synchronous rectification control chip U2 is connected with a drain of the NMOS transistor Q11 via the third resistor R23. An EN pin of the intelligent synchronous rectification control chip U2 is respectively connected with one end of the second resistor R22 and a cathode of the Zener diode ZD21. An anode of the Zener diode ZD21 is connected with the charging negative terminal 92. The other end of the second resistor R22 is respectively connected with a VCC pin of the intelligent synchronous rectification control chip U2 and an output end of the power supply unit 10.

[0057] In this embodiment, please refer to FIG. 5. The battery charging circuit 500 further includes an NMOS transistor Q12, a controller 30 and a low-dropout linear regulator 60. The NMOS transistor Q12 is an NMOS transistor with a body diode, which is used for secondary protection to prevent a charger from running out of control and over charging. The controller 30 is connected with a gate of the NMOS transistor Q12. A source of the NMOS transistor Q12 is connected with the source of the NMOS transistor Q11. A drain of the NMOS transistor Q12 is connected with the negative electrode of the battery unit 40. The controller 30 is used to control on and off of the NMOS transistor Q12.

[0058] In this embodiment, please refer to FIG. 5. The battery charging circuit 500 further includes a voltage collection unit 70 and a temperature collection unit 50 connected with the controller 30. The voltage collection unit 70 is used to collect a battery voltage of the battery unit 40 and transmit it to the controller 30. The temperature collection unit 50 is used to collect a battery temperature of the battery unit 40 and transmit it to the controller 30. As an example, the temperature collection unit 50 includes, for example, a temperature sensor and a peripheral circuit. The temperature sensor may be, for example, a positive temperature coefficient sensor (abbreviated as PTC sensor) or a negative temperature coefficient sensor (abbreviated as NTC sensor).

[0059] Please refer to FIG.5 and FIG.6. When charging, a positive output terminal 11 and a negative output terminal 12 of the direct current charger 600 as shown in FIG. 6 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 500. A communication port 13 of the direct current charger 600 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 500 and a communication module 80, thereby realizing an information interaction between the battery unit 40 and the charger. As shown in FIG. 8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the direct current charger 600 is connected with the battery charging circuit 500; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging it; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0060] Please refer to FIG. 5 and FIG. 6. When charging, a direct current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a negative line (low end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. Since a power source of the power supply unit 10 is provided by the battery unit 40, the boost circuit chip U1 and the intelligent synchronous rectification control chip U2 are always in a wake-up working state.The eighth embodiment

[0061] In this embodiment, please refer to FIG. 5. A battery charging circuit 500 is suitable for an alternative current charging low-side control. A power supply unit 10 is powered by a battery unit 40. A circuit diagram of the battery charging circuit 500 in this embodiment is the same as the circuit diagram of the battery charging circuit 500 in the seventh embodiment. The difference is that the battery charging circuit 500 is connected with an output terminal of the alternative current charger 700 as shown in FIG. 7 through a charging terminal.

[0062] Please refer to FIG.5 and FIG.7. When charging, a positive output terminal 11 and a negative output terminal 12 of the alternative current charger 700 as shown in FIG. 7 are respectively connected with the charging positive terminal 91 and the charging negative terminal 92 of the battery charging circuit 500. A communication port 13 of the alternative current charger 700 is in turn communicatively connected with the controller 30 through a communication terminal 93 of the battery charging circuit 500 and a communication module 80, so as to realize an information interaction between the battery unit 40 and the charger. Please refer to FIG.8, a charging logic of the battery unit 40 is as follows: S10: waking up, by the communication module 80, the controller 30 when the alternative current charger 700 is connected with the battery charging circuit 500; S20: reading, by the controller 30, the battery voltage and battery temperature of the battery unit 40, and communicating, by the controller 30, with the charger through the communication module 80; S30: collecting the battery voltage and battery temperature of the battery unit 40 collected by the voltage collection unit 70 and the temperature collection unit 50, and detecting communication status of the communication module 80; S40: determining whether the battery voltage of the battery unit 40, the battery temperature of the battery unit 40 and a communication of the communication module 80 are normal or not, if yes, executing S50, if not, executing S70; S50: turning on the NMOS transistor Q12 and charging; S60: judging whether the charging is completed or not during a charging process, if yes, executing S70, if not, returning to S30; S70: turing off the NMOS transistor Q12; S80: powering off the controller 30 when the charging is over.

[0063] Please refer to FIG. 4 and FIG. 7. When charging, an alternative current signal is input, the NMOS transistor Q11 (NMOS transistor) is placed on a negative line (low end) of the battery unit 40. U2 (MP6905) is an intelligent synchronous rectification control chip, which controls on and off of the NMOS transistor Q11 by sampling a voltage Vsd of both ends of the NMOS transistor Q11 (a source-to-drain voltage of the NMOS transistor Q11). When the Vsd is greater than 30mV, the NMOS transistor Q11 is turned on to charge, when the Vsd is less than 0mV, the NMOS transistor Q11 is turned off to prevent the battery from discharging externally. At the same time, the voltage at both ends of the NMOS transistor Q11 may be maintained at 30mV when the NMOS transistor Q11 is turned on, which is suitable for a high-current fast charging. The VG pin of the intelligent synchronous rectification control chip U2 is a driving pin of the NMOS transistor Q11, and the VCC pin of the intelligent synchronous rectification control chip U2 provides a driving voltage for the VG pin. The VD pin and VSS pin of the intelligent synchronous rectification control chip U2 are respectively voltage input pins of the source and the drain of the NMOS transistor Q11, which are used as on-off signals for controlling the NMOS transistor Q11. The EN pin of the intelligent synchronous rectification control chip U2 is an enable pin of the intelligent synchronous rectification control chip U2, which controls power on and off of the intelligent synchronous rectification control chip U2. When the EN pin is at a high level, the intelligent synchronous rectification control chip U2 is powered on to control he NMOS transistor Q11 to be turned on. When the EN pin is at a low level, the intelligent synchronous rectification control chip U2 is powered off to control the NMOS transistor Q11 to be turned off. Since a power source of the power supply unit 10 is provided by the battery unit 40, the boost circuit chip U1 and the intelligent synchronous rectification control chip U2 are always in a wake-up working state.The ninth embodiment

[0064] This embodiment introduces a battery pack charging system including a battery pack and a charger. FIG. 9 shows an exploded schematic view of the battery pack and the charger. The battery pack charging system includes a charger 2 and a battery pack 1 that match each other, and the battery pack is inserted into the charger for charging.

[0065] Please refer to to FIG. 9, the battery pack 1 includes a housing 14, a battery unit 40 (not shown in FIG. 9) and a battery charging circuit (not shown in FIG. 9). The housing 14is provided with a housing cavity for housing the battery unit 40 and the battery charging circuit. The battery charging circuit is used to connect the battery unit 40 with the charger 2 to realize a charging of the battery unit 40. The battery unit 40 may also be called a battery pack, a battery module or a battery string, which includes several battery cells (also called cells). The battery charging circuit may adopt one of the battery charging circuits described in the first to eighth embodiments or combinations thereof.

[0066] Please refer to FIG. 9. The charger 2 may be, for example, an alternative current charger 700 as shown in FIG. 7 or a direct current charger 600 as shown in FIG. 6. It can be understood that the charger 2 may also be an integrated alternative current and direct current charger.

[0067] In summary, the battery charging circuit, the battery pack and the battery pack charging system of the disclosure control on-off of the charging circuit through the high-side driving or low-side driving NMOS transistors. Compared with the control of conventional PMOS transistor, the embodiments have the characteristics of low cost, strong overcurrent capability, low heat generation, high charging efficiency and prevention of discharge from the charging port. With the battery charging circuit system and the battery pack charging system of the disclosure, since an on-channel resistance of the NMOS transistor is smaller than that of the PMOS transistor, the NMOS transistor has low power consumption and low heat generation when it is turned on, and the cooling device may not be provided. The battery charging circuit system and the battery pack charging system of the disclosure may be applied to direct current charging and alternative current charging. With the battery charging circuit system and the battery pack charging system of the disclosure, a switching response time of the NMOS transistor is as low as 200ns.

[0068] In the description herein, many specific details are provided, such as examples of components and / or methods, to provide a complete understanding of the embodiments of the disclosure. However, those skilled in the art will recognize that the embodiments of the disclosure may be realized without one or more specific details or through other devices, systems, assemblies, methods, components, materials, parts, etc. In other cases, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of the embodiments of the disclosure.

[0069] It should also be understood that one or more of the components shown in the drawings may also be implemented in a more separate or integrated manner, or may even be removed because it cannot be operated in some cases or may be provided because it is useful according to a particular application.

[0070] In addition, unless expressly indicated otherwise, any marking arrows in the drawings should be regarded only as exemplary instead of limiting. What's more, unless specified otherwise, the term "or" as used herein generally means "and / or." In cases where the term is foreseen because it is unclear to provide separation or combination capabilities, the combination of components or operations will also be regarded as specified.

[0071] The above description of the illustrated embodiment of the disclosure (including content described in the abstract of the specification) is not intended to exhaustively enumerate or limit the disclosure to the precise form provided herein. Although specific embodiments of the disclosure and examples of the disclosure are described herein for illustrative purposes only, as those skilled in the art recognize and understand, various equivalent modifications are possible within the scope of the disclosure. As pointed out, these modifications may be made to the disclosure according to the above description of the embodiments of the disclosure, and these modifications will be within the scope of the disclosure.

[0072] This specification has generally described the system and method which are helpful in understanding the details of the disclosure. In addition, various specific details have been given to provide an overall understanding of the embodiments of the disclosure. However, those skilled in the relevant art will recognize that the embodiments of the disclosure may be realized without one or more specific details, or may be implemented through using other devices, systems, accessories, methods, assemblies, materials, parts, etc. In other cases, well-known structures, materials, and / or operations are not specifically shown or described in detail to avoid confusion in various aspects of the embodiments of the disclosure.

[0073] Therefore, although the disclosure has been described herein with reference to its specific embodiments, a freedom of modification, various changes and substitutions are also included in the above disclosure. And it should be understood that in some cases, without departing from the scope of the disclosure, some features of the disclosure will be adopted under the conditions without corresponding use of other features. Therefore, many modifications may be made to enable a specific environment or material to adapt the essential scope of the disclosure. The disclosure is not intended to limit the specific terms used in the claims and / or specific embodiments disclosed as the best embodiment for carrying out the disclosure, but the disclosure will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the disclosure will only be determined by the appended claims.

Claims

1. A battery charging circuit, comprising: a first control switch, being an NMOS transistor (Q11) with a body diode, a source of the first control switch (Q11) being connected with a charging positive terminal (91) and a drain of the first control switch (Q11) being connected with a positive electrode of a battery unit (40), a switch control unit (20), being connected with a gate and the source of the first control switch (Q11), and a power supply unit (10), connected with a power source end of the switch control unit (20) and configured to supply power to the switch control unit (20) characterized in that the switch control unit (20) is connected with the drain of the first control switch (Q11) and configured to control on-off of the first control switch (Q11) by sampling a voltage between the source and the drain of the first control switch (Q11), wherein the switch control unit (20) comprises an intelligent synchronous rectification control chip (U2), a first resistor (R21), a second resistor (R22), a third resistor (R23), a fourth resistor (R24), and a Zener diode (ZD21); a first end of the intelligent synchronous rectification control chip (U2) is respectively connected with a source of the NMOS transistor (Q11) and the charging positive terminal, simultaneously the first end of the intelligent synchronous rectification control chip (U2) is connected with one end of the first resistor (R21), the other end of the first resistor (R21) is connected with a second end of the intelligent synchronous rectification control chip (U2), a third end of the intelligent synchronous rectification control chip (U2) is respectively connected with the source of the NMOS transistor (Q11) and the charging positive terminal, a fourth end of the intelligent synchronous rectification control chip (U2) is connected with a gate of the NMOS transistor (Q11) through the fourth resistor (R24), a fifth end of the intelligent synchronous rectification control chip (U2) is connected with a drain of the nmos transistor (Q11) through the third resistor (R23), a sixth end of the intelligent synchronous rectification control chip (U2) is respectively connected with one end of the second resistor (R22) and a cathode of the Zener diode (ZD21), an anode of the Zener diode (ZD21) is connected with a charging negative terminal, and the other end of the second resistor (R22) is respectively connected with a seventh end of the intelligent synchronous rectification control chip (U2) and an output end of the power supply unit (10).

2. The battery charging circuit according to claim 1, comprising: a second control switch, being an NMOS transistor (Q12) with a body diode, a drain of the second control switch (Q12) being connected with the drain of the first control switch (Q11) and a source of the second control switch (Q12) being connected with the positive electrode of the battery unit (40), a controller (30), configured to control on-off of the second control switch (Q12), and a voltage regulator, a power supply end of the controller (30) being connected with the positive electrode of the battery unit (40) through the voltage regulator.

3. The battery charging circuit according to claim 2, further comprising a PMOS transistor (Q13), a resistor (R31) and a Zener diode (ZD31), wherein a source of the PMOS transistor (Q13) is connected with an output end of the power supply unit (10), a drain of the PMOS transistor (Q13) is connected with one end of the resistor (R31), the other end of the resistor (R31) is respectively connected with a gate of the NMOS transistor (Q12) and a cathode of the Zener diode (ZD31), an anode of the Zener diode (ZD31) is respectively connected with a source of the NMOS transistor (Q12) and the positive electrode of the battery unit (40), and a gate of the PMOS transistor (Q13) is connected with the controller (30).

4. The battery charging circuit according to claim 2 or 3, further comprising a voltage collection unit (70), wherein the voltage collection unit (70) is connected to the controller (30), and configured to collect a battery voltage of the battery unit (40) and transmit the battery voltage to the controller (30).

5. The battery charging circuit according to claim 2 or 3, further comprising a temperature collection unit (50), wherein the temperature collection unit (50) is connected to the controller (30), and configured to collect a battery temperature of the battery unit (40) and transmit the battery temperature to the controller (30).

6. The battery charging circuit according to any one of preceding claims, wherein a power source of the power supply unit (10) is provided by a voltage at a charging terminal or by the battery unit (40).

7. A battery charging circuit, comprising: a first control switch (Q11), being an NMOS transistor with a body diode, a source of the first control switch (Q11) being connected with a negative electrode of the battery unit (40), a drain of the first control switch being connected with a charging negative terminal (92), and the first control switch (Q11), a switch control unit (20), being connected with a gate and the source, and a power supply unit (10), an output end of the power supply unit (10) being connected with a power source end of the switch control unit (20) and being configured to supply power to the switch control unit (20) characterized in that the switch control unit (20) is connected with the drain of the first control switch (Q11) and configured to control on-off of the first control switch (Q11) by sampling a voltage between the source and the drain of the first control switch (Q11), wherein the switch control unit (20) comprises an intelligent synchronous rectification control chip (U2), a first resistor (R2)1, a second resistor (R22), a third resistor (R23), a fourth resistor (R24), and a Zener diode (ZD21); a first end of the intelligent synchronous rectification control chip (U2) is respectively connected with a source of the NMOS transistor (Q11) and the negative electrode of the battery unit (40), simultaneously the first end of the intelligent synchronous rectification control chip (U2) is connected with one end of the first resistor (R21), the other end of the first resistor (R21) is connected with a second end of the intelligent synchronous rectification control chip (U2), a third end of the intelligent synchronous rectification control chip U(2) is respectively connected with the source of the NMOS transistor (Q11) and the negative electrode of the battery unit (40), a fourth end of the intelligent synchronous rectification control chip (U2) is connected with a gate of the NMOS transistor (Q11) through the fourth resistor (R24), a fifth end of the intelligent synchronous rectification control chip (U2) is connected with a drain of the NMOS transistor (Q11) through the third resistor (R23), a sixth end of the intelligent synchronous rectification control chip (U2) is respectively connected with one end of the second resistor (R22) and a cathode of the Zener diode (ZD21), an anode of the Zener diode (ZD21) is connected with the charging negative terminal, and the other end of the second resistor (R22) is respectively connected with a seventh end of the intelligent synchronous rectification control chip (U2) and an output end of the power supply unit (10).

8. The battery charging circuit according to claim 7, comprising: a second control switch (Q12), being an NMOS transistor with a body diode, a source of the second control switch (Q12) being connected with the source of the first control switch (Q11) and a drain of the second control switch (Q12) being connected with the negative electrode of the battery unit (40), a controller (30), connected with a gate of the second control switch (Q12) and configured to control on-off of the second control switch (Q12), and a voltage regulator, a power supply end of the controller (30) is connected with a positive electrode of the battery unit (40) through the voltage regulator.

9. The battery charging circuit according to claim 8, further comprising a voltage collection unit (70), wherein the voltage collection unit (70) is connected with the controller (30), and configured to collect a battery voltage of the battery unit (40) and transmits the battery voltage to the controller (30).

10. The battery charging circuit according to claim 8 or 9, further comprising a temperature collection unit (50), wherein the temperature collection unit (50) is connected with the controller (30) and the temperature collection unit (50) is configured to collect a battery temperature of the battery unit (40) and transmit the battery temperature to the controller (30).

11. The battery charging circuit according to any one of claims 7 to 10, wherein a power source of the power supply unit (10) is provided by a voltage at the charging terminal or by the battery unit (40).

12. A battery pack, comprising: a housing with a housing cavity, a battery unit (40), mounted in the housing cavity, and the battery charging circuit (500) according to any one of preceding claims, mounted in the housing cavity and connected to the battery unit (40).

13. A battery pack charging system, comprising: the battery pack (1) according to claim 12, and a charger (700), matched with the battery pack, wherein the charger comprises an alternating current charger, a direct current charger, or an alternating current and direct current charger.