Generation of true random numbers using coherent scanning in FD-SOI technology

Description

Technical field

[0001] This description relates generally to electronic circuits, and more particularly to random number generation circuits. Prior art

[0002] Many electronic systems implement functionalities or applications, for example cryptographic primitives (session key generation, digital signature, masking, etc.), using random numbers. For this purpose, these electronic systems include a random number generation circuit, also simply called a random number generator (RNG). A random number generator includes a truly random number generation circuit, also simply called a truly random number generator (TRNG). The unpredictability of the generated random numbers makes it possible, for example, to ensure the unpredictability of the outputs of a cryptographic primitive so as to guarantee the level of security of this primitive.

[0003] Truly random number generators rely on one or more physical phenomena to generate the randomness from which random numbers are generated, such physical phenomena being, for example, radiation, phase noise, optical phenomena, etc.

[0004] This description is particularly concerned with truly random number generators based on ring oscillators, the randomness then resulting from clock jitter, that is to say the difference between the theoretical period of a ring oscillator and the real or effective period of this oscillator.

[0005] Several types of ring oscillator-based true random number generators are known, e.g., elementary ring oscillator (ERO TRNG), multiple ring oscillator (MURO TRNG), self-timed ring (STR TRNG), transition effect ring oscillator (TERO TRNG), and coherent sampling ring oscillator (COSO TRNG).

[0006] COSO-type truly random number generators have the following advantages: simpler implementation than MURO TRNG-type generators, higher output rate than ERO TRNG-type generators, and lower power consumption than STR TRNG-type generators.

[0007] However, known truly random number generators such as COSO TRNG have various drawbacks. Summary of the invention

[0008] There is a need for a coherently sampled ring oscillator truly random number generation circuit that overcomes some or all of the disadvantages of known coherently sampled ring oscillator truly random number generation circuits, for example, with respect to adjusting the frequency of the ring oscillators of the coherently sampled ring oscillator truly random number generation circuit.

[0009] One embodiment overcomes all or part of the disadvantages of known circuits for generating truly random numbers with coherently sampling ring oscillators.

[0010] One embodiment provides a correlated sampling ring oscillator type random number generation circuit comprising: a first ring oscillator and a second ring oscillator each comprising delay elements connected in series in a closed loop, the first and second oscillators being identical and implemented in fully depleted Complementary Metal Oxide Semiconductor on Silicon on Insulator technology; a first circuit configured to sample and store the state of an output of the first oscillator at a frequency of an output of the second oscillator and to provide a corresponding binary signal; and a second circuit configured to control back gates of PMOS and NMOS transistors of at least one delay element of at least one of the first and second oscillators, based on a period difference between the outputs of the first and second oscillators.

[0011] According to one embodiment, the control of the rear gates of said PMOS and NMOS transistors of said at least one delay element is configured to increase a frequency of the first oscillator relative to a frequency of the second oscillator when the period of the output of the first oscillator is smaller than the period of the output of the second oscillator, and to decrease the frequency of the first oscillator relative to the frequency of the second oscillator when the period of the output of the first oscillator is larger than the period of the output of the second oscillator.

[0012] According to one embodiment, the second circuit is configured to control the back gates of said PMOS and NMOS transistors of said at least one delay element so as to reduce the period deviation.

[0013] According to one embodiment, the second circuit is configured to control the rear gates of said PMOS and NMOS transistors of said at least one delay element so that the period difference is at least N times smaller than the period of the second oscillator, with N a number determined so that a contribution of the thermal noise is preponderant in front of a contribution of the quantization noise in the jitter of the output of the second oscillator.

[0014] According to one embodiment, N is greater than or equal to 1000, for example equal to 1000.

[0015] According to one embodiment, the second circuit comprises a counter configured to count, at a frequency of the output of the second oscillator, a number of times that said binary signal is in a first binary state during a duration of N periods of the output of the second oscillator.

[0016] According to one embodiment, said duration is a sliding duration.

[0017] According to one embodiment, the second circuit further comprises a comparator configured to compare said number to a value equal to N / 2.

[0018] According to one embodiment, the second circuit is configured to control the rear gates of said PMOS and NMOS transistors of said at least one delay element from an output signal of the comparator indicating the result of said comparison.

[0019] According to one embodiment, the second circuit comprises a phase frequency detector configured to receive the outputs of the first and second oscillators.

[0020] According to one embodiment, the random number generation circuit comprises at least one charge pump controlled by the phase frequency detector and configured to charge and discharge a capacitor connected to an output of said at least one charge pump, a control voltage of the rear gates of said PMOS and NMOS transistors of said at least one delay element being available across the capacitor.

[0021] According to one embodiment, the second circuit is configured to control the back gate of each of the PMOS and NMOS transistors of only one of the first and second oscillators.

[0022] According to one embodiment, the second circuit is configured to provide the same first voltage to the back gate of each of the PMOS transistors of said one of the first and second oscillators, and the same second voltage to the back gate of each of the NMOS transistors of said one of the first and second oscillators.

[0023] According to one embodiment, the second circuit is configured to control the back gate of each of the transistors of each of the first and second oscillators.

[0024] According to one embodiment, the second circuit is configured to provide the same first voltage to the back gate of each of the PMOS transistors of the first oscillator, the same second voltage to the back gate of each of the NMOS transistors of the first oscillator, the same third voltage to the back gate of each of the PMOS transistors of the second oscillator, and the same fourth voltage to the back gate of each of the NMOS transistors of the second oscillator. Brief description of the drawings

[0025] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 represents, in block form, an example of a random number generation circuit with coherently sampled ring oscillators; the figure 2represents, in block form, an embodiment of a coherent sampling ring oscillator random number generation circuit; figure 3 represents, in the form of blocks, an alternative embodiment of the random number generation circuit of the figure 1 ; and the figure 4 represents, in block form, another embodiment of a coherent sampling ring oscillator random number generation circuit. Description of the embodiments

[0026] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] It is known to those skilled in the art that a random number generation circuit generally comprises a truly random number generation circuit, which comprises an entropy (or randomness) source, and a processing circuit connected to the output of the truly random number generation circuit and configured to increase the throughput of the sampled randomness source, the processing circuit commonly comprising a pseudo-random number generation (PRNG) circuit. The remainder of this description relates more particularly to a truly random number generation circuit, and, even more particularly, to the sampled entropy source of this circuit. For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.In particular, known processing circuits intended to increase the throughput of a sampled randomness source, usual circuits or usual applications comprising a truly random number generation circuit have not been described or detailed, the embodiments and variants of the sampled entropy source, or sampled physical randomness source, described being compatible with these usual processing circuits, and with these usual circuits and applications comprising a truly random number generation circuit.

[0028] In the remainder of the description, the expressions "truly random number generation circuit" and "truly random number generator" designate indifferently a truly random number generation circuit or a random number generation circuit comprising a truly random number generation circuit.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0032] There figure 1 represents, in block form, an example of a coherent sampling ring oscillator truly random number generation circuit 1 (COSO TRNG), and, more particularly, only a part of the sampled entropy source of circuit 1.

[0033] Circuit 1 comprises two ring oscillators RO1 and RO2. The two oscillators RO1 and RO2 are identical, that is, they comprise the same delay elements connected in series in a closed loop (or ring) comprising an odd number of inverting functions. Each of the oscillators RO1 and RO2 receives, for example, a signal EN whose first binary state allows the oscillator loop to be closed so as to activate the oscillator so that oscillations propagate in the oscillator, and whose second binary state allows the oscillator loop to be opened so as to deactivate the oscillator to stop the propagation of oscillations in the oscillator.

[0034] For example, as illustrated in figure 1 , each oscillator RO1, RO2 comprises the same even number of inverters 100 in series between an output of a NAND gate 102 and an input of gate 102, the other input of gate 102 receiving the signal EN.

[0035] The two oscillators RO1 and RO2 provide two respective periodic slotted signals O1 and O2. Since the oscillators RO1 and RO2 are identical, the two signals O1 and O2 have, at least in theory, identical frequencies. The frequency of the signals O1 and O2 depends on the delay introduced by each delay element 100, 102 connected in series in the loops of the respective oscillators RO1 and RO2.

[0036] The circuit 1 further comprises a circuit 104 configured to sample and store the state of the output O1 of the oscillator RO1, at the frequency of the output O2 of the oscillator RO2, that is to say in synchronism with the output O2. In other words, at each edge of a first type, for example rising, of the signal O2, the circuit 104 is configured to update the binary state of a binary output signal Beat of the circuit 104 from, or as a function of, the binary state of the signal O1, then to maintain this updated binary state of the signal Beat until the next edge of the first type of the signal O2. In other words, the signal Beat is synchronous with the signal O2.

[0037] In the example of the figure 1 , circuit 104 is implemented by a D flip-flop, referenced 106 in figure 1 . The flip-flop 106 comprises a data input D receiving the signal O1, a synchronization input CK receiving the signal O2 and, in the example of the figure 1, an output Q providing the Beat signal updated with the binary state of the signal O1 at each edge of the first type of the signal O2. In another example, the flip-flop 106 comprises an output nQ providing the Beat signal updated with the complement of the binary state of the signal O1 at each edge of the first type of the signal O2, that is to say with a low binary state when the signal O1 is in the high state and with a high binary state when the signal O1 is in the low state.

[0038] The Beat signal oscillates between its two binary states, that is, between its first binary state and its second binary state depending on whether the signal O1 is in phase advance or in phase delay with respect to O2. In other words, the Beat signal is the image of the phase difference between the signals O1 and O2. In other words, the Beat signal indicates the sign of the phase difference between the signals O1 and O2. Because this phase difference depends on the random jitter of each of the oscillators RO1 and RO2, the physical randomness used in circuit 1 is the phase noise and the Beat signal is the image of this phase noise. It is this Beat signal that is then used to generate a truly random number. For example, it is the length (or duration) of one of the binary states of the Beat signal, for example its high state, which is then used to generate a truly random number.As an example, in circuit 1, a small difference between the periods of the two oscillators RO1 and RO2 changes the period of the Beat signal, and random numbers are generated by variations in the period of the Beat signal, the phase between the signals O1 and O2 being, for example, constantly changing between -Π / 2 and Π / 2.

[0039] In the example of the figure 1 , the Beat signal is supplied to a circuit 108 of circuit 1. The circuit 108 is configured to receive the Beat signal and the O2 signal and to provide, from the received Beat and O2 signals, a random output signal E.

[0040] As an example not shown, the circuit 108 may comprise a counter configured to increment at the frequency of the signal O2, for example at each edge of a first type of the signal O2, when the Beat signal is in a first binary state, for example the low state, and to be reset when the Beat signal is in a second binary state, for example the high state. In other words, this counter measures, in number of periods of the signal O2, the duration during which the Beat signal remains in its first binary state. The counter is, for example, followed by a circuit selecting the least significant bit of the output signal of the counter, this least significant bit preferably being resampled at the frequency of the Beat signal to ensure stability and corresponding to the random output signal E of the circuit 108.

[0041] In the example of the figure 1 , the counter of circuit 108 is implemented by a D flip-flop, referenced 110 in figure 1, configured to functionally correspond to keeping the least significant bit of the counter described in the preceding example. For example, flip-flop 110 has its data input D connected to its output nQ, its timing input CK connected to the signal O2 and a reset input R receiving the Beat signal. The output nQ of flip-flop 110, preferably resampled to the frequency of the Beat signal to ensure stability, then corresponds to the random output signal E of circuit 108. In another example not shown, it is the output Q of flip-flop 110 which is connected to the input D of flip-flop 110.

[0042] The person skilled in the art is able to provide other examples of circuit 108.

[0043] In practice, for circuit 1 to provide a truly random signal E, that is to say for circuit 1 to be a truly random number generation circuit, the period difference between signals O1 and O2, that is to say the difference between the period of signal O1 and that of signal O2, must be very small compared to the period of these signals, and in particular compared to the period of signal O2 which sets the timing for memorization.

[0044] The person skilled in the art is able to determine what is meant here by the term very low. For example, the person skilled in the art is able to determine a maximum value that the period deviation should not exceed so that the accuracy with which the clock jitter is measured is satisfactory, i.e. so that the resolution of the Beat signal is sufficient to measure the clock jitter of the O2 signal which is, for example, about three orders of magnitude lower than the period of the O2 signal.

[0045] For example, the inventors have shown using the Allan variance that it is desirable for the maximum period difference between the signals O1 and O2 to be N times smaller than the period of the signal O2, therefore for the period of the signals O1 and O2 to be N times smaller than the period of the Beat signal, with N a number determined so that the contribution of the thermal noise is preponderant compared to the contribution of the quantization noise, for example so that the thermal noise is at least ten times higher than the quantization noise, in the jitter of the signal O2. For example, N is greater than or equal to 1000, for example equal to 1000.

[0046] In other words, when the maximum difference between the periods of the signals O1 and O2 is N times smaller than the period of the signal O2, the resolution of the Beat signal is 1 / N and, to measure using the Beat signal a jitter of the signal O2 in which the contribution of the thermal noise is preponderant in front of the contribution of the quantization noise, N is, for example, chosen greater than or equal to 1000, for example equal to 1000.

[0047] To ensure that the period difference between the O1 and O2 signals is very small compared to the period of the O1 and O2 signals, there are ring oscillators with reconfigurable structures implemented on FPGA (Field Programmable Gate Array). However, these reconfigurable ring oscillator structures are bulky.

[0048] To ensure that the period difference between signals O1 and O2 is very small compared to the period of signals O1 and O2, there are also ring oscillators comprising capacitors with adjustable value controllable at the input of each delay element of these oscillators. However, the ranges of values ​​that these variable capacitors can take and the routing placement of each oscillator will have to be adapted to each change of technology, which is not desirable. Furthermore, the introduction of these variable capacitors increases the size and / or the consumption of circuit 1.

[0049] According to one embodiment, a circuit 2 for generating truly random numbers similar to the circuit 1 described above is proposed, in which the oscillators RO1 and RO2 are implemented in complementary metal oxide semiconductor (CMOS) and fully depleted silicon on insulator (FDSOI) technology, and in which the rear gates of PMOS (P-channel MOS transistor) and NMOS (N-channel MOS transistor) transistors of at least one delay element of at least one of the oscillators RO1 and RO2 are controlled by a control (or calibration) circuit 200 of the circuit 2.

[0050] By controlling the back gates of PMOS and NMOS transistors of at least one of the delay elements of oscillators RO1 and RO2, it is then possible to modify the frequencies of oscillators RO1 and RO2 relative to each other, so as to reduce the period difference between signals O1 and O2 to very small values ​​compared to the periods of signals O1 and O2. For example, when a delay element of ring oscillator RO1 or RO2 has PMOS and NMOS transistors having back gates controlled by control circuit 200, these PMOS and NMOS transistors of the delay element include at least the PMOS and NMOS transistors of the delay element which have their front gates connected to the output of the preceding delay element in the ring oscillator.

[0051] Changing the frequencies of oscillators RO1 and RO2 by controlling the back gates of PMOS and NMOS transistors of at least one of the delay elements of oscillators RO1 and RO2 to obtain a period difference between signals O1 and O2 less than a target value is more precise than if the modification of the frequencies of oscillators RO1 and RO2 were implemented using a current starving method.

[0052] According to one embodiment, when a delay element of the ring oscillator RO1 or RO2 has PMOS and NMOS transistors having back gates controlled by the control circuit 200, the control of these back gates by the circuit 200 is based on the period difference between the signals O1 and O2. For example, the circuit 200 is then able to obtain an indication of the current value of the period difference between the signals O1 and O2, for example from the Beat signal or from the signals O1 and O2 directly, although the person skilled in the art will be able to provide other ways of obtaining this indication.

[0053] According to one embodiment, the control of the back gate of PMOS and NMOS transistors of at least one delay element of at least one of the oscillators RO1 and RO2 by the circuit 200 is configured to reduce the period difference between the signals O1 and O2, for example to a value less than or equal to a target value, this target value of difference between the periods of the signals O1 and O2 being for example N times smaller than the period of the signal O2, with N determined so that, in the jitter of the signal O2, the contribution of the quantization noise is negligible, for example at least ten times smaller, compared to the contribution of the thermal noise which is the source of entropy. For example, N is greater than or equal to 1000, for example equal to 1000.

[0054] More particularly, according to one embodiment, the circuit 200 is configured to control the back gate of PMOS and NMOS transistors of at least one delay element of the oscillators RO1 and RO2 so that: the frequency of oscillator RO1 decreases relative to that of oscillator RO2 when the frequency of signal O1 is faster than that of signal O2, that is to say that: the frequency of oscillator RO1 is reduced while that of oscillator RO2 remains unchanged, or the frequency of oscillator RO1 is reduced and, at the same time, that of oscillator RO2 is increased, or the frequency of oscillator RO2 is increased while that of oscillator RO1 remains unchanged; and the frequency of oscillator RO1 increases relative to that of oscillator RO2 when the frequency of signal O1 is lower than that of signal O2, that is to say: the frequency of oscillator RO1 is increased while that of oscillator RO2 remains unchanged, or the frequency of oscillator RO1 is increased and, at the same time, that of oscillator RO2 is reduced, or the frequency of oscillator RO2 is reduced while that of oscillator RO1 remains unchanged..

[0055] According to one embodiment, an indication of the current value of the period difference between the signals O1 and O2 is obtained by measuring, in number of periods of the signal O2, the period of the signal Beat, and the adjustment of the circuit 1 then consists of adjusting the period of the signals O1 and O2 so that the period of the signal Beat is equal to N periods of the signal O2. For this, a circuit, or counter, can be provided, configured to count, at the frequency of the signal O2, a number of times that the signal Beat is in a given binary state during a duration of N periods of the signal O2. Preferably, this duration of N periods of the signal O2 is a sliding duration. In other words, the counter is configured to measure, in number of periods of the signal O2, the half-period of the signal Beat.

[0056] According to another embodiment, to obtain an indication of the current value of the period difference between the signals O1 and O2, the circuit 200 comprises a phase frequency detector configured to receive the signals O1 and O2.

[0057] Examples of embodiments of such a circuit 2 will now be described.

[0058] There figure 2 represents, in the form of blocks, an example of an embodiment of a circuit 2.

[0059] Circuit 2 has many elements in common with Circuit 1, and only the differences between these two Circuits 1 and 2 are highlighted here. In addition, in figure 2 , circuit 108 is not shown so as not to overload the figure.

[0060] In this embodiment, the circuit 200 of the circuit 2 obtains an indication of the current value of the period difference between the signals O1 and O2 from the Beat signal and a counter 202 (block "ACC N") clocked at the frequency of the signal O2. For example, the counter 202 is synchronized on the edges of the first type of the signal O2, for example the rising edges. The counter 202 of the circuit 2 is configured to count, at the frequency of the signal O2, the number of times that, during a duration, preferably sliding, of N periods of the signal O2, the Beat signal is in a given binary state, for example the high state. The counter 202 therefore receives the two signals Beat and O2, and provides an output signal Ni indicating the number counted.

[0061] The signal or number Ni is representative of the current value, in number of periods of the signal O2, of the half-period of the Beat signal, therefore of the period of the Beat signal, and therefore of the period difference between the signals O1 and O2. By counting the number Ni during a duration, preferably sliding, of N periods of the signal O2, if the periods of the signals O1 and O2 are close enough to allow the generation of truly random numbers, for example if the period difference between the signals O1 and O2 is at least N times smaller than the period of the signal O2, then the number Ni should be equal to N / 2 (half-period of the Beat signal equal to N / 2 periods of the signal O2 and period of the Beat signal equal to N periods of the signal O2). On the other hand, if this is not the case, for example if the period difference between the signals O1 and O2 is not N times smaller than the period of the signals O1 and O2, then the number Ni should be different from N / 2.

[0062] For example, as illustrated in figure 2 : circuit 104 is synchronized to the rising edges of signal O2, signal Beat is updated with the binary state of signal O1, circuit 202 is synchronized to the rising edges of signal O2, and circuit 202 counts the number Ni of times that signal Beat is in the high state during a duration, preferably sliding, of N periods of signal O2. In this particular example, the number Ni is greater than N / 2 if the frequency of signal O1 is greater than that of signal O2 and the difference between the periods of signals O2 and O2 is not N times smaller than the period of signals O1 and O2, and is less than N / 2 if the frequency of signal O1 is lower than that of signal O2 and the difference between the periods of signals O2 and O2 is not N times smaller than the period of signals O1 and O2.

[0063] According to one embodiment, the circuit 200 comprises a circuit, or comparator, 204 (block "≥N / 2") configured to compare the output Ni of the counter 202 to the value N / 2. The circuit 204 provides a signal CMP indicating the result of this comparison. For example, the signal CMP is a binary signal having a first state indicating that Ni is less than N / 2 and a second state indicating that Ni is greater than or equal to N / 2.

[0064] The circuit 200 is then configured to control the rear gates of PMOS and NMOS transistors of at least one delay element of at least one of the oscillators RO1 and RO2 on the basis of the signal Ni.

[0065] For example, the circuit 200 comprises a circuit 206 (block "BG CTRL") configured to receive the CMP signal and to provide at least one voltage determined by the CMP signal to control the back gates of PMOS and NMOS transistors of at least one delay element of at least one of the oscillators RO1 and RO2.

[0066] In the embodiment of the figure 2 , the circuit 200, for example the circuit 206, is configured to control the rear gates of PMOS and NMOS transistors of at least one delay element of the oscillator RO1, the rear gates of the transistors of the oscillator RO2 being biased by fixed voltages. In other words, the circuit 200 is configured to control only the frequency of the oscillator RO1.

[0067] According to one embodiment, the circuit 200, for example the circuit 206, is configured to control the back gates of all the transistors of the oscillator RO1, by providing a control voltage VBG1 to the back gates of all the PMOS transistors of the oscillator RO1 and a control voltage -VGB1 to the back gates of all the NMOS transistors of the oscillator RO1.

[0068] For example, the PMOS transistors, respectively NMOS, are arranged in and on a silicon layer resting on an insulating layer itself resting on N-type doped silicon (or N-well silicon from the English "N-well"), respectively P-type doped silicon (or P-well silicon from the English "P-well"), forming the rear gate electrode of these transistors. In this example, the voltage VBG1 is then positive or zero and increases, respectively decreases, to increase, respectively decrease, the frequency of the oscillator RO1.

[0069] In another example, the PMOS transistors, respectively NMOS, are arranged in and on a silicon layer resting on an insulating layer itself resting on P-type doped silicon (or P-well silicon from the English "P-well"), respectively N-type doped silicon (or N-well silicon from the English "N-well"), forming the rear gate electrode of these transistors. In this other example, the voltage VBG1 is then negative or zero and increases, respectively decreases, in absolute value to increase, respectively decrease, the frequency of the oscillator RO1.

[0070] For example, the circuit 200 is further configured to provide a fixed bias voltage VBG2f, respectively -VBG2f, to the rear gates of all the PMOS, respectively NMOS, transistors of the oscillator RO2.

[0071] In the present description, when it is indicated that the circuit 200 controls the back gates of all the transistors of an oscillator RO1 or RO2, this preferably means that the circuit 200 controls the back gates of at least all the transistors of the delay elements of the closed loop of the oscillator, that is to say of the transistors of the oscillator having a threshold voltage directly influencing the frequency of the oscillations in the oscillator.

[0072] As an alternative embodiment not shown, the circuit 200 is configured to control the frequency of the oscillator RO2 only. The implementation of this alternative is within the abilities of those skilled in the art from the description given above of the case where the circuit 200 controls the frequency of the oscillator RO1 only.

[0073] Preferably, the counting duration, which here lasts N periods of the signal O2, is a sliding duration, which allows the circuit 200 to continuously control the frequency of at least one of the oscillators RO1 and RO2. For example, the duration of N periods is said to be sliding when each counting duration of N periods begins while the previous counting duration of N periods has not ended, that is to say when each counting duration of N periods partly overlaps the previous counting duration of N periods and the following counting duration of N periods. Alternatively, the counting duration is not a sliding duration, the counter then being reset at each counting duration corresponding to N periods of the signal O2. For example, each counting duration of N periods is said to be non-sliding when it does not overlap, even partly, the previous and following counting durations of N periods.For example, each non-sliding counting duration of N periods begins with an edge of a given type, for example a rising edge, of the Beat signal.

[0074] For example, the maximum step with which the period of oscillator RO1 is modified relative to that of oscillator RO2, so as to be able to obtain a period difference between signals O1 and O2 which is N times smaller than the period of signal O2, is equal to T / N with T the average or theoretical value of the period of signal O2. For example, for T equal to 2 ns, and N equal to 1000, the period of oscillator RO1 is modified relative to that of the oscillator with a step of at most 2 ps. The person skilled in the art will be able to determine the corresponding step on the control voltages of the rear gate(s) of the transistors controlled by circuit 200.

[0075] There figure 3represents, in the form of blocks, an alternative embodiment of circuit 2 described in relation to the figure 2 . Circuit 2 of the figure 3 has many similarities with that of the figure 2 , and only the differences between these circuits are highlighted here.

[0076] In particular, in relation to what has been described in relation to the figure 2 where circuit 200 controls the frequency of only one of the two oscillators RO1 and RO2, in the variant of the figure 3 circuit 200 controls the frequency of the two oscillators RO1 and RO2. In other words, in figure 3 , the circuit 200 is configured to control, on the basis of the difference between the periods of the signals O1 and O2, the back gates of NMOS and PMOS transistors of at least one delay element of the oscillator RO1 and the back gates of NMOS and PMOS transistors of at least one delay element of the oscillator RO2.

[0077] According to one embodiment, the circuit 200, for example the circuit 206, is configured to control the rear gates of all the transistors of the oscillator RO1, for example by providing a control voltage VBG1 to the rear gates of all the PMOS transistors of the oscillator RO1 and a control voltage -VBG1 to the rear gates of all the NMOS transistors of the oscillator RO1, as well as all the transistors of the oscillator RO2, for example by providing a voltage VBG2 to the rear gates of all the NMOS transistors of the oscillator RO2 and the same voltage -VBG2 to all the PMOS transistors of the oscillator RO2. The voltages VBG1 and -VBG1 have the same absolute value but opposite polarities and the voltages VBG2 and -VBG2 have the same absolute value but opposite polarities.

[0078] For example, voltage VBG2 is equal to voltage VBG1, such that a variation in voltage VBG1 resulting in an increase or reduction in the frequency of oscillator RO1 results in a decrease or increase in the frequency of oscillator RO2, respectively. However, the person skilled in the art will be able to provide implementations where voltage VBG2 is different from voltage VBG1 and / or only some of the transistors of oscillator RO1 and oscillator RO2 are controlled by circuit 200.

[0079] Compared to circuit 2 of the figure 2 in which a single oscillator RO1 or RO2 is controlled by circuit 200, circuit 2 of the figure 3 is less precise with respect to the adjustment of the frequency of oscillator RO1 relative to that of oscillator RO2, since both oscillators RO1 and RO2 are controlled simultaneously by circuit 200.

[0080] Exemplary embodiments in which the circuit 200 controls the oscillator RO1 and / or the oscillator RO2 using the Beat signal and a counter to obtain an indication of the period difference between the two signals O1 and O2 have been described in connection with the figures 2 And 3 .

[0081] In other exemplary embodiments, the circuit 200 directly uses the signals O1 and O2 to obtain an indication of the period difference between these two signals, for example by means of a phase frequency detector receiving these two signals O1 and O2.

[0082] There figure 4 represents, in the form of blocks, another embodiment of circuit 2. Circuit 2 of the figure 4 includes many similarities with the circuits 2 described in connection with the figures 2 And 3 , and only the differences between these circuits are highlighted here.

[0083] In particular, circuit 2 of the figure 4 differs from the circuits 2 described previously by the implementation of its circuit 200. Indeed, in figure 4 , the circuit 200 directly uses the signals O1 and O2 to obtain an indication of the period difference between these signals O1 and O2. Thus, instead of receiving the signals Beat and O2 as in the circuits 200 previously described, in figure 4 , circuit 200 receives signals O1 and O2.

[0084] According to one embodiment, the circuit 200 comprises a phase frequency detector 400 ("PFD" block) receiving the signals O1 and O2, and providing as output an indication of the value of the period difference between the signals O1 and O2. For example, the circuit 400 provides a UP pulse when the signal O1 is in phase lag with respect to the signal O2, the UP pulse having a duration representative of, or determined by, the value of the period difference between the signals O1 and O2, and a DW pulse when the signal O1 is in phase advance with respect to the signal O2, the DW pulse having a duration representative of, or determined by, the value of the period difference between the signals O1 and O2.

[0085] In the example of the figure 4, the circuit 200 is configured to control the back gate of PMOS and NMOS transistors of at least one delay element of the oscillator RO1 only. For example, the circuit 200 is configured to control the back gate of all the PMOS and NMOS transistors of the oscillator RO1, for example by providing the same voltage VBG1 to the back gates of all the PMOS transistors of the oscillator RO1 and the same voltage -VBG1 to the back gates of all the NMOS transistors of the oscillator RO1. Preferably, the voltages VB1 and -VBG1 have the same absolute value but an opposite polarity (or sign). In the example of the figure 4 , the circuit 200 does not control the frequency of the oscillator RO2, and the rear gates of all the PMOS, respectively NMOS, transistors of the oscillator RO2 receive for example the same constant bias voltage VBG2f, respectively -VBG2f.

[0086] According to one embodiment, the circuit 200 comprises at least one charge pump PC1, PC2 controlled by the phase frequency detector 400 and configured to supply the control voltage to each rear gate controlled by the circuit 200. For example, each charge pump PC1, PC2 is controlled by the phase frequency detector 400 so as to charge and discharge a capacitor C1, C2 connected to its output, a control voltage of the rear gate of at least one transistor of the oscillator RO1 being available at the terminals of the capacitor.

[0087] For example, as shown in figure 4, the circuit 200 comprises a first charge pump PC1 controlled by the circuit 400 and a second charge pump PC1 controlled by the circuit 400. The charge pump PC1 is configured to charge and discharge, under the control of the circuit 400, a capacitor C1 connected to its output and at the terminals of which the voltage VBG1 is available. The charge pump PC2 is configured to charge and discharge, under the control of the circuit 400, a capacitor C2 connected to its output and at the terminals of which the voltage - VBG1 is available.

[0088] The person skilled in the art is able to size each charge pump PC1, PC2 of the circuit 200, the current sources (not shown in figure 4) of the charge pump and the capacitor connected to the output of this charge pump, for example so that the variations in the voltage across this capacitor allow a period difference to be obtained between the signals O1 and O2 which is at least N times smaller than the period of the signal O2.

[0089] The person skilled in the art is also able to adapt the description given above in relation to the figure 4 , which corresponds to a case where circuit 200 controls the frequency of oscillator RO1 only, to other cases where either circuit 200 controls the frequency of oscillator RO1 and oscillator RO2 simultaneously, or circuit 200 controls the frequency of oscillator RO2 only.

[0090] In the exemplary embodiments described above, the edges of the first type of the signal O2 are rising edges. The person skilled in the art is able to adapt the description given above of these exemplary embodiments to the case where the edges of the first type of the signal O2 are falling edges.

[0091] In the exemplary embodiments described above in connection with the figures 2 And 3, the counter 202 is configured to count the number of times the Beat signal is in the high state for a duration of N periods of the signal O2, i.e. to measure the duration of the high half-period of the Beat signal in number of periods of the signal O2. The person skilled in the art is able to adapt the description given previously of these exemplary embodiments to the case where the counter 202 is configured to count the number of times the Beat signal is in the low state for a duration of N periods of the signal O2, i.e. to measure the duration of the low half-period of the Beat signal in number of periods of the signal O2.

[0092] In the exemplary embodiments described above, the oscillators RO1 and RO2 are configured to receive a signal EN activating or deactivating the oscillation propagation. The person skilled in the art is able to adapt the description given above of these exemplary embodiments to the case where the propagation of oscillations in the oscillators RO1 and RO2 is not conditioned by the signal EN, i.e. to the case where the oscillators do not receive the signal EN.

[0093] Furthermore, in the exemplary embodiments described above, the delay elements 100 of the oscillators RO1 and RO2 are inverting gates (or inverters). However, the oscillators RO1 and RO2 may be implemented with any type of delay element, for example with logic cells of an FPGA.

[0094] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Random numbers generating circuit of correlated sampling ring oscillator type (2) comprising: a first ring oscillator (RO1) and a second ring oscillator (RO2), each comprising delay elements series-connected in a closed loop, the first and second oscillators (RO1, RO2) being identical and implemented in complementary metal oxide semiconductor on fully depleted silicon-on-insulator technology; a first circuit (104) configured to sample and store the state of an output (01) of the first oscillator (RO1) at a frequency of an output (O2) of the second oscillator (RO2) and to deliver a corresponding binary signal (Beat); and a second circuit (200) configured to control back gates of PMOS and NMOS transistors of at least one delay element of at least one of the first and second oscillators (RO1, RO2), based on a period difference between the outputs (O1, O2) of the first and second oscillators (RO1, RO2).

2. Circuit according to claim 1, wherein the control of the back gates of said PMOS and NMOS transistors of said at least one delay element is configured to increase a frequency of the first oscillator (RO1) with respect to a frequency of the second oscillator (RO2) when the frequency of the output (01) of the first oscillator (RO1) is lower than the frequency of the output (O2) of the second oscillator (RO2), and to decrease the frequency of the first oscillator (RO1) with respect to the frequency of the second oscillator (RO2) when the frequency of the output (01) of the first oscillator (RO1) is greater than the frequency of the output (O2) of the second oscillator (RO2).

3. Circuit according to claim 1 or 2, wherein the second circuit (200) is configured to control the back gates of said PMOS and NMOS transistors of said at least one delay element to decrease the period difference.

4. Circuit according to any of claims 1 to 3, wherein the second circuit (200) is configured to control the back gates of said PMOS and NMOS transistors of said at least one delay element so that the period difference is at least N times shorter than the period of the second oscillator (RO2), with N a number determined so that a contribution of the thermal noise is preponderating over a contribution of the quantization noise in the jitter of the output (O2) of the second oscillator (RO2).

5. Circuit according to claim 4, wherein N is greater than or equal to 1,000, for example equal to 1,000.

6. Circuit according to claim 4 or 5, wherein the second circuit (200) comprises a counter (202) configured to count, at a frequency of the output (O2) of the second oscillator (RO2), a number (Ni) of times when said binary signal (Beat) is in a first binary state for a duration of N periods of the output (O2) of the second oscillator (RO2).

7. Circuit according to claim 6, wherein said duration is a sliding duration.

8. Circuit according to claim 6 or 7, wherein the second circuit (200) further comprises a comparator (204) configured to compare said number (Ni) with a value equal to N / 2.

9. Circuit according to claim 8, wherein the second circuit (200) is configured to control the back gates of said PMOS and NMOS transistors of said at least one delay element based on an output signal (CMP) of the comparator (204) indicating the result of said comparison.

10. Circuit according to any of claims 1 to 5, wherein the second circuit (200) comprises a phase frequency detector (PFD) configured to receive the outputs (O1, O2) of the first and second oscillators (RO1, RO2).

11. Circuit according to claim 10, wherein the random number generation circuit (2) comprises at least one charge pump (PC1, PC2) controlled by the phase frequency detector (PFD) and configured to charge and discharge a capacitive element (C1, C2) connected to an output of said at least one charge pump, a voltage (VBG1, -VBG1) for controlling the back gates of said PMOS and NMOS transistors of said at least one delay element being available across the capacitive element (C1, C2).

12. Circuit according to any of claims 1 to 11, wherein the second circuit (200) is configured to control the back gate of each of the PMOS and NMOS transistors of a single one of the first and second oscillators (RO1, RO2).

13. Circuit according to claim 12, wherein the second circuit is configured to deliver a same first voltage (VBG1) to the back gate of each of the PMOS transistors of said a single one of the first and second oscillators (RO1, RO2), and a same second voltage (-VBG1) to the back gate of each of the NMOS transistors of said a single one of the first and second oscillators (RO1, RO2).

14. Circuit according to any of claims 1 to 11, wherein the second circuit (200) is configured to control the back gate of each of the transistors of each of the first and second oscillators (RO1, RO2).

15. Circuit according to claim 14, wherein the second circuit (200) is configured to deliver a same first voltage (VBG1) to the back gate of each of the PMOS transistors of the first oscillator (RO1), a same second voltage (-VBG1) to the back gate of each of the NMOS transistors of the first oscillator (RO1), a same third voltage (-VBG2) to the back gate of each of the PMOS transistors of the second oscillator (RO2), and a same fourth voltage (VBG2) to the back gate of each of the NMOS transistors of the second oscillator (RO2).