DATA REFRESH CYCLE FOR ASYNCHRONE DEVICE COMMUNICATION
DE602024002918T2Active Publication Date: 2026-03-04HAMILTON SUNDSTRAND CORP
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Patent Information
- Application Number
- DE602024002918
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2023-04-27
- Filing Date
- 2024-04-29
- Publication Date
- 2026-03-04
- Estimated Expiration
- 2044-04-29
AI Technical Summary
Technical Problem
Asynchronous devices in communication networks experience data staleness due to clock skew, leading to read/write interval overlaps and the provision of stale data when one device's write cycle is ignored during overlap with a higher-priority read cycle.
Method used
Implementing a read/write overlap avoidance latch and delay mechanism in the device controller to prevent write operations during read cycles, using a rising edge D flip-flop and clear input to reset the latch after a delay period, ensuring data freshness by avoiding cycle overlaps.
Benefits of technology
Prevents the bus controller from receiving stale data by ensuring write cycles are delayed until read cycles are complete, maintaining data freshness and accuracy in asynchronous communication systems.
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