ELECTRONIC CIRCUIT BASED ON RRAM 2T2R CELLS WITH IMPROVED ACCURACY

Description

[0001] The present invention relates to an electronic circuit suitable for implementing computational operations, each providing a binary output.

[0002] The invention relates to any type of application using operations applied to binary operands, in particular applications using binary artificial neural networks, also called BNNs (from the English Binary Neural Network ) .

[0003] A neural network is generally composed of a succession of layers of neurons, each taking its inputs from the outputs of the previous layer. More precisely, each layer comprises neurons whose inputs are derived from the outputs of the neurons in the preceding layer. Each layer is connected to the next by a plurality of synapses. A synaptic weight is associated with each synapse. This is a number, such as a binary number, or a distribution, that takes on both positive and negative values. In the case of a dense layer, the input of a neuron is the weighted sum of the outputs of the neurons in the preceding layer, the weighting being determined by the synaptic weights, followed by activation via an activation function.

[0004] It is therefore desirable to develop dedicated hardware architectures, intertwining memory and computing, to create fast, low-power neural networks capable of learning in real time.

[0005] Such dedicated hardware architectures are generally designed to efficiently perform operations applied to binary operands.

[0006] A neural network based on optical technologies is known.

[0007] Another area of ​​research focuses on the realization of neurons and synapses of neural networks based on CMOS-type technology (from the English Complementary Metal-Oxide-Semiconductor ) . The acronym CMOS refers both to a manufacturing process and to a component obtained by such a manufacturing process.

[0008] However, with each of these technologies, each neuron occupies several tens of micrometers on each side. Furthermore, each synapse also occupies several tens of micrometers on each side. Consequently, on a limited surface area, such as an electronic chip, the number of neurons and synapses that can be integrated is limited, resulting in reduced performance of the neural network.

[0009] Therefore, to reduce clutter, architectures in which synapses are memritive are specifically studied.

[0010] Memoristic synapses are synapses that utilize memristors. In electronics, a memristor (or memristor) is a passive electronic component. The name is a portmanteau of the English words "memory" and "resistor." A memristor is a non-volatile memory component; its electrical resistance changes when a voltage is applied for a certain duration and remains at that value when the voltage is removed.

[0011] Examples of such an implementation are provided in the following documents.

[0012] The published application US 2023 / 059091 A1 shows an example of memritive synapses.

[0013] The article ""A compute-in-memory chip based on resistive random-access memory" by W. Wan et al., published in Nature in 2022, describes a classic technique consisting of encoding binary weights as a resistive state within memory cells (a high resistive state (HRS) to encode 1, and a low resistive state (LRS) to encode 0, for example), and applying input activations to the bit line or BL (from the English Bit Line) of each cell. This results, via Ohm's law, in a current in each cell that is proportional to the product of the weights and the inputs, which is summed via Kirchhoff's laws on the line of source or SL (from English Source Line The source line current is then proportional to the multiplication-accumulation (MAC) between input activations and their respective weights. This approach is highly sensitive to the variability of memory cells, which is not negligible for most resistive memories. This variability directly influences the multiplication current within each memory cell, accumulates at the column end via Kirchhoff's law, and makes reading the result of the multiplication-accumulation increasingly difficult as the number of activated cells increases. This results in a complex and large-area read circuit, as well as a limitation on the size of the memory cell matrix due to a maximum number of cells activated in parallel, beyond which reading becomes impossible because of the variability.The maximum number of inputs that can be activated in parallel with this technique is typically 256, and this also requires a complex drive circuit and the inclusion of a computer in the drive loop to adapt to the specific characteristics of each chip, making it incompatible with the constraints of the Internet of Things. More generally, the maximum number of inputs that can be activated in parallel is closer to 9.

[0014] The article "The paper "Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control" by L. Wang et al., published in May 2021, describes a more robust technique against variability by connecting weights to inputs to form a resistive bridge. This approach relies on a complementary weight ratio, which is more robust against the variability of resistive cells. Furthermore, in each 2T2R memory cell, current always flows through a sum of LRS and HRS resistors in series, instead of a single LRS or HRS resistor as in the aforementioned classical technique. This approach thus reduces current consumption. However, this technique remains sensitive to the variability of resistive cells, also limiting its reliable use to neurons with 9 inputs.

[0015] The article "A crossbar array of magnetoresistive memory devices for in-memory computing" by S. Jung et al., published in Nature in 2022, describes another approach involving connecting resistive weights in series, instead of in parallel. The weights are stored in 2T2R memory cells whose two transistors are differentially activated. The multiplication operation between an input and a weight is performed by applying the input to a word line (WL). Word Line The 2T2R cell selects only one of the two resistive elements, whose value is determined by the weight. A voltage is applied to one end of the series of weights, generating a weighted current corresponding to the multiplication-accumulation between the weights and the inputs. This current charges a capacitor at the bottom of the column. The voltage across the capacitor is compared to a time reference, thus digitizing the multi-bit multiplication value.

[0016] Connecting all the weights in series reduces current consumption compared to the two previous approaches. However, since the access transistors are also connected in series with the weights, they must be large to avoid interfering with the computation. Furthermore, this approach remains highly sensitive to the variability of the resistive cells, with a maximum neuron size of approximately 64 inputs, and can also suffer from delay errors that depend on the combination of weights activated.

[0017] The article ""Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges" by M. Ezzadeen et al., published in September 2021, and document EP 4 137 999 A1 describe a further approach aimed at eliminating the impact of resistive cell variability on the accuracy of the multiply-accumulate operation. Weights are stored differentially in 2T2R memory cells, and inputs are applied differentially to complementary bitline pairs BL, BLb. Bit Line ) .Therefore, the neuron's weights are stored in a memory row instead of a column. Applying inputs to the complementary bit lines BL and BLb generates a resistive bridge per 2T2R memory cell, with the source line SL as its midpoint. The source line voltage is amplified and digitized using an inverter, whose output then corresponds to the result of the multiplication. Combining the use of the 2T2R memory cell in a resistive bridge configuration with an inverter provides very high robustness for the multiplication calculation. Accumulation is performed using a capacitive bridge connected to the output of the inverters, which is also very robust by design. The accumulation result is compared to the neuron's threshold using a comparator. This approach has been shown to be robust for implementing neurons with up to 513 inputs or more.

[0018] The limitation of this approach then becomes the comparator's precision, rather than the variability of the memory cells. Indeed, with a neuron of 513 inputs, the minimum voltage difference across the comparator is on the order of 2mV, which is a relatively critical threshold for comparator design. Implementing larger neurons would further reduce this voltage difference, making the comparator more susceptible to errors.

[0019] There is therefore a need for an electronic circuit that allows, in particular, the creation of a binary neural network with resistive memory cells and for larger neurons, i.e., with a higher number of inputs.

[0020] To this end, the invention relates to an electronic circuit suitable for implementing computational operations, each providing a binary output, the circuit comprising: word lines; pairs of complementary bit lines; source lines; a set of memory cells arranged in a matrix of rows and columns, the memory cells in the same row being selectable by a word line, the memory cells in the same column being connected to a pair of complementary bit lines and a source line; each memory cell comprising two memristors and two switches, each memristor being connected to the same source line and to a respective switch, each memristor storing respectively a weight or the inverse of the same weight by having respectively different first and second resistance values; the switches being connected, for their activation, to a respective word line and connected respectively to a pair of complementary bit lines; a read device implemented during each computational operation,The reading device comprises: + a logic unit for each column, each logic unit including an input terminal connected to a respective source line to receive an input value, the logic unit being configured to perform a logical operation having a toggle between a low value and a high value depending solely on the value of the input of the logic unit which is connected to the source line during said calculation operation, + a conversion module configured to convert a number of high or low values ​​at the output of the logic units into an intermediate quantity depending on said number of high or low values ​​at the output of the logic units, the intermediate quantity being an electrical quantity, such as an electrical voltage, the variation of which over time depends on a time constant, and the value of the time constant being a function of the number of high or low values ​​at the output of the logic units,The conversion module comprises a set of identical interconnected elements and a set of switches, each element being associated with the output of a respective logic unit, each switch being connected to the output of a respective logic unit and configured to activate, or respectively inhibit, the corresponding element according to the high or low value at the output of the respective logic unit, and the value of the time constant depending on the number of activated elements, and + a comparison module configured to compare the intermediate quantity to a reference quantity and to output a one-bit digital signal, dependent on the comparison and corresponding to the output of the electronic circuit, the emitted signal being representative of the result of the calculation operation.

[0021] The electronic circuit according to the invention then offers the advantage of the latter approach mentioned above, not presenting any problem of variability of memory cells, while having no limit of precision, the precision being independent of the size of the neuron with the electronic circuit according to the invention, as will be explained in more detail later.

[0022] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following features, taken individually or in all technically possible combinations: The value of the time constant is directly proportional to the number of high or low values ​​at the output of the logic units; the value of the time constant is equal to the product of a capacitance and a resistance, one of which is a predefined capacitance and resistance, and the other of which is a capacitance and resistance depending on the number of high or low values ​​at the output of the logic units; each element preferably being a resistor or a capacitor; the set of the same elements is placed between a first supply potential and an intermediate node, and the conversion module further includes a complementary element placed between the intermediate node and a second supply potential; when each element is a capacitor, the complementary element is a resistor; when each element is a resistor, the complementary element is a capacitor;The comparison module is configured to transform the intermediate quantity into a square wave signal with a state change edge at a characteristic time instant. The characteristic time instant is then compared to a reference time instant associated with the reference quantity, and the signal representing the result of the calculation operation depends on said comparison. The intermediate quantity is transformed into the square wave signal via a comparator. The comparison module includes the comparator and a comparison voltage generator, and the comparator is capable of comparing the generated voltage to the comparison voltage from the comparison voltage generator. The characteristic time instant is compared to the reference time instant via a flip-flop or via a comparator with a clock reference.The reference time instant is obtained via a set of identical second elements connected together and a set of second switches, the second elements being the same as those of the entire conversion module, each second element being associated with the output of a respective logic unit, each second switch being connected to the output of a respective logic unit and configured to activate, or respectively inhibit, the corresponding second element according to the high or low value at the output of the respective logic unit, and each second switch being controlled in an inverse manner with respect to the switch of the conversion module which is connected to the output of the same respective logic unit; each second element being preferably a resistor or a capacitor; each logic unit performs an inverter-type logic function during the calculation operation;the logical operation performed by the logic unit is an inversion, and the computational operation is a neural computation operation, such as the MAC operation; the electronic circuit is a neuromorphic circuit suitable for implementing a binary output neural network, each memory cell being associated with a respective synaptic weight of a neuron, and each pair of complementary bit lines being capable of receiving complementary input voltages during a neural computation operation;The electronic circuit includes a first controller for selecting the memory cells in a row that are connected to the same word line, and includes a second controller connected to the pairs of bit lines and for applying different voltages symmetrical to each pair of bit lines with respect to an average voltage, the voltage applied to a bit line being greater or less than that applied to the associated complementary bit line; the electronic circuit includes several distinct sets of memory cells suitable for operating in parallel with the same set of complementary bit line pairs and distinct sets of word lines, each set of memory cells being connected to a respective set of word lines;the electronic circuit comprises several distinct sets of memory cells designed to operate in parallel with the same set of word lines and distinct sets of complementary bit line pairs, each set of memory cells being connected to a respective set of complementary bit line pairs; the reading devices of two successive sets of memory cells being preferably connected to each other via a switch, the switch being preferably still controlled in the closed position during a neural computation operation to perform said operation with the set of complementary input voltages received by the two sets of memory cells.

[0023] These features and advantages of the invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which: there figure 1 is a schematic representation of an electronic circuit, according to the invention, adapted to perform computational operations, each providing a binary output, the circuit comprising word lines, pairs of complementary bit lines, source lines, a set of memory cells organized according to a matrix comprising rows and columns, each memory cell comprising two memristors and two switches, and a read device implemented during each computational operation; figure 2 is a schematic representation of an example of a memory cell in the electronic circuit of the figure 1 ; there figure 3 is a graph showing the effect of the variability of the resistance values ​​of the states of a memristor; the figure 4 is a schematic representation of an example implementation of a component performing an XNOR operation and forming part of the reading device of the electronic circuit of the figure 1 ; there figure 5 illustrates the four possible operating cases of the XNOR component of the figure 4 ; there figure 6 is a schematic representation of the output voltage of the XNOR component of the figure 4 in some cases of the figure 5 ; there figure 7 is a more functional schematic representation of the electronic circuit of the figure 1 , and in particular the reading device; the figure 8 is a schematic representation of the reading device of the figure 1 according to a first example of implementation; the figure 9 is a timing diagram of the discharge of a conversion bridge and the generation of a conversion signal, in the case of the electronic circuit of the figure 8 without bias; the figure 10 is a chronogram analogous to that of the figure 9 , in the case of the electronic circuit of the figure 8 with bias; the figure 11 is a schematic representation analogous to that of the figure 8 according to the second and third examples of implementation; the figure 12 is a schematic representation analogous to that of the figure 8 according to a fourth example of implementation; the figure 13 is a schematic representation analogous to that of the figure 8 according to a fifth example of implementation; the figure 14 is a schematic representation analogous to that of the figure 8 according to the sixth and seventh examples of implementation; the figure 15 is a schematic representation analogous to that of the figure 8 according to an eighth example of implementation; the figure 16 is a schematic representation of an electronic circuit according to the invention comprising several distinct sets of memory cells connected in series with each other and to the same set of word lines, these sets of memory cells being adapted to operate in parallel by being driven by distinct sets of complementary bit line pairs; the figure 17 is a schematic representation of an electronic circuit according to the invention comprising a matrix of distinct sets of memory cells, the sets of memory cells being connected to each other in the form of rows and columns, the sets in the same row being connected to the same set of word rows, and the sets in the same column being connected to the same set of complementary bit row pairs; and the figure 18 is a view analogous to that of the figure 17 according to another example of implementation.

[0024] It should be noted that the expression "specific to" followed by a verb is considered equivalent to the expression "configured for" followed by the same verb. The expression "specific to" may therefore be replaced, if necessary, by the expression "configured for," without altering the content and substance of the present invention.

[0025] On the figure 1 An electronic circuit 10 is designed to take as input a vector x comprising n inputs xj and to implement computational operations, each providing a binary output. The computational operations performed by the electronic circuit 10 are, for example, neural computing operations, such as counting the number of 1s in a series of bits (from the English popcount ) , even MAC operations (from English) Multiply And Accumulate ) well known for neural network inference.

[0026] The electronic circuit 10 is a neuromorphic circuit suitable for implementing a binary output neural network, that is to say a network for which the synaptic weights and the neurons are binary.

[0027] The electronic circuit 10 includes a set of memory cells 12 arranged according to a two-dimensional matrix 14, configured to store the values ​​of the synaptic weights of each neuron and a reading device 16 implemented during each computation operation.

[0028] On the figure 1 , matrix 14 comprises m rows 18 and n columns 20, where m is the number of rows 18 in matrix 14, and similarly n is the number of columns 20 in matrix 14, m and n each being an integer greater than or equal to 1.

[0029] A memory cell 12 has the coordinates (i,j) when said memory cell 12 is positioned at the intersection of the i-th row 18i and the j-th column 20j, where i and j are two integers. The index i is then between 1 and m, and the index j is between 1 and n.

[0030] The memory cells 12 of the i-th row 18 store the synaptic weights of a neuron. The number of rows 18 is therefore a function of the number of neurons in the neural network implemented by the electronic circuit 10.

[0031] The electronic circuit 10 also includes WL word lines, BL and BLb complementary bit line pairs, SL source lines and two controllers 22 and 24.

[0032] In the preceding notations, a word line is referenced WL (from English Word Line ); the complementary bit lines BL and BLb use the abbreviation BL (from English Bit Line ) and the source lines are referenced with the abbreviation SL (from English Source Line ) .

[0033] In the example of the figure 1 , each memory cell 12 is connected to a respective word line WL, a respective source line SL and a respective pair of complementary bit lines BL and BLb.

[0034] Each memory cell 12 in the same row 18 shares the same word line WL, so the word lines WL can also be indexed with the index i. Thus, the first word line, that is, the one which links the memory cells 12 in the first row 18, can be referenced WL 1.

[0035] Memory cells 12 in the same column 20 share the same pair of complementary bit lines BL and BLb and the same source line SL. These three lines can therefore also be indexed with the index j.

[0036] For clarity, all source lines SL are shown, but only the pairs of complementary bit lines BL and BLb from the first column 201, the jth column 20j, and the last column 20n are shown as dashed lines on the figure 1 .

[0037] Memory cells 12 in the same row 18 are then selectable by a word line WL, and memory cells 12 in the same column 20 are linked to a pair of complementary bit lines BL, BLb and a source line SL.

[0038] The first controller 22 allows the selection of memory cells 12 of a row 18 which are connected to the same word line WL and thus to select a single neuron from the electronic circuit 10.

[0039] The second controller 24 is specifically designed to control the complementary bit line pairs BL and BLb and the source lines SL.

[0040] The second controller 24 is connected to the pairs of bit lines BL, BLb and allows different voltages to be applied to each pair of bit lines BL, BLb, the voltages applied during the calculation operation being advantageously symmetrical with respect to an average voltage, the voltage applied on a bit line BL being greater or less than that applied on the associated complementary bit line BLb.

[0041] The first controller 22 and the second controller 24 are configured to be driven in a coordinated manner to control the memory cells 12 using the lines they control according to the desired operation.

[0042] Each memory cell 12 is designed to store at least one binary value, such as a binary weight W, in particular a respective binary synaptic weight of the neural network when the computational operation performed is a neural computational operation.

[0043] An example of the structure of a memory cell 12 is shown more precisely on the figure 2 for the case of memory cell 12 having coordinates (i,j).

[0044] Each memory cell 12 has two memristors, namely a first memristor 28 and a second memristor 30, as well as two switches, a first switch 32 and a second switch 34.

[0045] Because memristors 28 and 30 are present, such a memory cell 12 is a resistive random-access memory cell. Memory cell 12 is more often referred to by the acronym RRAM or ReRAM (from the English Resistive random-access memory ) .

[0046] Furthermore, such an arrangement is generally called a 2T2R structure, referring to the presence of two switches (designated 2T) and two memristors (designated 2R). Memory cell 12 is sometimes referred to as a 2T2R cell.

[0047] A memristor is a component whose electrical resistance changes permanently when a current is applied. This allows data to be recorded and rewritten by a control current. Such behavior is observed in phase-change materials, ferroelectric tunnel junctions, and redox memories based on oxides such as HfO₂ₓ or TiO₂ₓ.

[0048] The change in conductance of a memristor depends on the amplitude and duration of the voltage pulses applied through the memristor as well as the maximum current value that can pass through the memristor, for example for a "SET" operation, i.e. the transition from a high resistance to a low resistance.

[0049] A memristor can therefore have two states, a high state and a low state.

[0050] The high state corresponds to strong resistance and is generally designated by the abbreviation HRS, referring to the English term " High Resistive State " which literally means highly resistive state. The high state is, therefore, referred to as the high HRS state in the following.

[0051] The low state corresponds to low resistance and is generally designated by the abbreviation LRS, referring to the English term " Low Resistive State " which literally means low resistance state. The low state is, therefore, referred to as the LRS low state in the following.

[0052] However, due to the variability of the memristors in operation, the resistance in the high state HRS may be less than the resistance in the low state LRS, which generates errors if the information (weight) is encoded in a single memristor.

[0053] This variability is presented schematically on the figure 3 This figure represents the probability that a memristor will actually exhibit the resistance value as a function of the memristor's state.

[0054] More specifically, the first curve, the curve marked 36, schematically represents the probability for all the values ​​observed in practice for the low state LRS while the second curve 38 represents the same curve for the high state HRS.

[0055] The graph of the figure 3 This clearly shows that there is an overlap zone 40. In this overlap zone 40, distinguishing between low LRS and high HRS states may be impossible.

[0056] This overlap can be greater with long-term temporal drifts of memristors.

[0057] To remedy this problem, in the present example, the information is encoded by the ratio between the two resistances of the two states thanks to a differential configuration of the two memristors 28 and 30.

[0058] Also, according to the example described, memristors 28 and 30 are serial and complementary memristors respecting the same logic coding.

[0059] By complementary, it is understood here that memristors 28 and 30 have a different state, a low state LRS for one and a high state HRS for the other.

[0060] Following the example of the figure 2 , a strong weight, i.e. a logical “1”, is represented by a high HRS state of the first memristor 28 (respectively a low LRS state of the second memristor 30) while a weak weight, i.e. a logical “0”, is represented by a low LRS state of the first memristor 28 (respectively a high HRS state of the second memristor 30).

[0061] In the example described, each of the two memristors 28 and 30 is connected to the common source line SL.

[0062] Each of the two switches 32 and 34 is, for example, a transistor and more specifically a field-effect transistor.

[0063] A field-effect transistor is often referred to by the abbreviation FET (from English Field-Effect Transistor).

[0064] According to the example described, the two switches 32 and 34 are insulated-gate field-effect transistors. Such a transistor is more often referred to by the acronym MOSFET (from the English Metal Oxide Semiconductor Field Effect Transistor ) .

[0065] Thus, each switch 32 and 34 has three electrodes, a grid G, a source S and a drain D.

[0066] In general, for a transistor whose reference sign is X, the electrodes will be marked on the figures according to the following notation: the gate XG, the source XS and the drain XD.

[0067] This notation is chosen here to simplify the representation, given that the positions of the source XS and the drain XD are defined relative to the principal polarization direction, that is, the one most commonly used for the circuit. Of course, if the polarization is reversed, those skilled in the art know that the roles and positions of the source XS and the drain XD are reversed.

[0068] Each grid 32G and 34G of the two switches 32 and 34 is connected to the word line WL. Depending on the voltage level present on the word line, switches 32 and 34 are either conducting or not conducting. The first controller 22 will, in practice, select a row 18 of cells 12 via a word line WL by making switches 32 and 34 of the memory cells 12 in that row conductive.

[0069] The 32S source of the first switch 32 is connected to the bit line BL while the 34S source of the second switch 34 is connected to the complementary bit line BLb.

[0070] The drain 32D of the first switch 32 is connected to one terminal of the first memristor 28, the other terminal of the first memristor 28 being connected to the common source line SL.

[0071] The drain 34D of the second switch 34 is connected to one terminal of the second memristor 30, the other terminal of the second memristor 30 being connected to the common source line SL.

[0072] The second controller 24 will control the power supply to the pairs of bit lines, so that the voltage presented on a bit line BL j is different and complementary to the voltage presented on the complementary bit line BL j. Thus, when a cell 12 with coordinates i,j is selected (its switches being made conducting by the activation voltage presented on the associated word line WL i), the memristors 28 and 30 of this cell are in series and constitute a resistive bridge between the bit lines BL j and BLb j.

[0073] In this particular case, memristors 28 and 30 are thus powered by voltages present on the bit lines BL j and BLb j, which are symmetrical with respect to a voltage, for example V DD 2 , referred to as the midpoint voltage. In this notation, VDD corresponds to a supply potential VDD. Furthermore, ground is denoted GND hereafter. Of course, another midpoint voltage could be chosen, such as, for example, a voltage of V DD 3 .

[0074] The reading device 16 implemented during each calculation operation will now be described with reference to the figure 7 .

[0075] To better understand what follows, it can be observed that a binary neural network exhibits a specificity in inference compared to a classical neural network.

[0076] When a classical neural network is applied to an input vector to calculate an output vector, each neuron receives input values ​​corresponding to output values ​​from neurons in a previous layer. x j and calculates a weighted sum ∑ j W ij . x j and the neuron then applies a non-linear function f to the result of the weighted sum.

[0077] In contrast, in a binary neural network, the weighted sum is obtained by performing the following operation: a i = sign popcount j XNOR W ij x j − Th i Or a i And x j represent the output values ​​calculated by the neurons of the current layer, respectively by the previous layer; W ij represents the respective binary weights for the neurons in the current layer; XNOR is the logical function giving the complement of the exclusive OR function (this function is sometimes called exclusive NOT-OR for this reason); popcount is the function that counts the number of 1s in a series of bits; Th i is a predefined threshold, and sign is a function that associates the value 1 with a positive input and associates -1 with a negative value.

[0078] This means that, in the case of a binary network, it is possible to perform a binary neural computation via the electronic circuit 10 comprising the reading device 16 as shown in the diagram. figure 7 .

[0079] The reading device 16 includes a logic unit 42 for each column 20, a conversion module 44 and a comparison module 46.

[0080] Each logic unit 42 forms, in combination with a memory cell 12 selected from the column 20 associated with said logic unit 42, an equivalent XNOR component 43.

[0081] Logic unit 42 includes an input terminal connected to the source line SL of said memory cell 12 to receive an input value.

[0082] Each logic unit 42 is configured to perform a logic operation featuring a switch between a low value and a high value based solely on the value of the input of the logic unit that is connected to the source line SL during said computation operation.

[0083] More specifically, a logical "1" is represented by a high value at the output of logic unit 42 and a logical "0" is represented by a low value at the output of logic unit 42.

[0084] The XNOR component 43, equivalent to the association between the selected memory cell 12 and the logic unit 42, is now described with reference to the figure 4 .

[0085] The XNOR 43 component performs an XNOR operation on two signals, namely a weight denoted W and an input signal denoted in.

[0086] In this case, the XNOR component 43 comprises two memristors M1 and M2 and a logic unit 42.

[0087] In the example of the figure 4 , logic unit 42 is an inverter 48.

[0088] The two memristors M1 and M2 are complementary memristors connected in series corresponding to the weight W.

[0089] Also, similarly to what has been described previously, following the example of the figure 5 , a logical "1" for the weight W is represented by a high HRS state of memristor M1 (the other memristor M2 being in the low LRS state) while a logical "0" for the weight W is represented by a low LRS state of memristor M1 (the other memristor M2 being in the high HRS state).

[0090] The memristors M1 and M2 are connected at one end to the inverter 48 and at the other end to a respective voltage.

[0091] We will note a first voltage V in and a second voltage V inb.

[0092] The electrical configuration is therefore that of a voltage divider 50 connected on one side to the first voltage Vin and on the other side to the second voltage Vinb, and whose midpoint 52 is connected to the input of the inverter 48. In other words, one of the memristors M1 is subjected to a voltage |Vin - Vmid| and the other memristor M2 is subjected to a voltage |Vmid - Vinb|. The notation Vmid designates the voltage at the midpoint 52 of the voltage divider 50.

[0093] Thus, in the case described, the input signal in corresponds to the pair of the first voltage V in and the second voltage V inb.

[0094] These voltages Vin and Vinb, for example, have the particularity of being symmetrical with respect to half of the supply potential. V DD 2 . In practice, it may be advantageous to choose to have V in equal to V DD or GND, and respectively V inb equal to GND or V DD .

[0095] In the example of the figure 5 The input signal encodes a logic "1" when the first voltage Vin is strictly greater than the second voltage Vinb, i.e., Vin > Vinb. Conversely, the input signal encodes a logic "0" when the first voltage Vin is strictly less than the second voltage Vinb, i.e., Vin < Vinb.

[0096] This schematic representation of two memristors M1, M2 in series between two voltages Vin and Vinb corresponds in practice to the equivalent circuit formed by a selected cell 12 (the associated word line WL has a voltage that makes its switches conduct) and receiving bias voltages corresponding to Vin and Vinb via the bit lines BL and BLb. In other words, the input signal in is brought to a selected cell 12 via the associated bit lines BL and BLb by the action of the second controller 24. The midpoint 52 of the voltage divider then corresponds to the source line SL connected to the cell 12 in question.

[0097] The inverter 48 is an element designed to receive an incident signal on an input 48E and perform a logic inversion calculation to output on an output 48S an output signal which is the inverse of the incident signal.

[0098] Here, the 48E input of the inverter 48 is connected to the midpoint 52 of the divider bridge 50 formed by the two memristors M1 and M2.

[0099] The output 48S of the inverter 48 gives the result of the XNOR operation applied to the input signal in and the weight W.

[0100] The operation of the equivalent XNOR 43 component is now described with reference to figures 5 And 6 which schematically represent respectively the four possible operating cases of the XNOR 43 component and the output voltage values ​​for two of the four possible cases. In the figure 5 The reference symbols are not included in order to avoid making these figures too cumbersome.

[0101] More specifically, the case in the top left corner of the figure 5 corresponds to the case where the input signal in is 0 and the value of the weight W is equal to 0.

[0102] In such a case, as explained previously, the first voltage V in is strictly less than the second voltage V inb, that is, V in < V inb (with for example V in = GND and V inb = V DD).

[0103] Furthermore, the first memristor M1 is in the low state LRS while the second memristor M2 is in the high state HRS.

[0104] Due to the configuration, the memristor in the high state (HRS) absorbs almost all of the voltage dynamics, pushing the midpoint voltage (Vmid) from point 52 towards the voltage at the end of the memristor in the low state (LRS).

[0105] In this case, it means that the voltage V mid of the midpoint 52 is pushed back towards the first voltage V in as schematically represented by curve 54 on the figure 6 .

[0106] As apparent on this figure 6 , the midpoint voltage V mid is distinctly below half of the supply potential V DD / 2.

[0107] Output 48S of inverter 48 is then at 1.

[0108] This shows that for a signal in at 0 and for a weight at 0, the output of inverter 48 is then at 1, which corresponds well to XNOR(0,0) = 1.

[0109] Thus, the output of logic unit 42 is therefore a logic "1", so the output of logic unit 42 is a high value.

[0110] The case in the bottom left corner of the figure 5 corresponds to the corresponding case in which the input signal in is 0 and the value of the weight W is equal to 1.

[0111] In such a case, compared to the previous case, the only difference is that the first memristor M1 is in the high state HRS while the second memristor M2 is in the low state LRS.

[0112] As a result, the midpoint voltage Vmid is pushed towards the second voltage Vinb, as schematically represented by curve 56 on the figure 6 .

[0113] The output 48S of inverter 48 is then at 0.

[0114] This shows that for a signal in at 0 and for a weight W at 1, the output of inverter 48 is then at 0, which corresponds well to XNOR(0,1) = 0.

[0115] Thus, the output of logic unit 42 is therefore a logic "0", so the output of logic unit 42 is a low value.

[0116] The same remarks apply to the cases on the right of the figure 5 .

[0117] The upper case corresponds to an input signal in with a value of 1 (V in > V inb, with, for example, V in = V DD and V inb = GND) and a weight W with a value of 0 (first memristor M1 in the low state LRS and second memristor M2 in the high state HRS), so that the midpoint voltage V mid is pushed back towards the first voltage V in, that is to say that V mid > V DD 2 Consequently, the output 48S of inverter 48, and therefore of logic unit 42, is a logic "0". This corresponds to performing the operation XNOR(1,0) = 0.

[0118] The lower case corresponds to an input signal in of value 1 (V in > V inb ) and a weight of 1 (first memristor M1 in the high state HRS and second memristor M2 in the low state LRS) so that the midpoint voltage V mid is pushed towards the second voltage V inb, that is to say that V mid < V DD 2 As a result, the output 48S of inverter 48, and therefore of the logic unit, is a logic "1". This corresponds to performing the operation XNOR(1,1) = 1.

[0119] The different cases described lead to obtaining the truth table visible on the figure 5 , which clearly illustrates that the 48S output of the inverter performs an XNOR operation.

[0120] Such an XNOR 43 component allows obtaining a voltage output that does not exhibit the resistance variability of memristors M1 and M2.

[0121] The reduction in variability stems from two complementary factors.

[0122] An initial reduction in variability is achieved by using a differential configuration of the two memristors M1 and M2. However, at the midpoint 52 of the voltage divider 50, the signal is still subject to the variability of the memristors M1 and M2. In fact, the midpoint voltage depends on the ratio between the resistance values ​​of memristors M1 and M2, which reduces the variability, but not completely.

[0123] The second reduction in variability is achieved using logic unit 42, as shown in reference to the figure 6 .

[0124] As a result, the output signal of logic unit 42 is much less sensitive to resistance variations in memristors M1 and M2. Only in the worst-case scenario, where the statistical distributions of resistance values ​​overlap, might residual errors occur. In practice, however, this overlap can be avoided by applying sufficient programming voltages and currents.

[0125] The conversion module 44 is configured to convert a number of high or low values ​​at the output of the logic units 42 into an intermediate quantity depending on said number of high or low values ​​at the output of the logic units 42.

[0126] As a reminder, a high value corresponds to a logical "1" and a low value corresponds to a logical "0".

[0127] By "intermediate" in "intermediate magnitude", we mean intermediate in the sequence of actions necessary to perform the calculation operation, from the reception of each input value at the bottom of the column to the emission of the signal representing the result of the calculation operation.

[0128] In other words, the intermediate quantity is representative of the number of logical "1"s and "0"s at the output of the logical units 42 in each column 20.

[0129] In particular, the intermediate quantity represents the result of the operation popcount XNOR ( W j ,x i ).

[0130] The intermediate quantity is, for example, an electrical quantity, such as an electrical voltage, whose variation over time depends on a time constant, and the value of the time constant is a function of the number of high or low values ​​at the output of the logic units 42.

[0131] The time constant is then directly proportional to the number of high or low values ​​output by the logic units 42. For example, the time constant is proportional to the result of the operation popcount XNOR ( W j ,x j ).

[0132] Preferably, the value of the time constant is equal to the product of a capacitance and a resistance, and is then denoted RC, one of the capacitance and the resistance being predefined, and the other of the capacitance and the resistance depending on the number of high or low values ​​at the output of the logic units 42.

[0133] The comparison module 46 is configured to compare the intermediate quantity to a reference quantity and to output a one-bit digital signal, dependent on the comparison and corresponding to the output of the electronic circuit 10, the signal emitted being representative of the result of the calculation operation.

[0134] With reference to the figure 7 , the comparison module 44 includes a unit 58 for obtaining the reference quantity and a comparison unit 60.

[0135] The obtaining unit 58 is configured to provide as output a reference quantity comparable to the intermediate quantity.

[0136] For example, if the intermediate quantity is an electrical voltage, the obtaining unit 58 is configured to provide an electrical voltage as output.

[0137] The comparison unit 60 is linked to the conversion module 44 and the obtaining unit 58.

[0138] The comparator unit 60 takes as input the reference quantity provided by the obtaining unit 58 and the intermediate quantity provided by the conversion module 44, and outputs a one-bit signal corresponding to the result of the comparison of the intermediate quantity and the reference quantity.

[0139] The signal emitted is representative of a logical "1" or a logical "0" depending on the comparison between the two previous quantities and therefore of the result of the operation.

[0140] A first example of an embodiment of the reading device 16 of the electronic circuit 10 according to the invention will now be described with reference to figures 8 à 10 .

[0141] The electronic circuit 10 comprises the matrix 14 of memory cells 12 with m rows 18 and n columns 20.

[0142] As an optional complement, the electronic circuit 10 includes an additional matrix 26 of memory cells 12, also called the bias matrix 26, described in more detail later.

[0143] The conversion module 44 comprises a set of identical first elements 62 connected together and a set of first switches 64, each first element 62 being associated with the output of a respective logic unit 42, as shown in the figure 8 .

[0144] The number of first elements 62 and the number of first switches 64 are equal, each being equal to the number n of columns 20, and therefore to the number of logical units 42.

[0145] Each first switch 64 is connected to the output of a respective logic unit 42 and is configured to activate, or respectively inhibit, the corresponding first element 62 depending on the high or low value at the output of the respective logic unit 42. The value of the time constant then depends on the number of first element(s) 62 activated.

[0146] In the example of the figure 8 If a logic "0" is calculated at the output of a respective logic unit 42, the respective first switch 64 is configured to activate the corresponding first element 62; and conversely, if a logic "1" is calculated at the output of a respective logic unit 42, the respective first switch 64 is configured to deactivate the corresponding first element 62. This example of the control logic for the first element 62 corresponds to the case where each first switch 64 contains a PMOS transistor. Those skilled in the art will understand that the aforementioned control logic is reversed if each first switch 64 contains an NMOS transistor, the respective first switch 64 then being configured to activate the corresponding first element 62 if a logic "1" is calculated at the output of a logic unit 42, and conversely to deactivate the corresponding first element 62 if a logic "0" is calculated at the output of the logic unit 42.The number of first 62 activated elements is then equal to . n - popcount XNOR ( W j , x j ).

[0147] The first element 62 and the corresponding first switch 64 form a conversion unit 61 connected to the output of the logic unit 42.

[0148] In the example of the figure 8 , each first element 62 comprises a capacitor 63, each first element 62 preferably being made up of the capacitor 63. The capacitors 63 advantageously all have the same capacitance of value C 0 .

[0149] Alternatively, as will be described in more detail in the example of the figure 15 , each first element 62 includes a resistor, each first element 62 preferably being a resistor.

[0150] Each first switch 64 includes, for example, a transistor, such as a field-effect transistor. Each gate 64G of the transistor of a respective first switch 64 is connected to the output of each logic unit 42. The source 64S of said transistor is connected to a voltage line of predefined value, such as the value VDD, and the drain 64D of said transistor is connected to a respective capacitor 63.

[0151] All the first 62 elements are arranged one after the other in the form of a 78 conversion bridge, also called a pop bridge.

[0152] The conversion units 61 are therefore arranged one after the other to form the conversion bridge 78. When each first element 62 includes a respective capacitor 63, the conversion units 61 are connected in parallel with each other, between a first line to a first predefined voltage, such as the voltage V DD, and a first complementary line to another voltage, called pop voltage and noted V pop, corresponding to the intermediate quantity at the output of the conversion module 44.

[0153] For the conversion bridge 78, the number of capacitor(s) 63 connected in parallel is then equal to the number of first element(s) 62 activated, that is to say n - popcount XNOR ( W j , x j ). The set of capacitors 63 in the conversion bridge 78 is therefore equivalent to a single capacitor of capacitance ( n - popcount XNOR ( W j ,x j )) * C 0 connected between the voltages VDD and Vpop.

[0154] The conversion module 44 further includes a first resistor 65 of predefined impedance R, connected between the first line complementary to the voltage Vpop and a predefined potential, such as an electrical ground GND. The first resistor 65 is included in the conversion bridge 78.

[0155] Thus, if the conversion bridge 78 is initially pre-charged to the first predefined voltage VDD, the implementation of a computational operation, i.e. the activation of a row 18 by its word line WL and the application of the input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance ( n - popcount XNOR ( W j , x j )) * C 0 through the first resistance 65.

[0156] The intermediate quantity being the voltage Vpop of the first complementary line connected to both the capacitors 63 of capacitance C0 and the first resistor 65 of impedance R, the variation over time of the intermediate quantity depends on a time constant equal to ( n - popcount XNOR ( W j , x j )) * RC 0 .

[0157] The variation over time of the voltage Vpop in the example of the figure 8 is represented for several values ​​of popcount and n=5 on curves 200 at the top of the figure 9 .

[0158] The obtaining unit 58 includes, for example, a reference voltage generator 66. In the example of the figure 8 , the reference voltage generator 66 is in the form of a generation bridge 80, symmetrical with respect to the conversion bridge 78 of the conversion module 44.

[0159] The reference voltage generator 66 then comprises a set of the same second elements 68 connected together and a set of second switches 70, the second elements 68 being advantageously identical to the first elements 62.

[0160] Each second element 68 is associated with the output of a respective logic unit 42, each second switch 70 being connected to the output of a respective logic unit 42 and configured to activate, or respectively inhibit, the corresponding second element 68 according to the high or low value at the output of the respective logic unit.

[0161] Each second switch 70 is controlled in reverse with respect to the first switch 64 of the conversion module 44 which is connected to the output of the same respective logic unit 42.

[0162] In particular, if a logic "1" is calculated at the output of a logic unit 42, the respective second switch 70 is configured to activate the corresponding second element 68; and conversely, if a logic "0" is calculated at the output of a logic unit 42, the respective second switch 70 is configured to deactivate the corresponding second element 68. This example of the control logic for the second element 68 corresponds to the case where each second switch 70 contains an NMOS transistor. Those skilled in the art will understand that the aforementioned control logic is reversed if each second switch 70 contains a PMOS transistor, the respective second switch 70 then being configured to activate the corresponding second element 68 if a logic "0" is calculated at the output of a logic unit 42, and conversely to deactivate the corresponding second element 68 if a logic "1" is calculated at the output of the logic unit 42.The number of second element(s) 68 activated is then equal to the result of the . popcount XNOR ( W i , x i ).

[0163] The second element 68 and the corresponding second switch 70 form a generation unit 67 connected to the output of the logic unit 42.

[0164] For this purpose, in the example of the figure 8 , each second element 68 also includes a capacitor 63, each second element 68 being preferably a capacitor 63. The capacitors 63 advantageously all have the same capacitance of value C 0 .

[0165] Alternatively, as will be described in more detail in the example of the figure 15 , each second element 68 includes a resistor, each second element 68 preferably being a resistor.

[0166] Each second switch 70 includes, for example, an inverter 69 and a transistor, such as a field-effect transistor. The transistor of the second switch 70 is advantageously of the same type as that of the first switch 64, that is to say, having the same control logic.

[0167] The output of each logic unit 42 is then connected to a respective inverter 69, itself connected to the transistor of the second corresponding switch 70, said transistor then being connected to a respective capacitor 63.

[0168] Alternatively, but not shown, each second switch 70 comprises only a transistor, such as a field-effect transistor, and specifically does not include an inverter. According to this alternative, the transistor in the second switch 70 has the opposite control logic to that of the transistor in the first switch 64.

[0169] Each gate 70G of the transistor of a second respective switch 70 is connected to the output of each logic unit 42. The source 70S of said transistor is connected to a voltage line of predefined value, such as the value VDD, and the drain 70D of said transistor is connected to a respective capacitor 63.

[0170] All the second 68 elements are arranged one after the other in the form of the generation bridge 80, also called pop bridge b.

[0171] The generation units 67 are therefore arranged one after the other to form the generation bridge 80. When each second element 68 includes a respective capacitor 63, the generation units 67 are connected in parallel with each other, between a second line to a second predefined voltage, such as the voltage V DD, and a second complementary line to another voltage, called voltage pop_b and denoted V pop_b, corresponding to the reference quantity.

[0172] For the generation bridge 80, the number of capacitor(s) 63 connected in parallel is then equal to the number of second element(s) 68 activated, that is to say popcount XNOR ( W j , x j ). The set of capacitors 63 in the generation bridge 80 is therefore equivalent to a single capacitor of capacitance popcount XNOR ( W j , x i ) * C 0 connected between the voltages V DD and V pop_b.

[0173] The reference voltage generator 66 further includes a second resistor 71, with a predefined impedance advantageously identical to the impedance R of the first resistor 65. The second resistor 71 is connected between the second line complementary to the voltage Vpop_b and a predefined potential, such as ground (GND). The second resistor 71 is included in the generation bridge 80.

[0174] Thus, if the generation bridge 80 is initially pre-charged to the second predefined voltage VDD, the implementation of a computational operation, that is, the activation of a row 18 by its word line WL and the application of input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance popcount XNOR ( W j , x j ) * C 0 through the second resistance 71.

[0175] The reference quantity being the voltage V pop_b of the second complementary line connected to both the capacitors 63 of capacitance C 0 and the second resistor 71 of impedance R, the variation over time of the reference quantity depends on a time constant equal to popcount XNOR ( W j , x j ) * RC 0 .

[0176] The comparator unit 60 includes, for example, two comparators 72 and 74, namely a first comparator 72 and a second comparator 74.

[0177] The first comparator 72 is configured to transform the intermediate quantity into a pop-temp square wave signal with a state-change edge 205 at a characteristic time instant tc, as illustrated in the figure 9 .

[0178] For this purpose, the first comparator 72 is configured to receive as input the intermediate quantity Vpop and a comparison voltage Vcomp. The comparison voltage Vcomp is, for example, chosen to be equal to V DD 2 .

[0179] During the discharge of the conversion bridge, when the intermediate quantity V pop becomes less than the comparison voltage V comp, the first comparator 72 causes a switching of the square wave signal pop temp, passing for example to a value greater than its initial value, the state change edge 205 being in other words a rising edge.

[0180] The variation over time of the pop temp square wave signal is shown for several popcount values ​​and for n=5 on curves 210 of the figure 9 .

[0181] For a given popcount value, the characteristic time instant tc is then equal to n − popcount XNOR W j x j ∗ ln V DD V comp RC 0 , where In represents the natural logarithm function.

[0182] Thus, a time difference Δt between two characteristic time instants tc for two successive popcount values ​​is ln V DD V comp RC 0 .

[0183] A person skilled in the art will then observe that this time difference Δt is independent of the number n of inputs to the electronic circuit 10 and therefore independent of the size of the neuron. The accuracy of the generation of the square wave signal pop temp is thus independent of the size of the neuron.

[0184] The second comparator 74 is configured to transform the reference quantity into a pop btemp square wave signal with a state change edge 215 at a reference time instant t ref, as illustrated in the figure 9 .

[0185] For this purpose, the second comparator 74 is configured to receive as input the reference quantity V pop_b and the comparison voltage V comp.

[0186] During the discharge of the generation bridge 80, when the reference quantity V pop_b becomes less than the comparison voltage V comp, the second comparator 74 causes a switching of the square wave signal pop btemp, moving to a value greater than its initial value, the state change edge 215 being in other words a rising edge.

[0187] The variation over time of the pop btemp square wave signal is shown for several values ​​of popcount and for n=5 on curves 220 of the figure 9 .

[0188] For a given popcount value, the reference time instant t ref is therefore equal to popcount XNOR W j x j ∗ ln V DD V comp RC 0 → .

[0189] Thus, a time difference Δt between two reference time instants t ref for two successive popcount values ​​is therefore also ln V DD V comp RC 0 .

[0190] A person skilled in the art will then observe that this time difference Δt is independent of the number n of inputs to the electronic circuit 10 and therefore independent of the size of the neuron. The accuracy of the generation of the square wave signal popb temp is thus independent of the size of the neuron.

[0191] The comparison unit 60 is then configured to compare the characteristic time instant tc and the reference time instant t ref.

[0192] In the example of the figure 8 , the comparison unit 60 further includes a flip-flop 76, such as a D flip-flop (from English Data ) ,that is, a flip-flop with only one data input, denoted D. The value of the input D is copied to the output, denoted Q, at each clock edge.

[0193] The D input of flip-flop 76 is connected to the output of the first comparator 72 to receive the pop temp signal, and the clock input of flip-flop 76 is connected to the output of the second comparator 74 to receive the pop btemp signal. The Q output of flip-flop 76 corresponds to the result a of the calculation operation.

[0194] If the characteristic time instant tc is less than, that is, earlier than, the reference time instant tref, then the value of the input D of flip-flop 76 is already high at the clock edge corresponding to the reference time instant tref, so that the high value is then copied to the output Q of flip-flop 76 at the reference time instant tref. In other words, in this case, flip-flop 76 provides the high value representing a logic "1" as the result, denoted a, of the calculation operation, as illustrated on the right of the figure 8 .

[0195] Conversely, if the characteristic time instant tc is greater than, that is, later than, the reference time instant tref, then the value of the input D of flip-flop 76 is still low at the clock edge corresponding to the reference time instant tref, so that the low value is then copied to the output Q of flip-flop 76 at the reference time instant tref. In other words, in this case, flip-flop 76 provides the low value representing a logical "0" as the result of the calculation operation, as also illustrated on the right of the figure 8 .

[0196] In this example of the figures 8 And 9 It appears that: t c < t ref ⇔ popcount XNOR W j x j > n 2

[0197] A logic “1” at the output of flip-flop 76 corresponds to a popcount greater than n / 2, that is to say that the number of high values ​​at the output of logic units 42 is greater than the number of low values.

[0198] Conversely, a logic "0" at the output of flip-flop 76 corresponds to a popcount less than n / 2, that is to say that the number of high values ​​at the output of logic units 42 is less than the number of low values.

[0199] Thus, the result of the operation performed by the neuron is defined according to a threshold Th. The result is a logical "1" if the number of high values ​​is greater than the threshold Th. In the case described above, the threshold Th is equal to n / 2.

[0200] When, as an optional complement, the electronic circuit 10 includes the additional matrix 26 of memory cells 12, also called the bias matrix 26, this bias matrix 26 makes it possible to obtain a threshold Th different from n / 2, as will now be described.

[0201] The bias matrix 26 comprises b columns 20 and m rows 18, that is, the same number of rows 18 as the matrix 14. The m rows of the bias matrix 26 are each related to the WL word row of the respective row of the matrix 14.

[0202] The memory cells 12 in the same column 20 of the bias matrix 26 share the same pair of complementary bit lines BL and BLb and the same source line SL.

[0203] The number b of columns added is typically even.

[0204] Adding b bias columns generates b+1 possible different threshold values ​​Th centered around n / 2.

[0205] Similar to the columns 20 of matrix 14, each column 20 of bias matrix 26 is followed by a logic unit 42. We denote p the number of column(s) 20 of bias matrix 26 whose output of the respective logic unit 42 corresponds to a logic “0”.

[0206] The number of logical "0"s obtained at the output of the logical units 42 of the columns 20 of the bias matrix 26 is configured by the weights W stored in the memory cells 12 of the bias matrix 26 being selected by the word line WL, and activated by the input signal in brought to the selected cell 12 via the associated bit lines BL and BLb.

[0207] The conversion module 44 and the reference voltage generator 66 are extended to take into account the outputs of the additional logic units 42 of each column 20 of the bias matrix 26. In other words, the conversion module 44 then comprises a total of n+b first elements 62 and n+b first switches 64, and the reference voltage generator 66 comprises n+b second elements 68 and n+b second switches 70, when the reference voltage generator 66 includes the generation bridge 80.

[0208] Each first element 62 is connected to a respective first switch 64, and each second element 68 is connected to a respective second switch 70, each switch 64, 70 activating or inhibiting element 62, 68 as described previously. According to this optional complement with bias matrix 26, each first element 62, and respectively each second element 68, are identical to the first 62, and respectively second 68, elements described for the previous case without a bias matrix.

[0209] The number of first element(s) 62 activated in the conversion module 44 is then equal to n - popcount XNOR ( W j , x j ) + p.

[0210] Thus, if the conversion bridge 78 is initially pre-charged to the first predefined voltage VDD, the implementation of a computational operation, i.e., the activation of a row 18 by its word line WL and the application of input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance ( n - popcount XNOR ( W j , x j ) + p ) * C 0 through the first resistance 65.

[0211] For a given popcount value, the characteristic time instant tc of the pop temp signal provided by the first comparator 72 is therefore equal to n − popcount XNOR W j x j + p ∗ ln V DD V comp RC 0 .

[0212] The number of second element(s) 68 activated in the reference voltage generator 66 is therefore equal to popcount XNOR ( W j , x j ) + b - p.

[0213] Thus, if the generation bridge 80 is initially pre-charged to the second predefined voltage VDD, the implementation of a computational operation, i.e. the activation of a row 18 by its word line WL and the application of the input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance ( popcount XNOR ( W j , x j ) + b - p ) * C 0 through the second resistance 71.

[0214] For a given popcount value, the reference time instant t ref of the pop btemp signal provided by the second comparator 74 is therefore equal to popcount XNOR W j x j + b − p ∗ ln V DD V comp RC 0 .

[0215] By analogy with the operation described above, we deduce that a characteristic time instant tc less than the reference time instant tref, and consequently an output Q of the flip-flop 76 representing a logic "1", is equivalent to: t c < t r é f ⇔ popcount XNOR W j x j > n 2 − b 2 + p

[0216] A logical "1" at the output of flip-flop 76 corresponds to a popcount greater than n 2 − b 2 + p .

[0217] Conversely, a logical "0" at the output of flip-flop 76 corresponds to a popcount less than n 2 − b 2 + p .

[0218] Thus, when, as an optional complement, the electronic circuit 10 also includes the bias matrix 26, the threshold Th is equal to n 2 − b 2 + p . The threshold Th then depends on the number of bias columns b and the number p of logical "0" outputs of the logical units 42 of each bias column.

[0219] For p = b 2 , that is, if half of the outputs of the logical units 42 of the bias columns correspond to a logical "0" and the other half to a logical "1", the threshold Th is equal to n 2 We therefore obtain a result equivalent to an electronic circuit 10 not including the bias matrix 26.

[0220] There figure 10 represents different possible thresholds Th for n=5 and b=2. In the example of the figure 10 , different possible values ​​for the characteristic time instant tc are indicated on a line denoted tm (pop), and similarly different possible values ​​for the reference time instant t ref are indicated on a line denoted tm (pop b).

[0221] In configuration (c1), the electronic circuit 10 does not include the bias matrix 26. Therefore, we have Th = n 2 .

[0222] In configuration (c2), the bias matrix 26 has two columns 20 of memory cells 12. The two memory cells 12 selected by the word line WL are both configured to obtain a logical "0" at the output of their respective logic unit 42, in other words, p=2. Thus, the characteristic time instant tc obtained with the bias for a given popcount is shifted by 2*Δt relative to the characteristic time instant tc obtained without bias for the same popcount, where Δt represents the time difference between two characteristic time instants tc for two successive popcount values, such as, for example ln V DD V comp RC 0 . This 2*Δt offset is represented by the box for configuration (c2) at the figure 10 We then have Th = n 2 − b 2 + p = n 2 + 1 The characteristic time instant tc corresponds to the threshold Th and is represented by the dotted line going back up to the chronogram.

[0223] In configuration (c3), the bias matrix 26 also has two columns 20 of memory cells 12. The two memory cells 12 selected by the word line WL are both configured to obtain a logic "1" at the output of their respective logic unit 42, in other words, p=0. Thus, the reference time t ref obtained with the bias for a given popcount is shifted by 2*Δt relative to the reference time t ref obtained without bias for the same popcount, where Δt represents the aforementioned time difference. This shift of 2*Δt is shown in the box for configuration (c3) in the figure 10 We then have Th = n 2 − b 2 + p = n 2 − 1 The reference time instant t ref corresponds to the threshold Th and is represented by the dotted line going back up to the chronogram.

[0224] The second and third examples of the implementation of the electronic circuit 10 exhibiting a bias will now be described, with reference to the figure 11 .

[0225] The second and third examples differ from the first example with respect to the reference voltage generator 66, and only the differences between the first example described above and the second and third examples of the figure 11 will therefore be described below.

[0226] In the second example of implementation illustrated on the left of the figure 11 The reference voltage generator 66 comprises the generation bridge 80 and a complementary matrix 82 of memory cells 12. The difference between this second embodiment and the first example described previously is that the generation bridge 80 is not connected to the output of the logic units 42; in this second example, the generation bridge 80 is connected to the output of the said complementary matrix 82. The second switches 70 are therefore not controlled by the outputs of these logic units 42, but by the complementary matrix 82.

[0227] The complementary matrix 82 is configured to provide n outputs to the second switches 70, n being, as a reminder, the number of columns of the matrix 14. Each output can take a high value corresponding to a logical "1" or a low value corresponding to a logical "0".

[0228] The complementary matrix 82 comprises n columns 20 like the matrix 14 and at least one row 18. Each memory cell 12 in the same row 18 shares the same word line WL. The memory cells 12 in the same column 20 share the same pair of complementary bit lines BL and BLb and the same source line SL.

[0229] The number of logical "1s" and logical "0s" at the output of the complementary matrix 82 defines the threshold Th. We denote by r the number of "0s" in the series of bits at the output of the complementary matrix 82. Preferably, r is between n 2 − 10 % And n 2 + 10 % .

[0230] The number of rows 18 in the complementary matrix 82 is therefore equal to the number of desired threshold values. The word line WL connecting the row of the complementary matrix 82 storing the desired threshold weights activates the memory cells 12 of said row 18.

[0231] The second switches 70 according to this second embodiment are identical to those described previously for the first example, and include, for example, the reversing switches 69 visible at the figure 11 .

[0232] For example, each second switch 70 is configured to activate the corresponding second element 68 if the output of the complementary matrix 82 is representative of a logic '0' and to inhibit the corresponding element if said output is representative of a logic '1'.

[0233] Thus, if the generation bridge 80 is initially pre-charged to VDD, the implementation of a computational operation, that is, the activation of a row 18 by its word line WL and the application of input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance r * C 0 across resistance R.

[0234] The reference time instant t ref of the signal a th provided by the second comparator 74 according to this second example of implementation is then equal to r ∗ ln V DD V comp RC 0 .

[0235] The reference time instant t ref obtained is compared by the flip-flop 76 to the characteristic time instant tc of the signal provided by the first comparator 72, the latter being denoted here a pop and obtained in the absence of bias matrix 26, in other words t c = n − popcount XNOR W j x j ∗ ln V DD V comp RC 0 .

[0236] Based on the previous reasoning, we have: t c < t r é f ⇔ popcount XNOR W j x j > n − r

[0237] The output signal of flip-flop 76 is therefore representative of a logic "1" if popcount XNOR ( W j , x j ) > n - r and the output signal of flip-flop 76 represents a logic "0" if popcount XNOR ( W j , x j ) < n - r .

[0238] The threshold Th is therefore nr.

[0239] According to one variant, each second switch 70 is configured to activate the corresponding second element 68 if the output of the complementary matrix 82 is representative of a logic '1' and to inhibit the corresponding second element 68 if the output is representative of a logic '0'.

[0240] Thus, if the generation bridge 80 is initially pre-charged to VDD, the implementation of a computational operation, i.e. the activation of a row 18 by its word line WL and the application of input activations on the complementary bit lines BL / BL B, will generate the discharge of an equivalent capacitor of capacitance (n - r ) * C 0 across resistance R.

[0241] The output signal of flip-flop 76 is therefore representative of a logic "1" if popcount XNOR ( W j , x j ) > r, and the output signal of flip-flop 76 is representative of a logic "0" if popcount XNOR ( W j , x j ) < r.

[0242] The threshold Th is therefore equal to r.

[0243] A person skilled in the art will observe that the complementary matrix 82 then allows the generation bridge 80 to be controlled independently of the matrix 14, which makes it possible to generate the desired threshold value Th, without having a bias matrix 26 associated with the memory cell matrix 14 12. This requires, however, that each row of the complementary matrix 82 corresponds to a different threshold to cover the n 2 ± 10 % necessary biases.

[0244] In the third example of implementation illustrated on the right of the figure 11 , the electronic circuit 10 includes the additional bias matrix 26, the latter comprising b columns 20.

[0245] The reference voltage generator 66 comprises a plurality of generation units 67. In the example of the figure 11 The reference voltage generator 66 includes n + b 2 generation units 67.

[0246] Each generation unit 67 has an input, and the inputs of all the conversion units are connected to the same potential, for example to ground (GND). Each generation unit 67 according to this third embodiment is identical to a respective generation unit 67 described according to the first embodiment.

[0247] The generation units 67 are connected in parallel between the voltage V DD and the voltage V pop_b.

[0248] In the case where the first elements 62 of the conversion module 44 are capacitors 63, the voltage generator further includes a resistor R.

[0249] Thus, the generation bridge 80 is initially pre-charged to VDD; the implementation of a calculation operation will generate the discharge of an equivalent capacitor of capacitance n + b 2 ∗ C 0 through resistance R.

[0250] The reference time instant t ref of the signal a half provided by the second comparator 74 according to this third example of implementation is therefore equal to n + b 2 ∗ ln V DD V comp RC 0 .

[0251] The reference time instant t ref obtained is compared by the flip-flop 76 to the characteristic time instant tc of the signal provided by the first comparator 72, the latter being denoted here a pop+bias and obtained by considering that p is the number of bias columns whose output of the respective logic unit 42 corresponds to a logic “0”, in other words t c = n − popcount XNOR W j x j + p ∗ ln V DD V comp RC 0 .

[0252] Based on the previous reasoning, we have: t c < t réf ⇔ popcount XNOR W j x j > n 2 + p − b 2

[0253] We obtain a threshold Th = n 2 + p − b 2 .

[0254] A fourth example of the implementation of electronic circuit 10 will now be described, with reference to the figure 12 Only the differences between the first and fourth implementation examples are described below.

[0255] According to the figure 12 The acquisition unit 58 includes a voltage source 84 providing a fixed comparison voltage V comp, of constant value, at the input of the comparison unit 60. Preferably, the comparison voltage V comp is equal to V DD / 2.

[0256] In the example of the figure 12 , the comparator unit 60 includes a comparator 86 with a clock reference, hereafter referred to as clocked comparator 86, which takes as input the intermediate quantity from the conversion module 44 at its negative terminal and the comparator voltage V comp from the gaining unit 58, and in particular from the voltage source 84, at its positive terminal, and generates at output a signal a representative of a logic “1” or a logic “0”.

[0257] The intermediate quantity is the voltage of the conversion bridge 78, denoted Vpop, whose variation over time depends on a time constant equal to n − popcount XNOR W j x j ∗ RC 0 .

[0258] The characteristic time instant tc is defined as the instant from which the voltage V pop is less than the comparison voltage V comp: V pop < V comp ⇔ t > t c , avec t c = n − popcount XNOR W j x j ln V DD V comp RC 0

[0259] The clock edge of the clocked comparator 86 is fixed to a clock reference t clock configured so that if t c < t clock , the result of the neural calculation is 1, therefore the signal at the output of the clocked comparator 86 is representative of a logical "1" and if t c > t clock , the result of neural computation is 0, therefore the signal at the output of the clocked comparator 86 is representative of a logical "0".

[0260] The value of the clock reference t then allows us to define a fixed threshold Th, such that: t c < t clock ⇔ popcount > Th , Th = n − t clock ln V DD V comp RC 0

[0261] For example, to have a threshold Th of n 2 , we fix the clock face to the clock reference t clock = n 2 ln V DD V r é f RC 0 .

[0262] A fifth example of the implementation of electronic circuit 10 will now be described, with reference to the figure 13 Only the differences between the fourth and fifth implementation examples are described below.

[0263] In the example of the figure 13 , the reference voltage generator 66 is the generation bridge 80, symmetrical to the conversion bridge 78 of the conversion module 44.

[0264] The reference voltage generator 66 is then obtained via a set of identical second elements 68 connected together and a set of second switches 70, the second elements 68 being identical to the first elements 62 of the conversion module assembly 44. Those skilled in the art will observe that in the example of the figure 13 The second 70 switches typically have reversed control logic compared to the second 70 switches in the example of the figure 8 In the example of the figure 8 , each second switch 70 typically contains an NMOS transistor; and in the example of the figure 13 , each second switch 70 typically includes a PMOS transistor.

[0265] In the example of the figure 13 , each first element 62 of the conversion module 44 includes a capacitor 63 of capacitance C 0 , and each second element 68 includes a capacitor 63 of capacitance C 0 .

[0266] The reference voltage generator 66 further includes the second resistance 71 of impedance R, identical to the first resistance 65 of the conversion module 44 and connected to the voltage VDD.

[0267] Thus, if the generation bridge 80 is initially discharged, the implementation of a computational operation, i.e. the activation of a row 18 by its word line WL and the application of input activations on the complementary bit lines BL / BL B, will generate the charging of an equivalent capacitor of capacitance ( n - popcount XNOR ( W j , x j )) * C 0 through the second resistance 71 of impedance R.

[0268] The reference quantity being the voltage V pop_b of the generation bridge 80, the variation over time of the reference quantity depends on a time constant equal to ( n - popcount XNOR ( W j , x j )) * RC 0 . This time constant is equal to the time constant of variation of the intermediate quantity provided by the conversion module 44.

[0269] The voltages V pop and V pop_b have an intersection point for a voltage value on the order of V DD 2 .

[0270] The clocked comparator 86 takes as input the intermediate quantity V pop from the conversion module 44 at its negative terminal and the reference quantity V pop_b at its positive terminal, and generates at output a signal a representing a logic “1” or a logic “0”.

[0271] The characteristic time instant tc is defined as the instant from which the voltage V pop is less than the reference voltage V pop_b: V pop < V popb ⇔ t > t c , avec t c = n − popcount XNOR W j x j ln 2 RC 0

[0272] The clock edge of the clocked comparator 86 is fixed to the clock reference t clock configured so that if t c < t clock , the result of the neural calculation is 1, therefore the signal at the output of the clocked comparator 86 is representative of a logical "1", and if t c > t clock , the result of neural computation is 0, therefore the signal at the output of the clocked comparator 86 is representative of a logical "0".

[0273] The clock reference value t clock allows us to define a fixed threshold Th such that: t c < t clock ⇔ popcount > Th , Th = n − t clock ln 2 RC 0

[0274] For example, to have a threshold Th of n 2 , we fix the clock edge to the clock reference t clock = n 2 ln 2 RC 0 .

[0275] The sixth and seventh examples of the realization of an electronic circuit 10 with a bias to shift the threshold value Th, and with a comparison unit 60 comprising the clocked comparator 86, will now be described, with reference to the figure 14 .

[0276] Only the differences between the fifth example described previously and the sixth and seventh examples of the figure 14 will therefore be described below.

[0277] In the sixth example of implementation illustrated at the top of the figure 14 , the electronic circuit 10 includes the bias matrix 26.

[0278] The bias matrix 26 comprises b columns 20 of memory cells 12.

[0279] The clock edge of the clocked comparator 86 is fixed and has the clock reference t clock. Preferably, the clock reference t clock is defined such that the threshold Th in the absence of bias is n 2 . That's to say t clock = n 2 ln 2 RC 0 .

[0280] The reference voltage generator 66 is for example the generation bridge 80, symmetrical to the conversion bridge 78 of the conversion module 44, but under load.

[0281] Since the reference quantity is the voltage V pop_b of the generation bridge 80, the variation over time of the reference quantity V pop_b then depends on a time constant equal to ( n - popcount XNOR ( W j , x j ) + p ) * RC 0 . As a reminder, p is the number of bias columns whose output from the respective logic unit 42 corresponds to a logic "0". This time constant is equal to the time constant of variation of the intermediate quantity Vpop provided by the conversion module 44.

[0282] From this, we deduce the characteristic time instant tc: V pop < V popb ⇔ t > t c , avec t c = n − popcount XNOR W j x j + p ln 2 RC 0 t c < t clock ⇔ popcount > Th , Th = n + p − t clock ln 2 RC 0

[0283] Thus, if a clock reference t clock = n 2 ln 2 RC 0 , the threshold Th is n 2 + p .

[0284] The bias matrix 26 thus allows us to obtain different threshold values ​​depending on the number p of bias columns whose output from the respective logic unit 42 corresponds to a logical "0". Therefore, 0 ≤ p ≤ b , which corresponds to b+1 possible threshold values ​​Th centered around n 2 .

[0285] In the seventh example of implementation illustrated at the bottom of the figure 14 The clock signal of the clocked comparator 86 is variable t clock = n 2 + B ln 2 RC 0 .

[0286] The value B is a natural number and allows us to obtain a variable threshold Th depending on the value of B: Th = n 2 + B .

[0287] Preferably, − n 2 ∗ 10 % ≤ B ≤ n 2 ∗ 10 % .

[0288] The embodiments of the electronic circuit 10 described above are not limiting and are given solely as examples. All technically feasible combinations of features described in the preceding and following examples also fall within the scope of the invention.

[0289] In particular, the comparison unit 60 includes, for example, the clocked comparator 86; or the flip-flop 76 as well as the first and second comparators 72 and 74.

[0290] Similarly, the obtaining unit 58 includes, for example, the reference voltage generator 66 as shown in the figure 8 ; or the voltage source 84 providing the fixed comparison voltage Vcomp at the input of the comparison unit 60 as shown in the figure 12 .

[0291] The reference voltage generator 66 is, for example, implemented by the generation bridge 80, symmetrical to the conversion bridge 78 of the conversion module 44, the generation bridge 80 being controlled by the matrix 14, as shown in the figure 8 ; or by the generation bridge 80 controlled by the complementary matrix 82, as illustrated on the left of the figure 11 .

[0292] In addition, the generation bridge 80, symmetrical to the conversion bridge 78, can be configured to be equivalent to a charge or discharge of a capacitor.

[0293] In the case where the comparison unit 60 includes the flip-flop 76, a bias can be added to the threshold Th by adding the bias matrix 26 or via the complementary matrix 82.

[0294] The reference voltage generator 66 may also include a half-bridge formed by n + b 2 generation units 67 in case of presence of the bias matrix 26.

[0295] In the case where the comparison unit 60 includes a clocked comparator 86, the threshold Th can be modified by the presence of a bias by adding the bias matrix 26 if the clock time of the clocked comparator 86 is fixed, or by varying the clock time according to the desired bias.

[0296] The electronic circuit 10 according to the invention therefore includes the comparison module 46 defined according to all technically possible combinations of the characteristics described above.

[0297] An additional variant, combinable with the implementation examples described above, is illustrated by an eighth implementation example with reference to the figure 15 Only the differences between the fifth and eighth implementation examples will be described below.

[0298] In the example of the figure 15 The conversion units 61 of the conversion module 44 are connected in series.

[0299] Each conversion unit 61 comprises the first element 62 and the first switch 64 connected in parallel.

[0300] Each first element 62 includes a resistor 88 of resistance R 0 and each first switch 64 includes a switch 90 configured to activate or inhibit the corresponding resistor 88.

[0301] In particular, if a logic '0' is calculated at the output of a logic unit 42, the respective first switch 64 is configured to activate the corresponding first element 62, so switch 90 is open; and if a logic '1' is calculated at the output of a respective logic unit 42, the respective first switch 64 is configured to inhibit the corresponding first element 62, so switch 90 is closed.

[0302] The resistor 88 located at the output of the first column 20 is connected to the electrical ground GND and the resistor 88 located at the output of the last column 20 is connected to the input of the comparator unit 60.

[0303] The conversion module 44 further includes a first capacitor 92 of capacitance C connected between the input of the comparator unit 60 and the potential V DD.

[0304] Thus, if the conversion bridge 78 is initially pre-charged to the potential VDD, the implementation of a computational operation, i.e. the activation of a row 18 by its word line WL and the inputs on the complementary bit lines BL / BL B, will generate the discharge of the capacitor of capacitance C through an equivalent resistance of resistance ( n - popcount XNOR ( W j ,x j )) * R 0 .

[0305] The intermediate quantity being the voltage Vpop of the conversion bridge 78, the variation over time of the intermediate quantity depends on a time constant equal to ( n - popcount XNOR ( W j , x j )) * CR 0 .

[0306] The resistances 88 of the first elements 62 forming the conversion bridge 78 are connected in series between the electrical ground GND and the voltage V pop.

[0307] Similarly, each second element 68 of the reference voltage generator 66 formed the generation bridge 80, symmetrical to the conversion bridge 78 of the conversion module 44, includes the resistor 88 of resistance R 0 and each second switch 70 includes the switch 90 in parallel with the resistor 88.

[0308] The resistances 88 of the second elements 68 forming the generation bridge 80 are connected in series between a potential VA and the voltage V pop_b.

[0309] The reference voltage generator 66 includes in addition a second capacitor 94 of capacitance C connected between the voltage V pop_b and a potential VB.

[0310] The values ​​of the potentials VA and VB, as well as the control logic of the second switches 70, are defined according to the charging or discharging of the second capacitor 94 during the implementation of a neural computation.

[0311] Thus, all other things being equal, all the previous examples of realization are technically possible using resistors 88 as first elements 62, and where appropriate second elements 68, instead of capacitors 63.

[0312] The calculation steps described above remain valid when replacing C 0 with R 0 , and respectively C with R.

[0313] The major advantage of the invention is the possibility of implementing a binary neuron whose accuracy is independent of the neuron's size. This allows for the implementation of very large neurons with very high accuracy, with the only drawback being a potentially longer computation time. Since the sizes of the implemented neurons can vary from one neural network architecture to another, and even from one layer to another, the electronic circuit 10 according to the invention optionally and advantageously features a sub-bank architecture 95 in the form of a row of neural nodes where each neural node 100 is configured to implement a respective neuron and where the neurons have minimum sizes of x inputs, as illustrated in the figure 16 .

[0314] In the example of the figure 16 , each neuronal node 100 includes the matrix 14 of resistive memory cells 12 for storing weights, and optionally the bias matrix 26; the conversion bridge 78 and associated first resistor 65, and optionally the generation bridge 80 and associated second resistor 71; the first and second comparators 72, 74 and the flip-flop 76.

[0315] The neural nodes 100 can then be connected to each other by first switches 102 to connect the conversion bridges 78 in series, and optionally by second switches 104 to connect the generation bridges 80 in series, in order to implement larger neurons. Connecting two neural nodes 100 of minimum size x is simple, as it is sufficient to connect their conversion bridges 78, and respectively their generation bridges 80, to implement a neuron of size 2x. However, care must be taken to connect only one discharge resistor 65, 71 per bridge 78, 80.

[0316] Controlling such an architecture with 100 neural nodes is simple, as shown by the figure 10 , with common control of WL word lines via the first controller 22; an input activation register 110 capable of storing inputs; a register 115 for controlling connections between neural nodes 100, then capable of controlling the first and second switches 100, 102; and an output register 120 retrieving the output activations of all neural nodes 100 in parallel.

[0317] There figure 17 illustrates the architecture of a bench constructed from several sub-benches 95, each sub-bench 95 being of the type described previously opposite the figure 16 The sub-banks 95 share the same input activation register 110 and the same control register 115 for connections between neural nodes 100, and the outputs of the neural nodes 100 are multiplexed to be captured by the common output register 120, which retrieves the output activations. This control can be made more complex for greater control granularity.

[0318] The invention thus offers great flexibility in mapping weights and neurons: one neuron per neuronal node 100 if the neurons are small; one neuron on several neuronal nodes 100 if the number of inputs from the neurons is too high to use a single neuronal node 100; the same neurons with several inputs in parallel by duplicating the weights on several neuronal nodes 100.

[0319] Another variant consists of integrating the first elements 62 and switches 64, and respectively the second elements 68 and switches 70, directly within the matrix 14 of memory cells 12, as illustrated in the figure 18 It should be noted that the pre-charging of the ends of the first elements 62, respectively of the second elements 68, for example in the form of capacitors 63, can be done simply by applying a signal to the potential GND, followed by a signal to the potential V DD on the common source line, which will allow the internal nodes of the first switches 64 to be pre-charged, followed by those of the second switches 70.

[0320] It is thus understood that the electronic circuit 10 according to the invention makes it possible to create a binary neural network with resistive memory cells 12 and for larger neurons, i.e. with a higher number of inputs.

Claims

1. An electronic circuit (10) suitable for implementing computing operations each providing a binary output, the circuit comprising: - word lines (WL); - pairs of complementary bit lines (BL, BLb); - source lines (SL); - a set of memory cells (12) organized according to a matrix (14) including rows (18) and columns (20), the memory cells (12) of a same row (18) being selectable by a word line (WL), the memory cells (12) of a same column (20) being connected to a pair of complementary bit lines (BL, BLb) and to a source line (SL); each memory cell (12) comprising two memristors and two switches, each memristor being connected to the same source line (SL) and to a respective switch, each memristor respectively storing a weight or the inverse of the same weight by respectively presenting first and second different resistance values; the switches being connected, for their activation, to a respective word line (WL) and connected respectively to a pair of complementary bit lines (BL, BLb); - a reading device (16) implemented during each calculation operation, the reading device (16) comprising: + a logic unit (42) for each column (20), each logic unit (42) comprising an input terminal connected to a respective source line (SL) for receiving an input value, the logic unit (42) being configured to perform a logic operation presenting a switching between a low value and a high value depending solely on the value of the input of the logic unit which is connected to the source line (SL) during said calculation operation, characterized in that the reading device (16) further includes: + a conversion module (44) configured to convert a number of high or low values at the output of the logic units (42) into an intermediate value dependent on said number of high or low values at the output of the logic units (42), the intermediate value is an electrical value, such as an electrical voltage, the variation of which over time depends on a time constant (RC), and the value of the time constant is a function of the number of high or low values at the output of the logic units (42), the conversion module (44) including a set of same elements (62) connected together and a set of switches (64), each element (62) being associated with the output of a respective logic unit (42), each switch (64) being connected to the output of a respective logic unit (42) and configured to activate, or respectively inhibit, the corresponding element (62) according to the high or low value at the output of the respective logic unit (42), and the value of the time constant depending on the number of elements (62) activated, and + a comparison module (46) configured to compare the intermediate value with a reference value and to output a one-bit digital signal, depending on the comparison and corresponding to the output of the electronic circuit (10), the output signal being representative of the result of the calculation operation.

2. The electronic circuit (10) according to claim 1, wherein the value of the time constant is directly proportional to the number of high or low values at the output of the logic units (42).

3. The electronic circuit (10) according to any one of the preceding claims, wherein the value of the time constant is equal to the product of a capacitance and a resistance, one from among the capacitance and the resistance being predefined, and the other from among the capacitance and the resistance depending on the number of high or low values at the output of the logic units (42).

4. The electronic circuit (10) according to any one of the preceding claims, wherein each element (62) is a resistor (88) or a capacitor (63).

5. The electronic circuit (10) according to any one of the preceding claims, wherein the set of same elements is placed between a first supply potential (VDD; GND) and an intermediate node (Vpop), and the conversion module (44) further includes a complementary element placed between the intermediate node (Vpop) and a second supply potential (GND; VDD).

6. The electronic circuit (10) according to claims 4 and 5, wherein when each element (62) is a capacitor (63), the complementary element is a resistor (65); wherein when each element (62) is a resistor (88), the complementary element is a capacitor (92).

7. The electronic circuit (10) according to any one of the preceding claims, wherein the comparison module (46) is configured to transform the intermediate value into a square-wave signal with a change-of-state edge at a characteristic time instant (tc), the characteristic time instant (tc) then being compared with a reference time instant (tref) associated with the reference value, and the signal representative of the result of the calculation operation then depending on said comparison.

8. The electronic circuit (10) according to claim 5, wherein the intermediate value is transformed into the square-wave signal via a comparator (72).

9. The electronic circuit (10) according to claim 6, wherein the comparison module (46) includes the comparator (72) and a comparison voltage generator (Vcomp), and the comparator (72) is able to compare the generated voltage with the comparison voltage coming from the comparison voltage generator.

10. The electronic circuit (10) according to any one of claims 5 to 7, wherein the characteristic time instant (tc) is compared with the reference time instant (tref) via a flip-flop (76) or via a comparator (86) with a clock reference (tclock).

11. The electronic circuit (10) according to any one of claims 5 to 8, taken together with claim 4, wherein the reference time instant (tref) is obtained via a set of the same second elements (68) connected together and a set of the second switches (70), the second elements (68) being the same as those of the conversion module assembly (44), each second element (68) being associated with the output of a respective logic unit (42), each second switch (70) being connected to the output of a respective logic unit (42) and configured to activate, or respectively inhibit, the corresponding second element (68) according to the high or low value at the output of the respective logic unit (42), and each second switch (70) being controlled inversely relative to the switch (68) of the conversion module (44) which is connected to the output of the same respective logic unit (42); each second element (68) preferably being a resistor (88) or a capacitor (63).

12. The electronic circuit (10) according to any one of the preceding claims, wherein each logic unit (42) performs an inverter-type logic function during the calculation operation.

13. The electronic circuit (10) according to any one of the preceding claims, wherein the logic operation performed by the logic unit (42) is an inversion, and the operation is a neural calculation operation, such as the MAC operation.

14. The electronic circuit (10) according to any one of the preceding claims, wherein the electronic circuit (10) is a neuromorphic circuit able to implement a neural network with binary output, each memory cell (12) being associated with a respective synaptic weight of a neuron, and each pair of complementary bit lines being able to receive complementary input voltages (Vin,Vinb) during a neural calculation operation.

15. The electronic circuit (10) according to any one of the preceding claims, comprising a first controller (22) allowing to select the memory cells (12) of a row (18) which are connected to a same word line (WL), and comprising a second controller (24) connected to the pairs of bit lines (BL, BLb) and allowing different voltages to be applied to each pair of bit lines (BL, BLb) which are symmetrical relative to a midpoint voltage, the voltage applied to a single bit line (BL) being greater or less than that applied to the associated complementary bit line (BLb).

16. The electronic circuit (10) according to any one of the preceding claims, wherein the electronic circuit (10) comprises a plurality of distinct sets of memory cells (12) able to operate in parallel with a same set of pairs of complementary bit lines (BL, BLb) and distinct sets of word lines (WL), each set of memory cells (12) being connected to a respective set of word lines.

17. The electronic circuit (10) according to any one of the preceding claims, wherein the electronic circuit (10) comprises a plurality of distinct sets of memory cells (12) able to operate in parallel with a same set of word lines and distinct sets of pairs of complementary bit lines, each set of memory cells (12) being connected to a respective set of pairs of complementary bit lines; the reading devices (16) of two successive sets of memory cells (12) being preferably connected to each other via a switch (102, 104), the switch (102, 104) being preferably further controlled to the closed position during a neural calculation operation to perform said operation with the set of complementary input voltages (Vin,Vinb) received by the two sets of memory cell (12).